Eric Lee / smarc-fsl-linux-kernel

03 Apr, 2015

1 commit

  • df3305156   [media] v4l: xilinx: Add Xilinx Video IP core ... Browse Code ยป

    Xilinx platforms have no hardwired video capture or video processing
    interface. Users create capture and memory to memory processing
    pipelines in the FPGA fabric to suit their particular needs, by
    instantiating video IP cores from a large library.

    The Xilinx Video IP core is a framework that models a video pipeline
    described in the device tree and expose the pipeline to userspace
    through the media controller and V4L2 APIs.

    Signed-off-by: Laurent Pinchart
    Signed-off-by: Hyun Kwon
    Signed-off-by: Radhey Shyam Pandey
    Signed-off-by: Michal Simek
    Acked-by: Hans Verkuil
    Signed-off-by: Mauro Carvalho Chehab

    Laurent Pinchart