Eric Lee / smarc-fsl-linux-kernel

16 Jul, 2015

1 commit

  • a3c83ff20   clk: tegra: Add DFLL DVCO reset control for Tegra124 ... Browse Code ยป

    The DVCO present in the DFLL IP block has a separate reset line,
    exposed via the CAR IP block. This reset line is asserted upon SoC
    reset. Unless something (such as the DFLL driver) deasserts this
    line, the DVCO will not oscillate, although reads and writes to the
    DFLL IP block will complete.

    Thanks to Aleksandr Frid for identifying this and
    saving hours of debugging time.

    Signed-off-by: Paul Walmsley
    [ttynkkynen: ported to tegra124 from tegra114]
    Signed-off-by: Tuomas Tynkkynen
    [mikko.perttunen: ported to special reset callback]
    Signed-off-by: Mikko Perttunen
    Acked-by: Michael Turquette
    Signed-off-by: Thierry Reding

    Paul Walmsley