17 Aug, 2016
1 commit
-
This layer is responsible for
- Enumerating over PCI bus
- Inform FW about host readiness
- Provide HW interface to transport layer for control and messages
- Interrupt handling and routingOriginal-author: Daniel Drubin
Reviewed-and-tested-by: Ooi, Joyce
Tested-by: Grant Likely
Tested-by: Rann Bar-On
Tested-by: Atri Bhattacharya
Signed-off-by: Srinivas Pandruvada
Signed-off-by: Jiri Kosina