12 Apr, 2022
1 commit
05 Apr, 2022
1 commit
29 Apr, 2019
1 commit
03 Apr, 2019
2 commits
13 Mar, 2018
1 commit
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kernel panic when run opencl cts test_buffers on mScale850D,
use get_user and put_user to touch and validate user memory,Signed-off-by: Xianzhong
(cherry picked from commit 381665e0a47639fe8085f28e50598a701f14bccc)
12 Mar, 2018
18 commits
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Signed-off-by: Olivier Masse
(cherry picked from commit d051f656ea23845a428dd12c8ad96fd37c515d29) -
Signed-off-by: Antoine Bouyer
(cherry picked from commit 642119b966e25a6a6606460470b0def9418647ae) -
These pointers are required for drm dts
Signed-off-by: Antoine Bouyer
(cherry picked from commit 5f048351c272121cb82481a680407c415a898b3e) -
Signed-off-by: Antoine Bouyer
(cherry picked from commit eebe0cbb951dcf287b58ec0002d3e817be43d810) -
Signed-off-by: Antoine Bouyer
(cherry picked from commit 044c0200431a08e90435b47d4b0ff6bcc0aa925a) -
Signed-off-by: Hervé Fache
Signed-off-by: Antoine BouyerMMIOT-6-2 android: ion: Minor changes for readability
Signed-off-by: Alexandre Jutras
(cherry picked from commit 627f870847ab5f2763dc1a84f06d39a50ad514e5) -
Fixes: 7c7d9c446252 "staging/ion: CONFIG_ION_UNMAPPED_HEAP conditions unmapped heap"
Signed-off-by: Etienne Carriere
Acked-by: Joakim Bech
(cherry picked from commit bf829aa7c001c085a47c715e04cb3c347b1a38f8
linaro repo https://github.com/linaro-swg/linux.git
tag optee-v4.9-20171005)(cherry picked from commit 3d8ce9b2a78f5aea9455fe59a13111dcba53f512)
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Signed-off-by: Etienne Carriere
Acked-by: Joakim Bech
(cherry picked from commit 916d9f36e107c37a88cb15924e0da8c5a572f90a
linaro repo https://github.com/linaro-swg/linux.git
tag optee-v4.9-20171005)(cherry picked from commit a63fc891ce78ec136411cdaaa92698264be8027f)
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Condition ION unmapped heap implementation to architectures that
currently support it. ARM is one of these.Signed-off-by: Etienne Carriere
Reviewed-by: Joakim Bech
(cherry picked from commit 7c7d9c446252829aa138c87c47a937e2a3b4fd26
linaro repo https://github.com/linaro-swg/linux.git
tag optee-v4.9-20171005)(cherry picked from commit a3fd09542ff46c16c409a7ae76698326264ad9f4)
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If one enables ION_DUMMY_UNMAPPED_HEAP without providing the target
unmapped heap configuration settings (physical base address and size),
the kernel cannot build. This situation occurs in Linux test build
cases, i.e running the allmodconfig configuration.This change overcomes the issue by providing default null settings for
both ION_DUMMY_UNMAPPED_BASE and ION_DUMMY_UNMAPPED_SIZE.Signed-off-by: Etienne Carriere
Acked-by: Jens Wiklander
(cherry picked from commit ac0c2c26b9819c5e95d56cb2d8937de0357eecaa
linaro repo https://github.com/linaro-swg/linux.git
tag optee-v4.9-20171005)(cherry picked from commit 533987a37a218309a49f0ad292402f91b6abf76a)
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Add configuration ION_DUMMY_UNMAPPED_HEAP to enable optional definition
of a statically defined "unmapped" heap for test purpose: kernel config
must provide the memory pool base address and byte size.Signed-off-by: Etienne Carriere
Reviewed-by: Joakim Bech
(cherry picked from commit 961993fde60ebd06715d1433f8eb265471a0f38c
linaro repo https://github.com/linaro-swg/linux.git
tag optee-v4.9-20171005)(cherry picked from commit 7289344f7a6b4ee1c863930110c18744b7e3a3cc)
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OP-TEE/SDP (Secure Data Path) memory pools are created through ION
secure type heap" from Allwinner. This change renames "secure" into
"unmapped" as, from Linux point of view, the heap constraint is
manipulating unmapped memory pools/buffers."Unmapped" heap support is integrated in ION UAPI (actually this was
the Allwinner initial proposal) and ION DT parsing support.Based in work from Sunny for Allwinner.
Signed-off-by: Etienne Carriere
Reviewed-by: Joakim Bech
(cherry picked from commit 4a95713514ddc3d55d5df213513aeec5a3717243
linaro repo https://github.com/linaro-swg/linux.git
tag optee-v4.9-20171005)(cherry picked from commit 4cb0f7b04d70d3c475185a98094b556abfc4d68a)
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Dumped from:
https://github.com/loboris/OrangePI-Kernel/tree/master/linux-3.4
0cc8d855adb
Author: Sunny for Allwinner.Changes made on original "secure heap" implementation:
- minor coding style: fix includes, empty lines and overlong lines,
indentation, comment layout.
- Original path modified the ion uapi. We do not attempt to modify
uapi/ion.h. "secure" (or "domain") heaps are under ID
ION_HEAP_TYPE_CUSTOM + 1 (legacy 'secure heap type' value).Signed-off-by: Etienne Carriere
Reviewed-by: Joakim Bech
(cherry picked from commit e31dd54997b050b6a6965d7cfbc795492256847c
linaro repo https://github.com/linaro-swg/linux.git
tag optee-v4.9-20171005)(cherry picked from commit 63160a1b0ac4e482ba9369614f225956cfd96af7)
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For some cases (like AMIX) pinctrl may be null - this
breaks SAI functionality. Enforce pinctrl null pointer
checking prior calling any function which involves
pins state changes.Signed-off-by: Viorel Suman
(cherry picked from commit 76b745dc501835e938d7ec6d81942568a27872a4) -
Add a dedicated DSD512 pinmux group for DSD512 in order
to eliminate the noise caused by a hight MCLK rate.
With the new option the SAI1 BCLK is routed to codec MCLK pin.Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com
(cherry picked from commit f9c65f44d0e7da0e5a59dae9434dc0d70cf2039b) -
Replace DSD related code with calls to DSD helper functions.
Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com
(cherry picked from commit d2af0ee812d563db7b9cc21c12b7670605d6e2f4) -
Add DSD utilities helper.
Signed-off-by: Viorel Suman
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com
(cherry picked from commit 2fd2577e7565b76365db60366949d9f20a721a4b) -
With the current multipliers SAI isn't able to derive a correct bitclk.
e.g: When playing at 786Khz with current multiplier
MCLK = 22579200, requested freq 22579200 but SAI wants:
MCLK = (DIV + 1) * 2 * freq [SAI TCR2], so an acceptable solution
is to add a 2x factor to mclk.Signed-off-by: Viorel Suman
(cherry picked from commit 74168d9e1e02d27d1f737c146d7909601049f197)
10 Mar, 2018
2 commits
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The iMX8 QX and QM have SECO/SCU enabled and the access
to SM registers is different as long as the addresses of
the pages.Signed-off-by: Franck LENORMAND
(cherry picked from commit b4f1f3761d6e40996a19e4e6d26d7483d2f1661f) -
We enable the SM keystore and its test by default to be
tested at the boot of the kernel.Signed-off-by: Franck LENORMAND
(cherry picked from commit a32bfdc010dfbdce35a065c0ede19296f4523d7d)
09 Mar, 2018
8 commits
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This commit allows one to select if a firmware file is used, for loading
the HDR10 tables, or a header. By default, this will be header file.
This is until a proper way of passing the file from bootloader is found.Also, fix a minor bug which made parsing the tables over the actual data
limit.Signed-off-by: Laurentiu Palcu
(cherry picked from commit 825755bb599fba99e8ed16caa3738b8f66c3448d) -
This commit adds HDR10 tables as a header. Using a FW file is
problematic since the tables need to be available immediately after
boot. After the rootfs is mounted, as is the case for loading a FW file,
it's already too late if some conversion tables are needed.This usually happens if the output pipe is configured as YUV420.
Signed-off-by: Laurentiu Palcu
(cherry picked from commit dfb6fa2943119c2b371809f3b3b0463dc4ada3de) -
Fix bug when PDN gpio is requested instead of mute gpio.
Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Daniel Baluta
(cherry picked from commit 9705bdb54a1eec7e7ecffcddc668674d5f233ed4) -
It is better to clear wakeup flag in status register before enable
wakeup interrupt bits, which can avoid system suspend fail during
devices no irq suspend stage.Reviewed-by: Gao Pan
Signed-off-by: Fugang Duan
(cherry picked from commit e8e3a042847f7ca3b24103fdc7647f231a0b3cbf) -
Fix the cherry pick and merge issue by below commit on kernel 4.9:
Fixes: 19b76fd012ce ("net: fec: add stop mode support for dts register set")Reviewed-by: Gao Pan
Signed-off-by: Fugang Duan
(cherry picked from commit f8e7532ae5c120c1ff8b827595c72fffcd447c2e) -
Using TDM256 mode (our only supported mode) in order to
support 192KHz we would need a MCLK of 192000 * 512 = 98304000.But maximum frequency supported by the Audio PLL is 4.91 MHz.
Reviewed-by: Shengjiu Wang
Signed-off-by: Daniel Baluta
(cherry picked from commit 11aa41d02e69e6f23b28f0df4c74194703cb720b) -
In order for TDM to correctly work we need that MCLK and
BCLK to follow the values in Table 9.Thus,
* TDM128: BCLK = 128fs, MCLK = 128-1024fs
* TDM256: BCLK = 256fs, MCLK = 256-1024fs
* TDM512: BCLK = 512fs, MCLK = 512-1024fsWe assume only support TDM256 for the moment.
Reviewed-by: Shengjiu Wang
Signed-off-by: Daniel Baluta
(cherry picked from commit 63d9fd2177a0199f0565091a8e64126d411a8717) -
The commit:
44c45128 - MLK-17634-1: drm: imx: dcss: send vblank event from ISR
made some changes related to vblank handling. However, it looks like
they were not robust enough and, sometimes, the flip events are not
sent. This happens only when playing videos over Weston.This patch, effectively, reverts those changes.
Signed-off-by: Laurentiu Palcu
(cherry picked from commit 1319160b42390947864eb01e8385ea8e80087288)
08 Mar, 2018
5 commits
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Currently, the default clock configuration for DCSS configures the pixel
clock to be sourced from VIDEO_PLL2, but this source cannot be used by the
DSI PHY_REF clock.
So, in order to make DCSS working with DSI, we need to have them both
(DCSS and DSI PHY) use the same clock source: VIDEO_PLL1.Signed-off-by: Robert Chiras
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Currently, the default clock configuration for DCSS configures the pixel
clock to be sourced from VIDEO_PLL2, but this source cannot be used by
the DSI PHY_REF clock.
So, in order to make DCSS working with DSI, we need to have them both
(DCSS and DSI PHY) use the same clock source: VIDEO_PLL1.Signed-off-by: Robert Chiras
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Fix the clock source selection for MIPI use-case.
Signed-off-by: Robert Chiras
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According to CEA-861-E section 6.6.2, add channel/speaker
allocation configuration for 4 channel.
0x0: FL, FR
0x3: FL, FR, LFE, FC
0x1F:FL, FR, LFE, FC, RL, RR, FLC, FRCSigned-off-by: Shengjiu Wang
Reviewed-by: Sandor Yu
(cherry picked from commit 0b4e6f2d6377c34c18a382c13913a5c96c8a18e8) -
There is channel swapping issue for 4 channel and 8 channel audio.
After dump the register, found that SMPL2PKT_CNFG is not set
correctly, the reason is that F_NUM_OF_I2S_PORTS should be
F_NUM_OF_I2S_PORTS_S.Signed-off-by: Shengjiu Wang
Reviewed-by: Sandor Yu
(cherry picked from commit 0bb30f24474dfce7f4ad70343f5f39a645e4b407)
07 Mar, 2018
1 commit
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We cannot both derive SAI BCLK for 384KHz-S32/768KHz-S16 and
respect the codec MCLK restrictions shown in AK4458 datasheet
Table 5, 6 and 7.
Since we can have same master clock for SAI and Codec in Manual
Mode, we've chosen to use it instead of Auto Mode.Signed-off-by: Cosmin-Gabriel Samoila
Reviewed-by: Shengjiu Wang
(cherry picked from commit 46a1f17da003feb8bcac6b3b1d1c24a84c988c06)