24 Apr, 2018
1 commit
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commit 89cd7aec21af26fd0c117bfc4bfc781724f201de upstream.
The clock for which all PWM devices on MT7623 or MT2701 actually depending
on has to be divided by four from its parent clock axi_sel in the clock
path prior to PWM devices.Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of
clock axi_sel allows that PWM devices can have the correct resolution
calculation.Cc: stable@vger.kernel.org
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Sean Wang
Signed-off-by: Stephen Boyd
Signed-off-by: Greg Kroah-Hartman
20 Dec, 2017
1 commit
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[ Upstream commit c955bf3998efa3355790a4d8c82874582f1bc727 ]
Since the previous setup always sets the PLL using crystal 26MHz, this
doesn't always happen in every MediaTek platform. So the patch added
flexibility for assigning extra member for determining the PLL source
clock.Signed-off-by: Chen Zhong
Signed-off-by: Sean Wang
Signed-off-by: Stephen Boyd
Signed-off-by: Sasha Levin
Signed-off-by: Greg Kroah-Hartman
02 Nov, 2017
1 commit
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Many source files in the tree are missing licensing information, which
makes it harder for compliance tools to determine the correct license.By default all files without license information are under the default
license of the kernel, which is GPL version 2.Update the files which contain no license information with the 'GPL-2.0'
SPDX license identifier. The SPDX identifier is a legally binding
shorthand, which can be used instead of the full boiler plate text.This patch is based on work done by Thomas Gleixner and Kate Stewart and
Philippe Ombredanne.How this work was done:
Patches were generated and checked against linux-4.14-rc6 for a subset of
the use cases:
- file had no licensing information it it.
- file was a */uapi/* one with no licensing information in it,
- file was a */uapi/* one with existing licensing information,Further patches will be generated in subsequent months to fix up cases
where non-standard license headers were used, and references to license
had to be inferred by heuristics based on keywords.The analysis to determine which SPDX License Identifier to be applied to
a file was done in a spreadsheet of side by side results from of the
output of two independent scanners (ScanCode & Windriver) producing SPDX
tag:value files created by Philippe Ombredanne. Philippe prepared the
base worksheet, and did an initial spot review of a few 1000 files.The 4.13 kernel was the starting point of the analysis with 60,537 files
assessed. Kate Stewart did a file by file comparison of the scanner
results in the spreadsheet to determine which SPDX license identifier(s)
to be applied to the file. She confirmed any determination that was not
immediately clear with lawyers working with the Linux Foundation.Criteria used to select files for SPDX license identifier tagging was:
- Files considered eligible had to be source code files.
- Make and config files were included as candidates if they contained >5
lines of source
- File already had some variant of a license header in it (even if
Reviewed-by: Philippe Ombredanne
Reviewed-by: Thomas Gleixner
Signed-off-by: Greg Kroah-Hartman
22 Jul, 2017
1 commit
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Now that we have a custom printf format specifier, convert users of
full_name to use %pOF instead. This is preparation to remove storing
of the full path string for each node.Signed-off-by: Rob Herring
Cc: Michael Turquette
Cc: Stephen Boyd
Cc: Maxime Coquelin
Cc: Alexandre Torgue
Cc: Russell King
Cc: Matthias Brugger
Cc: Geert Uytterhoeven
Cc: Maxime Ripard
Cc: Chen-Yu Tsai
Cc: "Emilio López"
Cc: Peter De Schrijver
Cc: Prashant Gaikwad
Cc: Thierry Reding
Cc: Jonathan Hunter
Cc: Tero Kristo
Cc: linux-clk@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mediatek@lists.infradead.org
Cc: linux-renesas-soc@vger.kernel.org
Cc: linux-tegra@vger.kernel.org
Cc: linux-omap@vger.kernel.org
Acked-by: Maxime Ripard
Reviewed-by: Geert Uytterhoeven
Acked-by: Geert Uytterhoeven
Acked-by: James Liao
Acked-by: Alexandre TORGUE
Reviewed-by: Matthias Brugger
Signed-off-by: Stephen Boyd
18 Jul, 2017
1 commit
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Fixed the signedness bug returning '(-22)' on the return type as u8 with
removing the sanity checker in clk_cpumux_get_parent() since
clk_cpumux_set_parent() always ensures validity in clk_cpumux_get_parent()
got called.Fixes: 1e17de9049da ("clk: mediatek: add missing cpu mux causing Mediatek cpufreq can't work")
Reported-by: Dan Carpenter
Signed-off-by: Sean Wang
Signed-off-by: Stephen Boyd
20 Jun, 2017
3 commits
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The patch enables CPU multiplexer clock on MT8173 SoC which fixes up
cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.Signed-off-by: Pi-Cheng Chen
Signed-off-by: Sean Wang
Signed-off-by: Stephen Boyd -
The patch enables CPU multiplexer clock on MT2701/MT7623 SoC which fixes
up cpufreq driver fails at acquiring intermediate clock source when driver
probe is called.Signed-off-by: Pi-Cheng Chen
Signed-off-by: Sean Wang
Signed-off-by: Stephen Boyd -
This patch adds CPU multiplexer clocks which are essential for Mediatek
cpufreq driver. It would use the CPU clock multiplexer to switch to the
intermediate clock source temporarily and then wait for the primary clock
changing getting stable.Signed-off-by: Pi-Cheng Chen
Signed-off-by: Sean Wang
Signed-off-by: Stephen Boyd
22 Apr, 2017
1 commit
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The ethernet clock core has a reset register that is currently not exposed
to the user. Fix this by adding the missing registration code.Signed-off-by: John Crispin
Signed-off-by: Stephen Boyd
20 Apr, 2017
1 commit
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Add MT6797 clock support, include topckgen, apmixedsys, infracfg
and subsystem clocksSigned-off-by: Kevin-CW Chen
Signed-off-by: Mars Cheng
Tested-by: Matthias Brugger
Signed-off-by: Stephen Boyd
27 Jan, 2017
2 commits
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The MT8135 is a 32-bit SoC, so only propose it on ARM architecture,
not ARM64.Signed-off-by: Jean Delvare
Fixes: 234d511d8c15 ("clk: mediatek: Add hardware dependency")
Cc: Andreas Färber
Acked-by: James Liao
Reviewed-by: Matthias Brugger
Signed-off-by: Stephen Boyd -
If I say "no" to "Clock driver for Mediatek MT2701", I don't want to
be asked individually about each sub-driver. No means no.Additionally, this driver shouldn't be proposed at all on non-mediatek
builds, unless build-testing.Signed-off-by: Jean Delvare
Fixes: e9862118272a ("clk: mediatek: Add MT2701 clock support")
Reviewed-by: Andreas Färber
Reviewed-by: James Liao
Cc: Shunli Wang
Cc: Erin Lo
Cc: Michael Turquette
Reviewed-by: Matthias Brugger
Signed-off-by: Stephen Boyd
09 Nov, 2016
2 commits
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In infrasys and perifsys, there are many reset
control bits for kinds of modules. These bits are
used as actual reset controllers to be registered
into kernel's generic reset controller framework.Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Signed-off-by: Erin Lo
Tested-by: John Crispin
Acked-by: Philipp Zabel
Signed-off-by: Stephen Boyd -
Add MT2701 clock support, include topckgen, apmixedsys,
infracfg, pericfg and subsystem clocks.Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Signed-off-by: Erin Lo
Tested-by: John Crispin
Signed-off-by: Stephen Boyd
18 Oct, 2016
1 commit
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Only propose the mediatek clock drivers on this platform, unless
build-testing.Signed-off-by: Jean Delvare
Cc: Shunli Wang
Cc: James Liao
Cc: Erin Lo
Cc: Matthias Brugger
Cc: Michael Turquette
Reviewed-by: Matthias Brugger
Signed-off-by: Stephen Boyd
21 Sep, 2016
1 commit
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Free memory mapping if init is not successful.
Signed-off-by: Arvind Yadav
Reviewed-by: James Liao
Signed-off-by: Stephen Boyd
20 Aug, 2016
1 commit
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Add a Kconfig to define clock configuration for each SoC, and
modify the Makefile to build drivers that only selected in config.Signed-off-by: Shunli Wang
Signed-off-by: James Liao
Signed-off-by: Erin Lo
Tested-by: John Crispin
Reviewed-by: Matthias Brugger
Signed-off-by: Stephen Boyd
19 Aug, 2016
1 commit
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Remove __init from functions that will be used by init functions
that support probe deferral.Signed-off-by: James Liao
Signed-off-by: Erin Lo
Signed-off-by: Stephen Boyd
06 May, 2016
3 commits
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The hdmitx_dig_cts clock signal is not a child of tvdpll_445p5m,
but is routed out of the HDMI PHY module.Signed-off-by: Philipp Zabel
Acked-by: Stephen Boyd -
The configurable hdmi_ref output of the PLL block is derived from
the tvdpll_594m clock signal via a configurable PLL post-divider.
It is used as the PLL reference input to the HDMI PHY module.Signed-off-by: Philipp Zabel
Acked-by: James Liao
Acked-by: Stephen Boyd -
This mux is supposed to select a fitting divider after the PLL
is already set to the correct rate.Signed-off-by: Philipp Zabel
Acked-by: James Liao
Acked-by: Stephen Boyd
30 Mar, 2016
1 commit
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The mtk_reset_ops structure is never modified. Make it const.
Signed-off-by: Philipp Zabel
Reviewed-by: Matthias Brugger
Signed-off-by: Stephen Boyd
03 Mar, 2016
1 commit
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This flag is a no-op now. Remove usage of the flag.
Acked-by: James Liao
Signed-off-by: Stephen Boyd
30 Jan, 2016
2 commits
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mtk_clk_register_composite() may leak memory due to some error
handling path don't free all allocated memory. This patch
free all pointers that may allocate memory before error return.
And it's safe because kfree() can handle NULL pointers.Signed-off-by: James Liao
Reviewed-by: Daniel Kurtz
Signed-off-by: Stephen Boyd -
to_clk_*(_hw) macros have been repeatedly defined in many places.
This patch moves all the to_clk_*(_hw) definitions in the common
clock framework to public header clk-provider.h, and drop the local
definitions.Signed-off-by: Geliang Tang
Signed-off-by: Stephen Boyd
01 Oct, 2015
8 commits
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Add REF2USB_TX clock support into MT8173 APMIXEDSYS. This clock
is needed by USB 3.0.Signed-off-by: James Liao
Reviewed-by: Daniel Kurtz -
Most multimedia subsystem clocks will be accessed by multiple
drivers, so it's a better way to manage these clocks in CCF.
This patch adds clock support for MM, IMG, VDEC, VENC and VENC_LT
subsystems.Signed-off-by: James Liao
Reviewed-by: Daniel Kurtz -
Remove the dependency from clk_null, and give all root clocks a
typical rate, include clkph_mck_o, usb_syspll_125m and hdmitx_dig_cts.dpi_ck was removed due to no clock reference to it.
Replace parent clock of infra_cpum with cpum_ck, which is an external
clock and can be defined in the device tree.Signed-off-by: James Liao
Reviewed-by: Daniel Kurtz -
This patch adds fixed clocks support by using CCF fixed-rate
clock implementation.Signed-off-by: James Liao
Reviewed-by: Daniel Kurtz -
Add __init for clock registration functions, and add __initdata for
mtk_gate_regs initial structures.Signed-off-by: James Liao
Reviewed-by: Daniel Kurtz -
Remove unused header files from MT8173, and remove unused
keywords from function declaration.Signed-off-by: James Liao
Reviewed-by: Daniel Kurtz -
The dpi_ck clock can be removed because it not actually used
in topckgen and subsystems.Signed-off-by: James Liao
Reviewed-by: Daniel Kurtz -
Add 13mhz clock used by GPT timer in infracfg.
Signed-off-by: Yingjoe Chen
Acked-by: Stephen Boyd
Signed-off-by: James Liao
29 Jul, 2015
4 commits
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* cleanup-clk-h-includes: (62 commits)
clk: Remove clk.h from clk-provider.h
clk: h8300: Remove clk.h and clkdev.h includes
clk: at91: Include clk.h and slab.h
clk: ti: Switch clk-provider.h include to clk.h
clk: pistachio: Include clk.h
clk: ingenic: Include clk.h
clk: si570: Include clk.h
clk: moxart: Include clk.h
clk: cdce925: Include clk.h
clk: Include clk.h in clk.c
clk: zynq: Include clk.h
clk: ti: Include clk.h
clk: sunxi: Include clk.h and remove unused clkdev.h includes
clk: st: Include clk.h
clk: qcom: Include clk.h
clk: highbank: Include clk.h
clk: bcm: Include clk.h
clk: versatile: Remove clk.h and clkdev.h includes
clk: ux500: Remove clk.h and clkdev.h includes
clk: tegra: Properly include clk.h
... -
MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting by adding
div-rate table to lookup suitable post divider setting under a
specified frequency.Signed-off-by: James Liao
Acked-by: Sascha Hauer
Signed-off-by: Stephen Boyd -
Avoid u32 overflow when calculate post divider setting, and
increase the max post divider setting from 3 (/8) to 4 (/16).Signed-off-by: James Liao
Acked-by: Sascha Hauer
Signed-off-by: Stephen Boyd -
Write postdiv and pcw settings at the same time for PLLs if postdiv
and pcw settings are on the same register.This is need by PLLs such as MT8173 MMPLL and ARM*PLL.
Signed-off-by: James Liao
Acked-by: Sascha Hauer
Signed-off-by: Stephen Boyd
21 Jul, 2015
1 commit
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We don't need to include clk.h in header files, just forward
declare struct clk here. This leads us to a few places where the
include of clk.h was missing in C files. Add them.Cc: James Liao
Cc: Henry Chen
Cc: Sascha Hauer
Signed-off-by: Stephen Boyd
07 Jul, 2015
1 commit
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On the MT8173 the clocks are provided by different units. To enable
the critical clocks we must be sure that all parent clocks are already
registered, otherwise the parents of the critical clocks end up being
unused and get disabled later. To find a place where all parents are
registered we try each time after we've registered some clocks if
all known providers are present now and only then we enable the critical
clocksSigned-off-by: Sascha Hauer
Signed-off-by: James Liao
[sboyd@codeaurora.org: Marked function and data __init]
Signed-off-by: Stephen Boyd
05 Jun, 2015
1 commit
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The size of clk_data should be the same as CLK_APMIXED_NR_CLK
instead of ARRAY_SIZE(plls). CLK_APMIXED_* is numbered from 1, so
CLK_APMIXED_NR_CLK will be greater than ARRAY_SIZE(plls).Signed-off-by: James Liao
Acked-by: Sascha Hauer
Signed-off-by: Stephen Boyd