25 Nov, 2019
1 commit
10 Apr, 2019
1 commit
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We should assign dedicated id for every tcon instance.
This makes us be able to figure out bewteen master and
slave tcon. Only side-by-side display mode is likely
impacted. Based on tests, no functional change is
observed before or after this patch is applied.Signed-off-by: Liu Ying
(cherry picked from commit e181d9e56b096bbdc919f65b223d1bde413df1bb)
27 Mar, 2019
1 commit
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Double check that the DTG IRQ STATUS register bit is set when handling
the vblank and CTXLD kick interrupts to make sure we avoid spurious
interrupts and kick the CTXLD in a bad moment.Signed-off-by: Laurentiu Palcu
Reviewed-by: Robert Chiras
(cherry picked from commit cc56e4e07f623d0b831e0f8347f2f3198697ee20)
22 Mar, 2019
1 commit
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Another coming patch will wait for framegen secondary channel syncup
for non-sync mode cases. It appears that waiting for 50ms for video
modes like 1920x1080p@24 and 1920x1080p@30 is not enough. So, this
patch increases the timeout value to 100ms.Signed-off-by: Liu Ying
(cherry picked from commit 5357bce465db659d69a5026882a899f2077ee078)
14 Mar, 2019
1 commit
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Change the log message to report "difference is" instead of "error is" to
avoid confusion. This message is just reports the actual pixel clock for
informational purposes. It is not an actual error.Signed-off-by: Oliver Brown
21 Feb, 2019
1 commit
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When do dpu blit and wait to finish, it will call usleep_range(10, 20)
to poll register state. Change to usleep_range(30, 50) to low down CPU loading.Change-Id: If84c436b31d228b8b7a2a41e89611d354270baba
Signed-off-by: Ivan.liu
19 Feb, 2019
1 commit
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The following commit:
459a5fac54d - MLK-20263: drm/imx/dcss: fix channel-0 line shift
removed the 5 tap filter for vertical luma/chroma when YUV formats were
used.Problem is that when the 7 tap filter is used for vertical luma/chroma,
artifacts can be seen on screen when scaling.RGB can, however, function correctly with only 7 tap filter.
This patch partially reverts the above patch and also does some cosmetic
changes when calling the dcss_scaler_filter_design() using false/true
instead of 0/1 for use_5_taps argument.Signed-off-by: Laurentiu Palcu
12 Feb, 2019
33 commits
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Implement mode_valid and mode_fixup functions for the dcss-crtc
driver so that DCSS can filter-out unsupported modes and save the
configuration for the supported ones.
Use mode_fixup to apply the saved configuration of a supported mode.
The mechanism to determine if a mode is supported or not is made in
dcss-dtg.Also, add 2 new clocks:
- pll: this is the video PLL that provides the pixel clock; it's rate
needs to be set such that the pixel clock can be achieved
- pll_src*: this is an oscillator that can be used as source clock for
the video pll; currently, there are possible maximum 3 pll sources,
defined as pll_src1, pll_src2 and pll_src3. The actual clocks that
can be used as pll source are: CLK_25M, CLK_27M and CLK_PHY_27MHZRemoved the pdiv_clk and pout_clk and replaced them with pix_clk,
since out of those two only one was used: pdiv_clk, representing the pixel
clock.In dcss-dtg, each mode is tested and if we can achieve it's pixel
clock we save this mode configuration into an internal list and apply this
configuration later on when mode_fixup is called.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
To avoid potential missing braces when initializing tmp_m, this patch
caches h/vdisplay, h/vsync_start and h/vsync_end locally in function
tcon_cfg_videomode() instead of declaring and initializing the local
variable tmp_m.Code change only, no functional impact.
Reported-by: Anson Huang
Signed-off-by: Liu Ying -
The clock referenece for the video pll 2 needs to be changed at runtime.
The HDMI/DP PHY reference clock is not available during module initialization
so the reference clock should be changed when the mode is set.Signed-off-by: Oliver Brown
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This patch adds two helpers to get and clear FrameGen secondary channel
status respectively. Via the two helpers, users may know if there is
empty FIFO read request on this channel or not after getting the status.
And, if yes, users may choose to clear the status. According to the IP
spec, the empty FIFO read request indicates that data stream from a Fetch
unit(e.g., AXI bandwidth not sufficient) fell down. Assuming the display
driver sets things up properly, the falling down is very likely caused by
the insufficient AXI bandwidth, that is, display underrun.Signed-off-by: Liu Ying
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Now that there is a generic SCCG clock added, it can also
be used by the DCSS. The HDMI_PHY_27M_CLK ref sel is hardcoded as parent
to VIDEO_PLL2 in dts.Signed-off-by: Abel Vesa
Reviewed-by: Laurentiu Palcu -
Nonzero CROP_ULC_X/Y are only valid for tile framebuffer cropping.
Thus, we should set them to be zero for linear framebuffer, otherwise,
an on-the-fly switch from tile framebuffer(with cropping enabled) to
linear framebuffer would cause hardware malfunction.Signed-off-by: Liu Ying
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This fixes Coverity issue since enable is always true.
Signed-off-by: Laurentiu Palcu
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This addresses Coverity issues related to "Suspicious sign extension"
when an u16 is promoted to int (32bit signed) and then to u64. If the
resulting int is greater than 0x7fffffff the upper bits of the u64 will
all be 1.Signed-off-by: Laurentiu Palcu
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The video mode tmp_m, as a local variable in tcon_cfg_videomode(),
is uninitialized and used to store a copy instance from the real
video mode. tcon_cfg_videomode() would change the timing of it if
side_by_side mode is enabled. Theoretically, there should be no
problem even if we don't initialize tmp_m. However, coverity
reports that tmp_m is an uninitialized scalar variable when the copy
is being done(CID 5233067: Uninitialized scalar variable (UNINIT)).
This patch fixes the issue reported by coverity.Signed-off-by: Liu Ying
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The logic in function h/vscaler_pixengcfg_dynamic_src_sel() to avoid
overrunning array src_sel[i][j] is wrong. The correct one is to check
on the index i which should be less than the array size of h/vs_id_array[].
This patch fixes the potential array overrunning issue, that is,
out-of-bounds array read issue. The issue is reported by coverity -
CID 1477349 and CID 1477345.Signed-off-by: Liu Ying
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The callers of dpu_{unit}_init() might provide an invalid id as
the parameter, it may cause overrunning dpu->{unit}_priv[] and
cf_shdlreqs[] arrays and out-of-bound array access. Although
the current only caller is dpu_submodules_init() and it always
provides valid ids, it would be good to fix the potential issue.
This patch fixes several issues reported by coverity - CID 1477330,
CID 1477335, CID 1477348, CID 1477346, CID 3298619, CID 1477347,
CID 5233021 and CID 1477321.Signed-off-by: Liu Ying
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The function get_xval() returns the C_XVAL and L_XVAL fields of
the CURPIXELCNT and LASTPIXELCNT registers. They are 16bit and
sit in the low 16bit of the registers. This patch fixes the way
we mask the register and read the fields out.Signed-off-by: Liu Ying
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The layerblend units don't contain the CONTROLWORD, CURPIXELCNT,
LASTPIXELCNT and PERFCOUNTER registers, so let's remove them
and their wrappers(no one is calling them), which were introduced
accidentally.Signed-off-by: Liu Ying
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If an RGB buffer is fed to channel-0, the output will have one line
shifted down, with the last line appearing on top.Using the 7-tap filter will fix the issue. The 5-tap filter code will be
removed completely.Signed-off-by: Dzung Hoang
Signed-off-by: Laurentiu Palcu -
The brightness, when REC709 was used in the configuration of the pipes,
was lower than expected.The reason was the HDR10 configuration application that was used to
create the tables had a parameter that was wrongly set.The tables were re-generated with the proper setting.
Signed-off-by: Laurentiu Palcu
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After activating CONFIG_DEBUG_SPINLOCK, the following warning was thrown
in kernel log:[ 1.261079] BUG: spinlock bad magic on CPU#0, kworker/0:2/1285
[ 1.266928] lock: 0xffff8000b92f0190, .magic: 00000000, .owner: /-1, .owner_cpu: 0
[ 1.275113] CPU: 0 PID: 1285 Comm: kworker/0:2 Not tainted 4.14.62-05296-gd695a5b #460
[ 1.283032] Hardware name: Freescale i.MX8MQ EVK (DT)
[ 1.288094] Workqueue: pm pm_runtime_work
[ 1.292111] Call trace:
[ 1.294567] [] dump_backtrace+0x0/0x3d8
[ 1.299974] [] show_stack+0x14/0x20
[ 1.305032] [] dump_stack+0x8c/0xac
[ 1.310091] [] spin_dump+0x70/0x90
[ 1.315060] [] do_raw_spin_lock+0xc0/0x108
[ 1.320726] [] _raw_spin_lock_irqsave+0x28/0x38
[ 1.326825] [] dcss_ctxld_kick+0x2c/0x200
[ 1.332402] [] dcss_ctxld_suspend+0x1c/0xa0
[ 1.338153] [] dcss_runtime_suspend+0x18/0x68
[ 1.344079] [] pm_generic_runtime_suspend+0x28/0x40
[ 1.350523] [] __rpm_callback+0xe0/0x268
[ 1.356015] [] rpm_callback+0x20/0x80
[ 1.361246] [] rpm_suspend+0xf4/0x4b8
[ 1.366474] [] rpm_idle+0x124/0x168
[ 1.371531] [] pm_runtime_work+0xa0/0xb8
[ 1.377025] [] process_one_work+0x1d4/0x360
[ 1.382774] [] worker_thread+0x48/0x478
[ 1.388180] [] kthread+0x138/0x140
[ 1.393151] [] ret_from_fork+0x10/0x18The reason was an uninitialized spinlock.
Signed-off-by: Laurentiu Palcu
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Activating CONFIG_SLEEP_ATOMIC_SLEEP detected a couple of potential sleeps
inside IRQ context:[ 23.609203] BUG: sleeping function called from invalid context at kernel/irq/manage.c:112
[ 23.617437] in_atomic(): 1, irqs_disabled(): 128, pid: 0, name: swapper/2
[ 23.624229] CPU: 2 PID: 0 Comm: swapper/2 Tainted: G W 4.14.62-05295-gf2fa7e6 #454
[ 23.632927] Hardware name: Freescale i.MX8MQ EVK (DT)
[ 23.637980] Call trace:
[ 23.640433] [] dump_backtrace+0x0/0x3d8
[ 23.645834] [] show_stack+0x14/0x20
[ 23.650891] [] dump_stack+0x9c/0xbc
[ 23.655946] [] ___might_sleep+0xf4/0x118
[ 23.661433] [] __might_sleep+0x50/0x88
[ 23.666750] [] synchronize_irq+0x30/0x98
[ 23.672237] [] disable_irq+0x20/0x30
[ 23.677378] [] dcss_dpr_irq_enable+0x78/0x98
[ 23.683211] [] dcss_dtg_vblank_irq_enable+0x40/0x78
[ 23.689652] [] dcss_vblank_irq_enable+0xc/0x18
[ 23.695661] [] dcss_disable_vblank+0x30/0x50
[ 23.701496] [] drm_vblank_disable_and_save+0xd4/0xe8
[ 23.708023] [] vblank_disable_fn+0x88/0xa8
[ 23.713685] [] call_timer_fn.isra.5+0x24/0x80
[ 23.719603] [] expire_timers+0xa4/0xb0
[ 23.724914] [] run_timer_softirq+0xb8/0x170
[ 23.730660] [] __do_softirq+0x12c/0x228
[ 23.736062] [] irq_exit+0xc4/0x100
[ 23.741025] [] __handle_domain_irq+0x60/0xb8
[ 23.746857] [] gic_handle_irq+0x78/0x17cThese sleep warnings were generated because disable_irq() may sleep. Use
disable_irq_nosync() instead.Signed-off-by: Laurentiu Palcu
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For channel 0 if 1920x1080@NV12 was used when setting a mode would
freeze the scaler. That's because the chroma vertical size was set to
540 (1920 / 2) instead of 544 (which is divisible to 8).This patch makes sure we round up the chroma vertical size for channel-0
properly.Signed-off-by: Laurentiu Palcu
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When the VIDEO_PLL2 clock code was moved to the DCSS driver, a
regression was introduced and any mode requiring a 27MHz pixel clock
would instantly freeze the platform.It turns out, after setting the clocks in bypass mode, PLL_CLKE was
never set. Hence, DCSS was not getting any clock. Without a valid clock,
any attempt to access DTG registers will freeze the system.This patch:
* sets PLL_CLKE when bypass is used;
* simplifies the pll code a little;
* increases the atomic CRTC enable timeout to 500ms to accommodate the
delay after which the clock is available when bypass is used;Signed-off-by: Laurentiu Palcu
CC: Oliver Brown -
RTRM clock reference was saved in apb_clk, instead of rtrm_clk. Hence,
when blanking and clocks go off, APB clock counter was 2, instead of 1.Because IRQ_STEER controller uses APB clock as well, the APB clock ref
counter will never go to 0. Unless DCSS is never used.Signed-off-by: Laurentiu Palcu
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After PM_QoS was removed by this commit:
f889273 - MLK-19460-2: drm: imx: dcss: remove PM_QoS
interrupt latency increased. Hence, any video playback using tiled
compressed formats will be affected because DTRC uses CTXLD to switch
its register banks. If CTXLD is not armed, at the right time, the DB
trigger moment will be missed. This leads to DTRC not switch to the other
register bank and scaler will be starved, leading to a channel freeze.This patch will lower the CTXLD trigger time to 90% of frame trace
allowing some more time between arming the context loader and DB trigger
time, in case the latency is too big.Signed-off-by: Laurentiu Palcu
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Pixel combiner uses two display streams to drive one single display.
Either one of the two streams can be master stream and the other
slave stream. If we use stream0 as the master stream, the overlay
covers the two streams could be unsynchronized sometimes. It looks
like there is one frame lag between the two streams. However, it
turns out that using stream1 as the master stream can workaround
this issue.Signed-off-by: Liu Ying
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Pixel combiner uses two display streams to drive a single display.
Either of the two display streams can be master stream and the
other slave stream. This patch supports auxiliary stream as master
stream when pixel combiner is used. The master stream ID can be
specified via the newly introduced entry 'master_stream_id' in the
device type of the DPU(s) in a particular SoC.Signed-off-by: Liu Ying
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According to pixel combiner spec, there is a clock mux before
the display clock input of stream1 to choose the clock from
disp1 clock(only for stream1) or disp0 clock(usually for stream0).
So, we should enable disp0 clock when pixel combiner is used
instead of enabling the display clock of master stream.Signed-off-by: Liu Ying
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While running suspend/resume tests it may happen to go to suspend while
CTXLD still has entries to be commited. Currently, when this happens,
the scaler freezes.This patch will fire up context loader just before going to suspend,
thus commiting everything to DCSS before cutting off the clocks.Signed-off-by: Laurentiu Palcu
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Store9 unit can be shared bewteen display engine(for sync mode fixup)
and blit engine. It's proper to get the store resource in the DPU
common driver and then pass it to relevant client drivers. From the
CRTC driver point of view, it's straightforward to get the store
resource via platform data instead of getting it directly, which avoids
the wrong situation where getting it twice(one time for one of the two
CRTCs of one DPU, respectively).Signed-off-by: Liu Ying
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The driver creates constant objects with the type of struct dpu_devtype,
so it's unnecessary to use const modifiers for those non-pointer entries.Signed-off-by: Liu Ying
-
retry logic cause high cpu load for multiple instances,
should use simple mutex to sync dpu blitter directly.Signed-off-by: Xianzhong
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video playback cause system hang with Wayland g2d compositor,
this also can be reproduced with Android G2D HWComposer.the problem is second prg not handled between GPU and video.
need re-enable dprc & prg pipes when modifier changed.Signed-off-by: Xianzhong
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This patch improves FrameGen kick and TCON kachuck signal configurations
as recommended by SoC designer. This should achieve more stability
and safety to set up a display pipeline and load prefetch engine shadow
registers.Signed-off-by: Liu Ying
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Moving video pll2 control to the display driver to allow more flexibility
for setting rates.Signed-off-by: Oliver Brown
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Currently, when enabling/disabling vblank interrupt, we also
enable/disable the CTXLD kick interrupt. Most of the time this is fine,
because when vblank gets disabled user-space does not submit any buffers
and CTXLD kick interrupt is not needed.There is one case when we actually need to be able to have the CTXLD
kick interrupt enabled: when disabling CRTC. Vblank interrupt, in this
case, is disabled before the crtc_atomic_disable routine is called.
However, we still need CTXLD to push the changes to SUBSAM and DTG.This patch will create a routine just for enabling/disabling CTXLD kick
interrupt and move the code from vblank routine to the new one.Signed-off-by: Laurentiu Palcu
-
prg_reg_update has kernel panic when play amphion video on 8qm:
[ 161.606147] Hardware name: Freescale i.MX8QM MEK (DT)
[ 161.611195] task: ffff8008f3585100 task.stack: ffff00000a738000
[ 161.617112] PC is at prg_reg_update+0x20/0x28
[ 161.621464] LR is at dprc_reg_update+0x38/0x58configure and enable second prg in dprc configuration.
Signed-off-by: Xianzhong
Signed-off-by: Liu Ying
