12 Feb, 2019
1 commit
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perf stat -a -e ddr0/cycles/,ddr0/read-bytes/,ddr0/write-bytes/,ddr1/cycles/,d
dr1/read-bytes/,ddr1/write-bytes/ dd if=/dev/zero of=/dev/null bs=10M count=1
1+0 records in
1+0 records outPerformance counter stats for 'system wide':
7236174 ddr0/cycles/ (99.97%)
8573 ddr0/read-bytes/ (99.99%)
163628 ddr0/write-bytes/
7256543 ddr1/cycles/ (99.99%)
9308 ddr1/read-bytes/ (100.00%)
165039 ddr1/write-bytes/0.008990125 seconds time elapsed
Signed-off-by: Frank Li
Signed-off-by: Tiberiu Breana
15 Jun, 2017
1 commit
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All PMU drivers are going to depend on PERF_EVENTS, so let's make this
dependency common and simplify the individual Kconfig entries.Signed-off-by: Mark Rutland
Cc: Will Deacon
Signed-off-by: Will Deacon
11 Apr, 2017
1 commit
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This patch adds framework code to handle parsing PMU data out of the
MADT, sanity checking this, and managing the association of CPUs (and
their interrupts) with appropriate logical PMUs.For the time being, we expect that only one PMU driver (PMUv3) will make
use of this, and we simply pass in a single probe function.This is based on an earlier patch from Jeremy Linton.
Signed-off-by: Mark Rutland
Tested-by: Jeremy Linton
Cc: Will Deacon
Signed-off-by: Will Deacon
04 Apr, 2017
1 commit
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This adds a new dynamic PMU to the Perf Events framework to program
and control the L3 cache PMUs in some Qualcomm Technologies SOCs.The driver supports a distributed cache architecture where the overall
cache for a socket is comprised of multiple slices each with its own PMU.
Access to each individual PMU is provided even though all CPUs share all
the slices. User space needs to aggregate to individual counts to provide
a global picture.The driver exports formatting and event information to sysfs so it can
be used by the perf user space tools with the syntaxes:
perf stat -a -e l3cache_0_0/read-miss/
perf stat -a -e l3cache_0_0/event=0x21/Acked-by: Mark Rutland
Signed-off-by: Agustin Vega-Frias
[will: fixed sparse issues]
Signed-off-by: Will Deacon
09 Feb, 2017
1 commit
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Adds perf events support for L2 cache PMU.
The L2 cache PMU driver is named 'l2cache_0' and can be used
with perf events to profile L2 events such as cache hits
and misses on Qualcomm Technologies processors.Reviewed-by: Mark Rutland
Signed-off-by: Neil Leeder
[will: minimise nesting in l2_cache_associate_cpu_with_cluster]
[will: use kstrtoul for unsigned long, remove redunant .owner setting]
Signed-off-by: Will Deacon
16 Sep, 2016
1 commit
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This patch adds a driver for the SoC-wide (AKA uncore) PMU hardware
found in APM X-Gene SoCs.Signed-off-by: Tai Nguyen
Reviewed-by: Mark Rutland
07 Oct, 2015
1 commit
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Now that the arm_pmu framework has been factored out to drivers/perf we
can make use of it for arm64, gaining support for heterogeneous PMUs
and unifying the two codebases before they diverge further.The as yet unused PMU name for PMUv3 is changed to armv8_pmuv3, matching
the style previously applied to the 32-bit PMUs.Signed-off-by: Mark Rutland
Acked-by: Will Deacon
Signed-off-by: Catalin Marinas
31 Jul, 2015
1 commit
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To enable sharing of the arm_pmu code with arm64, this patch factors it
out to drivers/perf/. A new drivers/perf directory is added for
performance monitor drivers to live under.MAINTAINERS is updated accordingly. Files added previously without a
corresponsing MAINTAINERS update (perf_regs.c, perf_callchain.c, and
perf_event.h) are also added.Cc: Arnaldo Carvalho de Melo
Cc: Greg Kroah-Hartman
Cc: Ingo Molnar
Cc: Linus Walleij
Cc: Paul Mackerras
Cc: Peter Zijlstra
Cc: Russell King
Cc: Will Deacon
Signed-off-by: Mark Rutland
[will: augmented Kconfig help slightly]
Signed-off-by: Will Deacon