12 Feb, 2019
2 commits
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GPIO is widely used as the reset control for various devices. Let's
build the support in by default.[shawn.guo: cherry-pick commit 795fcb3bc5bb from imx_3.10.y]
Signed-off-by: Shawn Guo(cherry picked from commit 0cbf78b5b02c57e6fd0e57e811cfe56509c4fd24)
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This driver implements a reset controller device that toggle a gpio
connected to a reset pin of a peripheral IC. The delay between assertion
and de-assertion of the reset signal can be configured via device tree.Signed-off-by: Philipp Zabel
Reviewed-by: Stephen Warren
Reviewed-by: Pavel Machek
Signed-off-by: Shawn Guo
21 Sep, 2017
1 commit
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The HSDK reset driver is only useful when building for an ARC HSDK
platform.While at it, drop the "default n", as that is the default.
Fixes: e0be864f14240cb1 ("ARC: reset: introduce HSDKv1 reset driver")
Signed-off-by: Geert Uytterhoeven
[p.zabel@pengutronix.de: rebased, renamed RESET_HSDK_V1 to RESET_HSDK]
Signed-off-by: Philipp Zabel
18 Sep, 2017
2 commits
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There is no plan yet to do a v2 board. And even if we were to do it only
some IPs would actually change, so it be best to add suffixes at that
point, not now !Signed-off-by: Vineet Gupta
Signed-off-by: Philipp Zabel -
This avoids the error:
drivers/reset/reset-hsdk-v1.o: In function `hsdkv1_reset_probe':
/home/thomas/git/linux/drivers/reset/reset-hsdk-v1.c:101: undefined
reference to `devm_ioremap_resource'
collect2: error: ld returned 1 exit statusSigned-off-by: Thomas Meyer
Signed-off-by: Philipp Zabel
16 Sep, 2017
1 commit
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Pull MIPS updates from Ralf Baechle:
"This is the main pull request for 4.14 for MIPS; below a summary of
the non-merge commits:CM:
- Rename mips_cm_base to mips_gcr_base
- Specify register size when generating accessors
- Use BIT/GENMASK for register fields, order & drop shifts
- Add cluster & block args to mips_cm_lock_other()CPC:
- Use common CPS accessor generation macros
- Use BIT/GENMASK for register fields, order & drop shifts
- Introduce register modify (set/clear/change) accessors
- Use change_*, set_* & clear_* where appropriate
- Add CM/CPC 3.5 register definitions
- Use GlobalNumber macros rather than magic numbers
- Have asm/mips-cps.h include CM & CPC headers
- Cluster support for topology functions
- Detect CPUs in secondary clustersCPS:
- Read GIC_VL_IDENT directly, not via irqchip driverDMA:
- Consolidate coherent and non-coherent dma_alloc code
- Don't use dma_cache_sync to implement fd_cacheflushFPU emulation / FP assist code:
- Another series of 14 commits fixing corner cases such as NaN
propgagation and other special input values.
- Zero bits 32-63 of the result for a CLASS.D instruction.
- Enhanced statics via debugfs
- Do not use bools for arithmetic. GCC 7.1 moans about this.
- Correct user fault_addr typeGeneric MIPS:
- Enhancement of stack backtraces
- Cleanup from non-existing options
- Handle non word sized instructions when examining frame
- Fix detection and decoding of ADDIUSP instruction
- Fix decoding of SWSP16 instruction
- Refactor handling of stack pointer in get_frame_info
- Remove unreachable code from force_fcr31_sig()
- Convert to using %pOF instead of full_name
- Remove the R6000 support.
- Move FP code from *_switch.S to *_fpu.S
- Remove unused ST_OFF from r2300_switch.S
- Allow platform to specify multiple its.S files
- Add #includes to various files to ensure code builds reliable and
without warning..
- Remove __invalidate_kernel_vmap_range
- Remove plat_timer_setup
- Declare various variables & functions static
- Abstract CPU core & VP(E) ID access through accessor functions
- Store core & VP IDs in GlobalNumber-style variable
- Unify checks for sibling CPUs
- Add CPU cluster number accessors
- Prevent direct use of generic_defconfig
- Make CONFIG_MIPS_MT_SMP default y
- Add __ioread64_copy
- Remove unnecessary inclusions of linux/irqchip/mips-gic.hGIC:
- Introduce asm/mips-gic.h with accessor functions
- Use new GIC accessor functions in mips-gic-timer
- Remove counter access functions from irq-mips-gic.c
- Remove gic_read_local_vp_id() from irq-mips-gic.c
- Simplify shared interrupt pending/mask reads in irq-mips-gic.c
- Simplify gic_local_irq_domain_map() in irq-mips-gic.c
- Drop gic_(re)set_mask() functions in irq-mips-gic.c
- Remove gic_set_polarity(), gic_set_trigger(), gic_set_dual_edge(),
gic_map_to_pin() and gic_map_to_vpe() from irq-mips-gic.c.
- Convert remaining shared reg access, local int mask access and
remaining local reg access to new accessors
- Move GIC_LOCAL_INT_* to asm/mips-gic.h
- Remove GIC_CPU_INT* macros from irq-mips-gic.c
- Move various definitions to the driver
- Remove gic_get_usm_range()
- Remove __gic_irq_dispatch() forward declaration
- Remove gic_init()
- Use mips_gic_present() in place of gic_present and remove
gic_present
- Move gic_get_c0_*_int() to asm/mips-gic.h
- Remove linux/irqchip/mips-gic.h
- Inline __gic_init()
- Inline gic_basic_init()
- Make pcpu_masks a per-cpu variable
- Use pcpu_masks to avoid reading GIC_SH_MASK*
- Clean up mti, reserved-cpu-vectors handling
- Use cpumask_first_and() in gic_set_affinity()
- Let the core set struct irq_common_data affinitymicroMIPS:
- Fix microMIPS stack unwinding on big endian systemsMIPS-GIC:
- SYNC after enabling GIC regionNUMA:
- Remove the unused parent_node() macroR6:
- Constify r2_decoder_tables
- Add accessor & bit definitions for GlobalNumberSMP:
- Constify smp ops
- Allow boot_secondary SMP op to return errorsVDSO:
- Drop gic_get_usm_range() usage
- Avoid use of linux/irqchip/mips-gic.hPlatform changes:
Alchemy:
- Add devboard machine type to cpuinfo
- update cpu feature overrides
- Threaded carddetect irqs for devboardsAR7:
- allow NULL clock for clk_get_rateBCM63xx:
- Fix ENETDMA_6345_MAXBURST_REG offset
- Allow NULL clock for clk_get_rateCI20:
- Enable GPIO and RTC drivers in defconfig
- Add ethernet and fixed-regulator nodes to DTSGeneric platform:
- Move Boston and NI 169445 FIT image source to their own files
- Include asm/bootinfo.h for plat_fdt_relocated()
- Include asm/time.h for get_c0_*_int()
- Include asm/bootinfo.h for plat_fdt_relocated()
- Include asm/time.h for get_c0_*_int()
- Allow filtering enabled boards by requirements
- Don't explicitly disable CONFIG_USB_SUPPORT
- Bump default NR_CPUS to 16JZ4700:
- Probe the jz4740-rtc driver from devicetreeLantiq:
- Drop check of boot select from the spi-falcon driver.
- Drop check of boot select from the lantiq-flash MTD driver.
- Access boot cause register in the watchdog driver through regmap
- Add device tree binding documentation for the watchdog driver
- Add docs for the RCU DT bindings.
- Convert the fpi bus driver to a platform_driver
- Remove ltq_reset_cause() and ltq_boot_select(
- Switch to a proper reset driver
- Switch to a new drivers/soc GPHY driver
- Add an USB PHY driver for the Lantiq SoCs using the RCU module
- Use of_platform_default_populate instead of __dt_register_buses
- Enable MFD_SYSCON to be able to use it for the RCU MFD
- Replace ltq_boot_select() with dummy implementation.Loongson 2F:
- Allow NULL clock for clk_get_rateMalta:
- Use new GIC accessor functionsNI 169445:
- Add support for NI 169445 board.
- Only include in 32r2el kernelsOcteon:
- Add support for watchdog of 78XX SOCs.
- Add support for watchdog of CN68XX SOCs.
- Expose support for mips32r1, mips32r2 and mips64r1
- Enable more drivers in config file
- Add support for accessing the boot vector.
- Remove old boot vector code from watchdog driver
- Define watchdog registers for 70xx, 73xx, 78xx, F75xx.
- Make CSR functions node aware.
- Allow access to CIU3 IRQ domains.
- Misc cleanups in the watchdog driverOmega2+:
- New board, add support and defconfigPistachio:
- Enable Root FS on NFS in defconfigRalink:
- Add Mediatek MT7628A SoC
- Allow NULL clock for clk_get_rate
- Explicitly request exclusive reset control in the pci-mt7620 PCI driver.SEAD3:
- Only include in 32 bit kernels by defaultVoCore:
- Add VoCore as a vendor t0 dt-bindings
- Add defconfig file"* '4.14-features' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (167 commits)
MIPS: Refactor handling of stack pointer in get_frame_info
MIPS: Stacktrace: Fix microMIPS stack unwinding on big endian systems
MIPS: microMIPS: Fix decoding of swsp16 instruction
MIPS: microMIPS: Fix decoding of addiusp instruction
MIPS: microMIPS: Fix detection of addiusp instruction
MIPS: Handle non word sized instructions when examining frame
MIPS: ralink: allow NULL clock for clk_get_rate
MIPS: Loongson 2F: allow NULL clock for clk_get_rate
MIPS: BCM63XX: allow NULL clock for clk_get_rate
MIPS: AR7: allow NULL clock for clk_get_rate
MIPS: BCM63XX: fix ENETDMA_6345_MAXBURST_REG offset
mips: Save all registers when saving the frame
MIPS: Add DWARF unwinding to assembly
MIPS: Make SAVE_SOME more standard
MIPS: Fix issues in backtraces
MIPS: jz4780: DTS: Probe the jz4740-rtc driver from devicetree
MIPS: Ci20: Enable RTC driver
watchdog: octeon-wdt: Add support for 78XX SOCs.
watchdog: octeon-wdt: Add support for cn68XX SOCs.
watchdog: octeon-wdt: File cleaning.
...
05 Sep, 2017
1 commit
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The reset controllers (on xRX200 and newer SoCs have two of them) are
provided by the RCU module. This was initially implemented as a simple
reset controller. However, the RCU module provides more functionality
(ethernet GPHYs, USB PHY, etc.), which makes it a MFD device.
The old reset controller driver implementation from
arch/mips/lantiq/xway/reset.c did not honor this fact.For some devices the request and the status bits are different.
Signed-off-by: Martin Blumenstingl
Signed-off-by: Hauke Mehrtens
Reviewed-by: Andy Shevchenko
Acked-by: Philipp Zabel
Acked-by: Rob Herring
Cc: john@phrozen.org
Cc: kishon@ti.com
Cc: mark.rutland@arm.com
Cc: linux-mips@linux-mips.org
Cc: linux-mtd@lists.infradead.org
Cc: linux-watchdog@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-spi@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/17125/
Signed-off-by: Ralf Baechle
07 Aug, 2017
1 commit
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This reverts commit 2acb037fc42b8ce5ae59a7d5db3c9b35672e3dd7.
We ended up merging the reset controller into the clock
controller so we can now get rid of this stand-alone
implementation.Signed-off-by: Linus Walleij
Signed-off-by: Philipp Zabel
20 Jul, 2017
1 commit
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The HSDK v1 periphery IPs can be reset by accessing some registers
from the CGU block.The list of available reset lines is documented in the DT bindings.
Signed-off-by: Eugeniy Paltsev
Signed-off-by: Philipp Zabel
06 Jun, 2017
1 commit
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Some TI Keystone family of SoCs contain a system controller (like the
Power Management Micro Controller (PMMC) on 66AK2G SoCs) that manage
the low-level device control (like clocks, resets etc) for the various
hardware modules present on the SoC. These device control operations
are provided to the host processor OS through a communication protocol
called the TI System Control Interface (TI SCI) protocol.This patch adds a reset driver that communicates to the system
controller over the TI SCI protocol for performing reset management
of various devices present on the SoC. Various reset functionalities
are achieved by the means of different TI SCI device operations
provided by the TI SCI framework.Signed-off-by: Andrew F. Davis
[s-anna@ti.com: documentation changes, revised commit message]
Signed-off-by: Suman Anna
Signed-off-by: Nishanth Menon
Acked-by: Santosh Shilimkar
[p.zabel@pengutronix.de: const struct reset_control_ops]
Signed-off-by: Philipp Zabel
24 May, 2017
2 commits
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The Cortina Systems Gemini reset controller is a simple
32bit register with self-deasserting reset lines. It is
accessed using regmap over syscon.Acked-by: Philipp Zabel
Signed-off-by: Linus Walleij
Signed-off-by: Philipp Zabel -
Rename the current Kconfig name used for the TI SYSCON Reset
driver from TI_SYSCON_RESET to RESET_TI_SYSCON to match the
convention used for all the reset drivers present at the
base reset folder.Signed-off-by: Suman Anna
Signed-off-by: Philipp Zabel
15 Mar, 2017
2 commits
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This patch adds the reset controller functionality for
Peripheral PHYs to the Arria10 System Resource Chip.Signed-off-by: Thor Thayer
Signed-off-by: Philipp Zabel -
Add reset controller driver exposing various reset faculties,
implemented by System Reset Controller IP block.Cc: Lucas Stach
Cc: Mark Rutland
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Andrey Smirnov
Acked-by: Rob Herring
Signed-off-by: Philipp Zabel
20 Jan, 2017
1 commit
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This patch adds reset controller driver for ZTE's zx2967 family.
Signed-off-by: Baoyou Xie
Reviewed-by: Shawn Guo
Signed-off-by: Philipp Zabel
18 Nov, 2016
1 commit
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This driver uses the services provided by the BPMP firmware driver to
implement a reset driver based on the MRQ_RESET request.Acked-by: Philipp Zabel
Signed-off-by: Thierry Reding
30 Aug, 2016
5 commits
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.Cc: Moritz Fischer
Cc: Sören Brinkmann
Acked-by: Michal Simek
Reviewed-by: Masahiro Yamada
Signed-off-by: Philipp Zabel -
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.Reviewed-by: Masahiro Yamada
Signed-off-by: Philipp Zabel -
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.Cc: Maxime Coquelin
Cc: Gabriel Fernandez
Reviewed-by: Masahiro Yamada
Signed-off-by: Philipp Zabel -
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.Acked-by: Dinh Nguyen
Reviewed-by: Masahiro Yamada
Signed-off-by: Philipp Zabel -
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.Cc: Damien Horsley
Acked-by: James Hartley
Reviewed-by: Masahiro Yamada
Signed-off-by: Philipp Zabel
25 Aug, 2016
4 commits
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Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.Acked-by: Neil Armstrong
Reviewed-by: Masahiro Yamada
Signed-off-by: Philipp Zabel -
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.Acked-by: Joachim Eastwood
Reviewed-by: Masahiro Yamada
Signed-off-by: Philipp Zabel -
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.Cc: Antoine Tenart
Cc: Sebastian Hesselbarth
Reviewed-by: Masahiro Yamada
Signed-off-by: Philipp Zabel -
Visible only if COMPILE_TEST is enabled, this allows to include the
driver in build tests.Acked-by: Aban Bedel
Reviewed-by: Masahiro Yamada
Signed-off-by: Philipp Zabel
24 Aug, 2016
1 commit
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This is the initial commit for UniPhier reset controller driver.
Signed-off-by: Masahiro Yamada
Acked-by: Rob Herring
Signed-off-by: Philipp Zabel
30 Jun, 2016
1 commit
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Add a reset-controller driver for performing reset management of
various devices present on the SoC, with the reset registers shared
between devices in a common register memory space. This driver uses
the syscon/regmap frameworks to actually implement the various reset
functionalities needed by the reset consumer devices.Signed-off-by: Andrew F. Davis
[s-anna@ti.com: add documentation, syscon name change]
Signed-off-by: Suman Anna
Signed-off-by: Philipp Zabel
30 May, 2016
1 commit
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In "make menuconfig", reset drivers are currently lined up together
with the reset sub-system menu, like this:-*- Reset Controller Support ----
< > Hi6220 Reset Driver(It also means, the menu "Reset Controller Support" is always empty.)
"Hi6220 Reset Driver" should go into the sub-menu of the
"Reset Controller Support".Signed-off-by: Masahiro Yamada
Signed-off-by: Philipp Zabel
01 Apr, 2016
1 commit
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Add System reset controller driver for Oxford Semiconductor OXNAS SoC
Family.CC: Ma Haijun
Signed-off-by: Neil Armstrong
Signed-off-by: Philipp Zabel
20 Nov, 2015
1 commit
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Add reset driver for hi6220-hikey board,this driver supply deassert
of IP on hi6220 SoC.Signed-off-by: Chen Feng
Signed-off-by: Philipp Zabel
11 Mar, 2014
1 commit
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This patch adds a reset controller implementation for STMicroelectronics
STi family SoCs; it allows a group of related reset like controls found
in multiple system configuration registers to be represented by a single
controller device. System configuration registers are accessed through
the regmap framework and the mfd/syscon driver.The implementation optionally supports waiting for the reset action to
be acknowledged in a separate status register and supports both
active high and active low reset lines. These properties are common across
all the reset channels in a specific reset controller instance, hence
all channels in a paritcular controller are expected to behave in the
same way.Signed-off-by: Stephen Gallimore
Signed-off-by: Srinivas Kandagatla
Acked-by: Philipp Zabel
12 Apr, 2013
1 commit
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This adds a simple API for devices to request being reset
by separate reset controller hardware and implements the
reset signal device tree binding.Signed-off-by: Philipp Zabel
Reviewed-by: Stephen Warren
Reviewed-by: Shawn Guo
Reviewed-by: Marek Vasut
Reviewed-by: Pavel Machek