27 Mar, 2019
1 commit
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A fixed PLL PMS setting for attached panel is obviously not
enough for any other mipi panel which needs a different PLL
output clock frequency, and besides, for the CEA-861 standard
display modes, the 'pll_pms' table also can not cover all the
modes requirements. So a general way is created to solve this
problem which can provide an optimum solution to output a PLL
bit clock to match the request frequency in a maximum degree
and also satisfy the input clock and intermediate clocks limit
according to the PLL specification.Signed-off-by: Fancy Fang
(cherry picked from commit a73fdd5e48fe0df47685cfc197fe66edc1e28405)
12 Feb, 2019
9 commits
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This patch removes the exported function nwl_dsi_get_bit_clock that was
used by nwl_dsi-imx driver in order to configure the phy driver speed
and move this configuration directly into the nwl-dsi driver.
This function is now used directly by nwl-dsi to verify which mode can or
cannot be supported by the DSI PHY.
Also, in nwl-dsi, add support for mode_valid and add each supported mode
into a list kept internally so that it can apply the needed
configuration (phyref rate, dsi lanes, bit-clock) later when the mode is
used.Signed-off-by: Robert Chiras
Reviewed-by: Laurentiu Palcu -
In the macro 'DSIM_DPHY_TIMING' definition, the field
'clk_trail' assignment to 'ctrail' is missing which
certainly needs to be added.Signed-off-by: Fancy Fang
(cherry picked from commit f2818410d3d8d3b09002a85b593cee192d60bb06) -
The SEC provides a table to guide the DPHY TIMINGS config based
on the PLL output bit clock frequency for DSIM. So create the
table which is used by SEC LN14LPP DPHY with HS Timing v1.2 and
this table will be used by the SEC DSIM Bridge driver to help to
config the corresponding DPHY Timings correctly for each display
mode. Along with the table, a DPHY TIMING table entry 'compare'
method is implemented for the binary search when lookup the
suitable DPHY TIMING entry.Signed-off-by: Fancy Fang
(cherry picked from commit eb899b434be6127db26c370bf200d8072eaf01c4)
(cherry picked from commit 3b23233dafd65d6ea8c1fa12e8992c58ebc412bc) -
Defer the PLL output check to the SEC DSIM Encoder's atomic check
from SEC DSIM Bridge's mode_fixup(), since in the attached DSI
device Bridge's mode_fixup(), it may change the data lanes number,
and this change is done after the SEC DSIM Bridge's mode_fixup().
And the DSIM Encoder's atomic check is the ideal place to do this
PLL check, since it happens after all the Bridges' mode_fixup()
done.Signed-off-by: Fancy Fang
(cherry picked from commit c9bce66fed982383dde189c428d4c2ee2c2fc623)
(cherry picked from commit ead3666313e552296da7e7b5094579b47dbdc364) -
This is the abstracted bridge driver for Samsung MIPI DSIM
controller. This driver only foucses on the DSIM controller
itself configurations and never care about any config about
the platforms. So it can be shared by different platforms
without any modifications.Signed-off-by: Fancy Fang
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Since the drm_bridge_attach function now supports chained bridges, there
is no need for nwl_dsi_add_bridge and nwl_dsi_del_bridge functions, so
remove them.
Now, we can pass the existent bridge to drm_bridge_attach.This fixes a bug created during kernel 4.14 rebase process.
Signed-off-by: Robert Chiras
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Use the bus format that was established by CRTC in
crtc->mode.private_flags.
This will be available during enable phase.The DSI host will be configured via interface_color_coding
and pixel_format (DPI-2 interface ports).
Previously the interface_color_coding was hardcoded to 24-bit.Set the DSI pixel format before it is necessary in
nwl_dsi_get_bit_clock, during imx_nwl_dsi_enable.Signed-off-by: Mirela Rabulea
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Currently, the Northwest Logic MIPI-DSI controller host specific code
resides under drm/bridge, but is not a real drm_bridge. It creates a
drm_bridge and adds itself to the drm_encoder that handles this file,
but this is wrong, since it does not implement the drm_bridge_funcs.The correct way to implement a drm_bridge is to add the drm_bridge and
let other components (another bridge or a drm_encoder) to attach to this
bridge.
Since we are doing this, a new compatible strings can be used for this
driver: "nwl,mipi-dsi".Since this was used by nwl_dsi-imx.c, update that driver to use this
bridge correctly.This is needed in order to add support for MIPI-DSI on 8MQ. The IMX_NWL
driver will either add a DSI encoder to DRM, or a DSI bridge.
The encoder will be used by imx-drm-core driver, while the bridge
will be used by MXSFB driver (which creates a simple display pipe).Signed-off-by: Robert Chiras
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Add support for the NorthWest Logit MIPI-DSI controller found in mx8
platforms: i.MX8qm, i.MX8qxp and i.MX8mq.
The NWL MIPI-DSI driver is implemented as a DRM bridge.
The MIPI-DSI encoder will contain the platform specific changes and will
use this bridge.Signed-off-by: Robert Chiras
26 Jul, 2017
1 commit
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I need this to be able to apply the deferred fbdev setup patches, I
need the relevant prep work that landed through the drm-intel tree.Also squash in conflict fixup from Laurent Pinchart.
Signed-off-by: Daniel Vetter
18 Jul, 2017
1 commit
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Add a Synopsys Designware MIPI DSI host DRM bridge driver, based on the
Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.Signed-off-by: Philippe CORNU
Signed-off-by: Archit Taneja
Link: https://patchwork.freedesktop.org/patch/msgid/1500277223-29553-5-git-send-email-philippe.cornu@st.com
26 Jun, 2017
1 commit
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The "supported input formats" table in dw_hdmi.h was incorrectly formatted,
using "+" signs where "|" needs to be. That, in turn, causes the PDF build
to fail.Fixes: def23aa7e982 ("drm: bridge: dw-hdmi: Switch to V4L bus format and encodings")
Signed-off-by: Jonathan Corbet
Signed-off-by: Daniel Vetter
Link: http://patchwork.freedesktop.org/patch/msgid/20170623140013.0703107a@lwn.net
05 Jun, 2017
1 commit
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Now that we have a callback to check if bridge supports a given mode
we can use it in Synopsys Designware HDMI bridge so that we restrict
the number of probbed modes to the ones we can actually display.Also, there is no need to use mode_fixup() callback as mode_valid()
will handle the mode validation.NOTE: I also had to change the pdata declaration of mode_valid
custom callback so that the passed modes are const. I also changed
in the platforms I found. Not even compiled it though.Signed-off-by: Jose Abreu
Acked-by: Neil Armstrong
Acked-by: Philipp Zabel
Cc: Carlos Palminha
Cc: Daniel Vetter
Cc: Archit Taneja
Cc: Andrzej Hajda
Cc: Laurent Pinchart
Cc: David Airlie
Cc: Philipp Zabel
Cc: Carlo Caione
Cc: Kevin Hilman
Cc: Mark Yao
Cc: Heiko Stuebner
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/3d8d449e4d13d2535fa292c75f5fa931de4a4fa8.1495720737.git.joabreu@synopsys.com
04 Apr, 2017
2 commits
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The HDMI TX controller support HPD and RXSENSE signaling from the PHY
via it's STAT0 PHY interface, but some vendor PHYs can manage these
signals independently from the controller, thus these STAT0 handling
should be moved to PHY specific operations and become optional.The existing STAT0 HPD and RXSENSE handling code is refactored into
a supplementaty set of default PHY operations that are used automatically
when the platform glue doesn't provide its own operations.Reviewed-by: Jose Abreu
Reviewed-by: Archit Taneja
Reviewed-by: Laurent Pinchart
Signed-off-by: Neil Armstrong
Link: http://patchwork.freedesktop.org/patch/msgid/1491309119-24220-2-git-send-email-narmstrong@baylibre.com -
Switch code to use the newly introduced V4L bus formats IDs instead of custom
defines. Also use the V4L encoding defines.Some display pipelines can only provide non-RBG input pixels to the HDMI TX
Controller, this patch takes the pixel format from the plat_data if provided.Reviewed-by: Jose Abreu
Reviewed-by: Archit Taneja
Reviewed-by: Laurent Pinchart
Signed-off-by: Neil Armstrong
10 Mar, 2017
4 commits
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The Synopsys Designware HDMI TX Controller does not enforce register
access on platforms instanciating it. The current driver supports two
different types of memory-mapped flat register access, but in order to
support the Amlogic Meson SoCs integration, and provide a more generic
way to handle all sorts of register mapping, switch the register access
to use the regmap infrastructure.In the case of registers that are not flat memory-mapped or do not
conform to the current driver implementation, a regmap struct can be
given in the plat_data and be used at probe or bind.Since the AHB audio driver is only available with direct memory access,
only allow the I2S audio driver to be registered is directly
memory-mapped.Signed-off-by: Neil Armstrong
Reviewed-by: Laurent Pinchart
Tested-by: Laurent Pinchart
Tested-by: Neil Armstrong
Reviewed-by: Jose Abreu
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-10-laurent.pinchart+renesas@ideasonboard.com -
The device type isn't used anymore now that workarounds and PHY-specific
operations are performed based on version information read at runtime.
Remove it.Signed-off-by: Kieran Bingham
Signed-off-by: Laurent Pinchart
Tested-by: Neil Armstrong
Reviewed-by: Jose Abreu
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-9-laurent.pinchart+renesas@ideasonboard.com -
The DWC HDMI TX controller interfaces with a companion PHY. While
Synopsys provides multiple standard PHYs, SoC vendors can also integrate
a custom PHY.Modularize PHY configuration to support vendor PHYs through platform
data. The existing PHY configuration code was originally written to
support the DWC HDMI 3D TX PHY, and seems to be compatible with the DWC
MLP PHY. The HDMI 2.0 PHY will require a separate configuration
function.Signed-off-by: Kieran Bingham
Signed-off-by: Laurent Pinchart
Tested-by: Neil Armstrong
Reviewed-by: Jose Abreu
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/20170303172007.26541-8-laurent.pinchart+renesas@ideasonboard.com -
The HDMI TX controller support different PHYs whose programming
interface can vary significantly, especially with vendor PHYs that are
not provided by Synopsys. To support them, create a PHY operation
structure that can be provided by the platform glue layer. The existing
PHY handling code (limited to Synopsys PHY support) is refactored into a
set of default PHY operations that are used automatically when the
platform glue doesn't provide its own operations.Signed-off-by: Laurent Pinchart
Tested-by: Neil Armstrong
Reviewed-by: Jose Abreu
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/20170305233615.11993-1-laurent.pinchart+renesas@ideasonboard.com
07 Mar, 2017
1 commit
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Add two simple functions that just take the drm_dp_aux from our struct
and calls the corresponding DP helpers with it.v6: Pass to the DP helper the drm_crtc of the current connector (Sean Paul)
Signed-off-by: Tomeu Vizoso
Signed-off-by: Sean Paul
Link: http://patchwork.freedesktop.org/patch/msgid/20170303133936.14964-4-tomeu.vizoso@collabora.com
02 Feb, 2017
2 commits
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MHL3 protocol uses vendor specific infoframes to transmit additional
information to the sink. This patch adds definitions of structures and
constants used to create such frames.Signed-off-by: Andrzej Hajda
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-20-git-send-email-a.hajda@samsung.com -
Burst transmissions are required in MHL3 modes.
Signed-off-by: Andrzej Hajda
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/1485935272-17337-7-git-send-email-a.hajda@samsung.com
18 Jan, 2017
4 commits
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Detect the PHY type and use it to handle the PHY type-specific SVSRET
signal.Signed-off-by: Laurent Pinchart
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-17-laurent.pinchart+renesas@ideasonboard.com -
As an option for drivers not based on the component framework, register
the bridge with the DRM core with the DRM bridge API. Existing drivers
based on dw_hdmi_bind() and dw_hdmi_unbind() are not affected as those
functions are preserved with their current behaviour.Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-11-laurent.pinchart+renesas@ideasonboard.com -
There's no need to duplicate identical code in multiple drivers (two at
the moment, one more to come soon). Move it to the dw-hdmi core where it
can be shared. If resource allocation ever becomes device-specific later
we'll always have the option of splitting it out again.While it at pass the platform device to the bind function to avoid
having to cast struct device to struct platform_device.Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-8-laurent.pinchart+renesas@ideasonboard.com -
The master argument isn't used. The data argument, a void pointer, is
used by the bind function only where it's cast to a drm_device pointer,
which can easily be obtained from the encoder argument instead. Remove
them.Signed-off-by: Laurent Pinchart
Reviewed-by: Jose Abreu
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/20170117082910.27023-3-laurent.pinchart+renesas@ideasonboard.com
26 Oct, 2016
1 commit
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This header adds definitions specific to MHL protocol.
Signed-off-by: Andrzej Hajda
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/1475823762-16237-2-git-send-email-a.hajda@samsung.com
04 Oct, 2016
1 commit
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So users know whether PSR should be enabled or not.
Cc: Yakir Yang
Reviewed-by: Sean Paul
Signed-off-by: Tomeu Vizoso
Signed-off-by: Archit Taneja
Link: http://patchwork.freedesktop.org/patch/msgid/1474639600-30090-1-git-send-email-tomeu.vizoso@collabora.com
23 Aug, 2016
1 commit
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The full name of PSR is Panel Self Refresh, panel device could refresh
itself with the hardware framebuffer in panel, this would make lots of
sense to save the power consumption.This patch have exported two symbols for platform driver to implement
the PSR function in hardware side:
- analogix_dp_active_psr()
- analogix_dp_inactive_psr()Reviewed-by: Archit Taneja
Signed-off-by: Yakir Yang
Signed-off-by: Sean Paul
05 Jul, 2016
3 commits
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It's better to pass the connector to platform driver in .get_modes()
callback, just like what the .get_modes() helper function designed.Signed-off-by: Yakir Yang
Reviewed-by: Sean Paul
Reviewed-by: Tomasz Figa -
RK3399 and RK3288 shared the same eDP IP controller, only some light
difference with VOP configure and GRF configure.Signed-off-by: Yakir Yang
Acked-by: Mark Yao
Reviewed-by: Tomasz Figa
Reviewed-by: Sean Paul -
As vendor document indicate, when REF_CLK bit set 0, then DP
phy's REF_CLK should switch to 24M source clock.But due to IC PHY layout mistaken, some chips need to flip this
bit(like RK3288), and unfortunately they didn't indicate in the
DP version register. That's why we have to make this little hack.Signed-off-by: Yakir Yang
Reviewed-by: Tomasz Figa
Tested-by: Javier Martinez Canillas
Reviewed-by: Sean Paul
05 Apr, 2016
2 commits
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Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.Acked-by: Mark Yao
Tested-by: Caesar Wang
Tested-by: Douglas Anderson
Tested-by: Heiko Stuebner
Signed-off-by: Yakir Yang
Signed-off-by: Heiko Stuebner -
Split the dp core driver from exynos directory to bridge directory,
and rename the core driver to analogix_dp_*, rename the platform
code to exynos_dp.Beside the new analogix_dp driver would export six hooks.
"analogix_dp_bind()" and "analogix_dp_unbind()"
"analogix_dp_suspned()" and "analogix_dp_resume()"
"analogix_dp_detect()" and "analogix_dp_get_modes()"The bind/unbind symbols is used for analogix platform driver to connect
with analogix_dp core driver. And the detect/get_modes is used for analogix
platform driver to init the connector.They reason why connector need register in helper driver is rockchip drm
haven't implement the atomic API, but Exynos drm have implement it, so
there would need two different connector helper functions, that's why we
leave the connector register in helper driver.Acked-by: Inki Dae
Tested-by: Caesar Wang
Tested-by: Douglas Anderson
Tested-by: Heiko Stuebner
Tested-by: Javier Martinez Canillas
Signed-off-by: Yakir Yang
Signed-off-by: Heiko Stuebner
27 Aug, 2015
1 commit
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Here are some development updates for the Synopsis Designware HDMI driver,
which clean up some of the code, and start preparing to add audio support
to the driver. This series of patches are based on a couple of dependent
commits from the ALSA tree.Briefly, the updates are:
- move comments which should have moved with the phy values to the IMX
part of the driver.
- clean up the phy configuration: to all lookups before starting to
program the phy.
- clean up the HDMI clock regenerator code
- use the drm_hdmi_avi_infoframe_from_display_mode() helper which allows
the code to be subsequently simplified
- remove the unused 'regmap' pointer in struct dw_hdmi
- use the bridge drm device rather than the connector (we're the bridge
code)
- remove private hsync/vsync/interlaced flags, getting them from the
DRM mode structure instead.
- implement interface functions to support audio - setting the audio
sample rate, and enabling the audio clocks.
- removal of broken pixel repetition support
- cleanup DVI vs HDMI sink handling
- enable audio only if connected device supports audio
- avoid double-enabling bridge in the sink path (once in mode_set, and
again in commit)
- rename mis-named dw_hdmi_phy_enable_power()
- fix bridge enable/disable handing, so a plug-in event doesn't
reconfigure the bridge if DRM has disabled the output
- fix from Vladimir Zapolskiy for the I2CM_ADDRESS macro nameThese are primerily preparitory patches for the AHB audio driver and
the I2S audio driver (from Rockchip) for this IP.* 'drm-dwhdmi-devel' of git://ftp.arm.linux.org.uk/~rmk/linux-arm:
drm: bridge/dw_hdmi: fix register I2CM_ADDRESS register name
drm: bridge/dw_hdmi: fix phy enable/disable handling
drm: bridge/dw_hdmi: rename dw_hdmi_phy_enable_power()
drm: bridge/dw_hdmi: avoid enabling interface in mode_set
drm: bridge/dw_hdmi: enable audio only if sink supports audio
drm: bridge/dw_hdmi: clean up HDMI vs DVI mode handling
drm: bridge/dw_hdmi: don't support any pixel doubled modes
drm: bridge/dw_hdmi: remove pixel repetition setting for all VICs
drm: bridge/dw_hdmi: introduce interfaces to enable and disable audio
drm: bridge/dw_hdmi: introduce interface to setting sample rate
drm: bridge/dw_hdmi: remove mhsyncpolarity/mvsyncpolarity/minterlaced
drm: bridge/dw_hdmi: use our own drm_device
drm: bridge/dw_hdmi: remove unused 'regmap' struct member
drm: bridge/dw_hdmi: simplify hdmi_config_AVI() a little
drm: bridge/dw_hdmi: use drm_hdmi_avi_infoframe_from_display_mode()
drm: bridge/dw_hdmi: clean up hdmi_set_clk_regenerator()
drm: bridge/dw_hdmi: clean up phy configuration
drm: imx/dw_hdmi: move phy comments
drm/edid: add function to help find SADs
18 Aug, 2015
2 commits
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iMX6 devices suffer from an errata (ERR005174) where the audio FIFO can
be emptied while it is partially full, resulting in misalignment of the
audio samples.To prevent this, the errata workaround recommends writing N as zero
until the audio FIFO has been loaded by DMA. Writing N=0 prevents the
HDMI bridge from reading from the audio FIFO, effectively disabling
audio.This means we need to provide the audio driver with a pair of functions
to enable/disable audio. These are dw_hdmi_audio_enable() and
dw_hdmi_audio_disable().A spinlock is introduced to ensure that setting the CTS/N values can't
race, ensuring that the audio driver calling the enable/disable
functions (which are called in an atomic context) can't race with a
modeset.Tested-by: Yakir Yang
Signed-off-by: Russell King -
Introduce dw_hdmi_set_sample_rate(), which allows us to configure the
audio sample rate, setting the CTS/N values appropriately.Tested-by: Yakir Yang
Signed-off-by: Russell King
05 Jun, 2015
1 commit
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This header file declares prototypes of functions that are no longer
used. Remove this file and all references to it.Signed-off-by: Thierry Reding
01 Apr, 2015
1 commit
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Because of iMX6 & Rockchip have differnet mpll config parameter,
the VLEVCTRL parameter would be different. In this case we should
separate VLEVCTRL setting from the common dw_hdmi driver, config
this parameter in platform driver(dw_hdmi-imx and dw_hdmi-rockchip)Signed-off-by: Yakir Yang
Signed-off-by: Russell King