Eric Lee / smarc-fsl-linux-kernel

12 Feb, 2019

4 commits

  • 14f5226b4   MLK-11316-3 video: mxc ipuv3 fb: Change pan display mechanism for PRE workaround ... Browse Code »

    In order to workaround the PRE SoC bug recorded by errata ERR009624, the
    software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
    register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.

    The software mechanism to set the PRE_CTRL register is different for PRE Y
    resolution higher than 9 lines and lower than or equal to 9 lines.

    For cases in which Y resolution is higher than 9 lines, before we update PRE
    shadow, we just need to wait until the PRE store engine status runs out of
    the problematic PRE automatic writing window.

    While for cases in which Y resolutin is lower than or equal to 9 lines, we
    have to update PRE shadow in the buffer flip interrupt handler.

    Signed-off-by: Liu Ying
    (cherry picked from commit bd9c14e24aaf67926dfd31bd819ab0c87129fe4b)

    Liu Ying
     
  • eb170f183   MLK-11316-2 mxc IPUv3: PRE: Define small Y resolution ... Browse Code »

    In order to workaround the PRE SoC bug recorded by errata ERR009624, the
    software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
    register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.

    The software mechanism to set the PRE_CTRL register is different for PRE Y
    resolution higher than 9 lines and lower than or equal to 9 lines. So,
    this patch defines the small Y resolution and adds a helper to check the
    Y resolution.

    Signed-off-by: Liu Ying
    (cherry picked from commit cf7df46e3b1d2142ff354498982194247bf07fea)

    Liu Ying
     
  • 3a7e70118   MLK-11316-1 mxc IPUv3: PRE: Export a function to set PRE_CTRL register ... Browse Code »

    In order to workaround the PRE SoC bug recorded by errata ERR009624, the
    software cannot write the PRE_CTRL register when the PRE writes the PRE_CTRL
    register automatically to set the ENABLE bit(bit0) to 1 in the PRE repeat mode.

    This patch exports a function to set the PRE_CTRL register so that it could be
    used by the software when the PRE automatic writing doesn't happen for sure.

    Signed-off-by: Liu Ying
    (cherry picked from commit e64bbcd9243a17f9eba9cb3abb6f2c1939eae110)

    Liu Ying
     
  • 0a9049343   MLK-11431-1: IPU: forward IPU display drivers to 4.1.y kernel ... Browse Code »

    Forward imx_3.14.y IPU and display drivers to 4.1 kernel.
    This includes IPU core driver, display driver, LDB and HDMI driver.

    Signed-off-by: Sandor Yu

    Sandor Yu