29 Sep, 2010

8 commits


28 Sep, 2010

31 commits


27 Sep, 2010

1 commit

  • The PL310 on the ct-ca9x4 tile for the Versatile Express does not need
    to add additional latency when accessing its cache RAMs. Unfortunately,
    the boot monitor sets this up for an 8-cycle delay on reads and writes,
    resulting in greatly reduced memory performance when the L2 cache is
    enabled.

    This patch sets the L2 RAM latencies to the correct value of 1 cycle
    on the ct-ca9x4 tile before enabling the L2 cache.

    Acked-by: Catalin Marinas
    Signed-off-by: Will Deacon
    Signed-off-by: Russell King

    Will Deacon