/*
   * Copyright 2017-2018 NXP
   *
   * SPDX-License-Identifier:	GPL-2.0+
   */
  #include <common.h>
  #include <malloc.h>
  #include <errno.h>
  #include <netdev.h>
  #include <fsl_ifc.h>
  #include <fdt_support.h>
  #include <linux/libfdt.h>
  #include <environment.h>
  #include <fsl_esdhc.h>
  #include <i2c.h>
  
  #include <asm/io.h>
  #include <asm/gpio.h>
  #include <asm/arch/clock.h>
  #include <asm/mach-imx/sci/sci.h>
  #include <asm/arch/imx8-pins.h>
  #include <dm.h>
  #include <imx8_hsio.h>
  #include <usb.h>
  #include <asm/arch/iomux.h>
  #include <asm/arch/sys_proto.h>
  #include <asm/mach-imx/video.h>
  #include <asm/arch/video_common.h>
  #include <power-domain.h>
  #include "../common/tcpc.h"

  #include <cdns3-uboot.h>

  #include <asm/arch/lpcg.h>

  
  DECLARE_GLOBAL_DATA_PTR;
  
  #define ENET_INPUT_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  
  #define ENET_NORMAL_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  						| (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  
  #define FSPI_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  
  #define GPIO_PAD_CTRL	((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  
  #define I2C_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  						| (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  
  #define UART_PAD_CTRL	((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  						| (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  
  static iomux_cfg_t uart0_pads[] = {
  	SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  	SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  };
  
  static void setup_iomux_uart(void)
  {
  	imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
  }
  
  int board_early_init_f(void)
  {
  	sc_ipc_t ipcHndl = 0;
  	sc_err_t sciErr = 0;

  	/* When start u-boot in XEN VM, directly return */

  	if (IS_ENABLED(CONFIG_XEN)) {
  		writel(0xF53535F5, (void __iomem *)0x80000000);

  		return 0;

  	}

  	ipcHndl = gd->arch.ipc_channel_handle;
  
  	/* Power up UART0, this is very early while power domain is not working */
  	sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_0, SC_PM_PW_MODE_ON);
  	if (sciErr != SC_ERR_NONE)
  		return 0;
  
  	/* Set UART0 clock root to 80 MHz */
  	sc_pm_clock_rate_t rate = 80000000;
  	sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, 2, &rate);
  	if (sciErr != SC_ERR_NONE)
  		return 0;
  
  	/* Enable UART0 clock root */
  	sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_0, 2, true, false);
  	if (sciErr != SC_ERR_NONE)
  		return 0;

  	LPCG_AllClockOn(LPUART_0_LPCG);

  	setup_iomux_uart();
  
  	return 0;
  }
  
  #ifdef CONFIG_FEC_MXC
  #include <miiphy.h>
  
  static iomux_cfg_t pad_enet1[] = {
  	SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  
  	/* Shared MDIO */
  	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  };
  
  static iomux_cfg_t pad_enet0[] = {
  	SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  	SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  
  	/* Shared MDIO */
  	SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  	SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  };
  
  static void setup_iomux_fec(void)
  {
  	if (0 == CONFIG_FEC_ENET_DEV)
  		imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
  	else
  		imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
  }
  
  int board_eth_init(bd_t *bis)
  {
  	int ret;
  	struct power_domain pd;
  
  	printf("[%s] %d
  ", __func__, __LINE__);
  
  	if (CONFIG_FEC_ENET_DEV) {
  		if (!power_domain_lookup_name("conn_enet1", &pd))
  			power_domain_on(&pd);
  	} else {
  		if (!power_domain_lookup_name("conn_enet0", &pd))
  			power_domain_on(&pd);
  	}
  
  	setup_iomux_fec();
  
  	ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  		CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  	if (ret)
  		printf("FEC1 MXC: %s:failed
  ", __func__);
  
  	return ret;
  }
  
  int board_phy_config(struct phy_device *phydev)
  {
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  
  	if (phydev->drv->config)
  		phydev->drv->config(phydev);
  
  	return 0;
  }
  #endif
  
  #ifdef CONFIG_MXC_GPIO
  
  #define LVDS_ENABLE IMX_GPIO_NR(1, 6)
  #define MIPI_ENABLE IMX_GPIO_NR(1, 7)
  
  #define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
  #define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
  #define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
  
  static void board_gpio_init(void)
  {
  	/* Enable BB 3V3 */
  	gpio_request(BB_GPIO_3V3_1, "bb_3v3_1");
  	gpio_direction_output(BB_GPIO_3V3_1, 1);
  	gpio_request(BB_GPIO_3V3_2, "bb_3v3_2");
  	gpio_direction_output(BB_GPIO_3V3_2, 1);
  	gpio_request(BB_GPIO_3V3_3, "bb_3v3_3");
  	gpio_direction_output(BB_GPIO_3V3_3, 1);
  
  	/* enable LVDS SAS boards */
  	gpio_request(LVDS_ENABLE, "lvds_enable");
  	gpio_direction_output(LVDS_ENABLE, 1);
  
  	/* enable MIPI SAS boards */
  	gpio_request(MIPI_ENABLE, "mipi_enable");
  	gpio_direction_output(MIPI_ENABLE, 1);
  }
  #endif
  
  int checkboard(void)
  {
  	puts("Board: iMX8QM MEK
  ");
  
  	print_bootinfo();
  
  	/* Note:  After reloc, ipcHndl will no longer be valid.  If handle
  	 *        returned by sc_ipc_open matches SC_IPC_CH, use this
  	 *        macro (valid after reloc) for subsequent SCI calls.
  	 */
  	if (gd->arch.ipc_channel_handle != SC_IPC_CH) {
  		printf("
  SCI error! Invalid handle
  ");
  	}
  
  	return 0;
  }
  
  #ifdef CONFIG_FSL_HSIO
  
  #define PCIE_PAD_CTRL	((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT))
  static iomux_cfg_t board_pcie_pins[] = {
  	SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
  	SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
  	SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
  };
  
  static void imx8qm_hsio_initialize(void)
  {
  	struct power_domain pd;
  	int ret;
  
  	if (!power_domain_lookup_name("hsio_sata0", &pd)) {
  		ret = power_domain_on(&pd);
  		if (ret)
  			printf("hsio_sata0 Power up failed! (error = %d)
  ", ret);
  	}
  
  	if (!power_domain_lookup_name("hsio_pcie0", &pd)) {
  		ret = power_domain_on(&pd);
  		if (ret)
  			printf("hsio_pcie0 Power up failed! (error = %d)
  ", ret);
  	}
  
  	if (!power_domain_lookup_name("hsio_pcie1", &pd)) {
  		ret = power_domain_on(&pd);
  		if (ret)
  			printf("hsio_pcie1 Power up failed! (error = %d)
  ", ret);
  	}

  	if (!power_domain_lookup_name("hsio_gpio", &pd)) {
  		ret = power_domain_on(&pd);
  		if (ret)
  			 printf("hsio_gpio Power up failed! (error = %d)
  ", ret);
  	}

  	LPCG_AllClockOn(HSIO_PCIE_X2_LPCG);
  	LPCG_AllClockOn(HSIO_PCIE_X1_LPCG);
  	LPCG_AllClockOn(HSIO_SATA_LPCG);
  	LPCG_AllClockOn(HSIO_PHY_X2_LPCG);
  	LPCG_AllClockOn(HSIO_PHY_X1_LPCG);
  	LPCG_AllClockOn(HSIO_PHY_X2_CRR0_LPCG);
  	LPCG_AllClockOn(HSIO_PHY_X1_CRR1_LPCG);
  	LPCG_AllClockOn(HSIO_PCIE_X2_CRR2_LPCG);
  	LPCG_AllClockOn(HSIO_PCIE_X1_CRR3_LPCG);
  	LPCG_AllClockOn(HSIO_SATA_CRR4_LPCG);
  	LPCG_AllClockOn(HSIO_MISC_LPCG);
  	LPCG_AllClockOn(HSIO_GPIO_LPCG);

  	imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins));
  }
  
  void pci_init_board(void)
  {
  	/* test the 1 lane mode of the PCIe A controller */
  	mx8qm_pcie_init();
  }
  #endif

  #ifdef CONFIG_USB

  #ifdef CONFIG_USB_TCPC

  #define USB_TYPEC_SEL IMX_GPIO_NR(4, 6)
  #define USB_TYPEC_EN IMX_GPIO_NR(4, 19)
  
  static iomux_cfg_t ss_mux_gpio[] = {
  	SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  	SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  };
  
  struct tcpc_port port;
  struct tcpc_port_config port_config = {
  	.i2c_bus = 0,
  	.addr = 0x51,
  	.port_type = TYPEC_PORT_DFP,
  };
  
  void ss_mux_select(enum typec_cc_polarity pol)
  {
  	if (pol == TYPEC_POLARITY_CC1)
  		gpio_direction_output(USB_TYPEC_SEL, 0);
  	else
  		gpio_direction_output(USB_TYPEC_SEL, 1);
  }
  
  static void setup_typec(void)
  {
  	imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
  	gpio_request(USB_TYPEC_SEL, "typec_sel");
  	gpio_request(USB_TYPEC_EN, "typec_en");
  
  	gpio_direction_output(USB_TYPEC_EN, 1);
  
  	tcpc_init(&port, port_config, &ss_mux_select);
  }

  #endif

  #ifdef CONFIG_USB_CDNS3_GADGET

  static struct cdns3_device cdns3_device_data = {
  	.none_core_base = 0x5B110000,
  	.xhci_base = 0x5B130000,
  	.dev_base = 0x5B140000,
  	.phy_base = 0x5B160000,
  	.otg_base = 0x5B120000,
  	.dr_mode = USB_DR_MODE_PERIPHERAL,
  	.index = 1,
  };

  int usb_gadget_handle_interrupts(int index)

  {

  	cdns3_uboot_handle_interrupt(index);

  	return 0;
  }

  #endif

  int board_usb_init(int index, enum usb_init_type init)
  {
  	int ret = 0;
  
  	if (index == 1) {
  		if (init == USB_INIT_HOST) {

  #ifdef CONFIG_USB_TCPC

  			ret = tcpc_setup_dfp_mode(&port);

  #endif

  #ifdef CONFIG_USB_CDNS3_GADGET

  		} else {

  #ifdef CONFIG_SPL_BUILD
  			sc_ipc_t ipcHndl = 0;
  
  			ipcHndl = gd->arch.ipc_channel_handle;
  
  			ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2, SC_PM_PW_MODE_ON);
  			if (ret != SC_ERR_NONE)
  				printf("conn_usb2 Power up failed! (error = %d)
  ", ret);
  
  			ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2_PHY, SC_PM_PW_MODE_ON);
  			if (ret != SC_ERR_NONE)
  				printf("conn_usb2_phy Power up failed! (error = %d)
  ", ret);
  #else

  			struct power_domain pd;
  			int ret;
  
  			/* Power on usb */
  			if (!power_domain_lookup_name("conn_usb2", &pd)) {
  				ret = power_domain_on(&pd);
  				if (ret)
  					printf("conn_usb2 Power up failed! (error = %d)
  ", ret);
  			}
  
  			if (!power_domain_lookup_name("conn_usb2_phy", &pd)) {
  				ret = power_domain_on(&pd);
  				if (ret)
  					printf("conn_usb2_phy Power up failed! (error = %d)
  ", ret);
  			}

  #endif

  #ifdef CONFIG_USB_TCPC

  			ret = tcpc_setup_ufp_mode(&port);
  			printf("%d setufp mode %d
  ", index, ret);

  #endif

  
  			ret = cdns3_uboot_init(&cdns3_device_data);
  			printf("%d cdns3_uboot_initmode %d
  ", index, ret);

  #endif

  		}
  	}
  	return ret;
  }
  
  int board_usb_cleanup(int index, enum usb_init_type init)
  {
  	int ret = 0;
  
  	if (index == 1) {
  		if (init == USB_INIT_HOST) {

  #ifdef CONFIG_USB_TCPC

  			ret = tcpc_disable_src_vbus(&port);

  #endif

  #ifdef CONFIG_USB_CDNS3_GADGET

  		} else {

  			cdns3_uboot_exit(1);
  
  #ifdef CONFIG_SPL_BUILD
  			sc_ipc_t ipcHndl = 0;
  
  			ipcHndl = gd->arch.ipc_channel_handle;
  
  			ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2, SC_PM_PW_MODE_OFF);
  			if (ret != SC_ERR_NONE)
  				printf("conn_usb2 Power down failed! (error = %d)
  ", ret);
  
  			ret = sc_pm_set_resource_power_mode(ipcHndl, SC_R_USB_2_PHY, SC_PM_PW_MODE_OFF);
  			if (ret != SC_ERR_NONE)
  				printf("conn_usb2_phy Power down failed! (error = %d)
  ", ret);
  #else

  			struct power_domain pd;
  			int ret;

  			/* Power off usb */
  			if (!power_domain_lookup_name("conn_usb2", &pd)) {
  				ret = power_domain_off(&pd);
  				if (ret)

  					printf("conn_usb2 Power down failed! (error = %d)
  ", ret);

  			}
  
  			if (!power_domain_lookup_name("conn_usb2_phy", &pd)) {
  				ret = power_domain_off(&pd);
  				if (ret)

  					printf("conn_usb2_phy Power down failed! (error = %d)
  ", ret);

  			}

  #endif

  #endif

  		}
  	}
  	return ret;
  }
  #endif
  
  int board_init(void)
  {

  	if (IS_ENABLED(CONFIG_XEN))
  		return 0;

  #ifdef CONFIG_MXC_GPIO
  	board_gpio_init();
  #endif
  
  #ifdef CONFIG_FSL_HSIO
  	imx8qm_hsio_initialize();
  #ifdef CONFIG_SCSI_AHCI_PLAT
  	sata_init();
  #endif
  #endif

  #if defined(CONFIG_USB_XHCI_IMX8) && defined(CONFIG_USB_TCPC)

  	setup_typec();
  #endif
  
  	return 0;
  }

  void board_quiesce_devices(void)
  {
  	const char *power_on_devices[] = {
  		"dma_lpuart0",
  	};

  	if (IS_ENABLED(CONFIG_XEN)) {
  		/* Clear magic number to let xen know uboot is over */
  		writel(0x0, (void __iomem *)0x80000000);

  		return;

  	}

  	power_off_pd_devices(power_on_devices, ARRAY_SIZE(power_on_devices));
  }

  void detail_board_ddr_info(void)
  {
  	puts("
  DDR    ");
  }
  
  /*
   * Board specific reset that is system reset.
   */
  void reset_cpu(ulong addr)
  {
  	puts("SCI reboot request");
  	sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD);
  	while (1)
  		putc('.');
  }
  
  #ifdef CONFIG_OF_BOARD_SETUP
  int ft_board_setup(void *blob, bd_t *bd)
  {
  	return 0;
  }
  #endif
  
  int board_mmc_get_env_dev(int devno)
  {

  	/* Use EMMC */
  	if (IS_ENABLED(CONFIG_XEN))
  		return 0;

  	return devno;
  }
  
  int mmc_map_to_kernel_blk(int dev_no)
  {

  	/* Use EMMC */
  	if (IS_ENABLED(CONFIG_XEN))
  		return 0;

  	return dev_no;
  }

  extern uint32_t _end_ofs;

  int board_late_init(void)
  {

  	char *fdt_file;
  	bool m4_boot;

  #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  	env_set("board_name", "MEK");
  	env_set("board_rev", "iMX8QM");
  #endif

  	env_set("sec_boot", "no");
  #ifdef CONFIG_AHAB_BOOT
  	env_set("sec_boot", "yes");
  #endif

  	fdt_file = env_get("fdt_file");
  	m4_boot = check_m4_parts_boot();
  
  	if (fdt_file && !strcmp(fdt_file, "undefined")) {
  		if (m4_boot)
  			env_set("fdt_file", "fsl-imx8qm-mek-rpmsg.dtb");
  		else
  			env_set("fdt_file", "fsl-imx8qm-mek.dtb");
  	}

  #ifdef CONFIG_ENV_IS_IN_MMC
  	board_late_mmc_env_init();
  #endif

  #ifdef IMX_LOAD_HDMI_FIMRWARE
  	char *end_of_uboot;
  	char command[256];
  	end_of_uboot = (char *)(ulong)(CONFIG_SYS_TEXT_BASE + _end_ofs + fdt_totalsize(gd->fdt_blob));
  	end_of_uboot += 9;

  	/* load hdmitxfw.bin and hdmirxfw.bin*/

  	memcpy((void *)IMX_HDMI_FIRMWARE_LOAD_ADDR, end_of_uboot,

  			IMX_HDMITX_FIRMWARE_SIZE + IMX_HDMIRX_FIRMWARE_SIZE);

  
  	sprintf(command, "hdp load 0x%x", IMX_HDMI_FIRMWARE_LOAD_ADDR);
  	run_command(command, 0);

  
  	sprintf(command, "hdprx load 0x%x",
  			IMX_HDMI_FIRMWARE_LOAD_ADDR + IMX_HDMITX_FIRMWARE_SIZE);
  	run_command(command, 0);

  #endif

  	return 0;
  }

  #ifdef CONFIG_FSL_FASTBOOT
  #ifdef CONFIG_ANDROID_RECOVERY
  int is_recovery_key_pressing(void)
  {
  	return 0; /*TODO*/
  }
  #endif /*CONFIG_ANDROID_RECOVERY*/
  #endif /*CONFIG_FSL_FASTBOOT*/

  #if defined(CONFIG_VIDEO_IMXDPUV1)
  static void enable_lvds(struct display_info_t const *dev)
  {
  	display_controller_setup((PS2KHZ(dev->mode.pixclock) * 1000));
  	lvds_soc_setup(dev->bus, (PS2KHZ(dev->mode.pixclock) * 1000));
  	lvds_configure(dev->bus);
  	lvds2hdmi_setup(6);
  }
  
  struct display_info_t const displays[] = {{
  	.bus	= 0, /* LVDS0 */
  	.addr	= 0, /* Unused */
  	.pixfmt	= IMXDPUV1_PIX_FMT_BGRA32,
  	.detect	= NULL,
  	.enable	= enable_lvds,
  	.mode	= {
  		.name           = "IT6263", /* 720P60 */
  		.refresh        = 60,
  		.xres           = 1280,
  		.yres           = 720,
  		.pixclock       = 13468, /* 74250000 */
  		.left_margin    = 110,
  		.right_margin   = 220,
  		.upper_margin   = 5,
  		.lower_margin   = 20,
  		.hsync_len      = 40,
  		.vsync_len      = 5,
  		.sync           = FB_SYNC_EXT,
  		.vmode          = FB_VMODE_NONINTERLACED
  } } };
  size_t display_count = ARRAY_SIZE(displays);
  
  #endif /* CONFIG_VIDEO_IMXDPUV1 */