Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit f8b0b8964d4b3606b170fffaedc30a861650de74

Authored by Ye Li
1 parent b785321d87
Exists in smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga and in 5 other branches smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga

MLK-18161-9 imx8qm_mek: Add i.MX8QM MEK board support 

Add board level codes and configs for i.MX8QM MEK board.

- Enabled DM driver:
  FEC, LPUART, LPI2C, GPIO, SD/MMC, FSPI, pinctrl, USB host(EHCI/XHCI)
  Power-domain, SC thermal

- Enabled Non-DM driver:
  SATA, PCIE, fuse, iomux, video(IMXDPUV1), USB device(CI-UDC)

- Disabled driver:
  mailbox

- Board defconfigs:
  imx8qm_mek_defconfig
  imx8qm_mek_fspi_defconfig

Signed-off-by: Ye Li <ye.li@nxp.com>

Showing 7 changed files with 905 additions and 0 deletions Side-by-side Diff

arch/arm/mach-imx/imx8/Kconfig
Diff comments   View file @ f8b0b89
... ... @@ -39,6 +39,11 @@
39 39 select BOARD_LATE_INIT
40 40 select IMX8QM
41 41  
  42 +config TARGET_IMX8QM_MEK
  43 + bool "Support i.MX8QM MEK board"
  44 + select BOARD_LATE_INIT
  45 + select IMX8QM
  46 +
42 47 config TARGET_IMX8QXP_LPDDR4_ARM2
43 48 bool "Support i.MX8QXP lpddr4 validation board"
44 49 select BOARD_LATE_INIT
... ... @@ -51,6 +56,7 @@
51 56  
52 57 endchoice
53 58 source "board/freescale/imx8qm_arm2/Kconfig"
  59 +source "board/freescale/imx8qm_mek/Kconfig"
54 60 source "board/freescale/imx8qxp_arm2/Kconfig"
55 61 endif
board/freescale/imx8qm_mek/Kconfig
Diff comments   View file @ f8b0b89
  1 +if TARGET_IMX8QM_MEK
  2 +
  3 +config SYS_BOARD
  4 + default "imx8qm_mek"
  5 +
  6 +config SYS_VENDOR
  7 + default "freescale"
  8 +
  9 +config SYS_CONFIG_NAME
  10 + default "imx8qm_mek"
  11 +
  12 +source "board/freescale/common/Kconfig"
  13 +
  14 +endif
board/freescale/imx8qm_mek/Makefile
Diff comments   View file @ f8b0b89
  1 +#
  2 +# Copyright 2017 NXP
  3 +#
  4 +# SPDX-License-Identifier: GPL-2.0+
  5 +#
  6 +
  7 +obj-y += imx8qm_mek.o
board/freescale/imx8qm_mek/imx8qm_mek.c
Diff comments   View file @ f8b0b89
  1 +/*
  2 + * Copyright 2017-2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +#include <common.h>
  7 +#include <malloc.h>
  8 +#include <errno.h>
  9 +#include <netdev.h>
  10 +#include <fsl_ifc.h>
  11 +#include <fdt_support.h>
  12 +#include <linux/libfdt.h>
  13 +#include <environment.h>
  14 +#include <fsl_esdhc.h>
  15 +#include <i2c.h>
  16 +
  17 +#include <asm/io.h>
  18 +#include <asm/gpio.h>
  19 +#include <asm/arch/clock.h>
  20 +#include <asm/mach-imx/sci/sci.h>
  21 +#include <asm/arch/imx8-pins.h>
  22 +#include <dm.h>
  23 +#include <imx8_hsio.h>
  24 +#include <usb.h>
  25 +#include <asm/arch/iomux.h>
  26 +#include <asm/arch/sys_proto.h>
  27 +#include <asm/mach-imx/video.h>
  28 +#include <asm/arch/video_common.h>
  29 +#include <power-domain.h>
  30 +#include "../common/tcpc.h"
  31 +
  32 +DECLARE_GLOBAL_DATA_PTR;
  33 +
  34 +#define ENET_INPUT_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  35 + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  36 +
  37 +#define ENET_NORMAL_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  38 + | (SC_PAD_28FDSOI_DSE_18V_10MA << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  39 +
  40 +#define FSPI_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  41 + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  42 +
  43 +#define GPIO_PAD_CTRL ((SC_PAD_CONFIG_NORMAL << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  44 + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  45 +
  46 +#define I2C_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  47 + | (SC_PAD_28FDSOI_DSE_DV_LOW << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  48 +
  49 +#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | (SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) \
  50 + | (SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | (SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
  51 +
  52 +static iomux_cfg_t uart0_pads[] = {
  53 + SC_P_UART0_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
  54 + SC_P_UART0_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
  55 +};
  56 +
  57 +static void setup_iomux_uart(void)
  58 +{
  59 + imx8_iomux_setup_multiple_pads(uart0_pads, ARRAY_SIZE(uart0_pads));
  60 +}
  61 +
  62 +int board_early_init_f(void)
  63 +{
  64 + sc_ipc_t ipcHndl = 0;
  65 + sc_err_t sciErr = 0;
  66 +
  67 + ipcHndl = gd->arch.ipc_channel_handle;
  68 +
  69 + /* Power up UART0, this is very early while power domain is not working */
  70 + sciErr = sc_pm_set_resource_power_mode(ipcHndl, SC_R_UART_0, SC_PM_PW_MODE_ON);
  71 + if (sciErr != SC_ERR_NONE)
  72 + return 0;
  73 +
  74 + /* Set UART0 clock root to 80 MHz */
  75 + sc_pm_clock_rate_t rate = 80000000;
  76 + sciErr = sc_pm_set_clock_rate(ipcHndl, SC_R_UART_0, 2, &rate);
  77 + if (sciErr != SC_ERR_NONE)
  78 + return 0;
  79 +
  80 + /* Enable UART0 clock root */
  81 + sciErr = sc_pm_clock_enable(ipcHndl, SC_R_UART_0, 2, true, false);
  82 + if (sciErr != SC_ERR_NONE)
  83 + return 0;
  84 +
  85 + setup_iomux_uart();
  86 +
  87 + return 0;
  88 +}
  89 +
  90 +#ifdef CONFIG_FEC_MXC
  91 +#include <miiphy.h>
  92 +
  93 +static iomux_cfg_t pad_enet1[] = {
  94 + SC_P_ENET1_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  95 + SC_P_ENET1_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  96 + SC_P_ENET1_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  97 + SC_P_ENET1_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  98 + SC_P_ENET1_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  99 + SC_P_ENET1_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  100 + SC_P_ENET1_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  101 + SC_P_ENET1_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  102 + SC_P_ENET1_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  103 + SC_P_ENET1_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  104 + SC_P_ENET1_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  105 + SC_P_ENET1_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  106 +
  107 + /* Shared MDIO */
  108 + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  109 + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  110 +};
  111 +
  112 +static iomux_cfg_t pad_enet0[] = {
  113 + SC_P_ENET0_RGMII_RX_CTL | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  114 + SC_P_ENET0_RGMII_RXD0 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  115 + SC_P_ENET0_RGMII_RXD1 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  116 + SC_P_ENET0_RGMII_RXD2 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  117 + SC_P_ENET0_RGMII_RXD3 | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  118 + SC_P_ENET0_RGMII_RXC | MUX_PAD_CTRL(ENET_INPUT_PAD_CTRL),
  119 + SC_P_ENET0_RGMII_TX_CTL | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  120 + SC_P_ENET0_RGMII_TXD0 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  121 + SC_P_ENET0_RGMII_TXD1 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  122 + SC_P_ENET0_RGMII_TXD2 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  123 + SC_P_ENET0_RGMII_TXD3 | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  124 + SC_P_ENET0_RGMII_TXC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  125 +
  126 + /* Shared MDIO */
  127 + SC_P_ENET0_MDC | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  128 + SC_P_ENET0_MDIO | MUX_PAD_CTRL(ENET_NORMAL_PAD_CTRL),
  129 +};
  130 +
  131 +static void setup_iomux_fec(void)
  132 +{
  133 + if (0 == CONFIG_FEC_ENET_DEV)
  134 + imx8_iomux_setup_multiple_pads(pad_enet0, ARRAY_SIZE(pad_enet0));
  135 + else
  136 + imx8_iomux_setup_multiple_pads(pad_enet1, ARRAY_SIZE(pad_enet1));
  137 +}
  138 +
  139 +int board_eth_init(bd_t *bis)
  140 +{
  141 + int ret;
  142 + struct power_domain pd;
  143 +
  144 + printf("[%s] %d\n", __func__, __LINE__);
  145 +
  146 + if (CONFIG_FEC_ENET_DEV) {
  147 + if (!power_domain_lookup_name("conn_enet1", &pd))
  148 + power_domain_on(&pd);
  149 + } else {
  150 + if (!power_domain_lookup_name("conn_enet0", &pd))
  151 + power_domain_on(&pd);
  152 + }
  153 +
  154 + setup_iomux_fec();
  155 +
  156 + ret = fecmxc_initialize_multi(bis, CONFIG_FEC_ENET_DEV,
  157 + CONFIG_FEC_MXC_PHYADDR, IMX_FEC_BASE);
  158 + if (ret)
  159 + printf("FEC1 MXC: %s:failed\n", __func__);
  160 +
  161 + return ret;
  162 +}
  163 +
  164 +int board_phy_config(struct phy_device *phydev)
  165 +{
  166 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f);
  167 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8);
  168 +
  169 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x00);
  170 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x82ee);
  171 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05);
  172 + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100);
  173 +
  174 + if (phydev->drv->config)
  175 + phydev->drv->config(phydev);
  176 +
  177 + return 0;
  178 +}
  179 +#endif
  180 +
  181 +#ifdef CONFIG_MXC_GPIO
  182 +
  183 +#define LVDS_ENABLE IMX_GPIO_NR(1, 6)
  184 +#define MIPI_ENABLE IMX_GPIO_NR(1, 7)
  185 +
  186 +#define BB_GPIO_3V3_1 IMX_GPIO_NR(4, 20)
  187 +#define BB_GPIO_3V3_2 IMX_GPIO_NR(4, 24)
  188 +#define BB_GPIO_3V3_3 IMX_GPIO_NR(4, 23)
  189 +
  190 +static void board_gpio_init(void)
  191 +{
  192 + /* Enable BB 3V3 */
  193 + gpio_request(BB_GPIO_3V3_1, "bb_3v3_1");
  194 + gpio_direction_output(BB_GPIO_3V3_1, 1);
  195 + gpio_request(BB_GPIO_3V3_2, "bb_3v3_2");
  196 + gpio_direction_output(BB_GPIO_3V3_2, 1);
  197 + gpio_request(BB_GPIO_3V3_3, "bb_3v3_3");
  198 + gpio_direction_output(BB_GPIO_3V3_3, 1);
  199 +
  200 + /* enable LVDS SAS boards */
  201 + gpio_request(LVDS_ENABLE, "lvds_enable");
  202 + gpio_direction_output(LVDS_ENABLE, 1);
  203 +
  204 + /* enable MIPI SAS boards */
  205 + gpio_request(MIPI_ENABLE, "mipi_enable");
  206 + gpio_direction_output(MIPI_ENABLE, 1);
  207 +}
  208 +#endif
  209 +
  210 +int checkboard(void)
  211 +{
  212 + puts("Board: iMX8QM MEK\n");
  213 +
  214 + print_bootinfo();
  215 +
  216 + /* Note: After reloc, ipcHndl will no longer be valid. If handle
  217 + * returned by sc_ipc_open matches SC_IPC_CH, use this
  218 + * macro (valid after reloc) for subsequent SCI calls.
  219 + */
  220 + if (gd->arch.ipc_channel_handle != SC_IPC_CH) {
  221 + printf("\nSCI error! Invalid handle\n");
  222 + }
  223 +
  224 + return 0;
  225 +}
  226 +
  227 +#ifdef CONFIG_FSL_HSIO
  228 +
  229 +#define PCIE_PAD_CTRL ((SC_PAD_CONFIG_OD_IN << PADRING_CONFIG_SHIFT))
  230 +static iomux_cfg_t board_pcie_pins[] = {
  231 + SC_P_PCIE_CTRL0_CLKREQ_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
  232 + SC_P_PCIE_CTRL0_WAKE_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
  233 + SC_P_PCIE_CTRL0_PERST_B | MUX_MODE_ALT(0) | MUX_PAD_CTRL(PCIE_PAD_CTRL),
  234 +};
  235 +
  236 +static void imx8qm_hsio_initialize(void)
  237 +{
  238 + struct power_domain pd;
  239 + int ret;
  240 +
  241 + if (!power_domain_lookup_name("hsio_sata0", &pd)) {
  242 + ret = power_domain_on(&pd);
  243 + if (ret)
  244 + printf("hsio_sata0 Power up failed! (error = %d)\n", ret);
  245 + }
  246 +
  247 + if (!power_domain_lookup_name("hsio_pcie0", &pd)) {
  248 + ret = power_domain_on(&pd);
  249 + if (ret)
  250 + printf("hsio_pcie0 Power up failed! (error = %d)\n", ret);
  251 + }
  252 +
  253 + if (!power_domain_lookup_name("hsio_pcie1", &pd)) {
  254 + ret = power_domain_on(&pd);
  255 + if (ret)
  256 + printf("hsio_pcie1 Power up failed! (error = %d)\n", ret);
  257 + }
  258 +
  259 + imx8_iomux_setup_multiple_pads(board_pcie_pins, ARRAY_SIZE(board_pcie_pins));
  260 +}
  261 +
  262 +void pci_init_board(void)
  263 +{
  264 + /* test the 1 lane mode of the PCIe A controller */
  265 + mx8qm_pcie_init();
  266 +}
  267 +#endif
  268 +
  269 +#ifdef CONFIG_USB_XHCI_IMX8
  270 +
  271 +#define USB_TYPEC_SEL IMX_GPIO_NR(4, 6)
  272 +#define USB_TYPEC_EN IMX_GPIO_NR(4, 19)
  273 +
  274 +static iomux_cfg_t ss_mux_gpio[] = {
  275 + SC_P_USB_SS3_TC3 | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  276 + SC_P_QSPI1A_SS0_B | MUX_MODE_ALT(3) | MUX_PAD_CTRL(GPIO_PAD_CTRL),
  277 +};
  278 +
  279 +struct tcpc_port port;
  280 +struct tcpc_port_config port_config = {
  281 + .i2c_bus = 0,
  282 + .addr = 0x51,
  283 + .port_type = TYPEC_PORT_DFP,
  284 +};
  285 +
  286 +void ss_mux_select(enum typec_cc_polarity pol)
  287 +{
  288 + if (pol == TYPEC_POLARITY_CC1)
  289 + gpio_direction_output(USB_TYPEC_SEL, 0);
  290 + else
  291 + gpio_direction_output(USB_TYPEC_SEL, 1);
  292 +}
  293 +
  294 +static void setup_typec(void)
  295 +{
  296 + imx8_iomux_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio));
  297 + gpio_request(USB_TYPEC_SEL, "typec_sel");
  298 + gpio_request(USB_TYPEC_EN, "typec_en");
  299 +
  300 + gpio_direction_output(USB_TYPEC_EN, 1);
  301 +
  302 + tcpc_init(&port, port_config, &ss_mux_select);
  303 +}
  304 +
  305 +int board_usb_init(int index, enum usb_init_type init)
  306 +{
  307 + int ret = 0;
  308 +
  309 + if (index == 1) {
  310 + if (init == USB_INIT_HOST) {
  311 + ret = tcpc_setup_dfp_mode(&port);
  312 + }
  313 + }
  314 + return ret;
  315 +}
  316 +
  317 +int board_usb_cleanup(int index, enum usb_init_type init)
  318 +{
  319 + int ret = 0;
  320 +
  321 + if (index == 1) {
  322 + if (init == USB_INIT_HOST) {
  323 + ret = tcpc_disable_src_vbus(&port);
  324 + }
  325 + }
  326 + return ret;
  327 +}
  328 +#endif
  329 +
  330 +int board_init(void)
  331 +{
  332 + /* Power up base board */
  333 + sc_pm_set_resource_power_mode(gd->arch.ipc_channel_handle,
  334 + SC_R_BOARD_R1, SC_PM_PW_MODE_ON);
  335 +
  336 +#ifdef CONFIG_MXC_GPIO
  337 + board_gpio_init();
  338 +#endif
  339 +
  340 +#ifdef CONFIG_FSL_HSIO
  341 + imx8qm_hsio_initialize();
  342 +#ifdef CONFIG_SCSI_AHCI_PLAT
  343 + sata_init();
  344 +#endif
  345 +#endif
  346 +
  347 +#ifdef CONFIG_USB_XHCI_IMX8
  348 + setup_typec();
  349 +#endif
  350 +
  351 + return 0;
  352 +}
  353 +
  354 +void detail_board_ddr_info(void)
  355 +{
  356 + puts("\nDDR ");
  357 +}
  358 +
  359 +/*
  360 + * Board specific reset that is system reset.
  361 + */
  362 +void reset_cpu(ulong addr)
  363 +{
  364 + puts("SCI reboot request");
  365 + sc_pm_reboot(SC_IPC_CH, SC_PM_RESET_TYPE_COLD);
  366 + while (1)
  367 + putc('.');
  368 +}
  369 +
  370 +#ifdef CONFIG_OF_BOARD_SETUP
  371 +int ft_board_setup(void *blob, bd_t *bd)
  372 +{
  373 + return 0;
  374 +}
  375 +#endif
  376 +
  377 +int board_mmc_get_env_dev(int devno)
  378 +{
  379 + return devno;
  380 +}
  381 +
  382 +int mmc_map_to_kernel_blk(int dev_no)
  383 +{
  384 + return dev_no;
  385 +}
  386 +
  387 +int board_late_init(void)
  388 +{
  389 +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  390 + env_set("board_name", "MEK");
  391 + env_set("board_rev", "iMX8QM");
  392 +#endif
  393 +
  394 +#ifdef CONFIG_ENV_IS_IN_MMC
  395 + board_late_mmc_env_init();
  396 +#endif
  397 +
  398 + return 0;
  399 +}
  400 +
  401 +#if defined(CONFIG_VIDEO_IMXDPUV1)
  402 +static void enable_lvds(struct display_info_t const *dev)
  403 +{
  404 + display_controller_setup((PS2KHZ(dev->mode.pixclock) * 1000));
  405 + lvds_soc_setup(dev->bus, (PS2KHZ(dev->mode.pixclock) * 1000));
  406 + lvds_configure(dev->bus);
  407 + lvds2hdmi_setup(6);
  408 +}
  409 +
  410 +struct display_info_t const displays[] = {{
  411 + .bus = 0, /* LVDS0 */
  412 + .addr = 0, /* Unused */
  413 + .pixfmt = IMXDPUV1_PIX_FMT_BGRA32,
  414 + .detect = NULL,
  415 + .enable = enable_lvds,
  416 + .mode = {
  417 + .name = "IT6263", /* 720P60 */
  418 + .refresh = 60,
  419 + .xres = 1280,
  420 + .yres = 720,
  421 + .pixclock = 13468, /* 74250000 */
  422 + .left_margin = 110,
  423 + .right_margin = 220,
  424 + .upper_margin = 5,
  425 + .lower_margin = 20,
  426 + .hsync_len = 40,
  427 + .vsync_len = 5,
  428 + .sync = FB_SYNC_EXT,
  429 + .vmode = FB_VMODE_NONINTERLACED
  430 +} } };
  431 +size_t display_count = ARRAY_SIZE(displays);
  432 +
  433 +#endif /* CONFIG_VIDEO_IMXDPUV1 */
configs/imx8qm_mek_defconfig
Diff comments   View file @ f8b0b89
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_IMX8=y
  3 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
  4 +CONFIG_TARGET_IMX8QM_MEK=y
  5 +CONFIG_SYS_TEXT_BASE=0x80020000
  6 +CONFIG_CMD_IMPORTENV=n
  7 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  8 +CONFIG_DM=y
  9 +CONFIG_CMD_CACHE=y
  10 +
  11 +CONFIG_DM_SERIAL=y
  12 +CONFIG_FSL_LPUART=y
  13 +CONFIG_OF_CONTROL=y
  14 +CONFIG_DM_I2C=y
  15 +# CONFIG_DM_I2C_COMPAT is not set
  16 +CONFIG_SYS_I2C_IMX_LPI2C=y
  17 +CONFIG_CMD_I2C=y
  18 +
  19 +CONFIG_USB_XHCI_HCD=y
  20 +CONFIG_USB_XHCI_IMX8=y
  21 +
  22 +CONFIG_DM_USB=y
  23 +CONFIG_USB_EHCI_HCD=y
  24 +
  25 +CONFIG_CMD_USB=y
  26 +CONFIG_USB=y
  27 +CONFIG_USB_STORAGE=y
  28 +CONFIG_USB_TCPC=y
  29 +
  30 +CONFIG_CMD_USB_MASS_STORAGE=y
  31 +CONFIG_USB_GADGET=y
  32 +CONFIG_CI_UDC=y
  33 +CONFIG_USB_GADGET_DOWNLOAD=y
  34 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  35 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  36 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  37 +
  38 +CONFIG_CMD_GPIO=y
  39 +CONFIG_DM_GPIO=y
  40 +CONFIG_DM_PCA953X=y
  41 +CONFIG_BOOTDELAY=3
  42 +CONFIG_IMX_BOOTAUX=y
  43 +CONFIG_FS_FAT=y
  44 +CONFIG_CMD_FAT=y
  45 +CONFIG_CMD_MMC=y
  46 +CONFIG_DM_MMC=y
  47 +CONFIG_FSL_FSPI=y
  48 +CONFIG_DM_SPI=y
  49 +CONFIG_DM_SPI_FLASH=y
  50 +CONFIG_SPI_FLASH=y
  51 +CONFIG_SPI_FLASH_4BYTES_ADDR=y
  52 +CONFIG_SPI_FLASH_STMICRO=y
  53 +CONFIG_CMD_SF=y
  54 +
  55 +CONFIG_CMD_PING=y
  56 +CONFIG_CMD_DHCP=y
  57 +CONFIG_CMD_MII=y
  58 +CONFIG_DM_ETH=y
  59 +# CONFIG_EFI_LOADER is not set
  60 +
  61 +CONFIG_DM_REGULATOR=y
  62 +CONFIG_DM_REGULATOR_FIXED=y
  63 +CONFIG_DM_REGULATOR_GPIO=y
  64 +
  65 +CONFIG_VIDEO=y
  66 +
  67 +CONFIG_PINCTRL=y
  68 +CONFIG_PINCTRL_IMX8=y
  69 +
  70 +CONFIG_POWER_DOMAIN=y
  71 +CONFIG_IMX8_POWER_DOMAIN=y
  72 +
  73 +CONFIG_DM_THERMAL=y
  74 +CONFIG_IMX_SC_THERMAL=y
  75 +
  76 +CONFIG_ENV_IS_IN_MMC=y
configs/imx8qm_mek_fspi_defconfig
Diff comments   View file @ f8b0b89
  1 +CONFIG_ARM=y
  2 +CONFIG_ARCH_IMX8=y
  3 +CONFIG_DEFAULT_DEVICE_TREE="fsl-imx8qm-mek"
  4 +CONFIG_TARGET_IMX8QM_MEK=y
  5 +CONFIG_SYS_TEXT_BASE=0x80020000
  6 +CONFIG_CMD_IMPORTENV=n
  7 +CONFIG_SYS_MALLOC_F_LEN=0x2000
  8 +CONFIG_DM=y
  9 +CONFIG_CMD_CACHE=y
  10 +
  11 +CONFIG_DM_SERIAL=y
  12 +CONFIG_FSL_LPUART=y
  13 +CONFIG_OF_CONTROL=y
  14 +CONFIG_DM_I2C=y
  15 +# CONFIG_DM_I2C_COMPAT is not set
  16 +CONFIG_SYS_I2C_IMX_LPI2C=y
  17 +CONFIG_CMD_I2C=y
  18 +
  19 +CONFIG_USB_XHCI_HCD=y
  20 +CONFIG_USB_XHCI_IMX8=y
  21 +
  22 +CONFIG_DM_USB=y
  23 +CONFIG_USB_EHCI_HCD=y
  24 +
  25 +CONFIG_CMD_USB=y
  26 +CONFIG_USB=y
  27 +CONFIG_USB_STORAGE=y
  28 +CONFIG_USB_TCPC=y
  29 +
  30 +CONFIG_CMD_USB_MASS_STORAGE=y
  31 +CONFIG_USB_GADGET=y
  32 +CONFIG_CI_UDC=y
  33 +CONFIG_USB_GADGET_DOWNLOAD=y
  34 +CONFIG_USB_GADGET_MANUFACTURER="FSL"
  35 +CONFIG_USB_GADGET_VENDOR_NUM=0x0525
  36 +CONFIG_USB_GADGET_PRODUCT_NUM=0xa4a5
  37 +
  38 +CONFIG_CMD_GPIO=y
  39 +CONFIG_DM_GPIO=y
  40 +CONFIG_DM_PCA953X=y
  41 +CONFIG_BOOTDELAY=3
  42 +CONFIG_IMX_BOOTAUX=y
  43 +CONFIG_FS_FAT=y
  44 +CONFIG_CMD_FAT=y
  45 +CONFIG_CMD_MMC=y
  46 +CONFIG_DM_MMC=y
  47 +CONFIG_QSPI_BOOT=y
  48 +CONFIG_FSL_FSPI=y
  49 +CONFIG_DM_SPI=y
  50 +CONFIG_DM_SPI_FLASH=y
  51 +CONFIG_SPI_FLASH=y
  52 +CONFIG_SPI_FLASH_4BYTES_ADDR=y
  53 +CONFIG_SPI_FLASH_STMICRO=y
  54 +CONFIG_CMD_SF=y
  55 +
  56 +CONFIG_CMD_PING=y
  57 +CONFIG_CMD_DHCP=y
  58 +CONFIG_CMD_MII=y
  59 +CONFIG_DM_ETH=y
  60 +# CONFIG_EFI_LOADER is not set
  61 +
  62 +CONFIG_DM_REGULATOR=y
  63 +CONFIG_DM_REGULATOR_FIXED=y
  64 +CONFIG_DM_REGULATOR_GPIO=y
  65 +
  66 +CONFIG_VIDEO=y
  67 +
  68 +CONFIG_PINCTRL=y
  69 +CONFIG_PINCTRL_IMX8=y
  70 +
  71 +CONFIG_POWER_DOMAIN=y
  72 +CONFIG_IMX8_POWER_DOMAIN=y
  73 +
  74 +CONFIG_DM_THERMAL=y
  75 +CONFIG_IMX_SC_THERMAL=y
  76 +
  77 +CONFIG_ENV_IS_IN_SPI_FLASH=y
include/configs/imx8qm_mek.h
Diff comments   View file @ f8b0b89
  1 +/*
  2 + * Copyright 2017-2018 NXP
  3 + *
  4 + * SPDX-License-Identifier: GPL-2.0+
  5 + */
  6 +
  7 +#ifndef __IMX8QM_MEK_H
  8 +#define __IMX8QM_MEK_H
  9 +
  10 +#include <linux/sizes.h>
  11 +#include <asm/arch/imx-regs.h>
  12 +
  13 +#define CONFIG_REMAKE_ELF
  14 +
  15 +#define CONFIG_BOARD_EARLY_INIT_F
  16 +#define CONFIG_ARCH_MISC_INIT
  17 +
  18 +/* Flat Device Tree Definitions */
  19 +#define CONFIG_OF_BOARD_SETUP
  20 +
  21 +#undef CONFIG_CMD_EXPORTENV
  22 +#undef CONFIG_CMD_IMPORTENV
  23 +#undef CONFIG_CMD_IMLS
  24 +
  25 +#undef CONFIG_CMD_CRC32
  26 +#undef CONFIG_BOOTM_NETBSD
  27 +
  28 +#define CONFIG_FSL_ESDHC
  29 +#define CONFIG_FSL_USDHC
  30 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0
  31 +#define USDHC1_BASE_ADDR 0x5B010000
  32 +#define USDHC2_BASE_ADDR 0x5B020000
  33 +#define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */
  34 +
  35 +#define CONFIG_ENV_OVERWRITE
  36 +
  37 +#define CONFIG_SCSI
  38 +#define CONFIG_SCSI_AHCI
  39 +#define CONFIG_SCSI_AHCI_PLAT
  40 +#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
  41 +#define CONFIG_CMD_SCSI
  42 +#define CONFIG_LIBATA
  43 +#define CONFIG_SYS_SCSI_MAX_LUN 1
  44 +#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
  45 +#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
  46 +#define CONFIG_SYS_SATA_MAX_DEVICE 1
  47 +#define CONFIG_SATA_IMX
  48 +
  49 +#define CONFIG_FSL_HSIO
  50 +#define CONFIG_PCIE_IMX8X
  51 +#define CONFIG_CMD_PCI
  52 +#define CONFIG_PCI
  53 +#define CONFIG_PCI_PNP
  54 +#define CONFIG_PCI_SCAN_SHOW
  55 +
  56 +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  57 +/* FUSE command */
  58 +#define CONFIG_CMD_FUSE
  59 +
  60 +/* GPIO configs */
  61 +#define CONFIG_MXC_GPIO
  62 +
  63 +/* ENET Config */
  64 +#define CONFIG_MII
  65 +
  66 +#define CONFIG_FEC_MXC
  67 +#define CONFIG_FEC_XCV_TYPE RGMII
  68 +#define FEC_QUIRK_ENET_MAC
  69 +
  70 +#define CONFIG_PHY_GIGE /* Support for 1000BASE-X */
  71 +#define CONFIG_PHYLIB
  72 +#define CONFIG_PHY_ATHEROS
  73 +
  74 +/* ENET0 connects AR8031 on CPU board, ENET1 connects to base board */
  75 +#define CONFIG_FEC_ENET_DEV 0
  76 +
  77 +#if (CONFIG_FEC_ENET_DEV == 0)
  78 +#define IMX_FEC_BASE 0x5B040000
  79 +#define CONFIG_FEC_MXC_PHYADDR 0x0
  80 +#define CONFIG_ETHPRIME "eth0"
  81 +#elif (CONFIG_FEC_ENET_DEV == 1)
  82 +#define IMX_FEC_BASE 0x5B050000
  83 +#define CONFIG_FEC_MXC_PHYADDR 0x1
  84 +#define CONFIG_ETHPRIME "eth1"
  85 +#endif
  86 +
  87 +/* ENET0 MDIO are shared */
  88 +#define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000
  89 +
  90 +#define CONFIG_LIB_RAND
  91 +#define CONFIG_NET_RANDOM_ETHADDR
  92 +
  93 +/* Boot M4 */
  94 +#define M4_BOOT_ENV \
  95 + "m4_0_image=m4_0.bin\0" \
  96 + "m4_1_image=m4_1.bin\0" \
  97 + "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \
  98 + "loadm4image_1=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_1_image}\0" \
  99 + "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  100 + "m4boot_1=run loadm4image_1; dcache flush; bootaux ${loadaddr} 1\0" \
  101 +
  102 +#ifdef CONFIG_NAND_BOOT
  103 +#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(boot),32m(kernel),16m(dtb),8m(misc),-(rootfs) "
  104 +#else
  105 +#define MFG_NAND_PARTITION ""
  106 +#endif
  107 +
  108 +#define CONFIG_MFG_ENV_SETTINGS \
  109 + "mfgtool_args=setenv bootargs console=${console},${baudrate} " \
  110 + "rdinit=/linuxrc " \
  111 + "g_mass_storage.stall=0 g_mass_storage.removable=1 " \
  112 + "g_mass_storage.idVendor=0x066F g_mass_storage.idProduct=0x37FF "\
  113 + "g_mass_storage.iSerialNumber=\"\" "\
  114 + MFG_NAND_PARTITION \
  115 + "clk_ignore_unused "\
  116 + "\0" \
  117 + "initrd_addr=0x83800000\0" \
  118 + "initrd_high=0xffffffff\0" \
  119 + "bootcmd_mfg=run mfgtool_args;booti ${loadaddr} ${initrd_addr} ${fdt_addr};\0" \
  120 +
  121 +/* Initial environment variables */
  122 +#define CONFIG_EXTRA_ENV_SETTINGS \
  123 + CONFIG_MFG_ENV_SETTINGS \
  124 + M4_BOOT_ENV \
  125 + "script=boot.scr\0" \
  126 + "image=Image\0" \
  127 + "panel=NULL\0" \
  128 + "console=ttyLP0,${baudrate} earlycon=lpuart32,0x5a060000,${baudrate}\0" \
  129 + "fdt_addr=0x83000000\0" \
  130 + "fdt_high=0xffffffffffffffff\0" \
  131 + "boot_fdt=try\0" \
  132 + "fdt_file=fsl-imx8qm-mek.dtb\0" \
  133 + "initrd_addr=0x83800000\0" \
  134 + "initrd_high=0xffffffffffffffff\0" \
  135 + "mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \
  136 + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \
  137 + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
  138 + "mmcautodetect=yes\0" \
  139 + "mmcargs=setenv bootargs console=${console} root=${mmcroot}\0 " \
  140 + "loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
  141 + "bootscript=echo Running bootscript from mmc ...; " \
  142 + "source\0" \
  143 + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
  144 + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
  145 + "mmcboot=echo Booting from mmc ...; " \
  146 + "run mmcargs; " \
  147 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  148 + "if run loadfdt; then " \
  149 + "booti ${loadaddr} - ${fdt_addr}; " \
  150 + "else " \
  151 + "echo WARN: Cannot load the DT; " \
  152 + "fi; " \
  153 + "else " \
  154 + "echo wait for boot; " \
  155 + "fi;\0" \
  156 + "netargs=setenv bootargs console=${console} " \
  157 + "root=/dev/nfs " \
  158 + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
  159 + "netboot=echo Booting from net ...; " \
  160 + "run netargs; " \
  161 + "if test ${ip_dyn} = yes; then " \
  162 + "setenv get_cmd dhcp; " \
  163 + "else " \
  164 + "setenv get_cmd tftp; " \
  165 + "fi; " \
  166 + "${get_cmd} ${loadaddr} ${image}; " \
  167 + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
  168 + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
  169 + "booti ${loadaddr} - ${fdt_addr}; " \
  170 + "else " \
  171 + "echo WARN: Cannot load the DT; " \
  172 + "fi; " \
  173 + "else " \
  174 + "booti; " \
  175 + "fi;\0"
  176 +
  177 +#define CONFIG_BOOTCOMMAND \
  178 + "mmc dev ${mmcdev}; if mmc rescan; then " \
  179 + "if run loadbootscript; then " \
  180 + "run bootscript; " \
  181 + "else " \
  182 + "if run loadimage; then " \
  183 + "run mmcboot; " \
  184 + "else run netboot; " \
  185 + "fi; " \
  186 + "fi; " \
  187 + "else booti ${loadaddr} - ${fdt_addr}; fi"
  188 +
  189 +/* Link Definitions */
  190 +#define CONFIG_LOADADDR 0x80280000
  191 +
  192 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
  193 +
  194 +#define CONFIG_SYS_INIT_SP_ADDR 0x80200000
  195 +
  196 +
  197 +/* Default environment is in SD */
  198 +#define CONFIG_ENV_SIZE 0x1000
  199 +
  200 +#ifdef CONFIG_QSPI_BOOT
  201 +#define CONFIG_ENV_OFFSET (4 * 1024 * 1024)
  202 +#define CONFIG_ENV_SECT_SIZE (128 * 1024)
  203 +#define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS
  204 +#define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS
  205 +#define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE
  206 +#define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED
  207 +#else
  208 +#define CONFIG_ENV_OFFSET (64 * SZ_64K)
  209 +#define CONFIG_SYS_MMC_ENV_PART 0 /* user area */
  210 +#endif
  211 +
  212 +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1
  213 +
  214 +#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */
  215 +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */
  216 +#define CONFIG_SYS_FSL_USDHC_NUM 2
  217 +
  218 +
  219 +/* Size of malloc() pool */
  220 +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024)
  221 +
  222 +#define CONFIG_SYS_SDRAM_BASE 0x80000000
  223 +#define CONFIG_NR_DRAM_BANKS 3
  224 +#define PHYS_SDRAM_1 0x80000000
  225 +#define PHYS_SDRAM_2 0x880000000
  226 +#define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */
  227 +#define PHYS_SDRAM_2_SIZE 0x100000000 /* 4 GB */
  228 +
  229 +/* Serial */
  230 +#define CONFIG_BAUDRATE 115200
  231 +
  232 +/* Monitor Command Prompt */
  233 +#define CONFIG_HUSH_PARSER
  234 +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  235 +#define CONFIG_SYS_CBSIZE 2048
  236 +#define CONFIG_SYS_MAXARGS 64
  237 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
  238 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  239 + sizeof(CONFIG_SYS_PROMPT) + 16)
  240 +
  241 +/* Generic Timer Definitions */
  242 +#define COUNTER_FREQUENCY 8000000 /* 8MHz */
  243 +
  244 +#define CONFIG_IMX_SMMU
  245 +
  246 +/* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */
  247 +#ifdef CONFIG_FSL_FSPI
  248 +#define CONFIG_SF_DEFAULT_BUS 0
  249 +#define CONFIG_SF_DEFAULT_CS 0
  250 +#define CONFIG_SF_DEFAULT_SPEED 40000000
  251 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
  252 +#define FSL_FSPI_FLASH_SIZE SZ_64M
  253 +#define FSL_FSPI_FLASH_NUM 1
  254 +#define FSPI0_BASE_ADDR 0x5d120000
  255 +#define FSPI0_AMBA_BASE 0
  256 +#define CONFIG_SYS_FSL_FSPI_AHB
  257 +#endif
  258 +
  259 +/* USB Config */
  260 +#ifdef CONFIG_CMD_USB
  261 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2
  262 +
  263 +/* USB OTG controller configs */
  264 +#ifdef CONFIG_USB_EHCI_HCD
  265 +#define CONFIG_USB_HOST_ETHER
  266 +#define CONFIG_USB_ETHER_ASIX
  267 +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
  268 +#endif
  269 +#endif /* CONFIG_CMD_USB */
  270 +
  271 +#ifdef CONFIG_USB_GADGET
  272 +#define CONFIG_USBD_HS
  273 +#endif
  274 +
  275 +/* Framebuffer */
  276 +#ifdef CONFIG_VIDEO
  277 +#define CONFIG_VIDEO_IMXDPUV1
  278 +#define CONFIG_VIDEO_BMP_RLE8
  279 +#define CONFIG_SPLASH_SCREEN
  280 +#define CONFIG_SPLASH_SCREEN_ALIGN
  281 +#define CONFIG_BMP_16BPP
  282 +#define CONFIG_VIDEO_LOGO
  283 +#define CONFIG_VIDEO_BMP_LOGO
  284 +#define CONFIG_IMX_VIDEO_SKIP
  285 +#endif
  286 +
  287 +#define CONFIG_OF_SYSTEM_SETUP
  288 +#define BOOTAUX_RESERVED_MEM_BASE 0x88000000
  289 +#define BOOTAUX_RESERVED_MEM_SIZE 0x08000000 /* Reserve from second 128MB */
  290 +
  291 +
  292 +#endif /* __IMX8QM_MEK_H */