Blame view
drivers/pinctrl/pinctrl-at91-pio4.c
4.33 KB
83d290c56
|
1 |
// SPDX-License-Identifier: GPL-2.0+ |
ac72e174f
|
2 3 4 5 6 |
/* * Atmel PIO4 pinctrl driver * * Copyright (C) 2016 Atmel Corporation * Wenyou.Yang <wenyou.yang@atmel.com> |
ac72e174f
|
7 8 9 |
*/ #include <common.h> |
9d922450a
|
10 |
#include <dm.h> |
ac72e174f
|
11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 |
#include <dm/pinctrl.h> #include <linux/io.h> #include <linux/err.h> #include <mach/atmel_pio4.h> DECLARE_GLOBAL_DATA_PTR; /* * Warning: * In order to not introduce confusion between Atmel PIO groups and pinctrl * framework groups, Atmel PIO groups will be called banks. */ struct atmel_pio4_platdata { struct atmel_pio4_port *reg_base; }; static const struct pinconf_param conf_params[] = { { "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 }, { "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 }, { "bias-pull-down", PIN_CONFIG_BIAS_PULL_DOWN, 1 }, { "drive-open-drain", PIN_CONFIG_DRIVE_OPEN_DRAIN, 0 }, { "input-schmitt-disable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 0 }, { "input-schmitt-enable", PIN_CONFIG_INPUT_SCHMITT_ENABLE, 1 }, { "input-debounce", PIN_CONFIG_INPUT_DEBOUNCE, 0 }, }; static u32 atmel_pinctrl_get_pinconf(const void *blob, int node) { const struct pinconf_param *params; u32 param, arg, conf = 0; u32 i; for (i = 0; i < ARRAY_SIZE(conf_params); i++) { params = &conf_params[i]; if (!fdt_get_property(blob, node, params->property, NULL)) continue; param = params->param; arg = params->default_value; switch (param) { case PIN_CONFIG_BIAS_DISABLE: conf &= (~ATMEL_PIO_PUEN_MASK); conf &= (~ATMEL_PIO_PDEN_MASK); break; case PIN_CONFIG_BIAS_PULL_UP: conf |= ATMEL_PIO_PUEN_MASK; break; case PIN_CONFIG_BIAS_PULL_DOWN: conf |= ATMEL_PIO_PDEN_MASK; break; case PIN_CONFIG_DRIVE_OPEN_DRAIN: if (arg == 0) conf &= (~ATMEL_PIO_OPD_MASK); else conf |= ATMEL_PIO_OPD_MASK; break; case PIN_CONFIG_INPUT_SCHMITT_ENABLE: if (arg == 0) conf |= ATMEL_PIO_SCHMITT_MASK; else conf &= (~ATMEL_PIO_SCHMITT_MASK); break; case PIN_CONFIG_INPUT_DEBOUNCE: if (arg == 0) { conf &= (~ATMEL_PIO_IFEN_MASK); conf &= (~ATMEL_PIO_IFSCEN_MASK); } else { conf |= ATMEL_PIO_IFEN_MASK; conf |= ATMEL_PIO_IFSCEN_MASK; } break; default: printf("%s: Unsupported configuration parameter: %u ", __func__, param); break; } } return conf; } static inline struct atmel_pio4_port *atmel_pio4_bank_base(struct udevice *dev, u32 bank) { struct atmel_pio4_platdata *plat = dev_get_platdata(dev); struct atmel_pio4_port *bank_base = (struct atmel_pio4_port *)((u32)plat->reg_base + ATMEL_PIO_BANK_OFFSET * bank); return bank_base; } #define MAX_PINMUX_ENTRIES 40 static int atmel_pinctrl_set_state(struct udevice *dev, struct udevice *config) { struct atmel_pio4_port *bank_base; const void *blob = gd->fdt_blob; |
e160f7d43
|
112 |
int node = dev_of_offset(config); |
ac72e174f
|
113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 |
u32 offset, func, bank, line; u32 cells[MAX_PINMUX_ENTRIES]; u32 i, conf; int count; conf = atmel_pinctrl_get_pinconf(blob, node); count = fdtdec_get_int_array_count(blob, node, "pinmux", cells, ARRAY_SIZE(cells)); if (count < 0) { printf("%s: bad pinmux array %d ", __func__, count); return -EINVAL; } if (count > MAX_PINMUX_ENTRIES) { printf("%s: unsupported pinmux array count %d ", __func__, count); return -EINVAL; } for (i = 0 ; i < count; i++) { offset = ATMEL_GET_PIN_NO(cells[i]); func = ATMEL_GET_PIN_FUNC(cells[i]); bank = ATMEL_PIO_BANK(offset); line = ATMEL_PIO_LINE(offset); bank_base = atmel_pio4_bank_base(dev, bank); writel(BIT(line), &bank_base->mskr); conf &= (~ATMEL_PIO_CFGR_FUNC_MASK); conf |= (func & ATMEL_PIO_CFGR_FUNC_MASK); writel(conf, &bank_base->cfgr); } return 0; } const struct pinctrl_ops atmel_pinctrl_ops = { .set_state = atmel_pinctrl_set_state, }; static int atmel_pinctrl_probe(struct udevice *dev) { struct atmel_pio4_platdata *plat = dev_get_platdata(dev); fdt_addr_t addr_base; dev = dev_get_parent(dev); |
a821c4af7
|
163 |
addr_base = devfdt_get_addr(dev); |
ac72e174f
|
164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 |
if (addr_base == FDT_ADDR_T_NONE) return -EINVAL; plat->reg_base = (struct atmel_pio4_port *)addr_base; return 0; } static const struct udevice_id atmel_pinctrl_match[] = { { .compatible = "atmel,sama5d2-pinctrl" }, {} }; U_BOOT_DRIVER(atmel_pinctrl) = { .name = "pinctrl_atmel_pio4", .id = UCLASS_PINCTRL, .of_match = atmel_pinctrl_match, .probe = atmel_pinctrl_probe, .platdata_auto_alloc_size = sizeof(struct atmel_pio4_platdata), .ops = &atmel_pinctrl_ops, }; |