15 Oct, 2019
6 commits
-
Latest SCFW has removed old MISC SECO commands. So update the codes
to use new SECO commands.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 8e54efce6d2a1691605ae23983ff91f4a702adba) -
Current codes have wrong definitions for SC_MISC_SECO_AUTH_SECO_FW,
SC_MISC_SECO_AUTH_HDMI_TX_FW and SC_MISC_SECO_AUTH_HDMI_RX_FW and
cause HDP firmware authentication failed.Sync the API definitions with latest SCFW export.
Signed-off-by: Ye Li
(cherry picked from commit 87ee3c16a649a418b8c6fdae53234f88a90c8fb3) -
flash in u-boot for imx8mm-evk
imx8mm-evk uses BCH encoding and randomizer
modify macro and print size_t with %zx
use CONFIG_IMX8M because it should apply to imx8mq/mm/mn
Signed-off-by: Alice Guo
(cherry picked from commit 8d95b51fd70be29ef6beaa0f65c101b329f04f8e) -
remove space from mtdparts definition and remove
"#define CONFIG_MTD_DEVICE" to make source code can be copiled correctlySigned-off-by: Alice Guo
(cherry picked from commit c01b869d5b9dc8cff340c9b911d8df9d2aa257dd) -
dependency of CMD_NANDBCB`s default value
compiling nandbcb of imx8mm-evk depends on NAND and CMD_MTDPARTS
modify dependency of CMD_NANDBCB`s default value
Signed-off-by: Alice Guo
(cherry picked from commit 1b14e8cbefdb0f8126ceb6a85b1fd0db142328e6) -
randomizer
imx8mm-evk needs to BCH encode and set NAND page number needed to be
randomizedmodify conditional compilation
Should use CONFIG_IMX8M, it should apply to imx8mq/mm/mn
Signed-off-by: Alice Guo
(cherry picked from commit da40cd99e4b3a78d2609ee777d60d651d6dbc313)
12 Oct, 2019
2 commits
-
Add HABv4 encrypted boot documentation for i.MX8M, i.MX8MM and i.MX8MN
family devices covering the following topics:- How to encrypt and sign a flash.bin image.
- How to manage CAAM PRIBLOBs when using encrypted boot
- Add 4 CSF examples.Reviewed-by: Ye Li
Reviewed-by: Marius Grigoras
Signed-off-by: Breno Lima
(cherry picked from commit eee57255e0b0ea3a2808d3a2c19c8685afbac39b) -
Currently is not possible to use dek_blob command in
mx8mq:u-boot=> dek_blob 0x40400000 0x40401000 128
Cannot get OP-TEE deviceAdd OP-TEE Device Tree Bindings to fix this issue.
Reviewed-by: Ye Li
Signed-off-by: Clement Faure
Signed-off-by: Breno Lima
(cherry picked from commit f762fe218ec60025e2dfd6173efaa826286ba297)
11 Oct, 2019
8 commits
-
Current flexspi driver enables the Quad DTR read, so the measured
100Mhz SCLK is actually for DTR mode not SDR. However, according to
MT25QU256ABA datasheet, this flash only supports max DTR at 90Mhz and
max SDR at 166Mhz. It means current clock setting violate the flash
spec. So change back the flexspi clock to align with imx8mm.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 3bf41bae974003550b70ea1a8b44ccb3117d818f)
(cherry picked from commit 4a369b527c3842751a4edf0171562a0e40c331ba) -
On B1 chips with HAB v4.4, the sticky bits are not locked up in
HAB closed mode. We introduce a workaround in SPL to lock up
these bits and clear Manufacturing Protection Private Key for
secure boot.For field return case, user has to build a SPL with
CONFIG_SECURE_STICKY_BITS_LOCKUP=n and set CONFIG_IMX_UNIQUE_ID to
part's unique id. When the UID check is passed, sticky bits are not
lockup and users can burn field return fuse. Otherwise the boot will
stop.Signed-off-by: Ye Li
(cherry picked from commit c98b47f1ff60e1f99807e24fd76053ad880f803e) -
According to i.MX7ULP Reference Manual the second word write for both
UNLOCK and REFRESH operations must occur in maximum 16 bus clock.The current code is using writel() function which has a DMB barrier to
order the memory access. The DMB between two words write may introduce
some delay in certain circumstance, causing a WDOG timeout due to 16 bus
clock window requirement.Replace writel() function by __raw_writel() to achieve a faster memory
access and avoid such issue.Signed-off-by: Breno Lima
Reviewed-by: Ye Li
(cherry picked from commit 5dd8c46d68d3267e989f980598a4e3e2ed04d4f9) -
ROM update emmc offset to 0.
previous B0 is 32K.Signed-off-by: Frank Li
(cherry picked from commit b642241380227b97f0fa434e3d38dc746adbd9e0)
(cherry picked from commit 2065bf0a12180f73eb918d09dbe809c10077b033) -
Add REVC informaiton.
Signed-off-by: Frank Li
(cherry picked from commit c7231f2c7a5c1dc754b5fb9bf05941141877a0ec)
(cherry picked from commit 9a33170a4f4ff2ad2ab0d87e74e722a0e833abaa) -
bchtype in FCB should be associated to the gf_13/14 settings in BCH, fix
the issue and test on Micron 29F64G08CBABB, it can boot after the
change.Signed-off-by: Han Xu
(cherry picked from commit 9cc7bf9b17565b4e0d73acd690e32394034dfae2) -
gf_13/14 mask was not set correctly in register definition.
Signed-off-by: Han Xu
(cherry picked from commit b8aed98b2ecfb0def64c474e1ae171930da4c9fc) -
imx6ul/ull were not set the mtdparts properly which causes the uuu cannot recognized the correct mtd partition.
Signed-off-by: Han Xu
(cherry picked from commit e7bbaadd03df7acbd84e5fbdbce037a369b82d68)
30 Sep, 2019
1 commit
-
Conditional compilation added in MLK-22444 caused U-Boot compilation
of i.MX8MM error. Delete the wrong conditional compilation.Signed-off-by: Alice Guo
(cherry picked from commit 5638f06c300edf87461b822e2c42df2c9ccdd40f)
29 Sep, 2019
12 commits
-
ROM SError happens on two cases:
1. ERR050342, on iMX8MQ HDCP enabled parts ROM writes to GPV1 register, but
when ROM patch lock is fused, this write will cause SError.2. ERR050350, on iMX8MQ/MM/MN, when the field return fuse is burned, HAB
is field return mode, but the last 4K of ROM is still protected and cause SError.Since ROM mask SError until ATF unmask it, so then ATF always meets the exception.
This patch works around the issue in SPL by enabling SPL Exception vectors table
and the SError exception, take the exception to eret immediately to clear the SError.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit f05dd45251ca82cc54e13a616f00744c26faab53)
(cherry picked from commit 25d059411e702a4002f1aa157839001f796dd9f6) -
Sometimes we met SERROR, but only to catch it when Linux boots up.
Let's enable catching in U-Boot to catch it ealier and ease debug.Signed-off-by: Peng Fan
(cherry picked from commit 7a0c9b08886e5dc7d50e640ed56eed0fe612161f)
(cherry picked from commit 33da22c4793e56077033a4f6c567894badb8e907)
(cherry picked from commit 4da3e872b7c61b93fa227935a7b45eb5fcb252e1) -
set the i.X7D default mtdids value as "nand0=gpmi-nand", nandbcb can
directly write to the nandboot partition after u-boot brings upSigned-off-by: Alice Guo
(cherry picked from commit 820e3bc68f1c8695e6dc9a93be2c7ef27ece929d) -
there should no extra space in mtdparts definition
Signed-off-by: Alice Guo
(cherry picked from commit 3e50cae62b1f83635ad835b8da840a7e294b7065) -
Add subcommand for add writing BCB only, where we provide appropriate
offsets for firmware1 and firmware2 and size.Example of usage:
> nandbcb bcbonly 0x00180000 0x00080000 0x00200000
Writing 1024 bytes to 0x0: randomizing
OK
Writing 1024 bytes to 0x20000: randomizing
OKSigned-off-by: Igor Opaniuk
(cherry picked from commit 353a38576ed6f21431bf499a4b402a5ca571f0fa) -
Move code for writing FCB/DBBT pages to a separate function
Signed-off-by: Igor Opaniuk
(cherry picked from commit c4e8b725681c9e7d18845260ac1061aedb9166a4) -
Add support for updating FCB/DBBT on i.MX7:
- additional new fields in FCB structure
- Leverage hardware BCH/randomizer for writing FCBSigned-off-by: Igor Opaniuk
Signed-off-by: Alice Guo
(cherry picked from commit b4b3049b1e4a069e522a1112bf4f9e0253836b2d) -
On i.MX7 in a sake of reducing the disturbances caused by a neighboring
cells in the FCB page in the NAND chip, a randomizer is enabled when
reading the FCB page by ROM bootloader.Add API for setting BCH to specific layout (and restoring it back) used by
ROM bootloader to be able to burn it in a proper way to NAND using
nandbcb command.Signed-off-by: Igor Opaniuk
Signed-off-by: Anti SullinSigned-off-by: Alice Guo
(cherry picked from commit eaba02830252ed044e319571a7f3ebed412ae93b) -
Extend GPMI Integrated ECC Control Register Description, include
additional defines for enabling randomizer function and providing
proper randomizer type.For additional details check i.MX7 APR, section
9.6.6.3 GPMI Integrated ECC Control Register Description
(GPMI_ECCCTRLn)Signed-off-by: Igor Opaniuk
(cherry picked from commit 212ab2205175b9be726ef6c00f523391882a7824) -
Since the USB HID limits the maximum bandwidth(3072) for interrupt
endpoint transfers, when the bInterval set to 1, we can only support 3
boards to run sdp at the same time. In order to support more boards,
change the bInterval of interrupt endpoint to 3, which will not affect
the transmission speed.Signed-off-by: Sherry Sun
Reviewed-by: Ye Li
(cherry picked from commit beb0283e6bac3d42cc87757e3c0e200e2ac3b68f) -
When use ep1out interrupt endpoint to receive data in sdp, the max
packetsize of ep1out is set to 1024. But in cdns3 gadget driver, the
max packetsize is limited to 512 bytes in high speed. So we can't
implement data download through ep1out of cdns3 driver, here need
change the max packesize of interrupt endpoints to 1024.Signed-off-by: Sherry Sun
Reviewed-by: Ye Li
(cherry picked from commit 17f321b4a32cfaac52339172dc354729e641451a) -
EP0 has been used to transfer file data in sdp before, but the max
packetsize of ep0 is 64 bytes. So in order to improve the file transfer
speed, here add the EP1_OUT interrupt endpoint which max packetsize is
set to 1024 byte.After testing, it turns out that using ep1out is twice as fast as using
ep0 while receiving data in sdp.Signed-off-by: Sherry Sun
Reviewed-by: Ye Li
(cherry picked from commit 22614e317b7fdf4a716f2e5bde876649414ffd6c)
24 Sep, 2019
2 commits
-
"CONFIG_IMX_TRUSTY_OS=y" is added to the corresponding defconfig files
to include trusty related code.MACROs are added in corresponding header files. standard android uboot
has more content than android auto uboot, the uboot malloc pool size is
changed from 76MB to 90MB to make the boot process can be handed over to
kernel without malloc problem.Change-Id: I5072c20aa28fb1da93e889bb920955d2f1cfbefd
Signed-off-by: faqiang.zhu -
add below two defconfig files:
configs/imx8qm_mek_android_trusty_defconfig
configs/imx8qxp_mek_android_trusty_defconfigthey are directly copied from below two files for the ease of tracking
the modifications:
configs/imx8qm_mek_android_defconfig
configs/imx8qxp_mek_android_defconfigChange-Id: I84ca6ce62698b48bceb651df95ad61cf3e565e99
Signed-off-by: faqiang.zhu
23 Sep, 2019
1 commit
-
Update the mx7ulp wdog disable sequence to avoid potential reset issue
in unlock or refresh sequence. Both sequence need two words write
to wdog CNT register in 16 bus clocks window, if miss the window,
the write will cause violation in wdog and reset the chip.Current u-boot code is using writel() function which has a DMB barrier
to order the memory access. The DMB between two words write may introduce
some delay in certain circumstance, causing the wdog reset due to 16 bus
clock window requirement.This patch replaces writel() function by __raw_writel() to avoid such issue,
and improve to check if watchdog is already disabled or unlocked.Signed-off-by: Ye Li
Tested-by: Breno Lima
Reviewed-by: Peng Fan
(cherry picked from commit b8c99d5f5bcc5573d3394b68890db16b6bb5fc88)
19 Sep, 2019
1 commit
-
Disable some unnecessary configs to decrease the spl
size.Test: build and boot on imx8mq_evk.
Change-Id: I6ad56af21ecf538c9e920581d870cce0d2fec286
Signed-off-by: Ji Luo
11 Sep, 2019
2 commits
-
When enable u-boot splash screen and set kernel dtb with -hdmi.dtb on
imx8qm, the kernel reboot (partition reboot) will hang in u-boot if HDMI
cable is plugged in.
The root cause is kernel set the clock source of DC0 display0 channel to
bypass clock, when doing reboot this clock setting may not be cleared. So
u-boot has wrong clock source and cause lpcg stop bit always set.Fix the issue by adding the clock parent setting and not depend on default
parent value.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 104c4b5cdc83fb671c6474708bdd00c2dfb01113)
(cherry picked from commit 8a287c629018e6bf647c3c617fca3e6c94a3d2a4) -
Have missed the lpcg settings when porting to 2019.04 u-boot
Signed-off-by: Ye Li
Reviewed-by: Peng Fan
(cherry picked from commit 4096d7806a0dcc501123c8c2cdf734620e37d169)
06 Sep, 2019
1 commit
-
Add the another 2Gb SPI-NAND flash which is 1.8v device and using
different device id.Signed-off-by: Ye Li
Reviewed-by: Peng Fan
05 Sep, 2019
4 commits
-
Add 4Gb micron SPI nand chip MT29F4G01 which does not support QUAD IO
and has two dies. Also fix the BBM size to 4 Bytes according to datasheet.Signed-off-by: Ye Li
-
Current print for unrecognized ID only shows the buffer address not
show its device ID. Add a print to show the ID.Signed-off-by: Ye Li
-
Miss including common.h in two files and cause build error
Signed-off-by: Ye Li
-
Add flexspi_nand driver which works on iMX flexspi controller to support
SPI NAND flash. This driver requires DM_SPI and follows SPI-MEM interfaces
to adapt to the SPI NAND framework.Note: Current implementation limits to the 12-bit column address. This is
popular in main stream SPI NAND and flash devices supported in u-boot.
If device with larger page size (> 4096) needs to support, we have to change
the driver.Signed-off-by: Ye Li