Blame view
include/virtex2.h
3.19 KB
83d290c56 SPDX: Convert all... |
1 |
/* SPDX-License-Identifier: GPL-2.0+ */ |
c609719b8 Initial revision |
2 3 4 5 |
/* * (C) Copyright 2002 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. * Keith Outwater, keith_outwater@mvis.com |
c609719b8 Initial revision |
6 7 8 9 10 11 |
*/ #ifndef _VIRTEX2_H_ #define _VIRTEX2_H_ #include <xilinx.h> |
c609719b8 Initial revision |
12 |
/* |
175dccd71 fpga: virtex2: Ad... |
13 |
* Slave SelectMap or Serial Implementation function table. |
c609719b8 Initial revision |
14 15 |
*/ typedef struct { |
2df9d5c43 fpga: xilinx: Fix... |
16 17 18 19 20 21 22 23 24 25 |
xilinx_pre_fn pre; xilinx_pgm_fn pgm; xilinx_init_fn init; xilinx_err_fn err; xilinx_done_fn done; xilinx_clk_fn clk; xilinx_cs_fn cs; xilinx_wr_fn wr; xilinx_rdata_fn rdata; xilinx_wdata_fn wdata; |
175dccd71 fpga: virtex2: Ad... |
26 |
xilinx_bwr_fn wbulkdata; |
2df9d5c43 fpga: xilinx: Fix... |
27 28 29 |
xilinx_busy_fn busy; xilinx_abort_fn abort; xilinx_post_fn post; |
175dccd71 fpga: virtex2: Ad... |
30 |
} xilinx_virtex2_slave_fns; |
c609719b8 Initial revision |
31 |
|
6a6acd12a fpga: xilinx: vir... |
32 33 34 35 36 37 |
#if defined(CONFIG_FPGA_VIRTEX2) extern struct xilinx_fpga_op virtex2_op; # define FPGA_VIRTEX2_OPS &virtex2_op #else # define FPGA_VIRTEX2_OPS NULL #endif |
c609719b8 Initial revision |
38 39 |
/* Device Image Sizes (in bytes) *********************************************************************/ |
a3607365f fpga: xilinx: vir... |
40 41 42 43 |
#define XILINX_XC2V40_SIZE (338208 / 8) #define XILINX_XC2V80_SIZE (597408 / 8) #define XILINX_XC2V250_SIZE (1591584 / 8) #define XILINX_XC2V500_SIZE (2557857 / 8) |
c609719b8 Initial revision |
44 45 46 47 48 49 50 51 52 53 54 55 |
#define XILINX_XC2V1000_SIZE (3749408 / 8) #define XILINX_XC2V1500_SIZE (5166240 / 8) #define XILINX_XC2V2000_SIZE (6808352 / 8) #define XILINX_XC2V3000_SIZE (9589408 / 8) #define XILINX_XC2V4000_SIZE (14220192 / 8) #define XILINX_XC2V6000_SIZE (19752096 / 8) #define XILINX_XC2V8000_SIZE (26185120 / 8) #define XILINX_XC2V10000_SIZE (33519264 / 8) /* Descriptor Macros *********************************************************************/ #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
56 57 |
{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
58 59 |
#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
60 61 |
{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
62 63 |
#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
64 65 |
{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
66 67 |
#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
68 69 |
{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
70 71 |
#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
72 73 |
{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
74 75 |
#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
76 77 |
{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
78 79 |
#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
80 81 |
{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
82 83 |
#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
84 85 |
{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
86 87 |
#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
88 89 |
{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
90 91 |
#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
92 93 |
{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
94 95 |
#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
96 97 |
{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
98 99 |
#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \ |
6a6acd12a fpga: xilinx: vir... |
100 101 |
{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS } |
c609719b8 Initial revision |
102 103 |
#endif /* _VIRTEX2_H_ */ |