Commit a3607365f78ce79f8592e3acb4a04ab4d4ac8f36

Authored by Michal Simek
1 parent 6a6acd12ad

fpga: xilinx: virtex2: Fix macro indentation

No functional changes.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>

Showing 1 changed file with 4 additions and 4 deletions Side-by-side Diff

... ... @@ -47,10 +47,10 @@
47 47  
48 48 /* Device Image Sizes (in bytes)
49 49 *********************************************************************/
50   -#define XILINX_XC2V40_SIZE (338208 / 8)
51   -#define XILINX_XC2V80_SIZE (597408 / 8)
52   -#define XILINX_XC2V250_SIZE (1591584 / 8)
53   -#define XILINX_XC2V500_SIZE (2557857 / 8)
  50 +#define XILINX_XC2V40_SIZE (338208 / 8)
  51 +#define XILINX_XC2V80_SIZE (597408 / 8)
  52 +#define XILINX_XC2V250_SIZE (1591584 / 8)
  53 +#define XILINX_XC2V500_SIZE (2557857 / 8)
54 54 #define XILINX_XC2V1000_SIZE (3749408 / 8)
55 55 #define XILINX_XC2V1500_SIZE (5166240 / 8)
56 56 #define XILINX_XC2V2000_SIZE (6808352 / 8)