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include/fpga.h
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/* * (C) Copyright 2002 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. * |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ |
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#include <linux/types.h> /* for ulong typedef */ |
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#ifndef _FPGA_H_ #define _FPGA_H_ #ifndef CONFIG_MAX_FPGA_DEVICES #define CONFIG_MAX_FPGA_DEVICES 5 #endif |
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/* fpga_xxxx function return value definitions */ |
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#define FPGA_SUCCESS 0 #define FPGA_FAIL -1 |
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/* device numbers must be non-negative */ |
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#define FPGA_INVALID_DEVICE -1 |
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/* root data type defintions */ |
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typedef enum { /* typedef fpga_type */ fpga_min_type, /* range check value */ fpga_xilinx, /* Xilinx Family) */ fpga_altera, /* unimplemented */ |
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fpga_lattice, /* Lattice family */ |
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fpga_undefined /* invalid range check value */ } fpga_type; /* end, typedef fpga_type */ |
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typedef struct { /* typedef fpga_desc */ fpga_type devtype; /* switch value to select sub-functions */ void *devdesc; /* real device descriptor */ } fpga_desc; /* end, typedef fpga_desc */ |
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typedef struct { /* typedef fpga_desc */ unsigned int blocksize; char *interface; char *dev_part; char *filename; int fstype; } fpga_fs_info; |
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typedef enum { BIT_FULL = 0, |
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BIT_PARTIAL, |
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BIT_NONE = 0xFF, |
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} bitstream_type; |
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/* root function definitions */ |
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void fpga_init(void); int fpga_add(fpga_type devtype, void *desc); int fpga_count(void); |
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const fpga_desc *const fpga_get_desc(int devnum); |
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int fpga_is_partial_data(int devnum, size_t img_len); |
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int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype); int fpga_fsload(int devnum, const void *buf, size_t size, fpga_fs_info *fpga_fsinfo); int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype); int fpga_dump(int devnum, const void *buf, size_t bsize); int fpga_info(int devnum); const fpga_desc *const fpga_validate(int devnum, const void *buf, size_t bsize, char *fn); |
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#endif /* _FPGA_H_ */ |