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include/virtex2.h 3.35 KB

c609719b8 wdenk Initial revision	1 2 3 4 5	/* * (C) Copyright 2002 * Rich Ireland, Enterasys Networks, rireland@enterasys.com. * Keith Outwater, keith_outwater@mvis.com *
1a4596601 Wolfgang Denk Add GPL-2.0+ SPDX...	6	* SPDX-License-Identifier: GPL-2.0+
c609719b8 wdenk Initial revision	7 8 9 10 11 12	*/ #ifndef _VIRTEX2_H_ #define _VIRTEX2_H_ #include <xilinx.h>
c609719b8 wdenk Initial revision	13 14 15 16	/* * Slave SelectMap Implementation function table. */ typedef struct {
2df9d5c43 Michal Simek fpga: xilinx: Fix...	17 18 19 20 21 22 23 24 25 26 27 28 29	xilinx_pre_fn pre; xilinx_pgm_fn pgm; xilinx_init_fn init; xilinx_err_fn err; xilinx_done_fn done; xilinx_clk_fn clk; xilinx_cs_fn cs; xilinx_wr_fn wr; xilinx_rdata_fn rdata; xilinx_wdata_fn wdata; xilinx_busy_fn busy; xilinx_abort_fn abort; xilinx_post_fn post;
d9071ce0a Michal Simek fpga: virtex2: Av...	30	} xilinx_virtex2_slave_selectmap_fns;
c609719b8 wdenk Initial revision	31 32 33	/* Slave Serial Implementation function table */ typedef struct {
2df9d5c43 Michal Simek fpga: xilinx: Fix...	34 35 36 37	xilinx_pgm_fn pgm; xilinx_clk_fn clk; xilinx_rdata_fn rdata; xilinx_wdata_fn wdata;
d9071ce0a Michal Simek fpga: virtex2: Av...	38	} xilinx_virtex2_slave_serial_fns;
c609719b8 wdenk Initial revision	39
6a6acd12a Michal Simek fpga: xilinx: vir...	40 41 42 43 44 45	#if defined(CONFIG_FPGA_VIRTEX2) extern struct xilinx_fpga_op virtex2_op; # define FPGA_VIRTEX2_OPS &virtex2_op #else # define FPGA_VIRTEX2_OPS NULL #endif
c609719b8 wdenk Initial revision	46 47	/* Device Image Sizes (in bytes) *********************************************************************/
a3607365f Michal Simek fpga: xilinx: vir...	48 49 50 51	#define XILINX_XC2V40_SIZE (338208 / 8) #define XILINX_XC2V80_SIZE (597408 / 8) #define XILINX_XC2V250_SIZE (1591584 / 8) #define XILINX_XC2V500_SIZE (2557857 / 8)
c609719b8 wdenk Initial revision	52 53 54 55 56 57 58 59 60 61 62 63	#define XILINX_XC2V1000_SIZE (3749408 / 8) #define XILINX_XC2V1500_SIZE (5166240 / 8) #define XILINX_XC2V2000_SIZE (6808352 / 8) #define XILINX_XC2V3000_SIZE (9589408 / 8) #define XILINX_XC2V4000_SIZE (14220192 / 8) #define XILINX_XC2V6000_SIZE (19752096 / 8) #define XILINX_XC2V8000_SIZE (26185120 / 8) #define XILINX_XC2V10000_SIZE (33519264 / 8) /* Descriptor Macros *********************************************************************/ #define XILINX_XC2V40_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	64 65	{ xilinx_virtex2, iface, XILINX_XC2V40_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	66 67	#define XILINX_XC2V80_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	68 69	{ xilinx_virtex2, iface, XILINX_XC2V80_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	70 71	#define XILINX_XC2V250_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	72 73	{ xilinx_virtex2, iface, XILINX_XC2V250_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	74 75	#define XILINX_XC2V500_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	76 77	{ xilinx_virtex2, iface, XILINX_XC2V500_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	78 79	#define XILINX_XC2V1000_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	80 81	{ xilinx_virtex2, iface, XILINX_XC2V1000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	82 83	#define XILINX_XC2V1500_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	84 85	{ xilinx_virtex2, iface, XILINX_XC2V1500_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	86 87	#define XILINX_XC2V2000_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	88 89	{ xilinx_virtex2, iface, XILINX_XC2V2000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	90 91	#define XILINX_XC2V3000_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	92 93	{ xilinx_virtex2, iface, XILINX_XC2V3000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	94 95	#define XILINX_XC2V4000_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	96 97	{ xilinx_virtex2, iface, XILINX_XC2V4000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	98 99	#define XILINX_XC2V6000_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	100 101	{ xilinx_virtex2, iface, XILINX_XC2V6000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	102 103	#define XILINX_XC2V8000_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	104 105	{ xilinx_virtex2, iface, XILINX_XC2V8000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	106 107	#define XILINX_XC2V10000_DESC(iface, fn_table, cookie) \
6a6acd12a Michal Simek fpga: xilinx: vir...	108 109	{ xilinx_virtex2, iface, XILINX_XC2V10000_SIZE, fn_table, cookie, \ FPGA_VIRTEX2_OPS }
c609719b8 wdenk Initial revision	110 111	#endif /* _VIRTEX2_H_ */