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include/atmel_lcd.h
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/* * atmel_lcd.h - Atmel LCD Controller structures * * (C) Copyright 2001 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _ATMEL_LCD_H_ #define _ATMEL_LCD_H_ |
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/** * struct atmel_lcd_platdata - platform data for Atmel LCDs with driver model * * @timing_index: Index of LCD timing to use in device tree node */ struct atmel_lcd_platdata { int timing_index; }; |
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typedef struct vidinfo { ushort vl_col; /* Number of columns (i.e. 640) */ ushort vl_row; /* Number of rows (i.e. 480) */ |
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ushort vl_rot; /* Rotation of Display (0, 1, 2, 3) */ u_long vl_clk; /* pixel clock in ps */ |
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/* LCD configuration register */ u_long vl_sync; /* Horizontal / vertical sync */ u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */ u_long vl_tft; /* 0 = passive, 1 = TFT */ u_long vl_cont_pol_low; /* contrast polarity is low */ u_long vl_clk_pol; /* clock polarity */ /* Horizontal control register. */ u_long vl_hsync_len; /* Length of horizontal sync */ u_long vl_left_margin; /* Time from sync to picture */ u_long vl_right_margin; /* Time from picture to sync */ /* Vertical control register. */ u_long vl_vsync_len; /* Length of vertical sync */ u_long vl_upper_margin; /* Time from sync to picture */ u_long vl_lower_margin; /* Time from picture to sync */ u_long mmio; /* Memory mapped registers */ } vidinfo_t; #endif |