lcd: move platform-specific structs to their own headers

common/lcd code is full of platform-specific code and definitions, which ideally should reside with the respective driver code. Take a step towards that goal by moving platform-specific structs from lcd.h to their own header files. The structs for the generic case (the #else for all the platform-specific cases) is retained in lcd.h as the default case. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bo Shen <voice.shen@atmel.com> Tested-by: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Simon Glass <sjg@chromium.org> Cc: Anatolij Gustschin <agust@denx.de>

lcd: move platform-specific structs to their own headers
common/lcd code is full of platform-specific code and definitions, which ideally should reside with the respective driver code. Take a step towards that goal by moving platform-specific structs from lcd.h to their own header files. The structs for the generic case (the #else for all the platform-specific cases) is retained in lcd.h as the default case. Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Bo Shen <voice.shen@atmel.com> Tested-by: Josh Wu <josh.wu@atmel.com> Cc: Bo Shen <voice.shen@atmel.com> Cc: Simon Glass <sjg@chromium.org> Cc: Anatolij Gustschin <agust@denx.de>
Nikita Kiryanov · Anatolij Gustschin
1 parent 7f641d53bb
Showing 5 changed files with 247 additions and 196 deletions Side-by-side Diff
include/atmel_lcd.h
include/exynos_lcd.h
include/lcd.h
include/mpc823_lcd.h
include/pxa_lcd.h
+/*
+ * atmel_lcd.h - Atmel LCD Controller structures
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _ATMEL_LCD_H_
+#define _ATMEL_LCD_H_
+
+typedef struct vidinfo {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	u_long vl_clk;	/* pixel clock in ps    */
+
+	/* LCD configuration register */
+	u_long vl_sync;		/* Horizontal / vertical sync */
+	u_long vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
+	u_long vl_tft;		/* 0 = passive, 1 = TFT */
+	u_long vl_cont_pol_low;	/* contrast polarity is low */
+	u_long vl_clk_pol;	/* clock polarity */
+
+	/* Horizontal control register. */
+	u_long vl_hsync_len;	/* Length of horizontal sync */
+	u_long vl_left_margin;	/* Time from sync to picture */
+	u_long vl_right_margin;	/* Time from picture to sync */
+
+	/* Vertical control register. */
+	u_long vl_vsync_len;	/* Length of vertical sync */
+	u_long vl_upper_margin;	/* Time from sync to picture */
+	u_long vl_lower_margin;	/* Time from picture to sync */
+
+	u_long	mmio;		/* Memory mapped registers */
+} vidinfo_t;
+
+#endif
+/*
+ * exynos_lcd.h - Exynos LCD Controller structures
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _EXYNOS_LCD_H_
+#define _EXYNOS_LCD_H_
+
+enum {
+	FIMD_RGB_INTERFACE = 1,
+	FIMD_CPU_INTERFACE = 2,
+};
+
+enum exynos_fb_rgb_mode_t {
+	MODE_RGB_P = 0,
+	MODE_BGR_P = 1,
+	MODE_RGB_S = 2,
+	MODE_BGR_S = 3,
+};
+
+typedef struct vidinfo {
+	ushort vl_col;		/* Number of columns (i.e. 640) */
+	ushort vl_row;		/* Number of rows (i.e. 480) */
+	ushort vl_width;	/* Width of display area in millimeters */
+	ushort vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char vl_freq;		/* Frequency */
+	u_char vl_clkp;		/* Clock polarity */
+	u_char vl_oep;		/* Output Enable polarity */
+	u_char vl_hsp;		/* Horizontal Sync polarity */
+	u_char vl_vsp;		/* Vertical Sync polarity */
+	u_char vl_dp;		/* Data polarity */
+	u_char vl_bpix;		/* Bits per pixel */
+
+	/* Horizontal control register. Timing from data sheet */
+	u_char vl_hspw;		/* Horz sync pulse width */
+	u_char vl_hfpd;		/* Wait before of line */
+	u_char vl_hbpd;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vspw;	/* Vertical sync pulse width */
+	u_char	vl_vfpd;	/* Wait before of frame */
+	u_char	vl_vbpd;	/* Wait end of frame */
+	u_char  vl_cmd_allow_len; /* Wait end of frame */
+
+	unsigned int win_id;
+	unsigned int init_delay;
+	unsigned int power_on_delay;
+	unsigned int reset_delay;
+	unsigned int interface_mode;
+	unsigned int mipi_enabled;
+	unsigned int dp_enabled;
+	unsigned int cs_setup;
+	unsigned int wr_setup;
+	unsigned int wr_act;
+	unsigned int wr_hold;
+	unsigned int logo_on;
+	unsigned int logo_width;
+	unsigned int logo_height;
+	int logo_x_offset;
+	int logo_y_offset;
+	unsigned long logo_addr;
+	unsigned int rgb_mode;
+	unsigned int resolution;
+
+	/* parent clock name(MPLL, EPLL or VPLL) */
+	unsigned int pclk_name;
+	/* ratio value for source clock from parent clock. */
+	unsigned int sclk_div;
+
+	unsigned int dual_lcd_enabled;
+} vidinfo_t;
+
+void init_panel_info(vidinfo_t *vid);
+
+#endif
@@ -41,205 +41,15 @@
 void lcd_set_flush_dcache(int flush);
  
 #if defined CONFIG_MPC823
-/*
- * LCD controller stucture for MPC823 CPU
- */
-typedef struct vidinfo {
-	ushort	vl_col;		/* Number of columns (i.e. 640) */
-	ushort	vl_row;		/* Number of rows (i.e. 480) */
-	ushort	vl_width;	/* Width of display area in millimeters */
-	ushort	vl_height;	/* Height of display area in millimeters */
-
-	/* LCD configuration register */
-	u_char	vl_clkp;	/* Clock polarity */
-	u_char	vl_oep;		/* Output Enable polarity */
-	u_char	vl_hsp;		/* Horizontal Sync polarity */
-	u_char	vl_vsp;		/* Vertical Sync polarity */
-	u_char	vl_dp;		/* Data polarity */
-	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
-	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
-	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
-	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
-	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
-
-	/* Horizontal control register. Timing from data sheet */
-	ushort	vl_wbl;		/* Wait between lines */
-
-	/* Vertical control register */
-	u_char	vl_vpw;		/* Vertical sync pulse width */
-	u_char	vl_lcdac;	/* LCD AC timing */
-	u_char	vl_wbf;		/* Wait between frames */
-} vidinfo_t;
-
+#include <mpc823_lcd.h>
 #elif defined(CONFIG_CPU_PXA25X) || defined(CONFIG_CPU_PXA27X) || \
 	defined CONFIG_CPU_MONAHANS
-/*
- * PXA LCD DMA descriptor
- */
-struct pxafb_dma_descriptor {
-	u_long	fdadr;		/* Frame descriptor address register */
-	u_long	fsadr;		/* Frame source address register */
-	u_long	fidr;		/* Frame ID register */
-	u_long	ldcmd;		/* Command register */
-};
-
-/*
- * PXA LCD info
- */
-struct pxafb_info {
-
-	/* Misc registers */
-	u_long	reg_lccr3;
-	u_long	reg_lccr2;
-	u_long	reg_lccr1;
-	u_long	reg_lccr0;
-	u_long	fdadr0;
-	u_long	fdadr1;
-
-	/* DMA descriptors */
-	struct	pxafb_dma_descriptor *	dmadesc_fblow;
-	struct	pxafb_dma_descriptor *	dmadesc_fbhigh;
-	struct	pxafb_dma_descriptor *	dmadesc_palette;
-
-	u_long	screen;		/* physical address of frame buffer */
-	u_long	palette;	/* physical address of palette memory */
-	u_int	palette_size;
-};
-
-/*
- * LCD controller stucture for PXA CPU
- */
-typedef struct vidinfo {
-	ushort	vl_col;		/* Number of columns (i.e. 640) */
-	ushort	vl_row;		/* Number of rows (i.e. 480) */
-	ushort	vl_width;	/* Width of display area in millimeters */
-	ushort	vl_height;	/* Height of display area in millimeters */
-
-	/* LCD configuration register */
-	u_char	vl_clkp;	/* Clock polarity */
-	u_char	vl_oep;		/* Output Enable polarity */
-	u_char	vl_hsp;		/* Horizontal Sync polarity */
-	u_char	vl_vsp;		/* Vertical Sync polarity */
-	u_char	vl_dp;		/* Data polarity */
-	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
-	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
-	u_char	vl_splt;	/* Split display, 0 = single-scan, 1 = dual-scan */
-	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
-	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
-
-	/* Horizontal control register. Timing from data sheet */
-	ushort	vl_hpw;		/* Horz sync pulse width */
-	u_char	vl_blw;		/* Wait before of line */
-	u_char	vl_elw;		/* Wait end of line */
-
-	/* Vertical control register. */
-	u_char	vl_vpw;		/* Vertical sync pulse width */
-	u_char	vl_bfw;		/* Wait before of frame */
-	u_char	vl_efw;		/* Wait end of frame */
-
-	/* PXA LCD controller params */
-	struct	pxafb_info pxa;
-} vidinfo_t;
-
+#include <pxa_lcd.h>
 #elif defined(CONFIG_ATMEL_LCD) || defined(CONFIG_ATMEL_HLCD)
-
-typedef struct vidinfo {
-	ushort vl_col;		/* Number of columns (i.e. 640) */
-	ushort vl_row;		/* Number of rows (i.e. 480) */
-	u_long vl_clk;	/* pixel clock in ps    */
-
-	/* LCD configuration register */
-	u_long vl_sync;		/* Horizontal / vertical sync */
-	u_long vl_bpix;		/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
-	u_long vl_tft;		/* 0 = passive, 1 = TFT */
-	u_long vl_cont_pol_low;	/* contrast polarity is low */
-	u_long vl_clk_pol;	/* clock polarity */
-
-	/* Horizontal control register. */
-	u_long vl_hsync_len;	/* Length of horizontal sync */
-	u_long vl_left_margin;	/* Time from sync to picture */
-	u_long vl_right_margin;	/* Time from picture to sync */
-
-	/* Vertical control register. */
-	u_long vl_vsync_len;	/* Length of vertical sync */
-	u_long vl_upper_margin;	/* Time from sync to picture */
-	u_long vl_lower_margin;	/* Time from picture to sync */
-
-	u_long	mmio;		/* Memory mapped registers */
-} vidinfo_t;
-
+#include <atmel_lcd.h>
 #elif defined(CONFIG_EXYNOS_FB)
-
-enum {
-	FIMD_RGB_INTERFACE = 1,
-	FIMD_CPU_INTERFACE = 2,
-};
-
-enum exynos_fb_rgb_mode_t {
-	MODE_RGB_P = 0,
-	MODE_BGR_P = 1,
-	MODE_RGB_S = 2,
-	MODE_BGR_S = 3,
-};
-
-typedef struct vidinfo {
-	ushort vl_col;		/* Number of columns (i.e. 640) */
-	ushort vl_row;		/* Number of rows (i.e. 480) */
-	ushort vl_width;	/* Width of display area in millimeters */
-	ushort vl_height;	/* Height of display area in millimeters */
-
-	/* LCD configuration register */
-	u_char vl_freq;		/* Frequency */
-	u_char vl_clkp;		/* Clock polarity */
-	u_char vl_oep;		/* Output Enable polarity */
-	u_char vl_hsp;		/* Horizontal Sync polarity */
-	u_char vl_vsp;		/* Vertical Sync polarity */
-	u_char vl_dp;		/* Data polarity */
-	u_char vl_bpix;		/* Bits per pixel */
-
-	/* Horizontal control register. Timing from data sheet */
-	u_char vl_hspw;		/* Horz sync pulse width */
-	u_char vl_hfpd;		/* Wait before of line */
-	u_char vl_hbpd;		/* Wait end of line */
-
-	/* Vertical control register. */
-	u_char	vl_vspw;	/* Vertical sync pulse width */
-	u_char	vl_vfpd;	/* Wait before of frame */
-	u_char	vl_vbpd;	/* Wait end of frame */
-	u_char  vl_cmd_allow_len; /* Wait end of frame */
-
-	unsigned int win_id;
-	unsigned int init_delay;
-	unsigned int power_on_delay;
-	unsigned int reset_delay;
-	unsigned int interface_mode;
-	unsigned int mipi_enabled;
-	unsigned int dp_enabled;
-	unsigned int cs_setup;
-	unsigned int wr_setup;
-	unsigned int wr_act;
-	unsigned int wr_hold;
-	unsigned int logo_on;
-	unsigned int logo_width;
-	unsigned int logo_height;
-	int logo_x_offset;
-	int logo_y_offset;
-	unsigned long logo_addr;
-	unsigned int rgb_mode;
-	unsigned int resolution;
-
-	/* parent clock name(MPLL, EPLL or VPLL) */
-	unsigned int pclk_name;
-	/* ratio value for source clock from parent clock. */
-	unsigned int sclk_div;
-
-	unsigned int dual_lcd_enabled;
-} vidinfo_t;
-
-void init_panel_info(vidinfo_t *vid);
-
+#include <exynos_lcd.h>
 #else
-
 typedef struct vidinfo {
 	ushort	vl_col;		/* Number of columns (i.e. 160) */
 	ushort	vl_row;		/* Number of rows (i.e. 100) */
@@ -250,8 +60,7 @@
  
 	void	*priv;		/* Pointer to driver-specific data */
 } vidinfo_t;
-
-#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */
+#endif
  
 extern vidinfo_t panel_info;
  
+/*
+ * mpc823_lcd.h - MPC823 LCD Controller structures
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _MPC823_LCD_H_
+#define _MPC823_LCD_H_
+
+/*
+ * LCD controller stucture for MPC823 CPU
+ */
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 640) */
+	ushort	vl_row;		/* Number of rows (i.e. 480) */
+	ushort	vl_width;	/* Width of display area in millimeters */
+	ushort	vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char	vl_clkp;	/* Clock polarity */
+	u_char	vl_oep;		/* Output Enable polarity */
+	u_char	vl_hsp;		/* Horizontal Sync polarity */
+	u_char	vl_vsp;		/* Vertical Sync polarity */
+	u_char	vl_dp;		/* Data polarity */
+	u_char	vl_bpix;	/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
+	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
+	u_char	vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
+	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
+	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
+
+	/* Horizontal control register. Timing from data sheet */
+	ushort	vl_wbl;		/* Wait between lines */
+
+	/* Vertical control register */
+	u_char	vl_vpw;		/* Vertical sync pulse width */
+	u_char	vl_lcdac;	/* LCD AC timing */
+	u_char	vl_wbf;		/* Wait between frames */
+} vidinfo_t;
+
+#endif
+/*
+ * pxa_lcd.h - PXA LCD Controller structures
+ *
+ * (C) Copyright 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef _PXA_LCD_H_
+#define _PXA_LCD_H_
+
+/*
+ * PXA LCD DMA descriptor
+ */
+struct pxafb_dma_descriptor {
+	u_long	fdadr;		/* Frame descriptor address register */
+	u_long	fsadr;		/* Frame source address register */
+	u_long	fidr;		/* Frame ID register */
+	u_long	ldcmd;		/* Command register */
+};
+
+/*
+ * PXA LCD info
+ */
+struct pxafb_info {
+	/* Misc registers */
+	u_long	reg_lccr3;
+	u_long	reg_lccr2;
+	u_long	reg_lccr1;
+	u_long	reg_lccr0;
+	u_long	fdadr0;
+	u_long	fdadr1;
+
+	/* DMA descriptors */
+	struct	pxafb_dma_descriptor *dmadesc_fblow;
+	struct	pxafb_dma_descriptor *dmadesc_fbhigh;
+	struct	pxafb_dma_descriptor *dmadesc_palette;
+
+	u_long	screen;		/* physical address of frame buffer */
+	u_long	palette;	/* physical address of palette memory */
+	u_int	palette_size;
+};
+
+/*
+ * LCD controller stucture for PXA CPU
+ */
+typedef struct vidinfo {
+	ushort	vl_col;		/* Number of columns (i.e. 640) */
+	ushort	vl_row;		/* Number of rows (i.e. 480) */
+	ushort	vl_width;	/* Width of display area in millimeters */
+	ushort	vl_height;	/* Height of display area in millimeters */
+
+	/* LCD configuration register */
+	u_char	vl_clkp;	/* Clock polarity */
+	u_char	vl_oep;		/* Output Enable polarity */
+	u_char	vl_hsp;		/* Horizontal Sync polarity */
+	u_char	vl_vsp;		/* Vertical Sync polarity */
+	u_char	vl_dp;		/* Data polarity */
+	u_char	vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
+	u_char	vl_lbw;		/* LCD Bus width, 0 = 4, 1 = 8 */
+	u_char	vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */
+	u_char	vl_clor;	/* Color, 0 = mono, 1 = color */
+	u_char	vl_tft;		/* 0 = passive, 1 = TFT */
+
+	/* Horizontal control register. Timing from data sheet */
+	ushort	vl_hpw;		/* Horz sync pulse width */
+	u_char	vl_blw;		/* Wait before of line */
+	u_char	vl_elw;		/* Wait end of line */
+
+	/* Vertical control register. */
+	u_char	vl_vpw;		/* Vertical sync pulse width */
+	u_char	vl_bfw;		/* Wait before of frame */
+	u_char	vl_efw;		/* Wait end of frame */
+
+	/* PXA LCD controller params */
+	struct	pxafb_info pxa;
+} vidinfo_t;
+
+#endif
	1	+/*
	2	+ * atmel_lcd.h - Atmel LCD Controller structures
	3	+ *
	4	+ * (C) Copyright 2001
	5	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#ifndef _ATMEL_LCD_H_
	11	+#define _ATMEL_LCD_H_
	12	+
	13	+typedef struct vidinfo {
	14	+ ushort vl_col; /* Number of columns (i.e. 640) */
	15	+ ushort vl_row; /* Number of rows (i.e. 480) */
	16	+ u_long vl_clk; /* pixel clock in ps */
	17	+
	18	+ /* LCD configuration register */
	19	+ u_long vl_sync; /* Horizontal / vertical sync */
	20	+ u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
	21	+ u_long vl_tft; /* 0 = passive, 1 = TFT */
	22	+ u_long vl_cont_pol_low; /* contrast polarity is low */
	23	+ u_long vl_clk_pol; /* clock polarity */
	24	+
	25	+ /* Horizontal control register. */
	26	+ u_long vl_hsync_len; /* Length of horizontal sync */
	27	+ u_long vl_left_margin; /* Time from sync to picture */
	28	+ u_long vl_right_margin; /* Time from picture to sync */
	29	+
	30	+ /* Vertical control register. */
	31	+ u_long vl_vsync_len; /* Length of vertical sync */
	32	+ u_long vl_upper_margin; /* Time from sync to picture */
	33	+ u_long vl_lower_margin; /* Time from picture to sync */
	34	+
	35	+ u_long mmio; /* Memory mapped registers */
	36	+} vidinfo_t;
	37	+
	38	+#endif
	1	+/*
	2	+ * exynos_lcd.h - Exynos LCD Controller structures
	3	+ *
	4	+ * (C) Copyright 2001
	5	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#ifndef _EXYNOS_LCD_H_
	11	+#define _EXYNOS_LCD_H_
	12	+
	13	+enum {
	14	+ FIMD_RGB_INTERFACE = 1,
	15	+ FIMD_CPU_INTERFACE = 2,
	16	+};
	17	+
	18	+enum exynos_fb_rgb_mode_t {
	19	+ MODE_RGB_P = 0,
	20	+ MODE_BGR_P = 1,
	21	+ MODE_RGB_S = 2,
	22	+ MODE_BGR_S = 3,
	23	+};
	24	+
	25	+typedef struct vidinfo {
	26	+ ushort vl_col; /* Number of columns (i.e. 640) */
	27	+ ushort vl_row; /* Number of rows (i.e. 480) */
	28	+ ushort vl_width; /* Width of display area in millimeters */
	29	+ ushort vl_height; /* Height of display area in millimeters */
	30	+
	31	+ /* LCD configuration register */
	32	+ u_char vl_freq; /* Frequency */
	33	+ u_char vl_clkp; /* Clock polarity */
	34	+ u_char vl_oep; /* Output Enable polarity */
	35	+ u_char vl_hsp; /* Horizontal Sync polarity */
	36	+ u_char vl_vsp; /* Vertical Sync polarity */
	37	+ u_char vl_dp; /* Data polarity */
	38	+ u_char vl_bpix; /* Bits per pixel */
	39	+
	40	+ /* Horizontal control register. Timing from data sheet */
	41	+ u_char vl_hspw; /* Horz sync pulse width */
	42	+ u_char vl_hfpd; /* Wait before of line */
	43	+ u_char vl_hbpd; /* Wait end of line */
	44	+
	45	+ /* Vertical control register. */
	46	+ u_char vl_vspw; /* Vertical sync pulse width */
	47	+ u_char vl_vfpd; /* Wait before of frame */
	48	+ u_char vl_vbpd; /* Wait end of frame */
	49	+ u_char vl_cmd_allow_len; /* Wait end of frame */
	50	+
	51	+ unsigned int win_id;
	52	+ unsigned int init_delay;
	53	+ unsigned int power_on_delay;
	54	+ unsigned int reset_delay;
	55	+ unsigned int interface_mode;
	56	+ unsigned int mipi_enabled;
	57	+ unsigned int dp_enabled;
	58	+ unsigned int cs_setup;
	59	+ unsigned int wr_setup;
	60	+ unsigned int wr_act;
	61	+ unsigned int wr_hold;
	62	+ unsigned int logo_on;
	63	+ unsigned int logo_width;
	64	+ unsigned int logo_height;
	65	+ int logo_x_offset;
	66	+ int logo_y_offset;
	67	+ unsigned long logo_addr;
	68	+ unsigned int rgb_mode;
	69	+ unsigned int resolution;
	70	+
	71	+ /* parent clock name(MPLL, EPLL or VPLL) */
	72	+ unsigned int pclk_name;
	73	+ /* ratio value for source clock from parent clock. */
	74	+ unsigned int sclk_div;
	75	+
	76	+ unsigned int dual_lcd_enabled;
	77	+} vidinfo_t;
	78	+
	79	+void init_panel_info(vidinfo_t *vid);
	80	+
	81	+#endif
...	...	@@ -41,205 +41,15 @@
41	41	void lcd_set_flush_dcache(int flush);
42	42
43	43	#if defined CONFIG_MPC823
44		-/*
45		- * LCD controller stucture for MPC823 CPU
46		- */
47		-typedef struct vidinfo {
48		- ushort vl_col; /* Number of columns (i.e. 640) */
49		- ushort vl_row; /* Number of rows (i.e. 480) */
50		- ushort vl_width; /* Width of display area in millimeters */
51		- ushort vl_height; /* Height of display area in millimeters */
52		-
53		- /* LCD configuration register */
54		- u_char vl_clkp; /* Clock polarity */
55		- u_char vl_oep; /* Output Enable polarity */
56		- u_char vl_hsp; /* Horizontal Sync polarity */
57		- u_char vl_vsp; /* Vertical Sync polarity */
58		- u_char vl_dp; /* Data polarity */
59		- u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
60		- u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
61		- u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
62		- u_char vl_clor; /* Color, 0 = mono, 1 = color */
63		- u_char vl_tft; /* 0 = passive, 1 = TFT */
64		-
65		- /* Horizontal control register. Timing from data sheet */
66		- ushort vl_wbl; /* Wait between lines */
67		-
68		- /* Vertical control register */
69		- u_char vl_vpw; /* Vertical sync pulse width */
70		- u_char vl_lcdac; /* LCD AC timing */
71		- u_char vl_wbf; /* Wait between frames */
72		-} vidinfo_t;
73		-
	44	+#include <mpc823_lcd.h>
74	45	#elif defined(CONFIG_CPU_PXA25X) \|\| defined(CONFIG_CPU_PXA27X) \|\| \
75	46	defined CONFIG_CPU_MONAHANS
76		-/*
77		- * PXA LCD DMA descriptor
78		- */
79		-struct pxafb_dma_descriptor {
80		- u_long fdadr; /* Frame descriptor address register */
81		- u_long fsadr; /* Frame source address register */
82		- u_long fidr; /* Frame ID register */
83		- u_long ldcmd; /* Command register */
84		-};
85		-
86		-/*
87		- * PXA LCD info
88		- */
89		-struct pxafb_info {
90		-
91		- /* Misc registers */
92		- u_long reg_lccr3;
93		- u_long reg_lccr2;
94		- u_long reg_lccr1;
95		- u_long reg_lccr0;
96		- u_long fdadr0;
97		- u_long fdadr1;
98		-
99		- /* DMA descriptors */
100		- struct pxafb_dma_descriptor * dmadesc_fblow;
101		- struct pxafb_dma_descriptor * dmadesc_fbhigh;
102		- struct pxafb_dma_descriptor * dmadesc_palette;
103		-
104		- u_long screen; /* physical address of frame buffer */
105		- u_long palette; /* physical address of palette memory */
106		- u_int palette_size;
107		-};
108		-
109		-/*
110		- * LCD controller stucture for PXA CPU
111		- */
112		-typedef struct vidinfo {
113		- ushort vl_col; /* Number of columns (i.e. 640) */
114		- ushort vl_row; /* Number of rows (i.e. 480) */
115		- ushort vl_width; /* Width of display area in millimeters */
116		- ushort vl_height; /* Height of display area in millimeters */
117		-
118		- /* LCD configuration register */
119		- u_char vl_clkp; /* Clock polarity */
120		- u_char vl_oep; /* Output Enable polarity */
121		- u_char vl_hsp; /* Horizontal Sync polarity */
122		- u_char vl_vsp; /* Vertical Sync polarity */
123		- u_char vl_dp; /* Data polarity */
124		- u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
125		- u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
126		- u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
127		- u_char vl_clor; /* Color, 0 = mono, 1 = color */
128		- u_char vl_tft; /* 0 = passive, 1 = TFT */
129		-
130		- /* Horizontal control register. Timing from data sheet */
131		- ushort vl_hpw; /* Horz sync pulse width */
132		- u_char vl_blw; /* Wait before of line */
133		- u_char vl_elw; /* Wait end of line */
134		-
135		- /* Vertical control register. */
136		- u_char vl_vpw; /* Vertical sync pulse width */
137		- u_char vl_bfw; /* Wait before of frame */
138		- u_char vl_efw; /* Wait end of frame */
139		-
140		- /* PXA LCD controller params */
141		- struct pxafb_info pxa;
142		-} vidinfo_t;
143		-
	47	+#include <pxa_lcd.h>
144	48	#elif defined(CONFIG_ATMEL_LCD) \|\| defined(CONFIG_ATMEL_HLCD)
145		-
146		-typedef struct vidinfo {
147		- ushort vl_col; /* Number of columns (i.e. 640) */
148		- ushort vl_row; /* Number of rows (i.e. 480) */
149		- u_long vl_clk; /* pixel clock in ps */
150		-
151		- /* LCD configuration register */
152		- u_long vl_sync; /* Horizontal / vertical sync */
153		- u_long vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
154		- u_long vl_tft; /* 0 = passive, 1 = TFT */
155		- u_long vl_cont_pol_low; /* contrast polarity is low */
156		- u_long vl_clk_pol; /* clock polarity */
157		-
158		- /* Horizontal control register. */
159		- u_long vl_hsync_len; /* Length of horizontal sync */
160		- u_long vl_left_margin; /* Time from sync to picture */
161		- u_long vl_right_margin; /* Time from picture to sync */
162		-
163		- /* Vertical control register. */
164		- u_long vl_vsync_len; /* Length of vertical sync */
165		- u_long vl_upper_margin; /* Time from sync to picture */
166		- u_long vl_lower_margin; /* Time from picture to sync */
167		-
168		- u_long mmio; /* Memory mapped registers */
169		-} vidinfo_t;
170		-
	49	+#include <atmel_lcd.h>
171	50	#elif defined(CONFIG_EXYNOS_FB)
172		-
173		-enum {
174		- FIMD_RGB_INTERFACE = 1,
175		- FIMD_CPU_INTERFACE = 2,
176		-};
177		-
178		-enum exynos_fb_rgb_mode_t {
179		- MODE_RGB_P = 0,
180		- MODE_BGR_P = 1,
181		- MODE_RGB_S = 2,
182		- MODE_BGR_S = 3,
183		-};
184		-
185		-typedef struct vidinfo {
186		- ushort vl_col; /* Number of columns (i.e. 640) */
187		- ushort vl_row; /* Number of rows (i.e. 480) */
188		- ushort vl_width; /* Width of display area in millimeters */
189		- ushort vl_height; /* Height of display area in millimeters */
190		-
191		- /* LCD configuration register */
192		- u_char vl_freq; /* Frequency */
193		- u_char vl_clkp; /* Clock polarity */
194		- u_char vl_oep; /* Output Enable polarity */
195		- u_char vl_hsp; /* Horizontal Sync polarity */
196		- u_char vl_vsp; /* Vertical Sync polarity */
197		- u_char vl_dp; /* Data polarity */
198		- u_char vl_bpix; /* Bits per pixel */
199		-
200		- /* Horizontal control register. Timing from data sheet */
201		- u_char vl_hspw; /* Horz sync pulse width */
202		- u_char vl_hfpd; /* Wait before of line */
203		- u_char vl_hbpd; /* Wait end of line */
204		-
205		- /* Vertical control register. */
206		- u_char vl_vspw; /* Vertical sync pulse width */
207		- u_char vl_vfpd; /* Wait before of frame */
208		- u_char vl_vbpd; /* Wait end of frame */
209		- u_char vl_cmd_allow_len; /* Wait end of frame */
210		-
211		- unsigned int win_id;
212		- unsigned int init_delay;
213		- unsigned int power_on_delay;
214		- unsigned int reset_delay;
215		- unsigned int interface_mode;
216		- unsigned int mipi_enabled;
217		- unsigned int dp_enabled;
218		- unsigned int cs_setup;
219		- unsigned int wr_setup;
220		- unsigned int wr_act;
221		- unsigned int wr_hold;
222		- unsigned int logo_on;
223		- unsigned int logo_width;
224		- unsigned int logo_height;
225		- int logo_x_offset;
226		- int logo_y_offset;
227		- unsigned long logo_addr;
228		- unsigned int rgb_mode;
229		- unsigned int resolution;
230		-
231		- /* parent clock name(MPLL, EPLL or VPLL) */
232		- unsigned int pclk_name;
233		- /* ratio value for source clock from parent clock. */
234		- unsigned int sclk_div;
235		-
236		- unsigned int dual_lcd_enabled;
237		-} vidinfo_t;
238		-
239		-void init_panel_info(vidinfo_t *vid);
240		-
	51	+#include <exynos_lcd.h>
241	52	#else
242		-
243	53	typedef struct vidinfo {
244	54	ushort vl_col; /* Number of columns (i.e. 160) */
245	55	ushort vl_row; /* Number of rows (i.e. 100) */
...	...	@@ -250,8 +60,7 @@
250	60
251	61	void priv; / Pointer to driver-specific data */
252	62	} vidinfo_t;
253		-
254		-#endif /* CONFIG_MPC823, CONFIG_CPU_PXA25X, CONFIG_ATMEL_LCD */
	63	+#endif
255	64
256	65	extern vidinfo_t panel_info;
257	66
	1	+/*
	2	+ * mpc823_lcd.h - MPC823 LCD Controller structures
	3	+ *
	4	+ * (C) Copyright 2001
	5	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#ifndef _MPC823_LCD_H_
	11	+#define _MPC823_LCD_H_
	12	+
	13	+/*
	14	+ * LCD controller stucture for MPC823 CPU
	15	+ */
	16	+typedef struct vidinfo {
	17	+ ushort vl_col; /* Number of columns (i.e. 640) */
	18	+ ushort vl_row; /* Number of rows (i.e. 480) */
	19	+ ushort vl_width; /* Width of display area in millimeters */
	20	+ ushort vl_height; /* Height of display area in millimeters */
	21	+
	22	+ /* LCD configuration register */
	23	+ u_char vl_clkp; /* Clock polarity */
	24	+ u_char vl_oep; /* Output Enable polarity */
	25	+ u_char vl_hsp; /* Horizontal Sync polarity */
	26	+ u_char vl_vsp; /* Vertical Sync polarity */
	27	+ u_char vl_dp; /* Data polarity */
	28	+ u_char vl_bpix; /* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8 */
	29	+ u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
	30	+ u_char vl_splt; /* Split display, 0 = single-scan, 1 = dual-scan */
	31	+ u_char vl_clor; /* Color, 0 = mono, 1 = color */
	32	+ u_char vl_tft; /* 0 = passive, 1 = TFT */
	33	+
	34	+ /* Horizontal control register. Timing from data sheet */
	35	+ ushort vl_wbl; /* Wait between lines */
	36	+
	37	+ /* Vertical control register */
	38	+ u_char vl_vpw; /* Vertical sync pulse width */
	39	+ u_char vl_lcdac; /* LCD AC timing */
	40	+ u_char vl_wbf; /* Wait between frames */
	41	+} vidinfo_t;
	42	+
	43	+#endif
	1	+/*
	2	+ * pxa_lcd.h - PXA LCD Controller structures
	3	+ *
	4	+ * (C) Copyright 2001
	5	+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	6	+ *
	7	+ * SPDX-License-Identifier: GPL-2.0+
	8	+ */
	9	+
	10	+#ifndef _PXA_LCD_H_
	11	+#define _PXA_LCD_H_
	12	+
	13	+/*
	14	+ * PXA LCD DMA descriptor
	15	+ */
	16	+struct pxafb_dma_descriptor {
	17	+ u_long fdadr; /* Frame descriptor address register */
	18	+ u_long fsadr; /* Frame source address register */
	19	+ u_long fidr; /* Frame ID register */
	20	+ u_long ldcmd; /* Command register */
	21	+};
	22	+
	23	+/*
	24	+ * PXA LCD info
	25	+ */
	26	+struct pxafb_info {
	27	+ /* Misc registers */
	28	+ u_long reg_lccr3;
	29	+ u_long reg_lccr2;
	30	+ u_long reg_lccr1;
	31	+ u_long reg_lccr0;
	32	+ u_long fdadr0;
	33	+ u_long fdadr1;
	34	+
	35	+ /* DMA descriptors */
	36	+ struct pxafb_dma_descriptor *dmadesc_fblow;
	37	+ struct pxafb_dma_descriptor *dmadesc_fbhigh;
	38	+ struct pxafb_dma_descriptor *dmadesc_palette;
	39	+
	40	+ u_long screen; /* physical address of frame buffer */
	41	+ u_long palette; /* physical address of palette memory */
	42	+ u_int palette_size;
	43	+};
	44	+
	45	+/*
	46	+ * LCD controller stucture for PXA CPU
	47	+ */
	48	+typedef struct vidinfo {
	49	+ ushort vl_col; /* Number of columns (i.e. 640) */
	50	+ ushort vl_row; /* Number of rows (i.e. 480) */
	51	+ ushort vl_width; /* Width of display area in millimeters */
	52	+ ushort vl_height; /* Height of display area in millimeters */
	53	+
	54	+ /* LCD configuration register */
	55	+ u_char vl_clkp; /* Clock polarity */
	56	+ u_char vl_oep; /* Output Enable polarity */
	57	+ u_char vl_hsp; /* Horizontal Sync polarity */
	58	+ u_char vl_vsp; /* Vertical Sync polarity */
	59	+ u_char vl_dp; /* Data polarity */
	60	+ u_char vl_bpix;/* Bits per pixel, 0 = 1, 1 = 2, 2 = 4, 3 = 8, 4 = 16 */
	61	+ u_char vl_lbw; /* LCD Bus width, 0 = 4, 1 = 8 */
	62	+ u_char vl_splt;/* Split display, 0 = single-scan, 1 = dual-scan */
	63	+ u_char vl_clor; /* Color, 0 = mono, 1 = color */
	64	+ u_char vl_tft; /* 0 = passive, 1 = TFT */
	65	+
	66	+ /* Horizontal control register. Timing from data sheet */
	67	+ ushort vl_hpw; /* Horz sync pulse width */
	68	+ u_char vl_blw; /* Wait before of line */
	69	+ u_char vl_elw; /* Wait end of line */
	70	+
	71	+ /* Vertical control register. */
	72	+ u_char vl_vpw; /* Vertical sync pulse width */
	73	+ u_char vl_bfw; /* Wait before of frame */
	74	+ u_char vl_efw; /* Wait end of frame */
	75	+
	76	+ /* PXA LCD controller params */
	77	+ struct pxafb_info pxa;
	78	+} vidinfo_t;
	79	+
	80	+#endif