Blame view
board/zpc1900/zpc1900.c
12.3 KB
54387ac93
* Patch by Yuli B...
|
1 2 3 4 |
/* * (C) Copyright 2001-2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * |
aba9f1af6
Memory configurat...
|
5 |
* (C) Copyright 2003-2005 Arabella Software Ltd. |
|
54387ac93
* Patch by Yuli B...
|
6 7 |
* Yuli Barcohen <yuli@arabellasw.com> * |
1a4596601
Add GPL-2.0+ SPDX...
|
8 |
* SPDX-License-Identifier: GPL-2.0+ |
|
54387ac93
* Patch by Yuli B...
|
9 10 11 12 13 |
*/ #include <common.h> #include <ioports.h> #include <mpc8260.h> |
|
54387ac93
* Patch by Yuli B...
|
14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 |
#include <miiphy.h>
/*
* I/O Port configuration table
*
* if conf is 1, then that port pin will be configured at boot time
* according to the five values podr/pdir/ppar/psor/pdat for that entry
*/
const iop_conf_t iop_conf_tab[4][32] = {
/* Port A */
{ /* conf ppar psor pdir podr pdat */
/* PA31 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxENB */
/* PA30 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 TxClav */
/* PA29 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 TxSOC */
/* PA28 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 RxENB */
/* PA27 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxSOC */
/* PA26 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 RxClav */
/* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */
/* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */
/* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */
/* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */
/* PA21 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[4] */
/* PA20 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[5] */
/* PA19 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[6] */
/* PA18 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[7] */
/* PA17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[7] */
/* PA16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[6] */
/* PA15 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[5] */
/* PA14 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[4] */
/* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */
/* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */
/* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */
/* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */
/* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* SMC2 TXD */
/* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* SMC2 RXD */
/* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */
/* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */
/* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */
/* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */
/* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */
/* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */
/* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */
/* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */
},
/* Port B */
{ /* conf ppar psor pdir podr pdat */
/* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */
/* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */
/* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */
/* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */
/* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */
/* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */
/* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */
/* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */
/* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */
/* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */
/* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */
/* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */
/* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */
/* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */
/* PB17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */
/* PB16 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */
/* PB15 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */
/* PB14 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */
/* PB13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:COL */
/* PB12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:CRS */
/* PB11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB9 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB8 */ { 0, 1, 0, 0, 0, 0 }, /* FCC3:RXD */
/* PB7 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB6 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB5 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB4 */ { 0, 1, 0, 1, 0, 0 }, /* FCC3:TXD */
/* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
},
/* Port C */
{ /* conf ppar psor pdir podr pdat */
/* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */
/* PC30 */ { 0, 0, 0, 0, 0, 0 }, /* PC30 */
/* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN CLSN */
/* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */
/* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */
/* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */
/* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */
/* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */
/* PC23 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */
/* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */
/* PC21 */ { 0, 0, 0, 0, 0, 0 }, /* PC21 */
/* PC20 */ { 0, 0, 0, 0, 0, 0 }, /* PC20 */
/* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Rx Clock (CLK13) */
/* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII Tx Clock (CLK14) */
/* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */
/* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */
/* PC15 */ { 0, 0, 0, 0, 0, 0 }, /* PC15 */
/* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RENA */
/* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */
/* PC12 */ { 0, 0, 0, 0, 0, 0 }, /* PC12 */
/* PC11 */ { 0, 0, 0, 0, 0, 0 }, /* PC11 */
/* PC10 */ { 1, 0, 0, 1, 0, 0 }, /* LXT972 MDC */
/* PC9 */ { 1, 0, 0, 0, 0, 0 }, /* LXT972 MDIO */
/* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */
/* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */
/* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */
/* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */
/* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */
/* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */
/* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */
/* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */
/* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */
},
/* Port D */
{ /* conf ppar psor pdir podr pdat */
/* PD31 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */
/* PD30 */ { 0, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */
/* PD29 */ { 0, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */
/* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */
/* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */
/* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */
/* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */
/* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */
/* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */
/* PD22 */ { 0, 0, 0, 0, 0, 0 }, /* PD22 */
/* PD21 */ { 0, 0, 0, 0, 0, 0 }, /* PD21 */
/* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD20 */
/* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */
/* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */
/* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */
/* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */
|
|
aba9f1af6
Memory configurat...
|
151 152 |
/* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */
/* PD14 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SCL */
|
|
54387ac93
* Patch by Yuli B...
|
153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 |
/* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */
/* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */
/* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */
/* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */
/* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TXD */
/* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RXD */
/* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */
/* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */
/* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */
/* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */
/* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */
/* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */
}
};
|
6d0f6bcf3
rename CFG_ macro...
|
169 |
#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE |
|
54387ac93
* Patch by Yuli B...
|
170 171 172 173 174 175 176 |
void *nvram_read(void *dest, long src, size_t count)
{
return memcpy(dest, (const void *)src, count);
}
void nvram_write(long dest, const void *src, size_t count)
{
|
|
6d0f6bcf3
rename CFG_ macro...
|
177 178 |
vu_char *p1 = (vu_char *)(CONFIG_SYS_EEPROM + 0x1555); vu_char *p2 = (vu_char *)(CONFIG_SYS_EEPROM + 0x0AAA); |
|
54387ac93
* Patch by Yuli B...
|
179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 |
vu_char *d = (vu_char *)dest;
const uchar *s = (const uchar *)src;
/* Unprotect the EEPROM */
*p1 = 0xAA;
*p2 = 0x55;
*p1 = 0x80;
*p1 = 0xAA;
*p2 = 0x55;
*p1 = 0x20;
udelay(10000);
/* Write the data to the EEPROM */
while (count--) {
*d++ = *s++;
while (*(d - 1) != *(s - 1))
/* wait */;
}
/* Protect the EEPROM */
*p1 = 0xAA;
*p2 = 0x55;
*p1 = 0xA0;
udelay(10000);
}
|
|
6d0f6bcf3
rename CFG_ macro...
|
204 |
#endif /* CONFIG_SYS_NVRAM_ACCESS_ROUTINE */ |
|
54387ac93
* Patch by Yuli B...
|
205 |
|
9973e3c61
Change initdram()...
|
206 |
phys_size_t initdram(int board_type) |
|
54387ac93
* Patch by Yuli B...
|
207 |
{
|
|
6d0f6bcf3
rename CFG_ macro...
|
208 209 |
vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; |
|
54387ac93
* Patch by Yuli B...
|
210 211 212 |
volatile memctl8260_t *memctl = &immap->im_memctl; vu_char *ramaddr; uchar c = 0xFF; |
|
6d0f6bcf3
rename CFG_ macro...
|
213 |
long int msize = CONFIG_SYS_SDRAM_SIZE; |
|
54387ac93
* Patch by Yuli B...
|
214 215 216 |
int i;
if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
|
|
aba9f1af6
Memory configurat...
|
217 |
immap->im_clkrst.car_sccr |= SCCR_PCI_MODE; |
|
54387ac93
* Patch by Yuli B...
|
218 219 220 221 |
immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) | SIUMCR_LBPC01; } |
|
6d0f6bcf3
rename CFG_ macro...
|
222 |
#ifndef CONFIG_SYS_RAMBOOT |
|
54387ac93
* Patch by Yuli B...
|
223 224 225 |
immap->im_siu_conf.sc_ppc_acr = 0x03; immap->im_siu_conf.sc_ppc_alrh = 0x30126745; immap->im_siu_conf.sc_tescr1 = 0x00004000; |
|
6d0f6bcf3
rename CFG_ macro...
|
226 |
memctl->memc_mptpr = CONFIG_SYS_MPTPR; |
|
54387ac93
* Patch by Yuli B...
|
227 |
|
|
6d0f6bcf3
rename CFG_ macro...
|
228 |
#ifdef CONFIG_SYS_LSDRAM_BASE |
|
54387ac93
* Patch by Yuli B...
|
229 230 231 232 233 |
/*
Initialise local bus SDRAM only if the pins
are configured as local bus pins and not as PCI.
*/
if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
|
|
6d0f6bcf3
rename CFG_ macro...
|
234 235 236 237 238 |
memctl->memc_lsrt = CONFIG_SYS_LSRT; memctl->memc_or4 = CONFIG_SYS_LSDRAM_OR; memctl->memc_br4 = CONFIG_SYS_LSDRAM_BR; ramaddr = (vu_char *)CONFIG_SYS_LSDRAM_BASE; memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_PREA; |
|
54387ac93
* Patch by Yuli B...
|
239 |
*ramaddr = c; |
|
6d0f6bcf3
rename CFG_ macro...
|
240 |
memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_CBRR; |
|
54387ac93
* Patch by Yuli B...
|
241 242 |
for (i = 0; i < 8; i++) *ramaddr = c; |
|
6d0f6bcf3
rename CFG_ macro...
|
243 |
memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_MRW; |
|
54387ac93
* Patch by Yuli B...
|
244 |
*ramaddr = c; |
|
6d0f6bcf3
rename CFG_ macro...
|
245 |
memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_RFEN; |
|
54387ac93
* Patch by Yuli B...
|
246 |
} |
|
6d0f6bcf3
rename CFG_ macro...
|
247 |
#endif /* CONFIG_SYS_LSDRAM_BASE */ |
|
54387ac93
* Patch by Yuli B...
|
248 249 |
/* Initialise 60x bus SDRAM */ |
|
6d0f6bcf3
rename CFG_ macro...
|
250 251 252 |
memctl->memc_psrt = CONFIG_SYS_PSRT; memctl->memc_or2 = CONFIG_SYS_PSDRAM_OR; memctl->memc_br2 = CONFIG_SYS_PSDRAM_BR; |
|
54387ac93
* Patch by Yuli B...
|
253 254 255 256 257 258 259 260 261 |
/* * The mode data for Mode Register Write command must appear on * the address lines during a mode-set cycle. It is driven by * the memory controller, in single PowerQUICC II mode, * according to PSDMR[CL] and PSDMR[BL] fields. In * 60x-compatible mode, software must drive the correct value on * the address lines. BL=0 because for 64-bit port size burst * length must be 4. */ |
|
6d0f6bcf3
rename CFG_ macro...
|
262 263 264 |
ramaddr = (vu_char *)(CONFIG_SYS_SDRAM_BASE | ((CONFIG_SYS_PSDMR & PSDMR_CL_MSK) << 7) | 0x10); memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */ |
|
54387ac93
* Patch by Yuli B...
|
265 |
*ramaddr = c; |
|
6d0f6bcf3
rename CFG_ macro...
|
266 |
memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */ |
|
54387ac93
* Patch by Yuli B...
|
267 268 |
for (i = 0; i < 8; i++) *ramaddr = c; |
|
6d0f6bcf3
rename CFG_ macro...
|
269 |
memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_MRW; /* Mode Register write */ |
|
54387ac93
* Patch by Yuli B...
|
270 |
*ramaddr = c; |
|
6d0f6bcf3
rename CFG_ macro...
|
271 |
memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_RFEN; /* Refresh enable */ |
|
54387ac93
* Patch by Yuli B...
|
272 |
*ramaddr = c; |
|
6d0f6bcf3
rename CFG_ macro...
|
273 |
#endif /* CONFIG_SYS_RAMBOOT */ |
|
54387ac93
* Patch by Yuli B...
|
274 275 276 277 278 279 280 |
/* Return total 60x bus SDRAM size */
return msize * 1024 * 1024;
}
int checkboard(void)
{
|
|
6d0f6bcf3
rename CFG_ macro...
|
281 |
vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR; |
|
54387ac93
* Patch by Yuli B...
|
282 283 284 285 286 |
printf("Board: Zephyr ZPC.1900 Rev. %c
", bcsr[2] + 0x40);
return 0;
}
|