Memory configuration changes for ZPC.1900 board

- Fix SDRAM timing on both local bus and 60x bus - Add support for second flash bank (SIMM) - Change boot flash base Patch by Yuli Barcohen, 05 Jun 2005

Memory configuration changes for ZPC.1900 board
- Fix SDRAM timing on both local bus and 60x bus - Add support for second flash bank (SIMM) - Change boot flash base Patch by Yuli Barcohen, 05 Jun 2005
Wolfgang Denk
1 parent 5797b821dc
Showing 4 changed files with 55 additions and 54 deletions Side-by-side Diff
CHANGELOG
board/zpc1900/config.mk
board/zpc1900/zpc1900.c
include/configs/ZPC1900.h
@@ -2,6 +2,12 @@
 Changes since U-Boot 1.1.4:
 ======================================================================
  
+* Memory configuration changes for ZPC.1900 board
+  - Fix SDRAM timing on both local bus and 60x bus
+  - Add support for second flash bank (SIMM)
+  - Change boot flash base
+  Patch by Yuli Barcohen, 05 Jun 2005
+
 * Add support for Adder boards with 16MB SDRAM;
   add support for second FEC on Adder87x board.
   Patch by Yuli Barcohen, 05 Jun 2005
@@ -27,5 +27,5 @@
 # ZPC.1900 board
 #
  
-TEXT_BASE = 0xFFE00000
+TEXT_BASE = 0xFE000000
@@ -2,7 +2,7 @@
  * (C) Copyright 2001-2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
- * (C) Copyright 2003 Arabella Software Ltd.
+ * (C) Copyright 2003-2005 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  *
  * See file CREDITS for list of people who contributed to this
@@ -27,9 +27,6 @@
 #include <common.h>
 #include <ioports.h>
 #include <mpc8260.h>
-#include <asm/m8260_pci.h>
-#include <i2c.h>
-#include <spd.h>
 #include <miiphy.h>
  
 /*
@@ -167,8 +164,8 @@
 	/* PD18 */ {   0,   0,   0,   0,   0,   0   }, /* PD18 */
 	/* PD17 */ {   0,   1,   0,   0,   0,   0   }, /* FCC1 ATMRXPRTY */
 	/* PD16 */ {   0,   1,   0,   1,   0,   0   }, /* FCC1 ATMTXPRTY */
-	/* PD15 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SDA */
-	/* PD14 */ {   1,   1,   1,   0,   1,   0   }, /* I2C SCL */
+	/* PD15 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SDA */
+	/* PD14 */ {   0,   1,   1,   0,   1,   0   }, /* I2C SCL */
 	/* PD13 */ {   0,   0,   0,   0,   0,   0   }, /* PD13 */
 	/* PD12 */ {   0,   0,   0,   0,   0,   0   }, /* PD12 */
 	/* PD11 */ {   0,   0,   0,   0,   0,   0   }, /* PD11 */
  
@@ -231,11 +228,10 @@
 	vu_char *ramaddr;
 	uchar c = 0xFF;
 	long int msize = CFG_SDRAM_SIZE;
-	uint psdmr = CFG_PSDMR;
 	int i;
  
 	if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
-		immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
+		immap->im_clkrst.car_sccr |= SCCR_PCI_MODE;
 		immap->im_siu_conf.sc_siumcr =
 			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
 			| SIUMCR_LBPC01;
  
@@ -255,10 +251,10 @@
 	*/
 	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
 		memctl->memc_lsrt  = CFG_LSRT;
-		memctl->memc_or4   = 0xFFC01480;
-		memctl->memc_br4   = CFG_LSDRAM_BASE | 0x00001861;
-		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
+		memctl->memc_or4   = CFG_LSDRAM_OR;
+		memctl->memc_br4   = CFG_LSDRAM_BR;
 		ramaddr = (vu_char *)CFG_LSDRAM_BASE;
+		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
 		*ramaddr = c;
 		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
 		for (i = 0; i < 8; i++)
@@ -271,8 +267,8 @@
  
 	/* Initialise 60x bus SDRAM */
 	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_or2  = 0xFC0028C0;
-	memctl->memc_br2  = CFG_SDRAM_BASE | 0x00000041;
+	memctl->memc_or2  = CFG_PSDRAM_OR;
+	memctl->memc_br2  = CFG_PSDRAM_BR;
 	/*
 	 * The mode data for Mode Register Write command must appear on
 	 * the address lines during a mode-set cycle. It is driven by
  
  
  
@@ -283,15 +279,15 @@
 	 * length must be 4.
 	 */
 	ramaddr = (vu_char *)(CFG_SDRAM_BASE |
-			      ((psdmr & PSDMR_CL_MSK) << 7) | 0x10);
-	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
+			      ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
+	memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
 	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
+	memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
 	for (i = 0; i < 8; i++)
 		*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
+	memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW;  /* Mode Register write */
 	*ramaddr = c;
-	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
+	memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN;    /* Refresh enable */
 	*ramaddr = c;
 #endif /* CFG_RAMBOOT */
  
 /*
- * Copyright (C) 2003-2004 Arabella Software Ltd.
+ * Copyright (C) 2003-2005 Arabella Software Ltd.
  * Yuli Barcohen <yuli@arabellasw.com>
  *
  * U-Boot configuration for Zephyr Engineering ZPC.1900 board.
@@ -32,11 +32,7 @@
 #define CPU_ID_STR		"MPC8265"
 #define CONFIG_CPM2		1	/* Has a CPM2 */
  
-#undef DEBUG
-
-#undef CONFIG_BOARD_EARLY_INIT_F	/* Don't call board_early_init_f */
-
-/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */
+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
 #define CONFIG_ENV_OVERWRITE
  
 /*
@@ -113,7 +109,6 @@
 #define CONFIG_COMMANDS		(CONFIG_CMD_DFL   \
 				| CFG_CMD_ASKENV  \
 				| CFG_CMD_DHCP    \
-				| CFG_CMD_ECHO    \
 				| CFG_CMD_IMMAP   \
 				| CFG_CMD_MII     \
 				| CFG_CMD_PING    \
  
  
  
  
  
  
@@ -154,32 +149,31 @@
 #define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size  */
  
 #define CFG_MEMTEST_START	0x00100000	/* memtest works on */
-#define CFG_MEMTEST_END		0x00f00000	/* 1 ... 15 MB in DRAM	*/
+#define CFG_MEMTEST_END		0x03800000	/* 1 ... 56 MB in DRAM	*/
  
-#define CFG_LOAD_ADDR		0x100000	/* default load address */
+#define CFG_LOAD_ADDR		0x400000	/* default load address */
  
 #define CFG_HZ			1000	/* decrementer freq: 1 ms ticks */
  
 #define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200, 230400 }
  
-#define CFG_FLASH_BASE		0xFFE00000
-#define CFG_FLASH_CFI
-#define CFG_FLASH_CFI_DRIVER
-#define CFG_MAX_FLASH_BANKS	1	/* max num of flash banks	*/
-#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
-
-#define CFG_DEFAULT_IMMR	0x0F010000
-
-#define CFG_IMMR		0xF0000000
 #define CFG_SDRAM_BASE		0x00000000
 #define CFG_SDRAM_SIZE		64
-#define CFG_FLSIMM_BASE		0xFC000000
-#define CFG_LSDRAM_BASE		0xFE000000
+
+#define CFG_IMMR		0xF0000000
+#define CFG_LSDRAM_BASE		0xFC000000
+#define CFG_FLASH_BASE		0xFE000000
 #define CFG_BCSR		0xFEA00000
 #define CFG_EEPROM		0xFEB00000
+#define CFG_FLSIMM_BASE		0xFF000000
  
-#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE }
+#define CFG_FLASH_CFI
+#define CFG_FLASH_CFI_DRIVER
+#define CFG_MAX_FLASH_BANKS	2	/* max num of flash banks	*/
+#define CFG_MAX_FLASH_SECT	32	/* max num of sects on one chip */
  
+#define CFG_FLASH_BANKS_LIST	{ CFG_FLASH_BASE, CFG_FLSIMM_BASE }
+
 #define BCSR_PCI_MODE		0x01
  
 #define CFG_INIT_RAM_ADDR	CFG_IMMR
@@ -190,10 +184,10 @@
  
 /* Hard reset configuration word */
 #define CFG_HRCW_MASTER		(HRCW_EBM | HRCW_BPS01| HRCW_CIP          |\
-				 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB010 |\
-				 HRCW_BMS | HRCW_LBPC01 | HRCW_APPC10     |\
-				 HRCW_MODCK_H0101                          \
-				) /* 0x16828605 */
+				 HRCW_L2CPC10 | HRCW_DPPC00 | HRCW_ISB100 |\
+				 HRCW_BMS | HRCW_LBPC00 | HRCW_APPC10     |\
+				 HRCW_MODCK_H0111                          \
+				) /* 0x16848207 */
 /* No slaves */
 #define CFG_HRCW_SLAVE1 	0
 #define CFG_HRCW_SLAVE2 	0
@@ -211,7 +205,7 @@
 #define CFG_RAMBOOT
 #endif
  
-#define CFG_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
+#define CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
 #define CFG_MALLOC_LEN		(4096 << 10)	/* Reserve 4 MB for malloc()	*/
 #define CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux */
  
  
@@ -233,14 +227,14 @@
 #  define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
  
-#define CFG_HID0_INIT		0
-#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE )
+#define CFG_HID0_INIT		(HID0_ICFI)
+#define CFG_HID0_FINAL		(HID0_ICE | HID0_IFEM | HID0_ABE)
  
 #define CFG_HID2		0
  
 #define CFG_SIUMCR		0x42200000
 #define CFG_SYPCR		0xFFFFFFC3
-#define CFG_BCR			0x90400000
+#define CFG_BCR			0x90000000
 #define CFG_SCCR		SCCR_DFBRG01
  
 #define CFG_RMR			RMR_CSRE
  
  
@@ -248,18 +242,23 @@
 #define CFG_PISCR		(PISCR_PS|PISCR_PTF|PISCR_PTE)
 #define CFG_RCCR		0
  
-#define CFG_PSDMR		0x014EB45A
-#define CFG_PSRT		0x0C
-#define CFG_LSDMR		0x008AB552
-#define CFG_LSRT		0x0E
+#define CFG_PSDMR		/* 0x834DA43B */0x014DA43A
+#define CFG_PSRT		0x0F/* 0x0C */
+#define CFG_LSDMR		0x0085A562
+#define CFG_LSRT		0x0F
 #define CFG_MPTPR		0x4000
  
+#define CFG_PSDRAM_BR		CFG_SDRAM_BASE | 0x00000041
+#define CFG_PSDRAM_OR		0xFC0028C0
+#define CFG_LSDRAM_BR		CFG_LSDRAM_BASE | 0x00001861
+#define CFG_LSDRAM_OR		0xFF803480
+
 #define CFG_BR0_PRELIM		CFG_FLASH_BASE | 0x00000801
 #define CFG_OR0_PRELIM		0xFFE00856
 #define CFG_BR5_PRELIM		CFG_EEPROM | 0x00000801
 #define CFG_OR5_PRELIM		0xFFFF03F6
-#define CFG_BR6_PRELIM		CFG_FLSIMM_BASE | 0x00000801
-#define CFG_OR6_PRELIM		0xFE000856
+#define CFG_BR6_PRELIM		CFG_FLSIMM_BASE | 0x00001801
+#define CFG_OR6_PRELIM		0xFF000856
 #define CFG_BR7_PRELIM		CFG_BCSR | 0x00000801
 #define CFG_OR7_PRELIM		0xFFFF83F6
...	...	@@ -2,6 +2,12 @@
2	2	Changes since U-Boot 1.1.4:
3	3	======================================================================
4	4
	5	+* Memory configuration changes for ZPC.1900 board
	6	+ - Fix SDRAM timing on both local bus and 60x bus
	7	+ - Add support for second flash bank (SIMM)
	8	+ - Change boot flash base
	9	+ Patch by Yuli Barcohen, 05 Jun 2005
	10	+
5	11	* Add support for Adder boards with 16MB SDRAM;
6	12	add support for second FEC on Adder87x board.
7	13	Patch by Yuli Barcohen, 05 Jun 2005
...	...	@@ -27,5 +27,5 @@
27	27	# ZPC.1900 board
28	28	#
29	29
30		-TEXT_BASE = 0xFFE00000
	30	+TEXT_BASE = 0xFE000000
...	...	@@ -2,7 +2,7 @@
2	2	* (C) Copyright 2001-2003
3	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4	4	*
5		- * (C) Copyright 2003 Arabella Software Ltd.
	5	+ * (C) Copyright 2003-2005 Arabella Software Ltd.
6	6	* Yuli Barcohen <yuli@arabellasw.com>
7	7	*
8	8	* See file CREDITS for list of people who contributed to this
...	...	@@ -27,9 +27,6 @@
27	27	#include <common.h>
28	28	#include <ioports.h>
29	29	#include <mpc8260.h>
30		-#include <asm/m8260_pci.h>
31		-#include <i2c.h>
32		-#include <spd.h>
33	30	#include <miiphy.h>
34	31
35	32	/*
...	...	@@ -167,8 +164,8 @@
167	164	/* PD18 / { 0, 0, 0, 0, 0, 0 }, / PD18 */
168	165	/* PD17 / { 0, 1, 0, 0, 0, 0 }, / FCC1 ATMRXPRTY */
169	166	/* PD16 / { 0, 1, 0, 1, 0, 0 }, / FCC1 ATMTXPRTY */
170		- /* PD15 / { 1, 1, 1, 0, 1, 0 }, / I2C SDA */
171		- /* PD14 / { 1, 1, 1, 0, 1, 0 }, / I2C SCL */
	167	+ /* PD15 / { 0, 1, 1, 0, 1, 0 }, / I2C SDA */
	168	+ /* PD14 / { 0, 1, 1, 0, 1, 0 }, / I2C SCL */
172	169	/* PD13 / { 0, 0, 0, 0, 0, 0 }, / PD13 */
173	170	/* PD12 / { 0, 0, 0, 0, 0, 0 }, / PD12 */
174	171	/* PD11 / { 0, 0, 0, 0, 0, 0 }, / PD11 */
175	172
...	...	@@ -231,11 +228,10 @@
231	228	vu_char *ramaddr;
232	229	uchar c = 0xFF;
233	230	long int msize = CFG_SDRAM_SIZE;
234		- uint psdmr = CFG_PSDMR;
235	231	int i;
236	232
237	233	if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
238		- immap->im_clkrst.car_sccr \|= M826X_SCCR_PCI_MODE_EN;
	234	+ immap->im_clkrst.car_sccr \|= SCCR_PCI_MODE;
239	235	immap->im_siu_conf.sc_siumcr =
240	236	(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
241	237	\| SIUMCR_LBPC01;
242	238
...	...	@@ -255,10 +251,10 @@
255	251	*/
256	252	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
257	253	memctl->memc_lsrt = CFG_LSRT;
258		- memctl->memc_or4 = 0xFFC01480;
259		- memctl->memc_br4 = CFG_LSDRAM_BASE \| 0x00001861;
260		- memctl->memc_lsdmr = CFG_LSDMR \| PSDMR_OP_PREA;
	254	+ memctl->memc_or4 = CFG_LSDRAM_OR;
	255	+ memctl->memc_br4 = CFG_LSDRAM_BR;
261	256	ramaddr = (vu_char *)CFG_LSDRAM_BASE;
	257	+ memctl->memc_lsdmr = CFG_LSDMR \| PSDMR_OP_PREA;
262	258	*ramaddr = c;
263	259	memctl->memc_lsdmr = CFG_LSDMR \| PSDMR_OP_CBRR;
264	260	for (i = 0; i < 8; i++)
...	...	@@ -271,8 +267,8 @@
271	267
272	268	/* Initialise 60x bus SDRAM */
273	269	memctl->memc_psrt = CFG_PSRT;
274		- memctl->memc_or2 = 0xFC0028C0;
275		- memctl->memc_br2 = CFG_SDRAM_BASE \| 0x00000041;
	270	+ memctl->memc_or2 = CFG_PSDRAM_OR;
	271	+ memctl->memc_br2 = CFG_PSDRAM_BR;
276	272	/*
277	273	* The mode data for Mode Register Write command must appear on
278	274	* the address lines during a mode-set cycle. It is driven by
279	275
280	276
281	277
...	...	@@ -283,15 +279,15 @@
283	279	* length must be 4.
284	280	*/
285	281	ramaddr = (vu_char *)(CFG_SDRAM_BASE \|
286		- ((psdmr & PSDMR_CL_MSK) << 7) \| 0x10);
287		- memctl->memc_psdmr = psdmr \| PSDMR_OP_PREA; /* Precharge all banks */
	282	+ ((CFG_PSDMR & PSDMR_CL_MSK) << 7) \| 0x10);
	283	+ memctl->memc_psdmr = CFG_PSDMR \| PSDMR_OP_PREA; /* Precharge all banks */
288	284	*ramaddr = c;
289		- memctl->memc_psdmr = psdmr \| PSDMR_OP_CBRR; /* CBR refresh */
	285	+ memctl->memc_psdmr = CFG_PSDMR \| PSDMR_OP_CBRR; /* CBR refresh */
290	286	for (i = 0; i < 8; i++)
291	287	*ramaddr = c;
292		- memctl->memc_psdmr = psdmr \| PSDMR_OP_MRW; /* Mode Register write */
	288	+ memctl->memc_psdmr = CFG_PSDMR \| PSDMR_OP_MRW; /* Mode Register write */
293	289	*ramaddr = c;
294		- memctl->memc_psdmr = psdmr \| PSDMR_RFEN; /* Refresh enable */
	290	+ memctl->memc_psdmr = CFG_PSDMR \| PSDMR_RFEN; /* Refresh enable */
295	291	*ramaddr = c;
296	292	#endif /* CFG_RAMBOOT */
297	293
1	1	/*
2		- * Copyright (C) 2003-2004 Arabella Software Ltd.
	2	+ * Copyright (C) 2003-2005 Arabella Software Ltd.
3	3	* Yuli Barcohen <yuli@arabellasw.com>
4	4	*
5	5	* U-Boot configuration for Zephyr Engineering ZPC.1900 board.
...	...	@@ -32,11 +32,7 @@
32	32	#define CPU_ID_STR "MPC8265"
33	33	#define CONFIG_CPM2 1 /* Has a CPM2 */
34	34
35		-#undef DEBUG
36		-
37		-#undef CONFIG_BOARD_EARLY_INIT_F /* Don't call board_early_init_f */
38		-
39		-/* Allow serial number (serial) and MAC address (ethaddr) to be overwritten */
	35	+/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
40	36	#define CONFIG_ENV_OVERWRITE
41	37
42	38	/*
...	...	@@ -113,7 +109,6 @@
113	109	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \
114	110	\| CFG_CMD_ASKENV \
115	111	\| CFG_CMD_DHCP \
116		- \| CFG_CMD_ECHO \
117	112	\| CFG_CMD_IMMAP \
118	113	\| CFG_CMD_MII \
119	114	\| CFG_CMD_PING \
120	115
121	116
122	117
123	118
124	119
125	120
...	...	@@ -154,32 +149,31 @@
154	149	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
155	150
156	151	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
157		-#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
	152	+#define CFG_MEMTEST_END 0x03800000 /* 1 ... 56 MB in DRAM */
158	153
159		-#define CFG_LOAD_ADDR 0x100000 /* default load address */
	154	+#define CFG_LOAD_ADDR 0x400000 /* default load address */
160	155
161	156	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
162	157
163	158	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
164	159
165		-#define CFG_FLASH_BASE 0xFFE00000
166		-#define CFG_FLASH_CFI
167		-#define CFG_FLASH_CFI_DRIVER
168		-#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */
169		-#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
170		-
171		-#define CFG_DEFAULT_IMMR 0x0F010000
172		-
173		-#define CFG_IMMR 0xF0000000
174	160	#define CFG_SDRAM_BASE 0x00000000
175	161	#define CFG_SDRAM_SIZE 64
176		-#define CFG_FLSIMM_BASE 0xFC000000
177		-#define CFG_LSDRAM_BASE 0xFE000000
	162	+
	163	+#define CFG_IMMR 0xF0000000
	164	+#define CFG_LSDRAM_BASE 0xFC000000
	165	+#define CFG_FLASH_BASE 0xFE000000
178	166	#define CFG_BCSR 0xFEA00000
179	167	#define CFG_EEPROM 0xFEB00000
	168	+#define CFG_FLSIMM_BASE 0xFF000000
180	169
181		-#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
	170	+#define CFG_FLASH_CFI
	171	+#define CFG_FLASH_CFI_DRIVER
	172	+#define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */
	173	+#define CFG_MAX_FLASH_SECT 32 /* max num of sects on one chip */
182	174
	175	+#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLSIMM_BASE }
	176	+
183	177	#define BCSR_PCI_MODE 0x01
184	178
185	179	#define CFG_INIT_RAM_ADDR CFG_IMMR
...	...	@@ -190,10 +184,10 @@
190	184
191	185	/* Hard reset configuration word */
192	186	#define CFG_HRCW_MASTER (HRCW_EBM \| HRCW_BPS01\| HRCW_CIP \|\
193		- HRCW_L2CPC10 \| HRCW_DPPC00 \| HRCW_ISB010 \|\
194		- HRCW_BMS \| HRCW_LBPC01 \| HRCW_APPC10 \|\
195		- HRCW_MODCK_H0101 \
196		- ) /* 0x16828605 */
	187	+ HRCW_L2CPC10 \| HRCW_DPPC00 \| HRCW_ISB100 \|\
	188	+ HRCW_BMS \| HRCW_LBPC00 \| HRCW_APPC10 \|\
	189	+ HRCW_MODCK_H0111 \
	190	+ ) /* 0x16848207 */
197	191	/* No slaves */
198	192	#define CFG_HRCW_SLAVE1 0
199	193	#define CFG_HRCW_SLAVE2 0
...	...	@@ -211,7 +205,7 @@
211	205	#define CFG_RAMBOOT
212	206	#endif
213	207
214		-#define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
	208	+#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
215	209	#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */
216	210	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
217	211
218	212
...	...	@@ -233,14 +227,14 @@
233	227	# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
234	228	#endif
235	229
236		-#define CFG_HID0_INIT 0
237		-#define CFG_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE )
	230	+#define CFG_HID0_INIT (HID0_ICFI)
	231	+#define CFG_HID0_FINAL (HID0_ICE \| HID0_IFEM \| HID0_ABE)
238	232
239	233	#define CFG_HID2 0
240	234
241	235	#define CFG_SIUMCR 0x42200000
242	236	#define CFG_SYPCR 0xFFFFFFC3
243		-#define CFG_BCR 0x90400000
	237	+#define CFG_BCR 0x90000000
244	238	#define CFG_SCCR SCCR_DFBRG01
245	239
246	240	#define CFG_RMR RMR_CSRE
247	241
248	242
...	...	@@ -248,18 +242,23 @@
248	242	#define CFG_PISCR (PISCR_PS\|PISCR_PTF\|PISCR_PTE)
249	243	#define CFG_RCCR 0
250	244
251		-#define CFG_PSDMR 0x014EB45A
252		-#define CFG_PSRT 0x0C
253		-#define CFG_LSDMR 0x008AB552
254		-#define CFG_LSRT 0x0E
	245	+#define CFG_PSDMR /* 0x834DA43B */0x014DA43A
	246	+#define CFG_PSRT 0x0F/* 0x0C */
	247	+#define CFG_LSDMR 0x0085A562
	248	+#define CFG_LSRT 0x0F
255	249	#define CFG_MPTPR 0x4000
256	250
	251	+#define CFG_PSDRAM_BR CFG_SDRAM_BASE \| 0x00000041
	252	+#define CFG_PSDRAM_OR 0xFC0028C0
	253	+#define CFG_LSDRAM_BR CFG_LSDRAM_BASE \| 0x00001861
	254	+#define CFG_LSDRAM_OR 0xFF803480
	255	+
257	256	#define CFG_BR0_PRELIM CFG_FLASH_BASE \| 0x00000801
258	257	#define CFG_OR0_PRELIM 0xFFE00856
259	258	#define CFG_BR5_PRELIM CFG_EEPROM \| 0x00000801
260	259	#define CFG_OR5_PRELIM 0xFFFF03F6
261		-#define CFG_BR6_PRELIM CFG_FLSIMM_BASE \| 0x00000801
262		-#define CFG_OR6_PRELIM 0xFE000856
	260	+#define CFG_BR6_PRELIM CFG_FLSIMM_BASE \| 0x00001801
	261	+#define CFG_OR6_PRELIM 0xFF000856
263	262	#define CFG_BR7_PRELIM CFG_BCSR \| 0x00000801
264	263	#define CFG_OR7_PRELIM 0xFFFF83F6
265	264