Eric Lee / smarc-uboot

Blame view

arch/mips/lib/cache.c 2.7 KB
edit raw normal view history
30374f98d   Paul Burton   MIPS: unify cache... 
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
 
  /*
   * (C) Copyright 2003
   * Wolfgang Denk, DENX Software Engineering, <wd@denx.de>
   *
   * SPDX-License-Identifier:	GPL-2.0+
   */
  
  #include <common.h>
  #include <asm/cacheops.h>
  #include <asm/mipsregs.h>
  
  #ifdef CONFIG_SYS_CACHELINE_SIZE
  
  static inline unsigned long icache_line_size(void)
  {
  	return CONFIG_SYS_CACHELINE_SIZE;
  }
  
  static inline unsigned long dcache_line_size(void)
  {
  	return CONFIG_SYS_CACHELINE_SIZE;
  }
  
  #else /* !CONFIG_SYS_CACHELINE_SIZE */
  
  static inline unsigned long icache_line_size(void)
  {
  	unsigned long conf1, il;
  	conf1 = read_c0_config1();
a3ab2ae7f   Daniel Schwierzeck   MIPS: sync proces... 
30
 
  	il = (conf1 & MIPS_CONF1_IL) >> MIPS_CONF1_IL_SHF;
30374f98d   Paul Burton   MIPS: unify cache... 
31
32
33
34
35
36
37
38
39
 
  	if (!il)
  		return 0;
  	return 2 << il;
  }
  
  static inline unsigned long dcache_line_size(void)
  {
  	unsigned long conf1, dl;
  	conf1 = read_c0_config1();
a3ab2ae7f   Daniel Schwierzeck   MIPS: sync proces... 
40
 
  	dl = (conf1 & MIPS_CONF1_DL) >> MIPS_CONF1_DL_SHF;
30374f98d   Paul Burton   MIPS: unify cache... 
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
 
  	if (!dl)
  		return 0;
  	return 2 << dl;
  }
  
  #endif /* !CONFIG_SYS_CACHELINE_SIZE */
  
  void flush_cache(ulong start_addr, ulong size)
  {
  	unsigned long ilsize = icache_line_size();
  	unsigned long dlsize = dcache_line_size();
  	const void *addr, *aend;
  
  	/* aend will be miscalculated when size is zero, so we return here */
  	if (size == 0)
  		return;
  
  	addr = (const void *)(start_addr & ~(dlsize - 1));
  	aend = (const void *)((start_addr + size - 1) & ~(dlsize - 1));
  
  	if (ilsize == dlsize) {
  		/* flush I-cache & D-cache simultaneously */
  		while (1) {
  			mips_cache(HIT_WRITEBACK_INV_D, addr);
  			mips_cache(HIT_INVALIDATE_I, addr);
  			if (addr == aend)
  				break;
  			addr += dlsize;
  		}
  		return;
  	}
  
  	/* flush D-cache */
  	while (1) {
  		mips_cache(HIT_WRITEBACK_INV_D, addr);
  		if (addr == aend)
  			break;
  		addr += dlsize;
  	}
  
  	/* flush I-cache */
  	addr = (const void *)(start_addr & ~(ilsize - 1));
  	aend = (const void *)((start_addr + size - 1) & ~(ilsize - 1));
  	while (1) {
  		mips_cache(HIT_INVALIDATE_I, addr);
  		if (addr == aend)
  			break;
  		addr += ilsize;
  	}
  }
  
  void flush_dcache_range(ulong start_addr, ulong stop)
  {
  	unsigned long lsize = dcache_line_size();
  	const void *addr = (const void *)(start_addr & ~(lsize - 1));
  	const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
fbb0de088   Marek Vasut   mips: cache: Bull... 
97
98
99
 
  	/* aend will be miscalculated when size is zero, so we return here */
  	if (start_addr == stop)
  		return;
30374f98d   Paul Burton   MIPS: unify cache... 
100
101
102
103
104
105
106
107
108
109
110
111
112
 
  	while (1) {
  		mips_cache(HIT_WRITEBACK_INV_D, addr);
  		if (addr == aend)
  			break;
  		addr += lsize;
  	}
  }
  
  void invalidate_dcache_range(ulong start_addr, ulong stop)
  {
  	unsigned long lsize = dcache_line_size();
  	const void *addr = (const void *)(start_addr & ~(lsize - 1));
  	const void *aend = (const void *)((stop - 1) & ~(lsize - 1));
fbb0de088   Marek Vasut   mips: cache: Bull... 
113
114
115
 
  	/* aend will be miscalculated when size is zero, so we return here */
  	if (start_addr == stop)
  		return;
30374f98d   Paul Burton   MIPS: unify cache... 
116
117
118
119
120
121
122
 
  	while (1) {
  		mips_cache(HIT_INVALIDATE_D, addr);
  		if (addr == aend)
  			break;
  		addr += lsize;
  	}
  }