02 Feb, 2016

1 commit

• fbb0de088   mips: cache: Bulletproof the code against cornercases ... Browse Code »

  This patch makes sure that the flush/invalidate_dcache_range() functions
  can handle corner-case calls like this -- invalidate_dcache_range(0, 0, 0);
  This call is valid and is happily produced by USB EHCI code for example.
  The expected behavior of the cache function(s) in this case is that they
  will do no operation, since the size is zero.

  The current implementation though has a problem where such invocation will
  result in a hard CPU hang. This is because under such conditions, where the
  start_addr = 0 and stop = 0, the addr = 0 and aend = 0xffffffe0 . The loop
  will then try to iterate over the entire address space, which in itself is
  wrong. But iterating over the entire address space might also hit some odd
  address which will cause bus hang. The later happens on the Atheros MIPS.

  Signed-off-by: Marek Vasut
  Cc: Daniel Schwierzeck
  Cc: Hans de Goede

  Marek Vasut

  2016-02-02 05:13:24 +0800  

17 Jan, 2016

1 commit

• a3ab2ae7f   MIPS: sync processor and register definitions with linux-4.4 ... Browse Code »

  Update definitions for processor, registers as well as assemby
  macros.

  Signed-off-by: Daniel Schwierzeck

  Daniel Schwierzeck

  2016-01-17 04:06:46 +0800  

29 Jan, 2015

1 commit

• 30374f98d   MIPS: unify cache maintenance functions ... Browse Code »

  Move the more developed mips32 version of the cache maintenance
  functions to a common arch/mips/lib/cache.c, in order to reduce
  duplication between mips32 & mips64.

  Signed-off-by: Paul Burton
  Cc: Daniel Schwierzeck

  Paul Burton

  2015-01-29 19:55:00 +0800