Blame view
post/tests.c
6.09 KB
324f6cfd1
|
1 2 3 4 |
/* * (C) Copyright 2002 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * |
1a4596601
|
5 |
* SPDX-License-Identifier: GPL-2.0+ |
324f6cfd1
|
6 7 8 |
*/ #include <common.h> |
324f6cfd1
|
9 |
#include <post.h> |
6e8ec6822
|
10 |
extern int ocm_post_test (int flags); |
324f6cfd1
|
11 12 13 14 15 16 |
extern int cache_post_test (int flags); extern int watchdog_post_test (int flags); extern int i2c_post_test (int flags); extern int rtc_post_test (int flags); extern int memory_post_test (int flags); extern int cpu_post_test (int flags); |
a11e06965
|
17 |
extern int fpu_post_test (int flags); |
324f6cfd1
|
18 19 20 21 22 |
extern int uart_post_test (int flags); extern int ether_post_test (int flags); extern int spi_post_test (int flags); extern int usb_post_test (int flags); extern int spr_post_test (int flags); |
4532cb696
|
23 |
extern int sysmon_post_test (int flags); |
5a8c51cd5
|
24 |
extern int dsp_post_test (int flags); |
79fa88f3e
|
25 |
extern int codec_post_test (int flags); |
531e3e8b8
|
26 |
extern int ecc_post_test (int flags); |
f6f7395eb
|
27 |
extern int flash_post_test(int flags); |
4532cb696
|
28 |
|
65b20dcef
|
29 30 31 32 33 34 |
extern int dspic_init_post_test (int flags); extern int dspic_post_test (int flags); extern int gdc_post_test (int flags); extern int fpga_post_test (int flags); extern int lwmon5_watchdog_post_test(int flags); extern int sysmon1_post_test(int flags); |
29fd7ceb3
|
35 |
extern int coprocessor_post_test(int flags); |
2151374fa
|
36 37 |
extern int led_post_test(int flags); extern int button_post_test(int flags); |
8d3fcb5e6
|
38 |
extern int memory_regions_post_test(int flags); |
65b20dcef
|
39 |
|
4532cb696
|
40 41 42 |
extern int sysmon_init_f (void); extern void sysmon_reloc (void); |
324f6cfd1
|
43 44 45 |
struct post_test post_list[] = { |
6d0f6bcf3
|
46 |
#if CONFIG_POST & CONFIG_SYS_POST_OCM |
6e8ec6822
|
47 48 49 50 |
{ "OCM test", "ocm", "This test checks on chip memory (OCM).", |
7845d4909
|
51 |
POST_ROM | POST_ALWAYS | POST_PREREL | POST_CRITICAL | POST_STOP, |
6e8ec6822
|
52 53 54 |
&ocm_post_test, NULL, NULL, |
6d0f6bcf3
|
55 |
CONFIG_SYS_POST_OCM |
6e8ec6822
|
56 57 |
}, #endif |
6d0f6bcf3
|
58 |
#if CONFIG_POST & CONFIG_SYS_POST_CACHE |
324f6cfd1
|
59 |
{ |
8bde7f776
|
60 61 62 63 64 65 66 |
"Cache test", "cache", "This test verifies the CPU cache operation.", POST_RAM | POST_ALWAYS, &cache_post_test, NULL, NULL, |
6d0f6bcf3
|
67 |
CONFIG_SYS_POST_CACHE |
324f6cfd1
|
68 69 |
}, #endif |
6d0f6bcf3
|
70 |
#if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG |
65b20dcef
|
71 72 73 |
#if defined(CONFIG_POST_WATCHDOG) CONFIG_POST_WATCHDOG, #else |
324f6cfd1
|
74 |
{ |
8bde7f776
|
75 76 77 |
"Watchdog timer test", "watchdog", "This test checks the watchdog timer.", |
8564acf93
|
78 |
POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, |
8bde7f776
|
79 80 81 |
&watchdog_post_test, NULL, NULL, |
6d0f6bcf3
|
82 |
CONFIG_SYS_POST_WATCHDOG |
324f6cfd1
|
83 84 |
}, #endif |
65b20dcef
|
85 |
#endif |
6d0f6bcf3
|
86 |
#if CONFIG_POST & CONFIG_SYS_POST_I2C |
324f6cfd1
|
87 |
{ |
8bde7f776
|
88 89 90 91 92 93 94 |
"I2C test", "i2c", "This test verifies the I2C operation.", POST_RAM | POST_ALWAYS, &i2c_post_test, NULL, NULL, |
6d0f6bcf3
|
95 |
CONFIG_SYS_POST_I2C |
324f6cfd1
|
96 97 |
}, #endif |
6d0f6bcf3
|
98 |
#if CONFIG_POST & CONFIG_SYS_POST_RTC |
324f6cfd1
|
99 |
{ |
8bde7f776
|
100 101 102 |
"RTC test", "rtc", "This test verifies the RTC operation.", |
8564acf93
|
103 |
POST_RAM | POST_SLOWTEST | POST_MANUAL, |
8bde7f776
|
104 105 106 |
&rtc_post_test, NULL, NULL, |
6d0f6bcf3
|
107 |
CONFIG_SYS_POST_RTC |
324f6cfd1
|
108 109 |
}, #endif |
6d0f6bcf3
|
110 |
#if CONFIG_POST & CONFIG_SYS_POST_MEMORY |
324f6cfd1
|
111 |
{ |
8bde7f776
|
112 113 114 |
"Memory test", "memory", "This test checks RAM.", |
8564acf93
|
115 |
POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL, |
8bde7f776
|
116 117 118 |
&memory_post_test, NULL, NULL, |
6d0f6bcf3
|
119 |
CONFIG_SYS_POST_MEMORY |
324f6cfd1
|
120 121 |
}, #endif |
6d0f6bcf3
|
122 |
#if CONFIG_POST & CONFIG_SYS_POST_CPU |
324f6cfd1
|
123 |
{ |
8bde7f776
|
124 125 126 127 128 129 130 131 |
"CPU test", "cpu", "This test verifies the arithmetic logic unit of" " CPU.", POST_RAM | POST_ALWAYS, &cpu_post_test, NULL, NULL, |
6d0f6bcf3
|
132 |
CONFIG_SYS_POST_CPU |
324f6cfd1
|
133 134 |
}, #endif |
6d0f6bcf3
|
135 |
#if CONFIG_POST & CONFIG_SYS_POST_FPU |
a11e06965
|
136 137 138 139 140 141 142 143 144 |
{ "FPU test", "fpu", "This test verifies the arithmetic logic unit of" " FPU.", POST_RAM | POST_ALWAYS, &fpu_post_test, NULL, NULL, |
6d0f6bcf3
|
145 |
CONFIG_SYS_POST_FPU |
a11e06965
|
146 147 |
}, #endif |
6d0f6bcf3
|
148 |
#if CONFIG_POST & CONFIG_SYS_POST_UART |
834a45d7e
|
149 150 151 |
#if defined(CONFIG_POST_UART) CONFIG_POST_UART, #else |
324f6cfd1
|
152 |
{ |
8bde7f776
|
153 154 155 |
"UART test", "uart", "This test verifies the UART operation.", |
8564acf93
|
156 |
POST_RAM | POST_SLOWTEST | POST_MANUAL, |
8bde7f776
|
157 158 159 |
&uart_post_test, NULL, NULL, |
6d0f6bcf3
|
160 |
CONFIG_SYS_POST_UART |
324f6cfd1
|
161 |
}, |
834a45d7e
|
162 |
#endif /* CONFIG_POST_UART */ |
324f6cfd1
|
163 |
#endif |
6d0f6bcf3
|
164 |
#if CONFIG_POST & CONFIG_SYS_POST_ETHER |
324f6cfd1
|
165 |
{ |
8bde7f776
|
166 167 168 |
"ETHERNET test", "ethernet", "This test verifies the ETHERNET operation.", |
5735bca5f
|
169 |
POST_RAM | POST_ALWAYS, |
8bde7f776
|
170 171 172 |
ðer_post_test, NULL, NULL, |
6d0f6bcf3
|
173 |
CONFIG_SYS_POST_ETHER |
324f6cfd1
|
174 175 |
}, #endif |
6d0f6bcf3
|
176 |
#if CONFIG_POST & CONFIG_SYS_POST_USB |
324f6cfd1
|
177 |
{ |
8bde7f776
|
178 179 180 |
"USB test", "usb", "This test verifies the USB operation.", |
5735bca5f
|
181 |
POST_RAM | POST_ALWAYS, |
8bde7f776
|
182 183 184 |
&usb_post_test, NULL, NULL, |
6d0f6bcf3
|
185 |
CONFIG_SYS_POST_USB |
324f6cfd1
|
186 187 |
}, #endif |
6d0f6bcf3
|
188 |
#if CONFIG_POST & CONFIG_SYS_POST_SPR |
324f6cfd1
|
189 |
{ |
8bde7f776
|
190 191 192 |
"SPR test", "spr", "This test checks SPR contents.", |
b2e2142c5
|
193 |
POST_RAM | POST_ALWAYS, |
8bde7f776
|
194 195 196 |
&spr_post_test, NULL, NULL, |
6d0f6bcf3
|
197 |
CONFIG_SYS_POST_SPR |
324f6cfd1
|
198 199 |
}, #endif |
6d0f6bcf3
|
200 |
#if CONFIG_POST & CONFIG_SYS_POST_SYSMON |
4532cb696
|
201 |
{ |
8bde7f776
|
202 203 204 205 206 207 208 |
"SYSMON test", "sysmon", "This test monitors system hardware.", POST_RAM | POST_ALWAYS, &sysmon_post_test, &sysmon_init_f, &sysmon_reloc, |
6d0f6bcf3
|
209 |
CONFIG_SYS_POST_SYSMON |
4532cb696
|
210 211 |
}, #endif |
6d0f6bcf3
|
212 |
#if CONFIG_POST & CONFIG_SYS_POST_DSP |
5a8c51cd5
|
213 214 215 216 |
{ "DSP test", "dsp", "This test checks any connected DSP(s).", |
5735bca5f
|
217 |
POST_RAM | POST_ALWAYS, |
5a8c51cd5
|
218 219 220 |
&dsp_post_test, NULL, NULL, |
6d0f6bcf3
|
221 |
CONFIG_SYS_POST_DSP |
5a8c51cd5
|
222 223 |
}, #endif |
6d0f6bcf3
|
224 |
#if CONFIG_POST & CONFIG_SYS_POST_CODEC |
79fa88f3e
|
225 226 227 228 229 230 231 232 |
{ "CODEC test", "codec", "This test checks any connected codec(s).", POST_RAM | POST_MANUAL, &codec_post_test, NULL, NULL, |
6d0f6bcf3
|
233 |
CONFIG_SYS_POST_CODEC |
79fa88f3e
|
234 235 |
}, #endif |
6d0f6bcf3
|
236 |
#if CONFIG_POST & CONFIG_SYS_POST_ECC |
531e3e8b8
|
237 238 239 |
{ "ECC test", "ecc", |
8dafa8747
|
240 241 |
"This test checks the ECC facility of memory.", POST_ROM | POST_ALWAYS | POST_PREREL, |
531e3e8b8
|
242 243 244 |
&ecc_post_test, NULL, NULL, |
6d0f6bcf3
|
245 |
CONFIG_SYS_POST_ECC |
531e3e8b8
|
246 247 |
}, #endif |
6d0f6bcf3
|
248 |
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1 |
65b20dcef
|
249 250 |
CONFIG_POST_BSPEC1, #endif |
6d0f6bcf3
|
251 |
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC2 |
65b20dcef
|
252 253 |
CONFIG_POST_BSPEC2, #endif |
6d0f6bcf3
|
254 |
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC3 |
65b20dcef
|
255 256 |
CONFIG_POST_BSPEC3, #endif |
6d0f6bcf3
|
257 |
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC4 |
65b20dcef
|
258 259 |
CONFIG_POST_BSPEC4, #endif |
6d0f6bcf3
|
260 |
#if CONFIG_POST & CONFIG_SYS_POST_BSPEC5 |
65b20dcef
|
261 262 |
CONFIG_POST_BSPEC5, #endif |
29fd7ceb3
|
263 264 265 266 267 268 269 270 271 272 |
#if CONFIG_POST & CONFIG_SYS_POST_COPROC { "Coprocessors communication test", "coproc_com", "This test checks communication with coprocessors.", POST_RAM | POST_ALWAYS | POST_CRITICAL, &coprocessor_post_test, NULL, NULL, CONFIG_SYS_POST_COPROC |
f6f7395eb
|
273 274 275 276 277 278 279 280 281 282 283 284 285 |
}, #endif #if CONFIG_POST & CONFIG_SYS_POST_FLASH { "Parallel NOR flash test", "flash", "This test verifies parallel flash operations.", POST_RAM | POST_SLOWTEST | POST_MANUAL, &flash_post_test, NULL, NULL, CONFIG_SYS_POST_FLASH }, |
29fd7ceb3
|
286 |
#endif |
8d3fcb5e6
|
287 288 289 290 291 292 293 294 295 296 297 298 |
#if CONFIG_POST & CONFIG_SYS_POST_MEM_REGIONS { "Memory regions test", "mem_regions", "This test checks regularly placed regions of the RAM.", POST_ROM | POST_SLOWTEST | POST_PREREL, &memory_regions_post_test, NULL, NULL, CONFIG_SYS_POST_MEM_REGIONS }, #endif |
324f6cfd1
|
299 |
}; |
d2397817f
|
300 |
unsigned int post_list_size = ARRAY_SIZE(post_list); |