Eric Lee / smarc-uboot

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Commit 8564acf936726c5568d71e4fa93a0ae9814e0d07

Authored by wdenk
1 parent 5702923e23
Exists in master and in 54 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

* Patches by Yuli Barcohen, 13 Jul 2003: 

- Correct flash and JFFS2 support for MPC8260ADS
  - fix PVR values and clock generation for PowerQUICC II family
    (8270/8275/8280)

* Patch by Bernhard Kuhn, 08 Jul 2003:
  - add support for M68K targets

* Patch by Ken Chou, 3 Jul:
  - Fix PCI config table for A3000
  - Fix iobase for natsemi.c
    (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)

* Allow to enable "slow" POST routines by key press on power-on
* Fix temperature dependend switching of LCD backlight on LWMON
* Tweak output format for LWMON

Showing 40 changed files with 819 additions and 446 deletions Side-by-side Diff

1 1 ======================================================================
2   -Changes for U-Boot 0.4.2:
  2 +Changes for U-Boot 0.4.3:
3 3 ======================================================================
4 4  
  5 +* Patches by Yuli Barcohen, 13 Jul 2003:
  6 + - Correct flash and JFFS2 support for MPC8260ADS
  7 + - fix PVR values and clock generation for PowerQUICC II family
  8 + (8270/8275/8280)
  9 +
  10 +* Patch by Bernhard Kuhn, 08 Jul 2003:
  11 + - add support for M68K targets
  12 +
  13 +* Patch by Ken Chou, 3 Jul:
  14 + - Fix PCI config table for A3000
  15 + - Fix iobase for natsemi.c
  16 + (PCI_BASE_ADDRESS_0 is the IO base register for DP83815)
  17 +
  18 +* Allow to enable "slow" POST routines by key press on power-on
  19 +* Fix temperature dependend switching of LCD backlight on LWMON
  20 +* Tweak output format for LWMON
  21 +
5 22 * Patch by Stefan Roese, 11 Jul 2003:
6 23 - Fix bug in CONFIG_VERSION_VARIABLE.
7 24 - AR405 config updated.
8 25 - OCRTC/ORSG: bsp command added.
9 26 - ASH405 bsp update.
  27 +
  28 +======================================================================
  29 +Changes for U-Boot 0.4.2:
  30 +======================================================================
10 31  
11 32 * Add support for NSCU board
12 33  
... ... @@ -72,7 +72,6 @@
72 72 TQM855L MPC855
73 73 TQM860L MPC860
74 74 TQM860L_FEC MPC860
75   - TTTech MPC823
76 75 c2mon MPC855
77 76 hermes MPC860
78 77 lwmon MPC823
... ... @@ -36,7 +36,7 @@
36 36 rmu RPXClassic RPXlite RRvision \
37 37 SM850 SPD823TS svm_sc8xx SXNI855T \
38 38 TOP860 TQM823L TQM823L_LCD TQM850L \
39   - TQM855L TQM860L TTTech v37 \
  39 + TQM855L TQM860L v37 \
40 40 "
41 41  
42 42 #########################################################################
... ... @@ -1481,6 +1481,16 @@
1481 1481 - CFG_FLASH_WRITE_TOUT:
1482 1482 Timeout for Flash write operations (in ms)
1483 1483  
  1484 +- CFG_FLASH_LOCK_TOUT
  1485 + Timeout for Flash set sector lock bit operation (in ms)
  1486 +
  1487 +- CFG_FLASH_UNLOCK_TOUT
  1488 + Timeout for Flash clear lock bits operation (in ms)
  1489 +
  1490 +- CFG_FLASH_PROTECTION
  1491 + If defined, hardware flash sectors protection is used
  1492 + instead of U-Boot software protection.
  1493 +
1484 1494 - CFG_DIRECT_FLASH_TFTP:
1485 1495  
1486 1496 Enable TFTP transfers directly to flash memory;
board/RRvision/video_ad7179.h
Diff comments   View file @ 8564acf
  1 +/*
  2 + * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#define VIDEO_ENCODER_NAME "Analog Devices AD7179"
  24 +
  25 +#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */
  26 +#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
  27 +
  28 +#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
  29 +#undef VIDEO_MODE_RGB
  30 +#define VIDEO_MODE_BPP 16
  31 +
  32 +#ifdef VIDEO_MODE_PAL
  33 +#define VIDEO_ACTIVE_COLS 720
  34 +#define VIDEO_ACTIVE_ROWS 576
  35 +#define VIDEO_VISIBLE_COLS 640
  36 +#define VIDEO_VISIBLE_ROWS 480
  37 +#else
  38 +#error "NTSC mode is not supported"
  39 +#endif
  40 +
  41 +static unsigned char video_encoder_data[] = {
  42 + 0x05, /* Mode Register 0 */
  43 + 0x11, /* Mode Register 1 */
  44 + 0x20, /* Mode Register 2 */
  45 + 0x0C, /* Mode Register 3 */
  46 + 0x01, /* Mode Register 4 */
  47 + 0x00, /* Reserved */
  48 + 0x00, /* Reserved */
  49 + 0x04, /* Timing Register 0 */
  50 + 0x00, /* Timing Register 1 */
  51 + 0xCB, /* Subcarrier Frequency Register 0 */
  52 + 0x0A, /* Subcarrier Frequency Register 1 */
  53 + 0x09, /* Subcarrier Frequency Register 2 */
  54 + 0x2A, /* Subcarrier Frequency Register 3 */
  55 + 0x00, /* Subcarrier Phase */
  56 + 0x00, /* Closed Captioning Ext Reg 0 */
  57 + 0x00, /* Closed Captioning Ext Reg 1 */
  58 + 0x00, /* Closed Captioning Reg 0 */
  59 + 0x00, /* Closed Captioning Reg 1 */
  60 + 0x00, /* Pedestal Control Reg 0 */
  61 + 0x00, /* Pedestal Control Reg 1 */
  62 + 0x00, /* Pedestal Control Reg 2 */
  63 + 0x00, /* Pedestal Control Reg 3 */
  64 + 0x00, /* CGMS_WSS Reg 0 */
  65 + 0x00, /* CGMS_WSS Reg 0 */
  66 + 0x00, /* CGMS_WSS Reg 0 */
  67 + 0x00 /* Teletext Req. Control Reg */
  68 +} ;
... ... @@ -2,6 +2,9 @@
2 2 * (C) Copyright 2001
3 3 * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
4 4 *
  5 + * Modified during 2003 by
  6 + * Ken Chou, kchou@ieee.org
  7 + *
5 8 * See file CREDITS for list of people who contributed to this
6 9 * project.
7 10 *
8 11  
9 12  
10 13  
11 14  
12 15  
... ... @@ -86,50 +89,40 @@
86 89 /*
87 90 * Initialize PCI Devices
88 91 */
89   -#if 1
90 92 #ifndef CONFIG_PCI_PNP
91 93 static struct pci_config_table pci_a3000_config_table[] = {
92   - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
93   - 0x0, 0x0, 0x0, /* unknown eth0 divice */
  94 + /* vendor, device, class */
  95 + /* bus, dev, func */
  96 + { PCI_VENDOR_ID_NS, PCI_DEVICE_ID_NS_83815, PCI_ANY_ID,
  97 + PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, /* dp83815 eth0 divice */
94 98 pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
95 99 PCI_ENET0_MEMADDR,
96 100 PCI_COMMAND_IO |
97 101 PCI_COMMAND_MEMORY |
98 102 PCI_COMMAND_MASTER }},
99 103 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
100   - 0x0, 0x0, 0x0, /* unknown eth1 device */
  104 + PCI_ANY_ID, 0x14, PCI_ANY_ID, /* PCI slot1 */
101 105 pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
102 106 PCI_ENET1_MEMADDR,
103 107 PCI_COMMAND_IO |
104 108 PCI_COMMAND_MEMORY |
105 109 PCI_COMMAND_MASTER }},
106 110 { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
107   - 0x0, 0x0, 0x0, /* unknown eth1 device */
  111 + PCI_ANY_ID, 0x15, PCI_ANY_ID, /* PCI slot2 */
108 112 pci_cfgfunc_config_device, { PCI_ENET2_IOADDR,
109 113 PCI_ENET2_MEMADDR,
110 114 PCI_COMMAND_IO |
111 115 PCI_COMMAND_MEMORY |
112 116 PCI_COMMAND_MASTER }},
  117 + { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  118 + PCI_ANY_ID, 0x16, PCI_ANY_ID, /* PCI slot3 */
  119 + pci_cfgfunc_config_device, { PCI_ENET3_IOADDR,
  120 + PCI_ENET3_MEMADDR,
  121 + PCI_COMMAND_IO |
  122 + PCI_COMMAND_MEMORY |
  123 + PCI_COMMAND_MASTER }},
113 124 { }
114 125 };
115   -#endif
116   -
117   -#else
118   -
119   -#ifndef CONFIG_PCI_PNP
120   -static struct pci_config_table pci_a3000_config_table[] = {
121   - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x0f, PCI_ANY_ID,
122   - pci_cfgfunc_config_device, { PCI_ENET0_IOADDR,
123   - PCI_ENET0_MEMADDR,
124   - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
125   - { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, 0x10, PCI_ANY_ID,
126   - pci_cfgfunc_config_device, { PCI_ENET1_IOADDR,
127   - PCI_ENET1_MEMADDR,
128   - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER }},
129   - { }
130   -};
131   -#endif
132   -
133 126 #endif
134 127  
135 128 struct pci_controller hose = {
board/gen860t/gen860t.c
Diff comments   View file @ 8564acf
... ... @@ -302,5 +302,16 @@
302 302 while (1);
303 303 }
304 304  
  305 +#ifdef CONFIG_POST
  306 +/*
  307 + * Returns 1 if keys pressed to start the power-on long-running tests
  308 + * Called from board_init_f().
  309 + */
  310 +int post_hotkeys_pressed(void)
  311 +{
  312 + return 0; /* No hotkeys supported */
  313 +}
  314 +#endif
  315 +
305 316 /* vim: set ts=4 sw=4 tw=78 : */
... ... @@ -184,7 +184,7 @@
184 184 ***********************************************************************/
185 185 int checkboard (void)
186 186 {
187   - puts ("Board: Litronic Monitor IV\n");
  187 + puts ("Board: LICCON Konsole LCD2\n");
188 188 return (0);
189 189 }
190 190  
... ... @@ -1071,4 +1071,24 @@
1071 1071 return (compare_magic(kbd_data, CONFIG_MODEM_KEY_MAGIC) == 0);
1072 1072 }
1073 1073 #endif /* CONFIG_MODEM_SUPPORT */
  1074 +
  1075 +#ifdef CONFIG_POST
  1076 +/*
  1077 + * Returns 1 if keys pressed to start the power-on long-running tests
  1078 + * Called from board_init_f().
  1079 + */
  1080 +int post_hotkeys_pressed(gd_t *gd)
  1081 +{
  1082 + uchar kbd_data[KEYBD_DATALEN];
  1083 + uchar val;
  1084 +
  1085 + /* Read keys */
  1086 + val = KEYBD_CMD_READ_KEYS;
  1087 + i2c_write (kbd_addr, 0, 0, &val, 1);
  1088 + i2c_read (kbd_addr, 0, 0, kbd_data, KEYBD_DATALEN);
  1089 +
  1090 + return (gd->post_hotkeys_latch =
  1091 + (compare_magic(kbd_data, CONFIG_POST_KEY_MAGIC) == 0));
  1092 +}
  1093 +#endif
board/mpc8260ads/flash.c
Diff comments   View file @ 8564acf
... ... @@ -7,6 +7,11 @@
7 7 * I started with board/ip860/flash.c and made changes I found in
8 8 * the MTD project by David Schleef.
9 9 *
  10 + * (C) Copyright 2003 Arabella Software Ltd.
  11 + * Yuli Barcohen <yuli@arabellasw.com>
  12 + * Re-written to support multi-bank flash SIMMs.
  13 + * Added support for real protection and JFFS2.
  14 + *
10 15 * See file CREDITS for list of people who contributed to this
11 16 * project.
12 17 *
13 18  
14 19  
15 20  
16 21  
17 22  
18 23  
19 24  
20 25  
21 26  
22 27  
23 28  
24 29  
... ... @@ -28,74 +33,120 @@
28 33  
29 34 #include <common.h>
30 35  
  36 +/* Intel-compatible flash ID */
  37 +#define INTEL_COMPAT 0x89898989
  38 +#define INTEL_ALT 0xB0B0B0B0
31 39  
32   -flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
  40 +/* Intel-compatible flash commands */
  41 +#define INTEL_PROGRAM 0x10101010
  42 +#define INTEL_ERASE 0x20202020
  43 +#define INTEL_CLEAR 0x50505050
  44 +#define INTEL_LOCKBIT 0x60606060
  45 +#define INTEL_PROTECT 0x01010101
  46 +#define INTEL_STATUS 0x70707070
  47 +#define INTEL_READID 0x90909090
  48 +#define INTEL_CONFIRM 0xD0D0D0D0
  49 +#define INTEL_RESET 0xFFFFFFFF
33 50  
34   -#if defined(CFG_ENV_IS_IN_FLASH)
35   -# ifndef CFG_ENV_ADDR
36   -# define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_ENV_OFFSET)
37   -# endif
38   -# ifndef CFG_ENV_SIZE
39   -# define CFG_ENV_SIZE CFG_ENV_SECT_SIZE
40   -# endif
41   -# ifndef CFG_ENV_SECT_SIZE
42   -# define CFG_ENV_SECT_SIZE CFG_ENV_SIZE
43   -# endif
44   -#endif
  51 +/* Intel-compatible flash status bits */
  52 +#define INTEL_FINISHED 0x80808080
  53 +#define INTEL_OK 0x80808080
45 54  
46   -/*-----------------------------------------------------------------------
47   - * Functions
48   - */
49   -static ulong flash_get_size (vu_long *addr, flash_info_t *info);
50   -static int write_word (flash_info_t *info, ulong dest, ulong data);
51   -static int clear_block_lock_bit(vu_long * addr);
  55 +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
52 56  
53 57 /*-----------------------------------------------------------------------
  58 + * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
  59 + * Up to 32MB of flash supported (up to 4 banks.)
  60 + * BCSR is used for flash presence detect (page 4-65 of the User's Manual)
  61 + *
  62 + * The following code can not run from flash!
54 63 */
55   -
56 64 unsigned long flash_init (void)
57 65 {
58   -#ifndef CONFIG_MPC8260ADS
59   - volatile immap_t *immap = (immap_t *)CFG_IMMR;
60   - volatile memctl8xx_t *memctl = &immap->im_memctl;
61   - volatile ip860_bcsr_t *bcsr = (ip860_bcsr_t *)BCSR_BASE;
62   -#endif
63   - unsigned long size;
64   - int i;
  66 + ulong size = 0, sect_start, sect_size = 0, bank_size;
  67 + ushort sect_count = 0;
  68 + int i, j, nbanks;
  69 + vu_long *addr = (vu_long *)CFG_FLASH_BASE;
  70 + vu_long *bcsr = (vu_long *)CFG_BCSR;
65 71  
66   - /* Init: enable write,
67   - * or we cannot even write flash commands
68   - */
69   -#ifndef CONFIG_MPC8260ADS
70   - bcsr->bd_ctrl |= BD_CTRL_FLWE;
71   -#endif
  72 + switch (bcsr[2] & 0xF) {
  73 + case 0:
  74 + nbanks = 4;
  75 + break;
  76 + case 1:
  77 + nbanks = 2;
  78 + break;
  79 + case 2:
  80 + nbanks = 1;
  81 + break;
  82 + default: /* Unsupported configurations */
  83 + nbanks = CFG_MAX_FLASH_BANKS;
  84 + }
72 85  
73   - for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
74   - flash_info[i].flash_id = FLASH_UNKNOWN;
  86 + if (nbanks > CFG_MAX_FLASH_BANKS)
  87 + nbanks = CFG_MAX_FLASH_BANKS;
75 88  
76   - /* set the default sector offset */
  89 + for (i = 0; i < nbanks; i++) {
  90 + *addr = INTEL_READID; /* Read Intelligent Identifier */
  91 + if ((addr[0] == INTEL_COMPAT) || (addr[0] == INTEL_ALT)) {
  92 + switch (addr[1]) {
  93 + case SHARP_ID_28F016SCL:
  94 + case SHARP_ID_28F016SCZ:
  95 + flash_info[i].flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
  96 + sect_count = 32;
  97 + sect_size = 0x40000;
  98 + break;
  99 + default:
  100 + flash_info[i].flash_id = FLASH_UNKNOWN;
  101 + sect_count = CFG_MAX_FLASH_SECT;
  102 + sect_size =
  103 + CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT;
  104 + }
  105 + }
  106 + else
  107 + flash_info[i].flash_id = FLASH_UNKNOWN;
  108 + if (flash_info[i].flash_id == FLASH_UNKNOWN) {
  109 + printf("### Unknown flash ID %08lX %08lX at address %08lX ###\n",
  110 + addr[0], addr[1], (ulong)addr);
  111 + size = 0;
  112 + *addr = INTEL_RESET; /* Reset bank to Read Array mode */
  113 + break;
  114 + }
  115 + flash_info[i].sector_count = sect_count;
  116 + flash_info[i].size = bank_size = sect_size * sect_count;
  117 + size += bank_size;
  118 + sect_start = (ulong)addr;
  119 + for (j = 0; j < sect_count; j++) {
  120 + addr = (vu_long *)sect_start;
  121 + flash_info[i].start[j] = sect_start;
  122 + flash_info[i].protect[j] = (addr[2] == 0x01010101);
  123 + sect_start += sect_size;
  124 + }
  125 + *addr = INTEL_RESET; /* Reset bank to Read Array mode */
  126 + addr = (vu_long *)sect_start;
77 127 }
78 128  
79   - /* Static FLASH Bank configuration here - FIXME XXX */
80   -
81   - size = flash_get_size((vu_long *)FLASH_BASE, &flash_info[0]);
82   -
83   - if (flash_info[0].flash_id == FLASH_UNKNOWN) {
84   - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
85   - size, size<<20);
  129 + if (size == 0) { /* Unknown flash, fill with hard-coded values */
  130 + sect_start = CFG_FLASH_BASE;
  131 + for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
  132 + flash_info[i].flash_id = FLASH_UNKNOWN;
  133 + flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS;
  134 + flash_info[i].sector_count = sect_count;
  135 + for (j = 0; j < sect_count; j++) {
  136 + flash_info[i].start[j] = sect_start;
  137 + flash_info[i].protect[j] = 0;
  138 + sect_start += sect_size;
  139 + }
  140 + }
  141 + size = CFG_FLASH_SIZE;
86 142 }
87   -#ifndef CONFIG_MPC8260ADS
88   - /* Remap FLASH according to real size */
89   - memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
90   - memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
91   - (memctl->memc_br1 & ~(BR_BA_MSK));
92   -#endif
  143 + else
  144 + for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) {
  145 + flash_info[i].flash_id = FLASH_UNKNOWN;
  146 + flash_info[i].size = 0;
  147 + flash_info[i].sector_count = 0;
  148 + }
93 149  
94   - /* Re-do sizing to get full correct info */
95   - size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
96   -
97   - flash_info[0].size = size;
98   -
99 150 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
100 151 /* monitor protection ON by default */
101 152 flash_protect(FLAG_PROTECT_SET,
... ... @@ -161,102 +212,6 @@
161 212  
162 213 /*-----------------------------------------------------------------------
163 214 */
164   -
165   -
166   -/*-----------------------------------------------------------------------
167   - */
168   -
169   -/*
170   - * The following code cannot be run from FLASH!
171   - */
172   -
173   -static ulong flash_get_size (vu_long *addr, flash_info_t *info)
174   -{
175   - short i;
176   - ulong value;
177   - ulong base = (ulong)addr;
178   - ulong sector_offset;
179   -
180   - /* Write "Intelligent Identifier" command: read Manufacturer ID */
181   - *addr = 0x90909090;
182   -
183   - value = addr[0] & 0x00FF00FF;
184   - switch (value) {
185   - case MT_MANUFACT: /* SHARP, MT or => Intel */
186   - case INTEL_ALT_MANU:
187   - info->flash_id = FLASH_MAN_INTEL;
188   - break;
189   - default:
190   - printf("unknown manufacturer: %x\n", (unsigned int)value);
191   - info->flash_id = FLASH_UNKNOWN;
192   - info->sector_count = 0;
193   - info->size = 0;
194   - return (0); /* no or unknown flash */
195   - }
196   -
197   - value = addr[1]; /* device ID */
198   -
199   - switch (value) {
200   - case (INTEL_ID_28F016S):
201   - info->flash_id += FLASH_28F016SV;
202   - info->sector_count = 32;
203   - info->size = 0x00400000;
204   - sector_offset = 0x20000;
205   - break; /* => 2x2 MB */
206   -
207   - case (INTEL_ID_28F160S3):
208   - info->flash_id += FLASH_28F160S3;
209   - info->sector_count = 32;
210   - info->size = 0x00400000;
211   - sector_offset = 0x20000;
212   - break; /* => 2x2 MB */
213   -
214   - case (INTEL_ID_28F320S3):
215   - info->flash_id += FLASH_28F320S3;
216   - info->sector_count = 64;
217   - info->size = 0x00800000;
218   - sector_offset = 0x20000;
219   - break; /* => 2x4 MB */
220   -
221   - case SHARP_ID_28F016SCL:
222   - case SHARP_ID_28F016SCZ:
223   - info->flash_id = FLASH_MAN_SHARP | FLASH_LH28F016SCT;
224   - info->sector_count = 32;
225   - info->size = 0x00800000;
226   - sector_offset = 0x40000;
227   - break; /* => 4x2 MB */
228   -
229   -
230   - default:
231   - info->flash_id = FLASH_UNKNOWN;
232   - return (0); /* => no or unknown flash */
233   -
234   - }
235   -
236   - /* set up sector start address table */
237   - for (i = 0; i < info->sector_count; i++) {
238   - info->start[i] = base;
239   - base += sector_offset;
240   - /* don't know how to check sector protection */
241   - info->protect[i] = 0;
242   - }
243   -
244   - /*
245   - * Prevent writes to uninitialized FLASH.
246   - */
247   - if (info->flash_id != FLASH_UNKNOWN) {
248   - addr = (vu_long *)info->start[0];
249   -
250   - *addr = 0xFFFFFF; /* reset bank to read array mode */
251   - }
252   -
253   - return (info->size);
254   -}
255   -
256   -
257   -/*-----------------------------------------------------------------------
258   - */
259   -
260 215 int flash_erase (flash_info_t *info, int s_first, int s_last)
261 216 {
262 217 int flag, prot, sect;
... ... @@ -292,12 +247,6 @@
292 247 printf ("\n");
293 248 }
294 249  
295   - /* Make Sure Block Lock Bit is not set. */
296   - if(clear_block_lock_bit((vu_long *)(info->start[s_first]))){
297   - return 1;
298   - }
299   -
300   -
301 250 /* Start erase on unprotected sectors */
302 251 for (sect = s_first; sect<=s_last; sect++) {
303 252 if (info->protect[sect] == 0) { /* not protected */
304 253  
305 254  
306 255  
307 256  
308 257  
309 258  
... ... @@ -308,36 +257,26 @@
308 257 /* Disable interrupts which might cause a timeout here */
309 258 flag = disable_interrupts();
310 259  
311   - /* Reset Array */
312   - *addr = 0xffffffff;
313 260 /* Clear Status Register */
314   - *addr = 0x50505050;
  261 + *addr = INTEL_CLEAR;
315 262 /* Single Block Erase Command */
316   - *addr = 0x20202020;
  263 + *addr = INTEL_ERASE;
317 264 /* Confirm */
318   - *addr = 0xD0D0D0D0;
  265 + *addr = INTEL_CONFIRM;
319 266  
320 267 if((info->flash_id & FLASH_TYPEMASK) != FLASH_LH28F016SCT) {
321 268 /* Resume Command, as per errata update */
322   - *addr = 0xD0D0D0D0;
  269 + *addr = INTEL_CONFIRM;
323 270 }
324 271  
325 272 /* re-enable interrupts if necessary */
326 273 if (flag)
327 274 enable_interrupts();
328 275  
329   - /* wait at least 80us - let's wait 1 ms */
330   - udelay (1000);
331   - while ((*addr & 0x80808080) != 0x80808080) {
332   - if(*addr & 0x20202020){
333   - printf("Error in Block Erase - Lock Bit may be set!\n");
334   - printf("Status Register = 0x%X\n", (uint)*addr);
335   - *addr = 0xFFFFFFFF; /* reset bank */
336   - return 1;
337   - }
  276 + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
338 277 if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
339 278 printf ("Timeout\n");
340   - *addr = 0xFFFFFFFF; /* reset bank */
  279 + *addr = INTEL_RESET; /* reset bank */
341 280 return 1;
342 281 }
343 282 /* show that we're waiting */
344 283  
... ... @@ -347,8 +286,15 @@
347 286 }
348 287 }
349 288  
  289 + if (*addr != INTEL_OK) {
  290 + printf("Block erase failed at %08X, CSR=%08X\n",
  291 + (uint)addr, (uint)*addr);
  292 + *addr = INTEL_RESET; /* reset bank */
  293 + return 1;
  294 + }
  295 +
350 296 /* reset to read mode */
351   - *addr = 0xFFFFFFFF;
  297 + *addr = INTEL_RESET;
352 298 }
353 299 }
354 300  
... ... @@ -357,6 +303,58 @@
357 303 }
358 304  
359 305 /*-----------------------------------------------------------------------
  306 + * Write a word to Flash, returns:
  307 + * 0 - OK
  308 + * 1 - write timeout
  309 + * 2 - Flash not erased
  310 + */
  311 +static int write_word (flash_info_t *info, ulong dest, ulong data)
  312 +{
  313 + ulong start;
  314 + int rc = 0;
  315 + int flag;
  316 + vu_long *addr = (vu_long *)dest;
  317 +
  318 + /* Check if Flash is (sufficiently) erased */
  319 + if ((*addr & data) != data) {
  320 + return (2);
  321 + }
  322 +
  323 + *addr = INTEL_CLEAR; /* Clear status register */
  324 +
  325 + /* Disable interrupts which might cause a timeout here */
  326 + flag = disable_interrupts();
  327 +
  328 + /* Write Command */
  329 + *addr = INTEL_PROGRAM;
  330 +
  331 + /* Write Data */
  332 + *addr = data;
  333 +
  334 + /* re-enable interrupts if necessary */
  335 + if (flag)
  336 + enable_interrupts();
  337 +
  338 + /* data polling for D7 */
  339 + start = get_timer (0);
  340 + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
  341 + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
  342 + printf("Write timed out\n");
  343 + rc = 1;
  344 + break;
  345 + }
  346 + }
  347 + if (*addr != INTEL_OK) {
  348 + printf ("Write failed at %08X, CSR=%08X\n", (uint)addr, (uint)*addr);
  349 + rc = 1;
  350 + }
  351 +
  352 + *addr = INTEL_RESET; /* Reset to read array mode */
  353 +
  354 + return rc;
  355 +}
  356 +
  357 +/*-----------------------------------------------------------------------
360 358 * Copy memory to flash, returns:
361 359 * 0 - OK
362 360 * 1 - write timeout
... ... @@ -370,6 +368,8 @@
370 368  
371 369 wp = (addr & ~3); /* get lower word aligned address */
372 370  
  371 + *(vu_long *)wp = INTEL_RESET; /* Reset to read array mode */
  372 +
373 373 /*
374 374 * handle unaligned start bytes
375 375 */
376 376  
377 377  
378 378  
379 379  
380 380  
381 381  
382 382  
383 383  
384 384  
385 385  
386 386  
387 387  
388 388  
389 389  
390 390  
391 391  
392 392  
393 393  
... ... @@ -424,86 +424,126 @@
424 424 data = (data << 8) | (*(uchar *)cp);
425 425 }
426 426  
427   - return (write_word(info, wp, data));
  427 + rc = write_word(info, wp, data);
  428 +
  429 + return rc;
428 430 }
429 431  
430 432 /*-----------------------------------------------------------------------
431   - * Write a word to Flash, returns:
  433 + * Set/Clear sector's lock bit, returns:
432 434 * 0 - OK
433   - * 1 - write timeout
434   - * 2 - Flash not erased
  435 + * 1 - Error (timeout, voltage problems, etc.)
435 436 */
436   -static int write_word (flash_info_t *info, ulong dest, ulong data)
  437 +int flash_real_protect(flash_info_t *info, long sector, int prot)
437 438 {
438   - vu_long *addr = (vu_long *)dest;
439   - ulong start, csr;
440   - int flag;
  439 + ulong start;
  440 + int i;
  441 + int rc = 0;
  442 + vu_long *addr = (vu_long *)(info->start[sector]);
  443 + int flag = disable_interrupts();
441 444  
442   - /* Check if Flash is (sufficiently) erased */
443   - if ((*addr & data) != data) {
444   - return (2);
  445 + *addr = INTEL_CLEAR; /* Clear status register */
  446 + if (prot) { /* Set sector lock bit */
  447 + *addr = INTEL_LOCKBIT; /* Sector lock bit */
  448 + *addr = INTEL_PROTECT; /* set */
445 449 }
446   - /* Disable interrupts which might cause a timeout here */
447   - flag = disable_interrupts();
  450 + else { /* Clear sector lock bit */
  451 + *addr = INTEL_LOCKBIT; /* All sectors lock bits */
  452 + *addr = INTEL_CONFIRM; /* clear */
  453 + }
448 454  
449   - /* Write Command */
450   - *addr = 0x10101010;
451   -
452   - /* Write Data */
453   - *addr = data;
454   -
455   - /* re-enable interrupts if necessary */
456   - if (flag)
457   - enable_interrupts();
458   -
459   - /* data polling for D7 */
460   - start = get_timer (0);
461   - flag = 0;
462   - while (((csr = *addr) & 0x80808080) != 0x80808080) {
463   - if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
464   - flag = 1;
  455 + start = get_timer(0);
  456 + while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
  457 + if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
  458 + printf("Flash lock bit operation timed out\n");
  459 + rc = 1;
465 460 break;
466 461 }
467 462 }
468   - if (csr & 0x40404040) {
469   - printf ("CSR indicates write error (%08lx) at %08lx\n", csr, (ulong)addr);
470   - flag = 1;
  463 +
  464 + if (*addr != INTEL_OK) {
  465 + printf("Flash lock bit operation failed at %08X, CSR=%08X\n",
  466 + (uint)addr, (uint)*addr);
  467 + rc = 1;
471 468 }
472 469  
473   - /* Clear Status Registers Command */
474   - *addr = 0x50505050;
475   - /* Reset to read array mode */
476   - *addr = 0xFFFFFFFF;
  470 + if (!rc)
  471 + info->protect[sector] = prot;
477 472  
478   - return (flag);
  473 + /*
  474 + * Clear lock bit command clears all sectors lock bits, so
  475 + * we have to restore lock bits of protected sectors.
  476 + */
  477 + if (!prot)
  478 + for (i = 0; i < info->sector_count; i++)
  479 + if (info->protect[i]) {
  480 + addr = (vu_long *)(info->start[i]);
  481 + *addr = INTEL_LOCKBIT; /* Sector lock bit */
  482 + *addr = INTEL_PROTECT; /* set */
  483 + udelay(CFG_FLASH_LOCK_TOUT * 1000);
  484 + }
  485 +
  486 + if (flag)
  487 + enable_interrupts();
  488 +
  489 + *addr = INTEL_RESET; /* Reset to read array mode */
  490 +
  491 + return rc;
479 492 }
480 493  
481 494 /*-----------------------------------------------------------------------
482   - * Clear Block Lock Bit, returns:
483   - * 0 - OK
484   - * 1 - Timeout
  495 + * Support for flash file system (JFFS2)
  496 + *
  497 + * We use custom partition info function because we have to fit the
  498 + * file system image between first sector (containing hard reset
  499 + * configuration word) and the sector containing U-Boot image. Standard
  500 + * partition info function does not allow for last sector specification
  501 + * and assumes that the file system occupies flash bank up to and
  502 + * including bank's last sector.
485 503 */
  504 +#if (CONFIG_COMMANDS & CFG_CMD_JFFS2) && defined(CFG_JFFS_CUSTOM_PART)
486 505  
487   -static int clear_block_lock_bit(vu_long * addr)
488   -{
489   - ulong start, now;
  506 +#ifndef CFG_JFFS2_FIRST_SECTOR
  507 +#define CFG_JFFS2_FIRST_SECTOR 0
  508 +#endif
  509 +#ifndef CFG_JFFS2_FIRST_BANK
  510 +#define CFG_JFFS2_FIRST_BANK 0
  511 +#endif
  512 +#ifndef CFG_JFFS2_NUM_BANKS
  513 +#define CFG_JFFS2_NUM_BANKS 1
  514 +#endif
  515 +#define CFG_JFFS2_LAST_BANK (CFG_JFFS2_FIRST_BANK + CFG_JFFS2_NUM_BANKS - 1)
490 516  
491   - /* Reset Array */
492   - *addr = 0xffffffff;
493   - /* Clear Status Register */
494   - *addr = 0x50505050;
  517 +#include <jffs2/jffs2.h>
495 518  
496   - *addr = 0x60606060;
497   - *addr = 0xd0d0d0d0;
  519 +static struct part_info partition;
498 520  
499   - start = get_timer (0);
500   - while(*addr != 0x80808080){
501   - if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
502   - printf ("Timeout on clearing Block Lock Bit\n");
503   - *addr = 0xFFFFFFFF; /* reset bank */
504   - return 1;
  521 +struct part_info *jffs2_part_info(int part_num)
  522 +{
  523 + int i;
  524 +
  525 + if (part_num == 0) {
  526 + if (partition.usr_priv == 0) {
  527 + partition.offset =
  528 + (unsigned char *) flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR];
  529 + for (i = CFG_JFFS2_FIRST_BANK; i <= CFG_JFFS2_LAST_BANK; i++)
  530 + partition.size += flash_info[i].size;
  531 + partition.size -=
  532 + flash_info[CFG_JFFS2_FIRST_BANK].start[CFG_JFFS2_FIRST_SECTOR] -
  533 + flash_info[CFG_JFFS2_FIRST_BANK].start[0];
  534 +#ifdef CFG_JFFS2_LAST_SECTOR
  535 + i = flash_info[CFG_JFFS2_LAST_BANK].sector_count - 1;
  536 + partition.size -=
  537 + flash_info[CFG_JFFS2_LAST_BANK].start[i] -
  538 + flash_info[CFG_JFFS2_LAST_BANK].start[CFG_JFFS2_LAST_SECTOR];
  539 +#endif
  540 +
  541 + partition.usr_priv = (void *)1;
505 542 }
  543 + return &partition;
506 544 }
507 545 return 0;
508 546 }
  547 +
  548 +#endif /* JFFS2 */
board/sacsng/sacsng.c
Diff comments   View file @ 8564acf
... ... @@ -816,4 +816,16 @@
816 816 #endif /* CFG_CMD_SPI */
817 817  
818 818 #endif /* CONFIG_MISC_INIT_R */
  819 +
  820 +#ifdef CONFIG_POST
  821 +/*
  822 + * Returns 1 if keys pressed to start the power-on long-running tests
  823 + * Called from board_init_f().
  824 + */
  825 +int post_hotkeys_pressed(void)
  826 +{
  827 + return 0; /* No hotkeys supported */
  828 +}
  829 +
  830 +#endif
... ... @@ -1024,6 +1024,7 @@
1024 1024 case IH_CPU_SH: arch = "SuperH"; break;
1025 1025 case IH_CPU_SPARC: arch = "SPARC"; break;
1026 1026 case IH_CPU_SPARC64: arch = "SPARC 64 Bit"; break;
  1027 + case IH_CPU_M68K: arch = "M68K"; break;
1027 1028 default: arch = "Unknown Architecture"; break;
1028 1029 }
1029 1030  
cpu/mpc8260/commproc.c
Diff comments   View file @ 8564acf
... ... @@ -111,9 +111,9 @@
111 111 * to port numbers). Documentation uses 1-based numbering.
112 112 */
113 113 #define BRG_INT_CLK gd->brg_clk
114   -#define BRG_UART_CLK ((BRG_INT_CLK + 15) / 16)
  114 +#define BRG_UART_CLK (BRG_INT_CLK / 16)
115 115  
116   -/* This function is used by UARTS, or anything else that uses a 16x
  116 +/* This function is used by UARTs, or anything else that uses a 16x
117 117 * oversampled clock.
118 118 */
119 119 void
120 120  
... ... @@ -123,9 +123,10 @@
123 123  
124 124 volatile immap_t *immr = (immap_t *)CFG_IMMR;
125 125 volatile uint *bp;
  126 + uint cd = BRG_UART_CLK / rate;
126 127  
127   - /* This is good enough to get SMCs running.....
128   - */
  128 + if ((BRG_UART_CLK % rate) < (rate / 2))
  129 + cd--;
129 130 if (brg < 4) {
130 131 bp = (uint *)&immr->im_brgc1;
131 132 }
... ... @@ -134,7 +135,7 @@
134 135 brg -= 4;
135 136 }
136 137 bp += brg;
137   - *bp = (((((BRG_UART_CLK+rate-1)/rate)-1)&0xfff)<<1)|CPM_BRG_EN;
  138 + *bp = (cd << 1) | CPM_BRG_EN;
138 139 }
139 140  
140 141 /* This function is used to set high speed synchronous baud rate
... ... @@ -22,7 +22,7 @@
22 22 */
23 23  
24 24 /*
25   - * CPU specific code for the MPC8255 / MPC8260 CPUs
  25 + * CPU specific code for the MPC825x / MPC826x / MPC827x / MPC828x
26 26 *
27 27 * written or collected and sometimes rewritten by
28 28 * Magnus Damm <damm@bitsmart.com>
... ... @@ -35,6 +35,9 @@
35 35 *
36 36 * added 8260 masks by
37 37 * Marius Groeger <mag@sysgo.de>
  38 + *
  39 + * added HiP7 (8270/8275/8280) processors support by
  40 + * Yuli Barcohen <yuli@arabellasw.com>
38 41 */
39 42  
40 43 #include <common.h>
41 44  
42 45  
... ... @@ -56,15 +59,27 @@
56 59  
57 60 puts ("CPU: ");
58 61  
59   - if (((pvr >> 16) & 0xff) != 0x81)
  62 + switch (pvr) {
  63 + case PVR_8260:
  64 + case PVR_8260_HIP3:
  65 + k = 3;
  66 + break;
  67 + case PVR_8260_HIP4:
  68 + k = 4;
  69 + break;
  70 + case PVR_8260_HIP7:
  71 + k = 7;
  72 + break;
  73 + default:
60 74 return -1; /* whoops! not an MPC8260 */
  75 + }
61 76 rev = pvr & 0xff;
62 77  
63 78 immr = immap->im_memctl.memc_immr;
64 79 if ((immr & IMMR_ISB_MSK) != CFG_IMMR)
65 80 return -1; /* whoops! someone moved the IMMR */
66 81  
67   - printf (CPU_ID_STR " (Rev %02x, Mask ", rev);
  82 + printf (CPU_ID_STR " (HiP%d Rev %02x, Mask ", k, rev);
68 83  
69 84 /*
70 85 * the bottom 16 bits of the immr are the Part Number and Mask Number
... ... @@ -103,6 +118,12 @@
103 118 break;
104 119 case 0x0062:
105 120 printf ("B.1 4K25A");
  121 + break;
  122 + case 0x0A00:
  123 + printf ("0.0 0K49M");
  124 + break;
  125 + case 0x0A01:
  126 + printf ("0.1 1K49M");
106 127 break;
107 128 default:
108 129 printf ("unknown [immr=0x%04x,k=0x%04x]", m, k);
... ... @@ -120,15 +120,19 @@
120 120  
121 121 scmr = immap->im_clkrst.car_scmr;
122 122 corecnf = (scmr & SCMR_CORECNF_MSK) >> SCMR_CORECNF_SHIFT;
  123 + cp = &corecnf_tab[corecnf];
  124 +
123 125 busdf = (scmr & SCMR_BUSDF_MSK) >> SCMR_BUSDF_SHIFT;
124 126 cpmdf = (scmr & SCMR_CPMDF_MSK) >> SCMR_CPMDF_SHIFT;
125   - plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
126   - pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
127 127  
128   - cp = &corecnf_tab[corecnf];
129   -
130   - gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
131   -
  128 + if (get_pvr () == PVR_8260_HIP7) { /* HiP7 */
  129 + pllmf = (scmr & SCMR_PLLMF_MSKH7) >> SCMR_PLLMF_SHIFT;
  130 + gd->vco_out = clkin * (pllmf + 1);
  131 + } else { /* HiP3, HiP4 */
  132 + pllmf = (scmr & SCMR_PLLMF_MSK) >> SCMR_PLLMF_SHIFT;
  133 + plldf = (scmr & SCMR_PLLDF) ? 1 : 0;
  134 + gd->vco_out = (clkin * 2 * (pllmf + 1)) / (plldf + 1);
  135 + }
132 136 #if 0
133 137 if (gd->vco_out / (busdf + 1) != clkin) {
134 138 /* aaarrrggghhh!!! */
... ... @@ -25,6 +25,8 @@
25 25 /* ** HEADER FILES */
26 26 /************************************************************************/
27 27  
  28 +/* #define DEBUG */
  29 +
28 30 #include <config.h>
29 31 #include <common.h>
30 32 #include <watchdog.h>
... ... @@ -1056,6 +1058,23 @@
1056 1058 udelay(200000); /* wait 200ms */
1057 1059 /* Now turn on LCD_ON */
1058 1060 immr->im_cpm.cp_pbdat |= 0x00001000;
  1061 +#endif
  1062 +#ifdef CONFIG_RRVISION
  1063 + debug ("PC4->Output(1): enable LVDS\n");
  1064 + debug ("PC5->Output(0): disable PAL clock\n");
  1065 + immr->im_ioport.iop_pddir |= 0x1000;
  1066 + immr->im_ioport.iop_pcpar &= ~(0x0C00);
  1067 + immr->im_ioport.iop_pcdir |= 0x0C00 ;
  1068 + immr->im_ioport.iop_pcdat |= 0x0800 ;
  1069 + immr->im_ioport.iop_pcdat &= ~(0x0400);
  1070 + debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
  1071 + immr->im_ioport.iop_pdpar,
  1072 + immr->im_ioport.iop_pddir,
  1073 + immr->im_ioport.iop_pddat);
  1074 + debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
  1075 + immr->im_ioport.iop_pcpar,
  1076 + immr->im_ioport.iop_pcdir,
  1077 + immr->im_ioport.iop_pcdat);
1059 1078 #endif
1060 1079 }
1061 1080  
... ... @@ -23,7 +23,7 @@
23 23 * MA 02111-1307 USA
24 24 */
25 25  
26   -/* #define DEBUG */
  26 +/* #define DEBUG */
27 27  
28 28 /************************************************************************/
29 29 /* ** HEADER FILES */
... ... @@ -86,6 +86,14 @@
86 86 #define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7177_ADDR
87 87 #endif
88 88  
  89 +#ifdef CONFIG_VIDEO_ENCODER_AD7179
  90 +
  91 +#include <video_ad7179.h> /* Sets encoder data, mode, and visible and active area */
  92 +
  93 +#define VIDEO_I2C 1
  94 +#define VIDEO_I2C_ADDR CONFIG_VIDEO_ENCODER_AD7179_ADDR
  95 +#endif
  96 +
89 97 /************************************************************************/
90 98 /* ** VIDEO MODE CONSTANTS */
91 99 /************************************************************************/
... ... @@ -155,7 +163,7 @@
155 163 /* ** CONSOLE CONSTANTS */
156 164 /************************************************************************/
157 165  
158   -#ifdef CONFIG_VIDEO_LOGO
  166 +#ifdef CONFIG_VIDEO_LOGO
159 167 #define CONSOLE_ROWS ((VIDEO_ROWS - VIDEO_LOGO_HEIGHT) / VIDEO_FONT_HEIGHT)
160 168 #define VIDEO_LOGO_SKIP (VIDEO_COLS - VIDEO_LOGO_WIDTH)
161 169 #else
162 170  
163 171  
... ... @@ -163,11 +171,11 @@
163 171 #endif
164 172  
165 173 #define CONSOLE_COLS (VIDEO_COLS / VIDEO_FONT_WIDTH)
166   -#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN)
  174 +#define CONSOLE_ROW_SIZE (VIDEO_FONT_HEIGHT * VIDEO_LINE_LEN)
167 175 #define CONSOLE_ROW_FIRST (video_console_address)
168   -#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE)
  176 +#define CONSOLE_ROW_SECOND (video_console_address + CONSOLE_ROW_SIZE)
169 177 #define CONSOLE_ROW_LAST (video_console_address + CONSOLE_SIZE - CONSOLE_ROW_SIZE)
170   -#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS)
  178 +#define CONSOLE_SIZE (CONSOLE_ROW_SIZE * CONSOLE_ROWS)
171 179 #define CONSOLE_SCROLL_SIZE (CONSOLE_SIZE - CONSOLE_ROW_SIZE)
172 180  
173 181 /*
... ... @@ -287,8 +295,8 @@
287 295 /* Calculate YUV values (0-255) from RGB beetween 0-100 */
288 296  
289 297 YUYV.Y1 = YUYV.Y2 = 209 * (pR + pG + pB) / 300 + 16;
290   - YUYV.U = pR - (pG * 3 / 4) - (pB / 4) + 128;
291   - YUYV.V = pB - (pR / 4) - (pG * 3 / 4) + 128;
  298 + YUYV.U = pR - (pG * 3 / 4) - (pB / 4) + 128;
  299 + YUYV.V = pB - (pR / 4) - (pG * 3 / 4) + 128;
292 300 return *ret;
293 301 #endif
294 302 #ifdef VIDEO_MODE_RGB
... ... @@ -473,6 +481,7 @@
473 481 /* ** VIDEO CONTROLLER LOW-LEVEL FUNCTIONS */
474 482 /************************************************************************/
475 483  
  484 +#if !defined(CONFIG_RRVISION)
476 485 static void video_mode_dupefield (VRAM * source, VRAM * dest, int entries)
477 486 {
478 487 int i;
... ... @@ -485,6 +494,7 @@
485 494 dest[0].lcyc++; /* Add a cycle to the first entry */
486 495 dest[entries - 1].lst = 1; /* Set end of ram entries */
487 496 }
  497 +#endif
488 498  
489 499 static void inline video_mode_addentry (VRAM * vr,
490 500 int Hx, int Vx, int Fx, int Bx,
... ... @@ -501,7 +511,7 @@
501 511 vr->lst = LST;
502 512 }
503 513  
504   -#define ADDENTRY(a,b,c,d,e,f,g,h,i) video_mode_addentry(&vr[entry++],a,b,c,d,e,f,g,h,i)
  514 +#define ADDENTRY(a,b,c,d,e,f,g,h,i) video_mode_addentry(&vr[entry++],a,b,c,d,e,f,g,h,i)
505 515  
506 516 static int video_mode_generate (void)
507 517 {
508 518  
... ... @@ -539,9 +549,12 @@
539 549 Y1 = video_panning_value_y & 0xfffe;
540 550 Y2 = DY - Y1;
541 551  
  552 + debug("X1=%d, X2=%d, Y1=%d, Y2=%d, DX=%d, DY=%d VIDEO_COLS=%d \n",
  553 + X1, X2, Y1, Y2, DX, DY, VIDEO_COLS);
  554 +
542 555 #ifdef VIDEO_MODE_NTSC
543 556 /*
544   - * Hx Vx Fx Bx VDS INT LCYC LP LST
  557 + * Hx Vx Fx Bx VDS INT LCYC LP LST
545 558 *
546 559 * Retrace blanking
547 560 */
548 561  
... ... @@ -641,7 +654,74 @@
641 654 #endif
642 655  
643 656 #ifdef VIDEO_MODE_PAL
  657 +
  658 +#if defined(CONFIG_RRVISION)
  659 +
  660 +#define HPW 160 /* horizontal pulse width (was 139) */
  661 +#define VPW 2 /* vertical pulse width */
  662 +#define HBP 104 /* horizontal back porch (was 112) */
  663 +#define VBP 19 /* vertical back porch (was 19) */
  664 +#define VID_R 240 /* number of rows */
  665 +
  666 + debug ("[VIDEO CTRL] Starting to add controller entries...");
644 667 /*
  668 + * Even field
  669 + */
  670 + ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0);
  671 + ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0);
  672 + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0);
  673 +
  674 + ADDENTRY (0, 0, 0, 3, 1, 0, VPW, 1, 0);
  675 + ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0);
  676 + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
  677 +
  678 + ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0);
  679 + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
  680 + ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
  681 +/*
  682 + * Active area
  683 + */
  684 + ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0);
  685 + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
  686 + ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0);
  687 + ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0);
  688 + ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1);
  689 +
  690 + ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0);
  691 + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
  692 + ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0);
  693 +/*
  694 + * Odd field
  695 + */
  696 + ADDENTRY (0, 3, 0, 3, 1, 0, 2, 0, 0);
  697 + ADDENTRY (0, 0, 0, 3, 1, 0, HPW, 0, 0);
  698 + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 0, 0);
  699 +
  700 + ADDENTRY (0, 0, 0, 3, 1, 0, VPW+1, 1, 0);
  701 + ADDENTRY (0, 0, 0, 3, 1, 0, HPW-1, 0, 0);
  702 + ADDENTRY (3, 0, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
  703 +
  704 + ADDENTRY (0, 3, 0, 3, 1, 0, VBP, 1, 0);
  705 + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
  706 + ADDENTRY (3, 3, 0, 3, 1, 0, HBP + (VIDEO_COLS * 2) + 72, 1, 0);
  707 +/*
  708 + * Active area
  709 + */
  710 + ADDENTRY (0, 3, 0, 3, 1, 0, VID_R , 1, 0);
  711 + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
  712 + ADDENTRY (3, 3, 0, 3, 1, 0, HBP, 0, 0);
  713 + ADDENTRY (3, 3, 0, 3, 0, 0, VIDEO_COLS*2, 0, 0);
  714 + ADDENTRY (3, 3, 0, 3, 1, 0, 72, 1, 1);
  715 +
  716 + ADDENTRY (0, 3, 0, 3, 1, 0, 51, 1, 0);
  717 + ADDENTRY (0, 3, 0, 3, 1, 0, HPW-1, 0, 0);
  718 + ADDENTRY (3, 3, 0, 3, 1, 0, HBP +(VIDEO_COLS * 2) + 72 , 1, 0);
  719 +
  720 + debug ("done\n");
  721 +
  722 +#else /* !CONFIG_RRVISION */
  723 +
  724 +/*
645 725 * Hx Vx Fx Bx VDS INT LCYC LP LST
646 726 *
647 727 * vertical; blanking
648 728  
... ... @@ -692,8 +772,10 @@
692 772 * one more cycle loop and a last identifier)
693 773 */
694 774 video_mode_dupefield (vr, &vr[entry], entry);
695   -#endif
  775 +#endif /* CONFIG_RRVISION */
696 776  
  777 +#endif /* VIDEO_MODE_PAL */
  778 +
697 779 /* See what FIFO are we using */
698 780 fifo = GETBIT (immap->im_vid.vid_vsr, VIDEO_VSR_CAS);
699 781  
700 782  
... ... @@ -829,26 +911,19 @@
829 911 debug ("[VIDEO CTRL] Turning on video port led...\n");
830 912 SETBIT (*(int *) BCSR4, VIDEO_BCSR4_VIDLED_BIT, 0);
831 913 #endif
832   -
833 914 #ifdef CONFIG_RRVISION
834   - /* enable clock: set PD3 to VCLK, PC5 to HIGH */
835   - {
836   - volatile immap_t *immr = (immap_t *) CFG_IMMR;
837   -
838   - debug ("PDPAR=%04X PDDIR=%04X PDDAT=%04X\n",
839   - immr->im_ioport.iop_pdpar,
840   - immr->im_ioport.iop_pddir,
841   - immr->im_ioport.iop_pddat);
842   -
843   - debug ("[RRvision] PC5 -> Output (1): ");
844   - immr->im_ioport.iop_pcpar &= ~(0x0400);
845   - immr->im_ioport.iop_pcdir |= 0x0400 ;
846   - immr->im_ioport.iop_pcdat |= 0x0400 ;
847   - debug ("PCPAR=%04X PCDIR=%04X PCDAT=%04X\n",
848   - immr->im_ioport.iop_pcpar,
849   - immr->im_ioport.iop_pcdir,
850   - immr->im_ioport.iop_pcdat);
851   - }
  915 + debug ("PC5->Output(1): enable PAL clock");
  916 + immap->im_ioport.iop_pcpar &= ~(0x0400);
  917 + immap->im_ioport.iop_pcdir |= 0x0400 ;
  918 + immap->im_ioport.iop_pcdat |= 0x0400 ;
  919 + debug ("PDPAR=0x%04X PDDIR=0x%04X PDDAT=0x%04X\n",
  920 + immap->im_ioport.iop_pdpar,
  921 + immap->im_ioport.iop_pddir,
  922 + immap->im_ioport.iop_pddat);
  923 + debug ("PCPAR=0x%04X PCDIR=0x%04X PCDAT=0x%04X\n",
  924 + immap->im_ioport.iop_pcpar,
  925 + immap->im_ioport.iop_pcdir,
  926 + immap->im_ioport.iop_pcdat);
852 927 #endif /* CONFIG_RRVISION */
853 928  
854 929 /* Blanking the screen. */
... ... @@ -212,7 +212,7 @@
212 212 argument will be a pointer to the board info structure, while
213 213 the second will be a combination of bit flags specifying the
214 214 mode the test is running in (POST_POWERON, POST_NORMAL,
215   - POST_POWERFAIL, POST_MANUAL) and whether the last execution of
  215 + POST_SLOWTEST, POST_MANUAL) and whether the last execution of
216 216 the test caused system rebooting (POST_REBOOT). The routine will
217 217 return 0 on successful execution of the test, and 1 if the test
218 218 failed.
... ... @@ -220,7 +220,7 @@
220 220 The lists of the POST tests that should be run at power-on/normal/
221 221 power-fail booting will be kept in the environment. Namely, the
222 222 following environment variables will be used: post_poweron,
223   -powet_normal, post_shutdown.
  223 +powet_normal, post_slowtest.
224 224  
225 225 2.1.2. Test results
226 226  
... ... @@ -253,7 +253,7 @@
253 253 "On-board peripherals test", "board", \
254 254 " This test performs full check-up of the " \
255 255 "on-board hardware.", \
256   - POST_RAM | POST_POWERFAIL, \
  256 + POST_RAM | POST_SLOWTEST, \
257 257 &board_post_test \
258 258 }
259 259  
... ... @@ -141,7 +141,7 @@
141 141 Using the CONFIG_AUTOBOOT_DELAY_STR2 / bootdelaykey2 and/or
142 142 CONFIG_AUTOBOOT_STOP_STR2 / bootstopkey #defines and/or
143 143 environment variables you can specify a second, alternate
144   - string (which allows you to haw two "password" strings).
  144 + string (which allows you to have two "password" strings).
145 145  
146 146 CONFIG_ZERO_BOOTDELAY_CHECK
147 147  
... ... @@ -306,8 +306,8 @@
306 306 break;
307 307 }
308 308  
309   - pci_read_config_dword(devno, PCI_BASE_ADDRESS_1, &iobase);
310   - iobase &= ~0xF; /* Masked out the low bits that are addresses. */
  309 + pci_read_config_dword(devno, PCI_BASE_ADDRESS_0, &iobase);
  310 + iobase &= ~0x3; /* bit 1: unused and bit 0: I/O Space Indicator */
311 311  
312 312 pci_write_config_dword(devno, PCI_COMMAND,
313 313 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
... ... @@ -85,7 +85,7 @@
85 85 * Calculate sensor address and register.
86 86 *
87 87 */
88   - sensor = DTT_I2C_DEV_CODE + (sensor & sensor);
  88 + sensor = DTT_I2C_DEV_CODE + (sensor & 0x07);
89 89  
90 90 /*
91 91 * Handle various data sizes.
include/asm-ppc/global_data.h
Diff comments   View file @ 8564acf
... ... @@ -73,6 +73,7 @@
73 73 #ifdef CONFIG_POST
74 74 unsigned long post_log_word; /* Record POST activities */
75 75 unsigned long post_init_f_time; /* When post_init_f started */
  76 + unsigned long post_hotkeys_latch; /* If the post hotkeys pressed */
76 77 #endif
77 78 #ifdef CONFIG_BOARD_TYPES
78 79 unsigned long board_type;
include/asm-ppc/processor.h
Diff comments   View file @ 8564acf
... ... @@ -524,8 +524,15 @@
524 524 #define PVR_860 PVR_821
525 525 #define PVR_7400 0x000C0000
526 526 #define PVR_8240 0x00810100
527   -#define PVR_8260 PVR_8240
528 527  
  528 +/*
  529 + * PowerQUICC II family processors report different PVR values depending
  530 + * on silicon process (HiP3, HiP4, HiP7, etc.)
  531 + */
  532 +#define PVR_8260 PVR_8240
  533 +#define PVR_8260_HIP3 0x00810101
  534 +#define PVR_8260_HIP4 0x80811014
  535 +#define PVR_8260_HIP7 0x80822011
529 536  
530 537 /* I am just adding a single entry for 8260 boards. I think we may be
531 538 * able to combine mbx, fads, rpxlite, bseip, and classic into a single
include/configs/A3000.h
Diff comments   View file @ 8564acf
... ... @@ -114,6 +114,8 @@
114 114 #define PCI_ENET1_MEMADDR 0x81000000
115 115 #define PCI_ENET2_IOADDR 0x82000000
116 116 #define PCI_ENET2_MEMADDR 0x82000000
  117 +#define PCI_ENET3_IOADDR 0x83000000
  118 +#define PCI_ENET3_MEMADDR 0x83000000
117 119  
118 120  
119 121 /*-----------------------------------------------------------------------
include/configs/MPC8260ADS.h
Diff comments   View file @ 8564acf
... ... @@ -206,6 +206,14 @@
206 206 #define CFG_FLASH_SIZE 8
207 207 #define CFG_FLASH_ERASE_TOUT 8000 /* Timeout for Flash Erase (in ms) */
208 208 #define CFG_FLASH_WRITE_TOUT 5 /* Timeout for Flash Write (in ms) */
  209 +#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
  210 +#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
  211 +#define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
  212 +
  213 +#define CFG_JFFS2_FIRST_SECTOR 1
  214 +#define CFG_JFFS2_LAST_SECTOR 27
  215 +#define CFG_JFFS2_SORT_FRAGMENTS
  216 +#define CFG_JFFS_CUSTOM_PART
209 217  
210 218 /* this is stuff came out of the Motorola docs */
211 219 #define CFG_DEFAULT_IMMR 0x0F010000
include/configs/RRvision.h
Diff comments   View file @ 8564acf
... ... @@ -100,13 +100,13 @@
100 100 #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
101 101  
102 102  
103   -#if 1
  103 +#ifndef CONFIG_LCD
104 104 #define CONFIG_VIDEO 1 /* To enable the video initialization */
105 105  
106 106 /* Video related */
107 107 #define CONFIG_VIDEO_LOGO 1 /* Show the logo */
108   -#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
109   -#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x2A /* ALSB to ground */
  108 +#define CONFIG_VIDEO_ENCODER_AD7179 1 /* Enable this encoder */
  109 +#define CONFIG_VIDEO_ENCODER_AD7179_ADDR 0x2A /* ALSB to ground */
110 110 #endif
111 111  
112 112 /* enable I2C and select the hardware/software driver */
... ... @@ -344,6 +344,7 @@
344 344 *-----------------------------------------------------------------------
345 345 *
346 346 */
  347 +/*#define CFG_DER 0x2002000F*/
347 348 #define CFG_DER 0
348 349  
349 350 /*
include/configs/lwmon.h
Diff comments   View file @ 8564acf
... ... @@ -579,7 +579,7 @@
579 579 #define CONFIG_MODEM_SUPPORT 1 /* enable modem initialization stuff */
580 580 #undef CONFIG_MODEM_SUPPORT_DEBUG
581 581  
582   -#define CONFIG_MODEM_KEY_MAGIC "3C+3F" /* hold down these keys to enable modem */
583   -
  582 +#define CONFIG_MODEM_KEY_MAGIC "3C+3F" /* press F3 + F6 keys to enable modem */
  583 +#define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
584 584 #endif /* __CONFIG_H */
... ... @@ -63,6 +63,7 @@
63 63 #define IH_CPU_SH 9 /* SuperH */
64 64 #define IH_CPU_SPARC 10 /* Sparc */
65 65 #define IH_CPU_SPARC64 11 /* Sparc 64 Bit */
  66 +#define IH_CPU_M68K 12 /* M68K */
66 67  
67 68 /*
68 69 * Image Types
... ... @@ -300,14 +300,15 @@
300 300 /*-----------------------------------------------------------------------
301 301 * SCMR - System Clock Mode Register 9-9
302 302 */
303   -#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */
  303 +#define SCMR_CORECNF_MSK 0x1f000000 /* Core Configuration Mask */
304 304 #define SCMR_CORECNF_SHIFT 24
305   -#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */
306   -#define SCMR_BUSDF_SHIFT 20
307   -#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */
308   -#define SCMR_CPMDF_SHIFT 16
309   -#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */
310   -#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/
  305 +#define SCMR_BUSDF_MSK 0x00f00000 /* 60x Bus Division Factor Mask */
  306 +#define SCMR_BUSDF_SHIFT 20
  307 +#define SCMR_CPMDF_MSK 0x000f0000 /* CPM Division Factor Mask */
  308 +#define SCMR_CPMDF_SHIFT 16
  309 +#define SCMR_PLLDF 0x00001000 /* PLL Pre-divider Value */
  310 +#define SCMR_PLLMF_MSK 0x00000fff /* PLL Multiplication Factor Mask*/
  311 +#define SCMR_PLLMF_MSKH7 0x0000000f /* for HiP7 processors */
311 312 #define SCMR_PLLMF_SHIFT 0
312 313  
313 314  
... ... @@ -30,8 +30,8 @@
30 30 #ifdef CONFIG_POST
31 31  
32 32 #define POST_POWERON 0x01 /* test runs on power-on booting */
33   -#define POST_POWERNORMAL 0x02 /* test runs on normal booting */
34   -#define POST_POWERFAIL 0x04 /* test runs on power-fail booting */
  33 +#define POST_NORMAL 0x02 /* test runs on normal booting */
  34 +#define POST_SLOWTEST 0x04 /* test is slow, enabled by key press */
35 35 #define POST_POWERTEST 0x08 /* test runs after watchdog reset */
36 36  
37 37 #define POST_ROM 0x0100 /* test runs in ROM */
... ... @@ -41,9 +41,9 @@
41 41 #define POST_PREREL 0x1000 /* test runs before relocation */
42 42  
43 43 #define POST_MEM (POST_RAM | POST_ROM)
44   -#define POST_ALWAYS (POST_POWERNORMAL | \
45   - POST_POWERFAIL | \
46   - POST_MANUAL | \
  44 +#define POST_ALWAYS (POST_NORMAL | \
  45 + POST_SLOWTEST | \
  46 + POST_MANUAL | \
47 47 POST_POWERON )
48 48  
49 49 #ifndef __ASSEMBLY__
... ... @@ -71,6 +71,7 @@
71 71  
72 72 extern struct post_test post_list[];
73 73 extern unsigned int post_list_size;
  74 +extern int post_hotkeys_pressed(gd_t *);
74 75  
75 76 #endif /* __ASSEMBLY__ */
76 77  
... ... @@ -24,7 +24,7 @@
24 24 #ifndef __VERSION_H__
25 25 #define __VERSION_H__
26 26  
27   -#define U_BOOT_VERSION "U-Boot 0.4.2"
  27 +#define U_BOOT_VERSION "U-Boot 0.4.3"
28 28  
29 29 #endif /* __VERSION_H__ */
include/video_ad7176.h
Diff comments   View file @ 8564acf
... ... @@ -12,7 +12,7 @@
12 12 *
13 13 * This program is distributed in the hope that it will be useful,
14 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 16 * GNU General Public License for more details.
17 17 *
18 18 * You should have received a copy of the GNU General Public License
19 19  
20 20  
21 21  
... ... @@ -26,21 +26,21 @@
26 26  
27 27 #define VIDEO_ENCODER_NAME "Analog Devices AD7176"
28 28  
29   -#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */
  29 +#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */
30 30 #define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
31 31  
32   -#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
33   -#undef VIDEO_MODE_RGB
  32 +#define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
  33 +#undef VIDEO_MODE_RGB
34 34 #define VIDEO_MODE_BPP 16
35 35  
36   -#ifdef VIDEO_MODE_PAL
  36 +#ifdef VIDEO_MODE_PAL
37 37 #define VIDEO_ACTIVE_COLS 720
38 38 #define VIDEO_ACTIVE_ROWS 576
39 39 #define VIDEO_VISIBLE_COLS 640
40 40 #define VIDEO_VISIBLE_ROWS 480
41 41 #endif
42 42  
43   -#ifdef VIDEO_MODE_NTSC
  43 +#ifdef VIDEO_MODE_NTSC
44 44 #define VIDEO_ACTIVE_COLS 720
45 45 #define VIDEO_ACTIVE_ROWS 525
46 46 #define VIDEO_VISIBLE_COLS 640
... ... @@ -54,7 +54,7 @@
54 54 0x82,
55 55 #else
56 56 0x02, /* Mode Register 1 */
57   -#endif
  57 +#endif /* VIDEO_DEBUG_COLORBARS */
58 58 0x16, /* Subcarrier Freq 0 */
59 59 0x7c, /* Subcarrier Freq 1 */
60 60 0xf0, /* Subcarrier Freq 2 */
... ... @@ -81,7 +81,7 @@
81 81 0x82,
82 82 #else
83 83 0x02, /* Mode Register 1 (2) */
84   -#endif
  84 +#endif /* VIDEO_DEBUG_COLORBARS */
85 85 0xcb, /* Subcarrier Freq 0 */
86 86 0x8a, /* Subcarrier Freq 1 */
87 87 0x09, /* Subcarrier Freq 2 */
include/video_ad7177.h
Diff comments   View file @ 8564acf
... ... @@ -12,7 +12,7 @@
12 12 *
13 13 * This program is distributed in the hope that it will be useful,
14 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15   - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 16 * GNU General Public License for more details.
17 17 *
18 18 * You should have received a copy of the GNU General Public License
19 19  
20 20  
21 21  
22 22  
... ... @@ -24,25 +24,25 @@
24 24 #ifndef _VIDEO_AD7177_H_
25 25 #define _VIDEO_AD7177_H_
26 26  
27   -/*#define VIDEO_DEBUG_DISABLE_COLORS 0 */
  27 +/* #define VIDEO_DEBUG_DISABLE_COLORS 0 */
28 28  
29 29 #define VIDEO_ENCODER_NAME "Analog Devices AD7177"
30 30  
31   -#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100Khz */
32   -#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
  31 +#define VIDEO_ENCODER_I2C_RATE 100000 /* Max rate is 100 kHz */
  32 +#define VIDEO_ENCODER_CB_Y_CR_Y /* Use CB Y CR Y format... */
33 33  
34 34 #define VIDEO_MODE_YUYV /* The only mode supported by this encoder */
35   -#undef VIDEO_MODE_RGB
  35 +#undef VIDEO_MODE_RGB
36 36 #define VIDEO_MODE_BPP 16
37 37  
38   -#ifdef VIDEO_MODE_PAL
  38 +#ifdef VIDEO_MODE_PAL
39 39 #define VIDEO_ACTIVE_COLS 720
40 40 #define VIDEO_ACTIVE_ROWS 576
41 41 #define VIDEO_VISIBLE_COLS 640
42 42 #define VIDEO_VISIBLE_ROWS 480
43 43 #endif
44 44  
45   -#ifdef VIDEO_MODE_NTSC
  45 +#ifdef VIDEO_MODE_NTSC
46 46 #define VIDEO_ACTIVE_COLS 720
47 47 #define VIDEO_ACTIVE_ROWS 525
48 48 #define VIDEO_VISIBLE_COLS 640
49 49  
50 50  
51 51  
52 52  
53 53  
54 54  
55 55  
56 56  
57 57  
58 58  
59 59  
60 60  
61 61  
62 62  
... ... @@ -52,98 +52,99 @@
52 52 static unsigned char
53 53 video_encoder_data[] = {
54 54 #ifdef VIDEO_MODE_NTSC
55   - 0x04, /* Mode Register 0 */
  55 + 0x04, /* Mode Register 0 */
56 56 #ifdef VIDEO_DEBUG_COLORBARS
57 57 0xc2,
58 58 #else
59   - 0x42, /* Mode Register 1 */
60   -#endif
61   - 0x16, /* Subcarrier Freq 0 */
62   - 0x7c, /* Subcarrier Freq 1 */
63   - 0xf0, /* Subcarrier Freq 2 */
64   - 0x21, /* Subcarrier Freq 3 */
65   - 0x00, /* Subcarrier phase */
66   - 0x02, /* Timing Register 0 */
67   - 0x00, /* Extended Captioning 0 */
68   - 0x00, /* Extended Captioning 1 */
69   - 0x00, /* Closed Captioning 0 */
70   - 0x00, /* Closed Captioning 1 */
71   - 0x00, /* Timing Register 1 */
72   - 0x08, /* Mode Register 2 */
73   - 0x00, /* Pedestal Register 0 */
74   - 0x00, /* Pedestal Register 1 */
75   - 0x00, /* Pedestal Register 2 */
76   - 0x00, /* Pedestal Register 3 */
77   - 0x08 /* Mode Register 3 */
  59 + 0x42, /* Mode Register 1 */
  60 +#endif /* VIDEO_DEBUG_COLORBARS */
  61 + 0x16, /* Subcarrier Freq 0 */
  62 + 0x7c, /* Subcarrier Freq 1 */
  63 + 0xf0, /* Subcarrier Freq 2 */
  64 + 0x21, /* Subcarrier Freq 3 */
  65 + 0x00, /* Subcarrier phase */
  66 + 0x02, /* Timing Register 0 */
  67 + 0x00, /* Extended Captioning 0 */
  68 + 0x00, /* Extended Captioning 1 */
  69 + 0x00, /* Closed Captioning 0 */
  70 + 0x00, /* Closed Captioning 1 */
  71 + 0x00, /* Timing Register 1 */
  72 + 0x08, /* Mode Register 2 */
  73 + 0x00, /* Pedestal Register 0 */
  74 + 0x00, /* Pedestal Register 1 */
  75 + 0x00, /* Pedestal Register 2 */
  76 + 0x00, /* Pedestal Register 3 */
  77 + 0x08, /* Mode Register 3 */
78 78  
79   -#endif
  79 +#endif /* VIDEO_MODE_NTSC */
  80 +
80 81 #ifdef VIDEO_MODE_PAL
81 82 #ifdef VIDEO_MODE_RGB_OUT
82 83  
83   - 0x69, /* Mode Register 0 */
  84 + 0x69, /* Mode Register 0 */
84 85 #ifdef VIDEO_DEBUG_COLORBARS
85   - 0xc0, /* Mode Register 1 (c0) */
  86 + 0xc0, /* Mode Register 1 (c0) */
86 87 #else
87   - 0x40, /* Mode Register 1 (c0) */
88   -#endif
89   - 0xcb, /* Subcarrier Freq 0 */
90   - 0x8a, /* Subcarrier Freq 1 */
91   - 0x09, /* Subcarrier Freq 2 */
92   - 0x2a, /* Subcarrier Freq 3 */
93   - 0x00, /* Subcarrier phase */
94   - 0x02, /* Timing Register 0 */
95   - 0x00, /* Extended Captioning 0 */
96   - 0x00, /* Extended Captioning 1 */
97   - 0x00, /* Closed Captioning 0 */
98   - 0x00, /* Closed Captioning 1 */
99   - 0x00, /* Timing Register 1 */
100   - 0x28, /* Mode Register 2 */
101   - 0x00, /* Pedestal Register 0 */
102   - 0x00, /* Pedestal Register 1 */
103   - 0x00, /* Pedestal Register 2 */
104   - 0x00, /* Pedestal Register 3 */
105   - 0x08 /* Mode Register 3 */
  88 + 0x40, /* Mode Register 1 (c0) */
  89 +#endif /* VIDEO_DEBUG_COLORBARS */
  90 + 0xcb, /* Subcarrier Freq 0 */
  91 + 0x8a, /* Subcarrier Freq 1 */
  92 + 0x09, /* Subcarrier Freq 2 */
  93 + 0x2a, /* Subcarrier Freq 3 */
  94 + 0x00, /* Subcarrier phase */
  95 + 0x02, /* Timing Register 0 */
  96 + 0x00, /* Extended Captioning 0 */
  97 + 0x00, /* Extended Captioning 1 */
  98 + 0x00, /* Closed Captioning 0 */
  99 + 0x00, /* Closed Captioning 1 */
  100 + 0x00, /* Timing Register 1 */
  101 + 0x28, /* Mode Register 2 */
  102 + 0x00, /* Pedestal Register 0 */
  103 + 0x00, /* Pedestal Register 1 */
  104 + 0x00, /* Pedestal Register 2 */
  105 + 0x00, /* Pedestal Register 3 */
  106 + 0x08, /* Mode Register 3 */
106 107  
107   -#else
  108 +#else /* ! VIDEO_MODE_RGB_OUT */
108 109  
109 110 0x09, /* Mode Register 0 (was 01) */
110 111 #ifdef VIDEO_DEBUG_COLORBARS
111   - 0xd8, /* */
  112 + 0xd8, /* */
112 113 #else
113 114 0x59, /* Mode Register 1 (was 58) */
114   -#endif
115   - 0xcb, /* Subcarrier Freq 0 */
116   - 0x8a, /* Subcarrier Freq 1 */
117   - 0x09, /* Subcarrier Freq 2 */
118   - 0x2a, /* Subcarrier Freq 3 */
119   - 0x00, /* Subcarrier phase */
  115 +#endif /* VIDEO_DEBUG_COLORBARS */
  116 + 0xcb, /* Subcarrier Freq 0 */
  117 + 0x8a, /* Subcarrier Freq 1 */
  118 + 0x09, /* Subcarrier Freq 2 */
  119 + 0x2a, /* Subcarrier Freq 3 */
  120 + 0x00, /* Subcarrier phase */
120 121 0x02, /* Timing Register 0 (was a) */
121   - 0x00, /* Extended Captioning 0 */
122   - 0x00, /* Extended Captioning 1 */
123   - 0x00, /* Closed Captioning 0 */
124   - 0x00, /* Closed Captioning 1 */
125   - 0x00, /* Timing Register 1 */
  122 + 0x00, /* Extended Captioning 0 */
  123 + 0x00, /* Extended Captioning 1 */
  124 + 0x00, /* Closed Captioning 0 */
  125 + 0x00, /* Closed Captioning 1 */
  126 + 0x00, /* Timing Register 1 */
126 127 #ifdef VIDEO_DEBUG_LOWPOWER
127 128 #ifdef VIDEO_DEBUG_DISABLE_COLORS
128   - 0x98, /* Mode Register 2 */
  129 + 0x98, /* Mode Register 2 */
129 130 #else
130   - 0x88, /* Mode Register 2 */
131   -#endif
132   -#else
  131 + 0x88, /* Mode Register 2 */
  132 +#endif /* VIDEO_DEBUG_DISABLE_COLORS */
  133 +#else /* ! VIDEO_DEBUG_LOWPOWER */
133 134 #ifdef VIDEO_DEBUG_DISABLE_COLORS
134   - 0x18, /* Mode Register 2 */
  135 + 0x18, /* Mode Register 2 */
135 136 #else
136   - 0x08, /* Mode Register 2 */
137   -#endif
138   -#endif
139   - 0x00, /* Pedestal Register 0 */
140   - 0x00, /* Pedestal Register 1 */
141   - 0x00, /* Pedestal Register 2 */
142   - 0x00, /* Pedestal Register 3 */
143   - 0x08 /* Mode Register 3 */
144   -#endif
145   -#endif
  137 + 0x08, /* Mode Register 2 */
  138 +#endif /* VIDEO_DEBUG_DISABLE_COLORS */
  139 +#endif /* VIDEO_DEBUG_LOWPOWER */
  140 + 0x00, /* Pedestal Register 0 */
  141 + 0x00, /* Pedestal Register 1 */
  142 + 0x00, /* Pedestal Register 2 */
  143 + 0x00, /* Pedestal Register 3 */
  144 + 0x08 /* Mode Register 3 */
  145 +#endif /* VIDEO_MODE_RGB_OUT */
  146 +#endif /* VIDEO_MODE_PAL */
146 147 } ;
147 148  
148   -#endif
  149 +#endif /* _VIDEO_AD7177_H_ */
include/video_ad7179.h
Diff comments   View file @ 8564acf
  1 +/*
  2 + * (C) Copyright 2003 Wolfgang Grandegger <wg@denx.de>
  3 + *
  4 + * See file CREDITS for list of people who contributed to this
  5 + * project.
  6 + *
  7 + * This program is free software; you can redistribute it and/or
  8 + * modify it under the terms of the GNU General Public License as
  9 + * published by the Free Software Foundation; either version 2 of
  10 + * the License, or (at your option) any later version.
  11 + *
  12 + * This program is distributed in the hope that it will be useful,
  13 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15 + * GNU General Public License for more details.
  16 + *
  17 + * You should have received a copy of the GNU General Public License
  18 + * along with this program; if not, write to the Free Software
  19 + * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20 + * MA 02111-1307 USA
  21 + */
  22 +
  23 +#ifndef _VIDEO_AD7179_H_
  24 +#define _VIDEO_AD7179_H_
  25 +
  26 +/*
  27 + * The video encoder data are board specific now!
  28 + */
  29 +
  30 +#if defined(CONFIG_RRVISION)
  31 +#include "../board/RRvision/video_ad7179.h"
  32 +#else
  33 +#error "Please provide a board-specific video_ad7179.h"
  34 +#endif
  35 +
  36 +#endif /* _VIDEO_AD7179_H_ */
... ... @@ -418,7 +418,7 @@
418 418  
419 419 #ifdef CONFIG_POST
420 420 post_run (NULL, POST_RAM | post_bootmode_get(0));
421   - if (post_bootmode_get(0) & POST_POWERFAIL) {
  421 + if (post_bootmode_get(0) & POST_SLOWTEST) {
422 422 post_bootmode_clear();
423 423 board_poweroff();
424 424 }
... ... @@ -526,7 +526,10 @@
526 526  
527 527 #ifdef CONFIG_POST
528 528 post_bootmode_init();
529   - post_run (NULL, POST_ROM | post_bootmode_get(0));
  529 + if (post_hotkeys_pressed(gd)) /* Force the long-running tests (memory) */
  530 + post_run (NULL, POST_ROM | POST_SLOWTEST);
  531 + else
  532 + post_run (NULL, POST_ROM | post_bootmode_get(0));
530 533 #endif
531 534  
532 535 WATCHDOG_RESET();
... ... @@ -897,8 +900,11 @@
897 900 #endif
898 901  
899 902 #ifdef CONFIG_POST
900   - post_run (NULL, POST_RAM | post_bootmode_get(0));
901   - if (post_bootmode_get(0) & POST_POWERFAIL) {
  903 + if (gd->post_hotkeys_latch)
  904 + post_run (NULL, POST_RAM | POST_SLOWTEST);
  905 + else
  906 + post_run (NULL, POST_RAM | post_bootmode_get(0));
  907 + if (post_bootmode_get(0) & POST_SLOWTEST) {
902 908 post_bootmode_clear();
903 909 board_poweroff();
904 910 }
... ... @@ -146,7 +146,7 @@
146 146 * regions of RAM around each 1Mb boundary. For example, for 64Mb
147 147 * RAM the following areas are verified: 0x00000000-0x00000800,
148 148 * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800-
149   - * 0x04000000. If the test is run in power-fail mode, it verifies
  149 + * 0x04000000. If the test is run in slow-test mode, it verifies
150 150 * the whole RAM.
151 151 */
152 152  
153 153  
... ... @@ -460,9 +460,9 @@
460 460 256 << 20 : bd->bi_memsize) - (1 << 20);
461 461  
462 462  
463   - if (flags & POST_POWERFAIL) {
  463 + if (flags & POST_SLOWTEST) {
464 464 ret = memory_post_tests (CFG_SDRAM_BASE, memsize);
465   - } else { /* POST_POWERNORMAL */
  465 + } else { /* POST_NORMAL */
466 466  
467 467 unsigned long i;
468 468  
... ... @@ -68,7 +68,7 @@
68 68 if (bootmode == 0) {
69 69 bootmode = POST_POWERON;
70 70 } else if (bootmode == POST_POWERON) {
71   - bootmode = POST_POWERNORMAL;
  71 + bootmode = POST_NORMAL;
72 72 } else {
73 73 return;
74 74 }
... ... @@ -153,8 +153,8 @@
153 153  
154 154 static void post_get_flags (int *test_flags)
155 155 {
156   - int flag[] = { POST_POWERON, POST_POWERNORMAL, POST_POWERFAIL };
157   - char *var[] = { "post_poweron", "post_normal", "post_shutdown" };
  156 + int flag[] = { POST_POWERON, POST_NORMAL, POST_SLOWTEST };
  157 + char *var[] = { "post_poweron", "post_normal", "post_slowtest" };
158 158 int varnum = sizeof (var) / sizeof (var[0]);
159 159 char list[128]; /* long enough for POST list */
160 160 char *name;
... ... @@ -98,6 +98,7 @@
98 98 void (*exec_before)(sysmon_table_t *);
99 99 void (*exec_after)(sysmon_table_t *);
100 100  
  101 + int unit_precision;
101 102 int unit_div;
102 103 int unit_min;
103 104 int unit_max;
104 105  
105 106  
106 107  
107 108  
108 109  
109 110  
110 111  
... ... @@ -105,31 +106,34 @@
105 106 uint val_min;
106 107 uint val_max;
107 108 int val_valid;
  109 + uint val_min_alt;
  110 + uint val_max_alt;
  111 + int val_valid_alt;
108 112 uint addr;
109 113 };
110 114  
111 115 static sysmon_table_t sysmon_table[] =
112 116 {
113 117 {"Board temperature", " C", &sysmon_lm87_sgn, NULL, sysmon_ccfl_disable,
114   - 1, -128, 127, 0xFF, 0x58, 0xD5, 0, 0x27},
  118 + 1, 1, -128, 127, 0xFF, 0x58, 0xD5, 0, 0x67, 0xC6, 0, 0x27},
115 119  
116 120 {"Front temperature", " C", &sysmon_lm87, NULL, sysmon_ccfl_disable,
117   - 100, -27316, 8984, 0xFF, 0xA4, 0xFC, 0, 0x29},
  121 + 1, 100, -27316, 8984, 0xFF, 0xA4, 0xFC, 0, 0xAE, 0xF1, 0, 0x29},
118 122  
119 123 {"+3.3V CPU logic", "V", &sysmon_lm87, NULL, NULL,
120   - 1000, 0, 4386, 0xFF, 0xB6, 0xC9, 0, 0x22},
  124 + 100, 1000, 0, 4386, 0xFF, 0xB6, 0xC9, 0, 0xB6, 0xC9, 0, 0x22},
121 125  
122   - {"+5V logic", "V", &sysmon_lm87, NULL, NULL,
123   - 1000, 0, 6630, 0xFF, 0xB6, 0xCA, 0, 0x23},
  126 + {"+ 5 V logic", "V", &sysmon_lm87, NULL, NULL,
  127 + 100, 1000, 0, 6630, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x23},
124 128  
125   - {"+12V PCMCIA", "V", &sysmon_lm87, NULL, NULL,
126   - 1000, 0, 15460, 0xFF, 0xBC, 0xD0, 0, 0x21},
  129 + {"+12 V PCMCIA", "V", &sysmon_lm87, NULL, NULL,
  130 + 100, 1000, 0, 15460, 0xFF, 0xBC, 0xD0, 0, 0xBC, 0xD0, 0, 0x21},
127 131  
128   - {"+12V CCFL", "V", &sysmon_lm87, NULL, sysmon_ccfl_enable,
129   - 1000, 0, 15900, 0xFF, 0xB6, 0xCA, 0, 0x24},
  132 + {"+12 V CCFL", "V", &sysmon_lm87, NULL, sysmon_ccfl_enable,
  133 + 100, 1000, 0, 15900, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x24},
130 134  
131   - {"+5V standby", "V", &sysmon_pic, NULL, NULL,
132   - 1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0x7C},
  135 + {"+ 5 V standby", "V", &sysmon_pic, NULL, NULL,
  136 + 100, 1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0xC8, 0xDE, 0, 0x7C},
133 137 };
134 138 static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]);
135 139  
136 140  
137 141  
138 142  
139 143  
140 144  
141 145  
142 146  
143 147  
... ... @@ -176,31 +180,38 @@
176 180 }
177 181 }
178 182  
179   -static char * sysmon_unit_value (sysmon_table_t * s, uint val)
  183 +static char *sysmon_unit_value (sysmon_table_t *s, uint val)
180 184 {
181 185 static char buf[32];
182 186 int unit_val =
183 187 s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask;
184   - char * p;
  188 + char *p, sign;
185 189 int dec, frac;
186 190  
187   - sprintf(buf, "%+d", unit_val / s->unit_div);
  191 + if (unit_val < 0) {
  192 + sign = '-';
  193 + unit_val = -unit_val;
  194 + } else {
  195 + sign = '+';
  196 + }
188 197  
189   - frac = (unit_val > 0 ? unit_val : -unit_val) % s->unit_div;
190   - p = buf + strlen(buf);
  198 + p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div);
191 199  
192   - dec = s->unit_div;
193 200  
  201 + frac = unit_val % s->unit_div;
  202 +
  203 + frac /= (s->unit_div / s->unit_precision);
  204 +
  205 + dec = s->unit_precision;
  206 +
194 207 if (dec != 1)
195 208 {
196 209 *p++ = '.';
197 210 }
198   -
199 211 for (dec /= 10; dec != 0; dec /= 10)
200 212 {
201   - *p++ = '0' + frac / dec % 10;
  213 + *p++ = '0' + (frac / dec) % 10;
202 214 }
203   -
204 215 strcpy(p, s->unit_name);
205 216  
206 217 return buf;
... ... @@ -256,7 +267,7 @@
256 267  
257 268 static void sysmon_ccfl_disable (sysmon_table_t * this)
258 269 {
259   - if (!this->val_valid)
  270 + if (!this->val_valid_alt)
260 271 {
261 272 sysmon_temp_invalid = 1;
262 273 }
... ... @@ -300,6 +311,7 @@
300 311  
301 312 val = t->sysmon->read(t->sysmon, t->addr);
302 313 t->val_valid = val >= t->val_min && val <= t->val_max;
  314 + t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt;
303 315  
304 316 if (t->exec_after)
305 317 {
... ... @@ -68,7 +68,7 @@
68 68 "Watchdog timer test",
69 69 "watchdog",
70 70 "This test checks the watchdog timer.",
71   - POST_RAM | POST_POWERON | POST_POWERFAIL | POST_MANUAL | POST_REBOOT,
  71 + POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT,
72 72 &watchdog_post_test,
73 73 NULL,
74 74 NULL,
... ... @@ -92,7 +92,7 @@
92 92 "RTC test",
93 93 "rtc",
94 94 "This test verifies the RTC operation.",
95   - POST_RAM | POST_POWERFAIL | POST_MANUAL,
  95 + POST_RAM | POST_SLOWTEST | POST_MANUAL,
96 96 &rtc_post_test,
97 97 NULL,
98 98 NULL,
... ... @@ -104,7 +104,7 @@
104 104 "Memory test",
105 105 "memory",
106 106 "This test checks RAM.",
107   - POST_ROM | POST_POWERON | POST_POWERFAIL | POST_PREREL,
  107 + POST_ROM | POST_POWERON | POST_SLOWTEST | POST_PREREL,
108 108 &memory_post_test,
109 109 NULL,
110 110 NULL,
... ... @@ -129,7 +129,7 @@
129 129 "UART test",
130 130 "uart",
131 131 "This test verifies the UART operation.",
132   - POST_RAM | POST_POWERFAIL | POST_MANUAL,
  132 + POST_RAM | POST_SLOWTEST | POST_MANUAL,
133 133 &uart_post_test,
134 134 NULL,
135 135 NULL,
... ... @@ -70,6 +70,7 @@
70 70 { IH_CPU_SH, "sh", "SuperH", },
71 71 { IH_CPU_SPARC, "sparc", "SPARC", },
72 72 { IH_CPU_SPARC64, "sparc64", "SPARC 64 Bit", },
  73 + { IH_CPU_M68K, "m68k", "MC68000", },
73 74 { -1, "", "", },
74 75 };
75 76