/*
   * Copyright (C) 2013 Freescale Semiconductor, Inc.

   * Copyright (C) 2014 O.S. Systems Software LTDA.

   *
   * Author: Fabio Estevam <fabio.estevam@freescale.com>
   *

   * SPDX-License-Identifier:	GPL-2.0+

   */
  
  #include <asm/arch/clock.h>

  #include <asm/arch/crm_regs.h>

  #include <asm/arch/iomux.h>
  #include <asm/arch/imx-regs.h>
  #include <asm/arch/mx6-pins.h>

  #include <asm/arch/mxc_hdmi.h>

  #include <asm/arch/sys_proto.h>
  #include <asm/gpio.h>
  #include <asm/imx-common/iomux-v3.h>

  #include <asm/imx-common/mxc_i2c.h>

  #include <asm/imx-common/boot_mode.h>

  #include <asm/imx-common/video.h>

  #include <asm/io.h>

  #include <linux/sizes.h>

  #include <common.h>
  #include <fsl_esdhc.h>
  #include <mmc.h>
  #include <miiphy.h>
  #include <netdev.h>

  #include <phy.h>

  #include <input.h>

  #include <i2c.h>

  
  DECLARE_GLOBAL_DATA_PTR;

  #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
  	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
  	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

  #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
  	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
  	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)

  #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
  	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

  #define I2C_PAD_CTRL	(PAD_CTL_PUS_100K_UP |			\
  	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |	\
  	PAD_CTL_ODE | PAD_CTL_SRE_FAST)

  #define USDHC1_CD_GPIO		IMX_GPIO_NR(1, 2)

  #define USDHC3_CD_GPIO		IMX_GPIO_NR(3, 9)

  #define ETH_PHY_RESET		IMX_GPIO_NR(3, 29)
  
  int dram_init(void)
  {

  	gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024;

  
  	return 0;
  }
  
  static iomux_v3_cfg_t const uart1_pads[] = {

  	MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
  	MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

  };

  static iomux_v3_cfg_t const usdhc1_pads[] = {

  	MX6_PAD_SD1_CLK__SD1_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD1_CMD__SD1_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

  	/* Carrier MicroSD Card Detect */

  	MX6_PAD_GPIO_2__GPIO1_IO02      | MUX_PAD_CTRL(NO_PAD_CTRL),

  };

  static iomux_v3_cfg_t const usdhc3_pads[] = {

  	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
  	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

  	/* SOM MicroSD Card Detect */

  	MX6_PAD_EIM_DA9__GPIO3_IO09     | MUX_PAD_CTRL(NO_PAD_CTRL),

  };
  
  static iomux_v3_cfg_t const enet_pads[] = {
  	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),

  	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),

  	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),

  	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),

  	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
  	/* AR8031 PHY Reset */

  	MX6_PAD_EIM_D29__GPIO3_IO29		| MUX_PAD_CTRL(NO_PAD_CTRL),

  };
  
  static void setup_iomux_uart(void)
  {
  	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
  }
  
  static void setup_iomux_enet(void)
  {
  	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
  
  	/* Reset AR8031 PHY */
  	gpio_direction_output(ETH_PHY_RESET, 0);
  	udelay(500);
  	gpio_set_value(ETH_PHY_RESET, 1);
  }

  static struct fsl_esdhc_cfg usdhc_cfg[2] = {

  	{USDHC3_BASE_ADDR},

  	{USDHC1_BASE_ADDR},

  };

  int board_mmc_getcd(struct mmc *mmc)
  {
  	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
  	int ret = 0;
  
  	switch (cfg->esdhc_base) {

  	case USDHC1_BASE_ADDR:
  		ret = !gpio_get_value(USDHC1_CD_GPIO);
  		break;

  	case USDHC3_BASE_ADDR:
  		ret = !gpio_get_value(USDHC3_CD_GPIO);
  		break;
  	}
  
  	return ret;
  }

  int board_mmc_init(bd_t *bis)
  {

  	int ret;

  	u32 index = 0;
  
  	/*
  	 * Following map is done:
  	 * (U-boot device node)    (Physical Port)
  	 * mmc0                    SOM MicroSD
  	 * mmc1                    Carrier board MicroSD
  	 */
  	for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
  		switch (index) {
  		case 0:
  			imx_iomux_v3_setup_multiple_pads(
  				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
  			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  			usdhc_cfg[0].max_bus_width = 4;
  			gpio_direction_input(USDHC3_CD_GPIO);
  			break;
  		case 1:
  			imx_iomux_v3_setup_multiple_pads(
  				usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
  			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
  			usdhc_cfg[1].max_bus_width = 4;
  			gpio_direction_input(USDHC1_CD_GPIO);
  			break;
  		default:
  			printf("Warning: you configured more USDHC controllers"
  			       "(%d) then supported by the board (%d)
  ",
  			       index + 1, CONFIG_SYS_FSL_USDHC_NUM);

  			return -EINVAL;

  		}

  		ret = fsl_esdhc_initialize(bis, &usdhc_cfg[index]);
  		if (ret)
  			return ret;

  	}

  	return 0;

  }
  
  static int mx6_rgmii_rework(struct phy_device *phydev)
  {
  	unsigned short val;
  
  	/* To enable AR8031 ouput a 125MHz clk from CLK_25M */
  	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  	phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  
  	val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  	val &= 0xffe3;
  	val |= 0x18;
  	phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  
  	/* introduce tx clock delay */
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  	val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  	val |= 0x0100;
  	phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  
  	return 0;
  }
  
  int board_phy_config(struct phy_device *phydev)
  {
  	mx6_rgmii_rework(phydev);
  
  	if (phydev->drv->config)
  		phydev->drv->config(phydev);
  
  	return 0;
  }

  #if defined(CONFIG_VIDEO_IPUV3)

  struct i2c_pads_info i2c2_pad_info = {
  	.scl = {
  		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL
  			| MUX_PAD_CTRL(I2C_PAD_CTRL),
  		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12
  			| MUX_PAD_CTRL(I2C_PAD_CTRL),
  		.gp = IMX_GPIO_NR(4, 12)
  	},
  	.sda = {
  		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA
  			| MUX_PAD_CTRL(I2C_PAD_CTRL),
  		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13
  			| MUX_PAD_CTRL(I2C_PAD_CTRL),
  		.gp = IMX_GPIO_NR(4, 13)
  	}

  };

  static iomux_v3_cfg_t const fwadapt_7wvga_pads[] = {
  	MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,
  	MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* HSync */
  	MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* VSync */
  	MX6_PAD_DI0_PIN4__IPU1_DI0_PIN04
  		| MUX_PAD_CTRL(PAD_CTL_DSE_120ohm), /* Contrast */
  	MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, /* DISP0_DRDY */
  
  	MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00,
  	MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01,
  	MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02,
  	MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03,
  	MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04,
  	MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05,
  	MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06,
  	MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07,
  	MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08,
  	MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09,
  	MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10,
  	MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11,
  	MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12,
  	MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13,
  	MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14,
  	MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15,
  	MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16,
  	MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17,
  
  	MX6_PAD_SD4_DAT2__GPIO2_IO10
  		| MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_BKLEN */
  	MX6_PAD_SD4_DAT3__GPIO2_IO11
  		| MUX_PAD_CTRL(NO_PAD_CTRL), /* DISP0_VDDEN */
  };

  static void do_enable_hdmi(struct display_info_t const *dev)
  {
  	imx_enable_hdmi_phy();
  }

  static int detect_i2c(struct display_info_t const *dev)
  {
  	return (0 == i2c_set_bus_num(dev->bus)) &&
  			(0 == i2c_probe(dev->addr));
  }

  static void enable_fwadapt_7wvga(struct display_info_t const *dev)
  {
  	imx_iomux_v3_setup_multiple_pads(
  		fwadapt_7wvga_pads,
  		ARRAY_SIZE(fwadapt_7wvga_pads));

  	gpio_direction_output(IMX_GPIO_NR(2, 10), 1);
  	gpio_direction_output(IMX_GPIO_NR(2, 11), 1);

  }

  struct display_info_t const displays[] = {{
  	.bus	= -1,
  	.addr	= 0,
  	.pixfmt	= IPU_PIX_FMT_RGB24,
  	.detect	= detect_hdmi,
  	.enable	= do_enable_hdmi,
  	.mode	= {
  		.name           = "HDMI",
  		.refresh        = 60,
  		.xres           = 1024,
  		.yres           = 768,
  		.pixclock       = 15385,
  		.left_margin    = 220,
  		.right_margin   = 40,
  		.upper_margin   = 21,
  		.lower_margin   = 7,
  		.hsync_len      = 60,
  		.vsync_len      = 10,
  		.sync           = FB_SYNC_EXT,
  		.vmode          = FB_VMODE_NONINTERLACED
  } }, {
  	.bus	= 1,
  	.addr	= 0x10,
  	.pixfmt	= IPU_PIX_FMT_RGB666,
  	.detect	= detect_i2c,
  	.enable	= enable_fwadapt_7wvga,
  	.mode	= {
  		.name           = "FWBADAPT-LCD-F07A-0102",
  		.refresh        = 60,
  		.xres           = 800,
  		.yres           = 480,
  		.pixclock       = 33260,
  		.left_margin    = 128,
  		.right_margin   = 128,
  		.upper_margin   = 22,
  		.lower_margin   = 22,
  		.hsync_len      = 1,
  		.vsync_len      = 1,
  		.sync           = 0,
  		.vmode          = FB_VMODE_NONINTERLACED
  } } };
  size_t display_count = ARRAY_SIZE(displays);

  static void setup_display(void)
  {
  	struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

  	int reg;

  	enable_ipu_clock();
  	imx_setup_hdmi();

  
  	reg = readl(&mxc_ccm->chsccdr);

  	reg |= (CHSCCDR_CLK_SEL_LDB_DI0

  		<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);

  	writel(reg, &mxc_ccm->chsccdr);

  
  	/* Disable LCD backlight */
  	imx_iomux_v3_setup_pad(MX6_PAD_DI0_PIN4__GPIO4_IO20);
  	gpio_direction_input(IMX_GPIO_NR(4, 20));

  }
  #endif /* CONFIG_VIDEO_IPUV3 */

  int board_eth_init(bd_t *bis)
  {

  	setup_iomux_enet();

  	return cpu_eth_init(bis);

  }
  
  int board_early_init_f(void)
  {
  	setup_iomux_uart();

  #if defined(CONFIG_VIDEO_IPUV3)
  	setup_display();
  #endif

  	return 0;
  }

  /*
   * Do not overwrite the console
   * Use always serial for U-Boot console
   */
  int overwrite_console(void)
  {
  	return 1;
  }

  #ifdef CONFIG_CMD_BMODE
  static const struct boot_mode board_boot_modes[] = {
  	/* 4 bit bus width */
  	{"mmc0",	  MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
  	{"mmc1",	  MAKE_CFGVAL(0x40, 0x20, 0x00, 0x00)},
  	{NULL,	 0},
  };
  #endif
  
  int board_late_init(void)
  {
  #ifdef CONFIG_CMD_BMODE
  	add_board_boot_modes(board_boot_modes);
  #endif
  
  	return 0;
  }

  int board_init(void)
  {
  	/* address of boot parameters */
  	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

  	setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c2_pad_info);

  	return 0;
  }

  int checkboard(void)
  {
  	puts("Board: Wandboard
  ");
  
  	return 0;
  }