Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit aad4659a2fde4b69e8124d6fe8b57bf28d3c747d

Authored by Abbas Raza
Committed by Stefano Babic
1 parent 2feae93ac0
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

mmc: i.MX6: fsl_esdhc: Define maximum bus width supported by a board 

Maximum bus width supported by some i.MX6 boards is not 8bit like
others. In case where both host controller and card support 8bit transfers,
they agree to communicate on 8bit interface while some boards support only 4bit interface.
Due to this reason the mmc 8bit default mode fails on these boards. To rectify this,
define maximum bus width supported by these boards (4bit). If max_bus_width is not
defined, it is 0 by default and 8bit width support will be enabled in host
capabilities otherwise host capabilities are modified accordingly.

It is tested with a MMCplus card.

Signed-off-by: Abbas Raza <Abbas_Raza@mentor.com>
cc: stefano Babic <sbabic@denx.de>
cc: Andy Fleming <afleming@gmail.com>
Acked-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Andrew Gabbasov <andrew_gabbasov@mentor.com>

Showing 5 changed files with 16 additions and 0 deletions Side-by-side Diff

board/boundary/nitrogen6x/nitrogen6x.c
Diff comments   View file @ aad4659
... ... @@ -304,6 +304,9 @@
304 304 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
305 305 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
306 306  
  307 + usdhc_cfg[0].max_bus_width = 4;
  308 + usdhc_cfg[1].max_bus_width = 4;
  309 +
307 310 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
308 311 switch (index) {
309 312 case 0:
board/freescale/mx6qsabrelite/mx6qsabrelite.c
Diff comments   View file @ aad4659
... ... @@ -274,6 +274,9 @@
274 274 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
275 275 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
276 276  
  277 + usdhc_cfg[0].max_bus_width = 4;
  278 + usdhc_cfg[1].max_bus_width = 4;
  279 +
277 280 for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) {
278 281 switch (index) {
279 282 case 0:
board/wandboard/wandboard.c
Diff comments   View file @ aad4659
... ... @@ -105,6 +105,8 @@
105 105 imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
106 106  
107 107 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  108 + usdhc_cfg[0].max_bus_width = 4;
  109 +
108 110 return fsl_esdhc_initialize(bis, &usdhc_cfg[0]);
109 111 }
110 112  
drivers/mmc/fsl_esdhc.c
Diff comments   View file @ aad4659
... ... @@ -580,6 +580,13 @@
580 580  
581 581 mmc->host_caps = MMC_MODE_4BIT | MMC_MODE_8BIT | MMC_MODE_HC;
582 582  
  583 + if (cfg->max_bus_width > 0) {
  584 + if (cfg->max_bus_width < 8)
  585 + mmc->host_caps &= ~MMC_MODE_8BIT;
  586 + if (cfg->max_bus_width < 4)
  587 + mmc->host_caps &= ~MMC_MODE_4BIT;
  588 + }
  589 +
583 590 if (caps & ESDHC_HOSTCAPBLT_HSS)
584 591 mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
585 592  
... ... @@ -168,6 +168,7 @@
168 168 struct fsl_esdhc_cfg {
169 169 u32 esdhc_base;
170 170 u32 sdhc_clk;
  171 + u8 max_bus_width;
171 172 };
172 173  
173 174 /* Select the correct accessors depending on endianess */