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board/socrates/socrates.c
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/* * (C) Copyright 2008 * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. * * Copyright 2004 Freescale Semiconductor. * (C) Copyright 2002,2003, Motorola Inc. * Xianghua Xiao, (X.Xiao@motorola.com) * * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com> * |
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* SPDX-License-Identifier: GPL-2.0+ |
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*/ #include <common.h> #include <pci.h> #include <asm/processor.h> #include <asm/immap_85xx.h> #include <ioports.h> #include <flash.h> |
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#include <libfdt.h> #include <fdt_support.h> |
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#include <asm/io.h> |
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#include <i2c.h> #include <mb862xx.h> #include <video_fb.h> |
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#include "upm_table.h" |
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DECLARE_GLOBAL_DATA_PTR; extern flash_info_t flash_info[]; /* FLASH chips info */ |
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extern GraphicDevice mb862xx; |
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void local_bus_init (void); ulong flash_get_size (ulong base, int banknum); int checkboard (void) { |
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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char buf[64]; |
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int f; |
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int i = getenv_f("serial#", buf, sizeof(buf)); #ifdef CONFIG_PCI char *src; #endif |
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puts("Board: Socrates"); |
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if (i > 0) { |
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puts(", serial# "); |
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puts(buf); |
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} putc(' '); #ifdef CONFIG_PCI |
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/* Check the PCI_clk sel bit */ if (in_be32(&gur->porpllsr) & (1<<15)) { |
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src = "SYSCLK"; f = CONFIG_SYS_CLK_FREQ; } else { src = "PCI_CLK"; f = CONFIG_PCI_CLK_FREQ; } printf ("PCI1: 32 bit, %d MHz (%s) ", f/1000000, src); |
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#else printf ("PCI1: disabled "); #endif /* * Initialize local bus. */ local_bus_init (); |
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return 0; } int misc_init_r (void) { |
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/* * Adjust flash start and offset to detected values */ gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0; /* * Check if boot FLASH isn't max size */ |
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if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) { |
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set_lbc_or(0, gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff)); set_lbc_br(0, gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff)); |
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/* * Re-check to get correct base address */ |
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flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1); |
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} /* * Check if only one FLASH bank is available */ |
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if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) { |
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set_lbc_or(1, 0); set_lbc_br(1, 0); |
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/* * Re-do flash protection upon new addresses */ flash_protect (FLAG_PROTECT_CLEAR, gd->bd->bi_flashstart, 0xffffffff, |
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
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/* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, |
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CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
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/* Environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR, CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, |
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
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/* Redundant environment protection ON by default */ flash_protect (FLAG_PROTECT_SET, |
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CONFIG_ENV_ADDR_REDUND, |
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CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, |
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&flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); |
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} return 0; } /* * Initialize Local Bus */ void local_bus_init (void) { |
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volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; |
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volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); |
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sys_info_t sysinfo; uint clkdiv; uint lbc_mhz; |
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uint lcrr = CONFIG_SYS_LBC_LCRR; |
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get_sys_info (&sysinfo); |
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clkdiv = lbc->lcrr & LCRR_CLKDIV; |
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lbc_mhz = sysinfo.freq_systembus / 1000000 / clkdiv; |
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/* Disable PLL bypass for Local Bus Clock >= 66 MHz */ if (lbc_mhz >= 66) lcrr &= ~LCRR_DBYP; /* DLL Enabled */ else lcrr |= LCRR_DBYP; /* DLL Bypass */ out_be32 (&lbc->lcrr, lcrr); asm ("sync;isync;msync"); |
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out_be32 (&lbc->ltesr, 0xffffffff); /* Clear LBC error interrupts */ out_be32 (&lbc->lteir, 0xffffffff); /* Enable LBC error interrupts */ out_be32 (&ecm->eedr, 0xffffffff); /* Clear ecm errors */ out_be32 (&ecm->eeer, 0xffffffff); /* Enable ecm errors */ |
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/* Init UPMA for FPGA access */ out_be32 (&lbc->mamr, 0x44440); /* Use a customer-supplied value */ upmconfig (UPMA, (uint *)UPMTableA, sizeof(UPMTableA)/sizeof(int)); |
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/* Init UPMB for Lime controller access */ out_be32 (&lbc->mbmr, 0x444440); /* Use a customer-supplied value */ upmconfig (UPMB, (uint *)UPMTableB, sizeof(UPMTableB)/sizeof(int)); |
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} #if defined(CONFIG_PCI) /* * Initialize PCI Devices, report devices found. */ #ifndef CONFIG_PCI_PNP static struct pci_config_table pci_mpc85xxads_config_table[] = { {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_IDSEL_NUMBER, PCI_ANY_ID, pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, PCI_ENET0_MEMADDR, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, {} }; #endif static struct pci_controller hose = { #ifndef CONFIG_PCI_PNP config_table:pci_mpc85xxads_config_table, #endif }; #endif /* CONFIG_PCI */ void pci_init_board (void) { #ifdef CONFIG_PCI pci_mpc85xx_init (&hose); #endif /* CONFIG_PCI */ } #ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) { |
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volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); |
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/* set and reset the GPIO pin 2 which will reset the W83782G chip */ out_8((unsigned char*)&gur->gpoutdr, 0x3F ); out_be32((unsigned int*)&gur->gpiocr, 0x200 ); /* enable GPOut */ udelay(200); out_8( (unsigned char*)&gur->gpoutdr, 0x1F ); |
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return (0); } #endif /* CONFIG_BOARD_EARLY_INIT_R */ |
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { |
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u32 val[12]; int rc, i = 0; |
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ft_cpu_setup(blob, bd); |
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/* Fixup NOR FLASH mapping */ val[i++] = 0; /* chip select number */ val[i++] = 0; /* always 0 */ val[i++] = gd->bd->bi_flashstart; val[i++] = gd->bd->bi_flashsize; |
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if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) { |
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/* Fixup LIME mapping */ val[i++] = 2; /* chip select number */ val[i++] = 0; /* always 0 */ |
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val[i++] = CONFIG_SYS_LIME_BASE; val[i++] = CONFIG_SYS_LIME_SIZE; |
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} |
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/* Fixup FPGA mapping */ val[i++] = 3; /* chip select number */ val[i++] = 0; /* always 0 */ |
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val[i++] = CONFIG_SYS_FPGA_BASE; val[i++] = CONFIG_SYS_FPGA_SIZE; |
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rc = fdt_find_and_setprop(blob, "/localbus", "ranges", val, i * sizeof(u32), 1); |
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if (rc) |
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printf("Unable to update localbus ranges, err=%s ", |
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fdt_strerror(rc)); |
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} #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ |
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#define DEFAULT_BRIGHTNESS 25 #define BACKLIGHT_ENABLE (1 << 31) |
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static const gdc_regs init_regs [] = { {0x0100, 0x00010f00}, {0x0020, 0x801901df}, {0x0024, 0x00000000}, {0x0028, 0x00000000}, {0x002c, 0x00000000}, {0x0110, 0x00000000}, {0x0114, 0x00000000}, {0x0118, 0x01df0320}, {0x0004, 0x041f0000}, {0x0008, 0x031f031f}, {0x000c, 0x017f0349}, {0x0010, 0x020c0000}, {0x0014, 0x01df01e9}, {0x0018, 0x00000000}, {0x001c, 0x01e00320}, {0x0100, 0x80010f00}, {0x0, 0x0} }; const gdc_regs *board_get_regs (void) { return init_regs; } |
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int lime_probe(void) { |
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uint cfg_br2; uint cfg_or2; |
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int type; |
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cfg_br2 = get_lbc_br(2); cfg_or2 = get_lbc_or(2); |
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/* Configure GPCM for CS2 */ |
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set_lbc_br(2, 0); set_lbc_or(2, 0xfc000410); set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901); |
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/* Get controller type */ type = mb862xx_probe(CONFIG_SYS_LIME_BASE); |
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/* Restore previous CS2 configuration */ |
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set_lbc_br(2, 0); set_lbc_or(2, cfg_or2); set_lbc_br(2, cfg_br2); |
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return (type == MB862XX_TYPE_LIME) ? 1 : 0; |
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} |
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/* Returns Lime base address */ unsigned int board_video_init (void) { |
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if (!lime_probe()) |
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return 0; |
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mb862xx.winSizeX = 800; mb862xx.winSizeY = 480; |
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mb862xx.gdfIndex = GDF_15BIT_555RGB; mb862xx.gdfBytesPP = 2; |
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return CONFIG_SYS_LIME_BASE; |
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} #define W83782D_REG_CFG 0x40 #define W83782D_REG_BANK_SEL 0x4e #define W83782D_REG_ADCCLK 0x4b #define W83782D_REG_BEEP_CTRL 0x4d #define W83782D_REG_BEEP_CTRL2 0x57 #define W83782D_REG_PWMOUT1 0x5b #define W83782D_REG_VBAT 0x5d static int w83782d_hwmon_init(void) { u8 buf; |
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if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1)) |
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return -1; |
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i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80); i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0); i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40); |
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buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL); i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL, |
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buf | 0x80); |
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i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0); i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47); i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01); |
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buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG); i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, |
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(buf & 0xf4) | 0x01); return 0; } static void board_backlight_brightness(int br) { u32 reg; u8 buf; u8 old_buf; /* Select bank 0 */ |
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if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) |
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goto err; else buf = old_buf & 0xf8; |
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if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1)) |
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goto err; if (br > 0) { /* PWMOUT1 duty cycle ctrl */ buf = 255 / (100 / br); |
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if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) |
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goto err; /* LEDs on */ |
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reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); |
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if (!(reg & BACKLIGHT_ENABLE)); |
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out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), |
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reg | BACKLIGHT_ENABLE); } else { buf = 0; |
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if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1)) |
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goto err; /* LEDs off */ |
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reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c)); |
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reg &= ~BACKLIGHT_ENABLE; |
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out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg); |
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} /* Restore previous bank setting */ |
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if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1)) |
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goto err; return; err: printf("W83782G I2C access failed "); } void board_backlight_switch (int flag) { char * param; int rc; if (w83782d_hwmon_init()) printf ("hwmon IC init failed "); if (flag) { param = getenv("brightness"); rc = param ? simple_strtol(param, NULL, 10) : -1; if (rc < 0) rc = DEFAULT_BRIGHTNESS; } else { rc = 0; } board_backlight_brightness(rc); } #if defined(CONFIG_CONSOLE_EXTRA_INFO) /* * Return text to be printed besides the logo. */ void video_get_info_str (int line_number, char *info) { if (line_number == 1) { strcpy (info, " Board: Socrates"); } else { info [0] = '\0'; } } #endif |