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Commit f51cdaf19141151ce2b40d562a468605340f2315

Authored by Becky Bruce
Committed by Kumar Gala
1 parent 0914f48328
Exists in master and in 55 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, emb_lf_v2023.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, u-boot-2013.01.y, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

83xx/85xx/86xx: LBC register cleanup 

Currently, 83xx, 86xx, and 85xx have a lot of duplicated code
dedicated to defining and manipulating the LBC registers.  Merge
this into a single spot.

To do this, we have to decide on a common name for the data structure
that holds the lbc registers - it will now be known as fsl_lbc_t, and we
adopt a common name for the immap layouts that include the lbc - this was
previously known as either im_lbc or lbus; use the former.

In addition, create accessors for the BR/OR regs that use in/out_be32
and use those instead of the mismash of access methods currently in play.

I have done a successful ppc build all and tested a board or two from
each processor family.

Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

Showing 52 changed files with 318 additions and 500 deletions Side-by-side Diff

arch/powerpc/cpu/mpc83xx/cpu.c
Diff comments   View file @ f51cdaf
... ... @@ -157,16 +157,16 @@
157 157 void upmconfig (uint upm, uint *table, uint size)
158 158 {
159 159 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
160   - volatile fsl_lbus_t *lbus = &immap->lbus;
  160 + volatile fsl_lbc_t *lbc = &immap->im_lbc;
161 161 volatile uchar *dummy = NULL;
162 162 const u32 msel = (upm + 4) << BR_MSEL_SHIFT; /* What the MSEL field in BRn should be */
163   - volatile u32 *mxmr = &lbus->mamr + upm; /* Pointer to mamr, mbmr, or mcmr */
  163 + volatile u32 *mxmr = &lbc->mamr + upm; /* ptr to mamr, mbmr, or mcmr */
164 164 uint i;
165 165  
166   - /* Scan all the banks to determine the base address of the device */
  166 + /* Find the address for the dummy write transaction */
167 167 for (i = 0; i < 8; i++) {
168   - if ((lbus->bank[i].br & BR_MSEL) == msel) {
169   - dummy = (uchar *) (lbus->bank[i].br & BR_BA);
  168 + if ((get_lbc_br(i) & BR_MSEL) == msel) {
  169 + dummy = (uchar *) (get_lbc_br(i) & BR_BA);
170 170 break;
171 171 }
172 172 }
... ... @@ -180,7 +180,7 @@
180 180 *mxmr = (*mxmr & 0xCFFFFFC0) | 0x10000000;
181 181  
182 182 for (i = 0; i < size; i++) {
183   - lbus->mdr = table[i];
  183 + lbc->mdr = table[i];
184 184 __asm__ __volatile__ ("sync");
185 185 *dummy = 0; /* Write the value to memory and increment MAD */
186 186 __asm__ __volatile__ ("sync");
arch/powerpc/cpu/mpc83xx/cpu_init.c
Diff comments   View file @ f51cdaf
... ... @@ -236,8 +236,8 @@
236 236 /* LCRR - Clock Ratio Register (10.3.1.16)
237 237 * write, read, and isync per MPC8379ERM rev.1 CLKDEV field description
238 238 */
239   - clrsetbits_be32(&im->lbus.lcrr, lcrr_mask, lcrr_val);
240   - __raw_readl(&im->lbus.lcrr);
  239 + clrsetbits_be32(&im->im_lbc.lcrr, lcrr_mask, lcrr_val);
  240 + __raw_readl(&im->im_lbc.lcrr);
241 241 isync();
242 242  
243 243 /* Enable Time Base & Decrementer ( so we will have udelay() )*/
244 244  
245 245  
246 246  
247 247  
248 248  
249 249  
250 250  
251 251  
252 252  
... ... @@ -267,79 +267,40 @@
267 267 /* Config QE ioports */
268 268 config_qe_ioports();
269 269 #endif
  270 + /* Set up preliminary BR/OR regs */
  271 + init_early_memctl_regs();
270 272  
271   - /*
272   - * Memory Controller:
273   - */
274   -
275   - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
276   - * addresses - these have to be modified later when FLASH size
277   - * has been determined
278   - */
279   -
280   -#if defined(CONFIG_SYS_BR0_PRELIM) \
281   - && defined(CONFIG_SYS_OR0_PRELIM) \
282   - && defined(CONFIG_SYS_LBLAWBAR0_PRELIM) \
283   - && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
284   - im->lbus.bank[0].br = CONFIG_SYS_BR0_PRELIM;
285   - im->lbus.bank[0].or = CONFIG_SYS_OR0_PRELIM;
  273 + /* Local Access window setup */
  274 +#if defined(CONFIG_SYS_LBLAWBAR0_PRELIM) && defined(CONFIG_SYS_LBLAWAR0_PRELIM)
286 275 im->sysconf.lblaw[0].bar = CONFIG_SYS_LBLAWBAR0_PRELIM;
287 276 im->sysconf.lblaw[0].ar = CONFIG_SYS_LBLAWAR0_PRELIM;
288 277 #else
289   -#error CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
  278 +#error CONFIG_SYS_LBLAWBAR0_PRELIM & CONFIG_SYS_LBLAWAR0_PRELIM must be defined
290 279 #endif
291 280  
292   -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
293   - im->lbus.bank[1].br = CONFIG_SYS_BR1_PRELIM;
294   - im->lbus.bank[1].or = CONFIG_SYS_OR1_PRELIM;
295   -#endif
296 281 #if defined(CONFIG_SYS_LBLAWBAR1_PRELIM) && defined(CONFIG_SYS_LBLAWAR1_PRELIM)
297 282 im->sysconf.lblaw[1].bar = CONFIG_SYS_LBLAWBAR1_PRELIM;
298 283 im->sysconf.lblaw[1].ar = CONFIG_SYS_LBLAWAR1_PRELIM;
299 284 #endif
300   -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
301   - im->lbus.bank[2].br = CONFIG_SYS_BR2_PRELIM;
302   - im->lbus.bank[2].or = CONFIG_SYS_OR2_PRELIM;
303   -#endif
304 285 #if defined(CONFIG_SYS_LBLAWBAR2_PRELIM) && defined(CONFIG_SYS_LBLAWAR2_PRELIM)
305 286 im->sysconf.lblaw[2].bar = CONFIG_SYS_LBLAWBAR2_PRELIM;
306 287 im->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2_PRELIM;
307 288 #endif
308   -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
309   - im->lbus.bank[3].br = CONFIG_SYS_BR3_PRELIM;
310   - im->lbus.bank[3].or = CONFIG_SYS_OR3_PRELIM;
311   -#endif
312 289 #if defined(CONFIG_SYS_LBLAWBAR3_PRELIM) && defined(CONFIG_SYS_LBLAWAR3_PRELIM)
313 290 im->sysconf.lblaw[3].bar = CONFIG_SYS_LBLAWBAR3_PRELIM;
314 291 im->sysconf.lblaw[3].ar = CONFIG_SYS_LBLAWAR3_PRELIM;
315 292 #endif
316   -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
317   - im->lbus.bank[4].br = CONFIG_SYS_BR4_PRELIM;
318   - im->lbus.bank[4].or = CONFIG_SYS_OR4_PRELIM;
319   -#endif
320 293 #if defined(CONFIG_SYS_LBLAWBAR4_PRELIM) && defined(CONFIG_SYS_LBLAWAR4_PRELIM)
321 294 im->sysconf.lblaw[4].bar = CONFIG_SYS_LBLAWBAR4_PRELIM;
322 295 im->sysconf.lblaw[4].ar = CONFIG_SYS_LBLAWAR4_PRELIM;
323 296 #endif
324   -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
325   - im->lbus.bank[5].br = CONFIG_SYS_BR5_PRELIM;
326   - im->lbus.bank[5].or = CONFIG_SYS_OR5_PRELIM;
327   -#endif
328 297 #if defined(CONFIG_SYS_LBLAWBAR5_PRELIM) && defined(CONFIG_SYS_LBLAWAR5_PRELIM)
329 298 im->sysconf.lblaw[5].bar = CONFIG_SYS_LBLAWBAR5_PRELIM;
330 299 im->sysconf.lblaw[5].ar = CONFIG_SYS_LBLAWAR5_PRELIM;
331 300 #endif
332   -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
333   - im->lbus.bank[6].br = CONFIG_SYS_BR6_PRELIM;
334   - im->lbus.bank[6].or = CONFIG_SYS_OR6_PRELIM;
335   -#endif
336 301 #if defined(CONFIG_SYS_LBLAWBAR6_PRELIM) && defined(CONFIG_SYS_LBLAWAR6_PRELIM)
337 302 im->sysconf.lblaw[6].bar = CONFIG_SYS_LBLAWBAR6_PRELIM;
338 303 im->sysconf.lblaw[6].ar = CONFIG_SYS_LBLAWAR6_PRELIM;
339   -#endif
340   -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
341   - im->lbus.bank[7].br = CONFIG_SYS_BR7_PRELIM;
342   - im->lbus.bank[7].or = CONFIG_SYS_OR7_PRELIM;
343 304 #endif
344 305 #if defined(CONFIG_SYS_LBLAWBAR7_PRELIM) && defined(CONFIG_SYS_LBLAWAR7_PRELIM)
345 306 im->sysconf.lblaw[7].bar = CONFIG_SYS_LBLAWBAR7_PRELIM;
arch/powerpc/cpu/mpc83xx/nand_init.c
Diff comments   View file @ f51cdaf
... ... @@ -88,8 +88,8 @@
88 88 && defined(CONFIG_SYS_NAND_OR_PRELIM) \
89 89 && defined(CONFIG_SYS_NAND_LBLAWBAR_PRELIM) \
90 90 && defined(CONFIG_SYS_NAND_LBLAWAR_PRELIM)
91   - im->lbus.bank[0].br = CONFIG_SYS_NAND_BR_PRELIM;
92   - im->lbus.bank[0].or = CONFIG_SYS_NAND_OR_PRELIM;
  91 + set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM);
  92 + set_lbc_or(0, CONFIG_SYS_NAND_OR_PRELIM);
93 93 im->sysconf.lblaw[0].bar = CONFIG_SYS_NAND_LBLAWBAR_PRELIM;
94 94 im->sysconf.lblaw[0].ar = CONFIG_SYS_NAND_LBLAWAR_PRELIM;
95 95 #else
arch/powerpc/cpu/mpc83xx/speed.c
Diff comments   View file @ f51cdaf
... ... @@ -393,7 +393,7 @@
393 393  
394 394 lbiu_clk = csb_clk *
395 395 (1 + ((im->reset.rcwl & HRCWL_LBIUCM) >> HRCWL_LBIUCM_SHIFT));
396   - lcrr = (im->lbus.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
  396 + lcrr = (im->im_lbc.lcrr & LCRR_CLKDIV) >> LCRR_CLKDIV_SHIFT;
397 397 switch (lcrr) {
398 398 case 2:
399 399 case 4:
arch/powerpc/cpu/mpc85xx/cpu.c
Diff comments   View file @ f51cdaf
... ... @@ -257,8 +257,7 @@
257 257 {
258 258 int i, mdr, mad, old_mad = 0;
259 259 volatile u32 *mxmr;
260   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
261   - volatile u32 *brp,*orp;
  260 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
262 261 volatile u8* dummy = NULL;
263 262 int upmmask;
264 263  
... ... @@ -281,12 +280,9 @@
281 280 }
282 281  
283 282 /* Find the address for the dummy write transaction */
284   - for (brp = &lbc->br0, orp = &lbc->or0, i = 0; i < 8;
285   - i++, brp += 2, orp += 2) {
286   -
287   - /* Look for a valid BR with selected UPM */
288   - if ((in_be32(brp) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
289   - dummy = (volatile u8*)(in_be32(brp) & BR_BA);
  283 + for (i = 0; i < 8; i++) {
  284 + if ((get_lbc_br(i) & (BR_V | BR_MSEL)) == (BR_V | upmmask)) {
  285 + dummy = (volatile u8 *)(get_lbc_br(i) & BR_BA);
290 286 break;
291 287 }
292 288 }
arch/powerpc/cpu/mpc85xx/cpu_init.c
Diff comments   View file @ f51cdaf
... ... @@ -154,7 +154,6 @@
154 154  
155 155 void cpu_init_f (void)
156 156 {
157   - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
158 157 extern void m8560_cpm_reset (void);
159 158 #ifdef CONFIG_MPC8548
160 159 ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
161 160  
... ... @@ -177,61 +176,8 @@
177 176 config_8560_ioports((ccsr_cpm_t *)CONFIG_SYS_MPC85xx_CPM_ADDR);
178 177 #endif
179 178  
180   - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
181   - * addresses - these have to be modified later when FLASH size
182   - * has been determined
183   - */
184   -#if defined(CONFIG_SYS_OR0_REMAP)
185   - out_be32(&memctl->or0, CONFIG_SYS_OR0_REMAP);
186   -#endif
187   -#if defined(CONFIG_SYS_OR1_REMAP)
188   - out_be32(&memctl->or1, CONFIG_SYS_OR1_REMAP);
189   -#endif
  179 + init_early_memctl_regs();
190 180  
191   - /* now restrict to preliminary range */
192   - /* if cs1 is already set via debugger, leave cs0/cs1 alone */
193   - if (! memctl->br1 & 1) {
194   -#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
195   - out_be32(&memctl->br0, CONFIG_SYS_BR0_PRELIM);
196   - out_be32(&memctl->or0, CONFIG_SYS_OR0_PRELIM);
197   -#endif
198   -
199   -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
200   - out_be32(&memctl->or1, CONFIG_SYS_OR1_PRELIM);
201   - out_be32(&memctl->br1, CONFIG_SYS_BR1_PRELIM);
202   -#endif
203   - }
204   -
205   -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
206   - out_be32(&memctl->or2, CONFIG_SYS_OR2_PRELIM);
207   - out_be32(&memctl->br2, CONFIG_SYS_BR2_PRELIM);
208   -#endif
209   -
210   -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
211   - out_be32(&memctl->or3, CONFIG_SYS_OR3_PRELIM);
212   - out_be32(&memctl->br3, CONFIG_SYS_BR3_PRELIM);
213   -#endif
214   -
215   -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
216   - out_be32(&memctl->or4, CONFIG_SYS_OR4_PRELIM);
217   - out_be32(&memctl->br4, CONFIG_SYS_BR4_PRELIM);
218   -#endif
219   -
220   -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
221   - out_be32(&memctl->or5, CONFIG_SYS_OR5_PRELIM);
222   - out_be32(&memctl->br5, CONFIG_SYS_BR5_PRELIM);
223   -#endif
224   -
225   -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
226   - out_be32(&memctl->or6, CONFIG_SYS_OR6_PRELIM);
227   - out_be32(&memctl->br6, CONFIG_SYS_BR6_PRELIM);
228   -#endif
229   -
230   -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
231   - out_be32(&memctl->or7, CONFIG_SYS_OR7_PRELIM);
232   - out_be32(&memctl->br7, CONFIG_SYS_BR7_PRELIM);
233   -#endif
234   -
235 181 #if defined(CONFIG_CPM2)
236 182 m8560_cpm_reset();
237 183 #endif
... ... @@ -263,7 +209,7 @@
263 209 int cpu_init_r(void)
264 210 {
265 211 #ifdef CONFIG_SYS_LBC_LCRR
266   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  212 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
267 213 #endif
268 214  
269 215 puts ("L2: ");
arch/powerpc/cpu/mpc85xx/cpu_init_nand.c
Diff comments   View file @ f51cdaf
... ... @@ -25,7 +25,7 @@
25 25  
26 26 void cpu_init_f(void)
27 27 {
28   - ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  28 + fsl_lbc_t *lbc = LBC_BASE_ADDR;
29 29  
30 30 /*
31 31 * LCRR - Clock Ratio Register - set up local bus timing
... ... @@ -34,8 +34,8 @@
34 34 out_be32(&lbc->lcrr, LCRR_DBYP | LCRR_CLKDIV_8);
35 35  
36 36 #if defined(CONFIG_NAND_BR_PRELIM) && defined(CONFIG_NAND_OR_PRELIM)
37   - out_be32(&lbc->br0, CONFIG_NAND_BR_PRELIM);
38   - out_be32(&lbc->or0, CONFIG_NAND_OR_PRELIM);
  37 + set_lbc_br(0, CONFIG_NAND_BR_PRELIM);
  38 + set_lbc_or(0, CONFIG_NAND_OR_PRELIM);
39 39 #else
40 40 #error CONFIG_NAND_BR_PRELIM, CONFIG_NAND_OR_PRELIM must be defined
41 41 #endif
arch/powerpc/cpu/mpc85xx/speed.c
Diff comments   View file @ f51cdaf
... ... @@ -172,10 +172,7 @@
172 172 /* We will program LCRR to this value later */
173 173 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
174 174 #else
175   - {
176   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
177   - lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
178   - }
  175 + lcrr_div = in_be32(&(LBC_BASE_ADDR)->lcrr) & LCRR_CLKDIV;
179 176 #endif
180 177 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
181 178 #if defined(CONFIG_FSL_CORENET)
arch/powerpc/cpu/mpc86xx/cpu.c
Diff comments   View file @ f51cdaf
... ... @@ -180,22 +180,9 @@
180 180 */
181 181 void mpc86xx_reginfo(void)
182 182 {
183   - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
184   - ccsr_lbc_t *lbc = &immap->im_lbc;
185   -
186 183 print_bats();
187 184 print_laws();
188   -
189   - printf ("Local Bus Controller Registers\n"
190   - "\tBR0\t0x%08X\tOR0\t0x%08X \n", in_be32(&lbc->br0), in_be32(&lbc->or0));
191   - printf("\tBR1\t0x%08X\tOR1\t0x%08X \n", in_be32(&lbc->br1), in_be32(&lbc->or1));
192   - printf("\tBR2\t0x%08X\tOR2\t0x%08X \n", in_be32(&lbc->br2), in_be32(&lbc->or2));
193   - printf("\tBR3\t0x%08X\tOR3\t0x%08X \n", in_be32(&lbc->br3), in_be32(&lbc->or3));
194   - printf("\tBR4\t0x%08X\tOR4\t0x%08X \n", in_be32(&lbc->br4), in_be32(&lbc->or4));
195   - printf("\tBR5\t0x%08X\tOR5\t0x%08X \n", in_be32(&lbc->br5), in_be32(&lbc->or5));
196   - printf("\tBR6\t0x%08X\tOR6\t0x%08X \n", in_be32(&lbc->br6), in_be32(&lbc->or6));
197   - printf("\tBR7\t0x%08X\tOR7\t0x%08X \n", in_be32(&lbc->br7), in_be32(&lbc->or7));
198   -
  185 + print_lbc_regs();
199 186 }
200 187  
201 188 /*
arch/powerpc/cpu/mpc86xx/cpu_init.c
Diff comments   View file @ f51cdaf
... ... @@ -46,9 +46,6 @@
46 46  
47 47 void cpu_init_f(void)
48 48 {
49   - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
50   - volatile ccsr_lbc_t *memctl = &immap->im_lbc;
51   -
52 49 /* Pointer is writable since we allocated a register for it */
53 50 gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
54 51  
55 52  
... ... @@ -61,58 +58,8 @@
61 58  
62 59 setup_bats();
63 60  
64   - /* Map banks 0 and 1 to the FLASH banks 0 and 1 at preliminary
65   - * addresses - these have to be modified later when FLASH size
66   - * has been determined
67   - */
  61 + init_early_memctl_regs();
68 62  
69   -#if defined(CONFIG_SYS_OR0_REMAP)
70   - memctl->or0 = CONFIG_SYS_OR0_REMAP;
71   -#endif
72   -#if defined(CONFIG_SYS_OR1_REMAP)
73   - memctl->or1 = CONFIG_SYS_OR1_REMAP;
74   -#endif
75   -
76   - /* now restrict to preliminary range */
77   -#if defined(CONFIG_SYS_BR0_PRELIM) && defined(CONFIG_SYS_OR0_PRELIM)
78   - memctl->br0 = CONFIG_SYS_BR0_PRELIM;
79   - memctl->or0 = CONFIG_SYS_OR0_PRELIM;
80   -#endif
81   -
82   -#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
83   - memctl->or1 = CONFIG_SYS_OR1_PRELIM;
84   - memctl->br1 = CONFIG_SYS_BR1_PRELIM;
85   -#endif
86   -
87   -#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
88   - memctl->or2 = CONFIG_SYS_OR2_PRELIM;
89   - memctl->br2 = CONFIG_SYS_BR2_PRELIM;
90   -#endif
91   -
92   -#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
93   - memctl->or3 = CONFIG_SYS_OR3_PRELIM;
94   - memctl->br3 = CONFIG_SYS_BR3_PRELIM;
95   -#endif
96   -
97   -#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
98   - memctl->or4 = CONFIG_SYS_OR4_PRELIM;
99   - memctl->br4 = CONFIG_SYS_BR4_PRELIM;
100   -#endif
101   -
102   -#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
103   - memctl->or5 = CONFIG_SYS_OR5_PRELIM;
104   - memctl->br5 = CONFIG_SYS_BR5_PRELIM;
105   -#endif
106   -
107   -#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
108   - memctl->or6 = CONFIG_SYS_OR6_PRELIM;
109   - memctl->br6 = CONFIG_SYS_BR6_PRELIM;
110   -#endif
111   -
112   -#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
113   - memctl->or7 = CONFIG_SYS_OR7_PRELIM;
114   - memctl->br7 = CONFIG_SYS_BR7_PRELIM;
115   -#endif
116 63 #if defined(CONFIG_FSL_DMA)
117 64 dma_init();
118 65 #endif
arch/powerpc/cpu/mpc86xx/speed.c
Diff comments   View file @ f51cdaf
... ... @@ -97,10 +97,7 @@
97 97 /* We will program LCRR to this value later */
98 98 lcrr_div = CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV;
99 99 #else
100   - {
101   - volatile ccsr_lbc_t *lbc = &immap->im_lbc;
102   - lcrr_div = in_be32(&lbc->lcrr) & LCRR_CLKDIV;
103   - }
  100 + lcrr_div = in_be32(&immap->im_lbc.lcrr) & LCRR_CLKDIV;
104 101 #endif
105 102 if (lcrr_div == 2 || lcrr_div == 4 || lcrr_div == 8) {
106 103 sysInfo->freqLocalBus = sysInfo->freqSystemBus / (lcrr_div * 2);
arch/powerpc/cpu/mpc8xxx/Makefile
Diff comments   View file @ f51cdaf
... ... @@ -16,6 +16,7 @@
16 16 endif
17 17  
18 18 COBJS-$(CONFIG_OF_LIBFDT) += fdt.o
  19 +COBJS-$(CONFIG_FSL_LBC) += fsl_lbc.o
19 20  
20 21 SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
21 22 OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
arch/powerpc/cpu/mpc8xxx/fsl_lbc.c
Diff comments   View file @ f51cdaf
  1 +/*
  2 + * Copyright 2010 Freescale Semiconductor, Inc.
  3 + *
  4 + * This program is free software; you can redistribute it and/or
  5 + * modify it under the terms of the GNU General Public License
  6 + * Version 2 as published by the Free Software Foundation.
  7 + */
  8 +
  9 +#include <common.h>
  10 +#include <asm/fsl_lbc.h>
  11 +
  12 +void print_lbc_regs(void)
  13 +{
  14 + int i;
  15 +
  16 + printf("\nLocal Bus Controller Registers\n");
  17 + for (i = 0; i < 8; i++) {
  18 + printf("BR%d\t0x%08X\tOR%d\t0x%08X\n",
  19 + i, get_lbc_br(i), i, get_lbc_or(i));
  20 + }
  21 +}
  22 +
  23 +void init_early_memctl_regs(void)
  24 +{
  25 + uint init_br1 = 1;
  26 +
  27 +#ifdef CONFIG_MPC85xx
  28 + /* if cs1 is already set via debugger, leave cs0/cs1 alone */
  29 + if (get_lbc_br(1) & BR_V)
  30 + init_br1 = 0;
  31 +#endif
  32 +
  33 + /*
  34 + * Map banks 0 (and maybe 1) to the FLASH banks 0 (and 1) at
  35 + * preliminary addresses - these have to be modified later
  36 + * when FLASH size has been determined
  37 + */
  38 +#if defined(CONFIG_SYS_OR0_REMAP)
  39 + set_lbc_or(0, CONFIG_SYS_OR0_REMAP);
  40 +#endif
  41 +#if defined(CONFIG_SYS_OR1_REMAP)
  42 + set_lbc_or(1, CONFIG_SYS_OR1_REMAP);
  43 +#endif
  44 + /* now restrict to preliminary range */
  45 + if (init_br1) {
  46 + set_lbc_br(0, CONFIG_SYS_BR0_PRELIM);
  47 + set_lbc_or(0, CONFIG_SYS_OR0_PRELIM);
  48 +
  49 +#if defined(CONFIG_SYS_BR1_PRELIM) && defined(CONFIG_SYS_OR1_PRELIM)
  50 + set_lbc_or(1, CONFIG_SYS_OR1_PRELIM);
  51 + set_lbc_br(1, CONFIG_SYS_BR1_PRELIM);
  52 +#endif
  53 + }
  54 +
  55 +#if defined(CONFIG_SYS_BR2_PRELIM) && defined(CONFIG_SYS_OR2_PRELIM)
  56 + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  57 + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
  58 +#endif
  59 +
  60 +#if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
  61 + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
  62 + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
  63 +#endif
  64 +
  65 +#if defined(CONFIG_SYS_BR4_PRELIM) && defined(CONFIG_SYS_OR4_PRELIM)
  66 + set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
  67 + set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
  68 +#endif
  69 +
  70 +#if defined(CONFIG_SYS_BR5_PRELIM) && defined(CONFIG_SYS_OR5_PRELIM)
  71 + set_lbc_or(5, CONFIG_SYS_OR5_PRELIM);
  72 + set_lbc_br(5, CONFIG_SYS_BR5_PRELIM);
  73 +#endif
  74 +
  75 +#if defined(CONFIG_SYS_BR6_PRELIM) && defined(CONFIG_SYS_OR6_PRELIM)
  76 + set_lbc_or(6, CONFIG_SYS_OR6_PRELIM);
  77 + set_lbc_br(6, CONFIG_SYS_BR6_PRELIM);
  78 +#endif
  79 +
  80 +#if defined(CONFIG_SYS_BR7_PRELIM) && defined(CONFIG_SYS_OR7_PRELIM)
  81 + set_lbc_or(7, CONFIG_SYS_OR7_PRELIM);
  82 + set_lbc_br(7, CONFIG_SYS_BR7_PRELIM);
  83 +#endif
  84 +}
arch/powerpc/include/asm/config.h
Diff comments   View file @ f51cdaf
... ... @@ -85,5 +85,11 @@
85 85 /* Relocation to SDRAM works on all PPC boards */
86 86 #define CONFIG_RELOC_FIXUP_WORKS
87 87  
  88 +/* Since so many PPC SOCs have a semi-common LBC, define this here */
  89 +#if defined(CONFIG_MPC85xx) || defined(CONFIG_MPC86xx) || \
  90 + defined(CONFIG_MPC83xx)
  91 +#define CONFIG_FSL_LBC
  92 +#endif
  93 +
88 94 #endif /* _ASM_CONFIG_H_ */
arch/powerpc/include/asm/fsl_lbc.h
Diff comments   View file @ f51cdaf
... ... @@ -14,6 +14,7 @@
14 14 #define __ASM_PPC_FSL_LBC_H
15 15  
16 16 #include <config.h>
  17 +#include <common.h>
17 18  
18 19 /* BR - Base Registers
19 20 */
20 21  
21 22  
... ... @@ -453,50 +454,70 @@
453 454 #define LTESR_CC 0x00000001
454 455  
455 456 #ifndef __ASSEMBLY__
456   -/*
457   - * Local Bus Controller Registers.
458   - */
459   -typedef struct lbus_bank {
460   - u32 br; /* Base Register */
461   - u32 or; /* Option Register */
462   -} lbus_bank_t;
  457 +#include <asm/io.h>
463 458  
464   -typedef struct fsl_lbus {
465   - lbus_bank_t bank[8];
466   - u8 res0[0x28];
467   - u32 mar; /* UPM Address Register */
468   - u8 res1[0x4];
469   - u32 mamr; /* UPMA Mode Register */
470   - u32 mbmr; /* UPMB Mode Register */
471   - u32 mcmr; /* UPMC Mode Register */
472   - u8 res2[0x8];
473   - u32 mrtpr; /* Memory Refresh Timer Prescaler Register */
474   - u32 mdr; /* UPM Data Register */
475   - u8 res3[0x4];
476   - u32 lsor; /* Special Operation Initiation Register */
477   - u32 lsdmr; /* SDRAM Mode Register */
478   - u8 res4[0x8];
479   - u32 lurt; /* UPM Refresh Timer */
480   - u32 lsrt; /* SDRAM Refresh Timer */
481   - u8 res5[0x8];
482   - u32 ltesr; /* Transfer Error Status Register */
483   - u32 ltedr; /* Transfer Error Disable Register */
484   - u32 lteir; /* Transfer Error Interrupt Register */
485   - u32 lteatr; /* Transfer Error Attributes Register */
486   - u32 ltear; /* Transfer Error Address Register */
487   - u8 res6[0xC];
488   - u32 lbcr; /* Configuration Register */
489   - u32 lcrr; /* Clock Ratio Register */
490   - u8 res7[0x8];
491   - u32 fmr; /* Flash Mode Register */
492   - u32 fir; /* Flash Instruction Register */
493   - u32 fcr; /* Flash Command Register */
494   - u32 fbar; /* Flash Block Addr Register */
495   - u32 fpar; /* Flash Page Addr Register */
496   - u32 fbcr; /* Flash Byte Count Register */
497   - u8 res8[0xF08];
498   -} fsl_lbus_t;
499   -#endif /* __ASSEMBLY__ */
  459 +extern void print_lbc_regs(void);
  460 +extern void init_early_memctl_regs(void);
500 461  
  462 +#define LBC_BASE_ADDR ((fsl_lbc_t *)CONFIG_SYS_LBC_ADDR)
  463 +#define get_lbc_br(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].br))
  464 +#define get_lbc_or(i) (in_be32(&(LBC_BASE_ADDR)->bank[i].or))
  465 +#define set_lbc_br(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].br, v))
  466 +#define set_lbc_or(i, v) (out_be32(&(LBC_BASE_ADDR)->bank[i].or, v))
  467 +
  468 +typedef struct lbc_bank {
  469 + u32 br;
  470 + u32 or;
  471 +} lbc_bank_t;
  472 +
  473 +/* Local Bus Controller Registers */
  474 +typedef struct fsl_lbc {
  475 + lbc_bank_t bank[8];
  476 + u8 res1[40];
  477 + u32 mar; /* LBC UPM Addr */
  478 + u8 res2[4];
  479 + u32 mamr; /* LBC UPMA Mode */
  480 + u32 mbmr; /* LBC UPMB Mode */
  481 + u32 mcmr; /* LBC UPMC Mode */
  482 + u8 res3[8];
  483 + u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
  484 + u32 mdr; /* LBC UPM Data */
  485 +#ifdef CONFIG_FSL_ELBC
  486 + u8 res4[4];
  487 + u32 lsor;
  488 + u8 res5[12];
  489 + u32 lurt; /* LBC UPM Refresh Timer */
  490 + u8 res6[4];
  491 +#else
  492 + u8 res4[8];
  493 + u32 lsdmr; /* LBC SDRAM Mode */
  494 + u8 res5[8];
  495 + u32 lurt; /* LBC UPM Refresh Timer */
  496 + u32 lsrt; /* LBC SDRAM Refresh Timer */
  497 +#endif
  498 + u8 res7[8];
  499 + u32 ltesr; /* LBC Transfer Error Status */
  500 + u32 ltedr; /* LBC Transfer Error Disable */
  501 + u32 lteir; /* LBC Transfer Error IRQ */
  502 + u32 lteatr; /* LBC Transfer Error Attrs */
  503 + u32 ltear; /* LBC Transfer Error Addr */
  504 + u8 res8[12];
  505 + u32 lbcr; /* LBC Configuration */
  506 + u32 lcrr; /* LBC Clock Ratio */
  507 +#ifdef CONFIG_NAND_FSL_ELBC
  508 + u8 res9[0x8];
  509 + u32 fmr; /* Flash Mode Register */
  510 + u32 fir; /* Flash Instruction Register */
  511 + u32 fcr; /* Flash Command Register */
  512 + u32 fbar; /* Flash Block Addr Register */
  513 + u32 fpar; /* Flash Page Addr Register */
  514 + u32 fbcr; /* Flash Byte Count Register */
  515 + u8 res10[0xF08];
  516 +#else
  517 + u8 res9[0xF28];
  518 +#endif
  519 +} fsl_lbc_t;
  520 +
  521 +#endif /* __ASSEMBLY__ */
501 522 #endif /* __ASM_PPC_FSL_LBC_H */
arch/powerpc/include/asm/immap_83xx.h
Diff comments   View file @ f51cdaf
... ... @@ -646,7 +646,7 @@
646 646 u8 res2[0x1300];
647 647 duart83xx_t duart[2]; /* DUART */
648 648 u8 res3[0x900];
649   - fsl_lbus_t lbus; /* Local Bus Controller Registers */
  649 + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
650 650 u8 res4[0x1000];
651 651 spi8xxx_t spi; /* Serial Peripheral Interface */
652 652 dma83xx_t dma; /* DMA */
... ... @@ -686,7 +686,7 @@
686 686 u8 res1[0x1300];
687 687 duart83xx_t duart[2]; /* DUART */
688 688 u8 res2[0x900];
689   - fsl_lbus_t lbus; /* Local Bus Controller Registers */
  689 + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
690 690 u8 res3[0x1000];
691 691 spi8xxx_t spi; /* Serial Peripheral Interface */
692 692 dma83xx_t dma; /* DMA */
... ... @@ -721,7 +721,7 @@
721 721 u8 res1[0x1300];
722 722 duart83xx_t duart[2]; /* DUART */
723 723 u8 res2[0x900];
724   - fsl_lbus_t lbus; /* Local Bus Controller Registers */
  724 + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
725 725 u8 res3[0x1000];
726 726 spi8xxx_t spi; /* Serial Peripheral Interface */
727 727 dma83xx_t dma; /* DMA */
... ... @@ -766,7 +766,7 @@
766 766 u8 res1[0x1300];
767 767 duart83xx_t duart[2]; /* DUART */
768 768 u8 res2[0x900];
769   - fsl_lbus_t lbus; /* Local Bus Controller Registers */
  769 + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
770 770 u8 res3[0x1000];
771 771 spi8xxx_t spi; /* Serial Peripheral Interface */
772 772 dma83xx_t dma; /* DMA */
... ... @@ -816,7 +816,7 @@
816 816 u8 res4[0x1300];
817 817 duart83xx_t duart[2]; /* DUART */
818 818 u8 res5[0x900];
819   - fsl_lbus_t lbus; /* Local Bus Controller Registers */
  819 + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
820 820 u8 res6[0x2000];
821 821 dma83xx_t dma; /* DMA */
822 822 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
... ... @@ -855,7 +855,7 @@
855 855 u8 res3[0x1300];
856 856 duart83xx_t duart[2]; /* DUART */
857 857 u8 res4[0x900];
858   - fsl_lbus_t lbus; /* Local Bus Controller Registers */
  858 + fsl_lbc_t im_lbc; /* Local Bus Controller Regs */
859 859 u8 res5[0x2000];
860 860 dma83xx_t dma; /* DMA */
861 861 pciconf83xx_t pci_conf[1]; /* PCI Software Configuration Registers */
... ... @@ -879,6 +879,7 @@
879 879 #endif
880 880 #define CONFIG_SYS_MPC83xx_USB_ADDR \
881 881 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_USB_OFFSET)
  882 +#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
882 883  
883 884 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
884 885 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
arch/powerpc/include/asm/immap_85xx.h
Diff comments   View file @ f51cdaf
... ... @@ -266,50 +266,6 @@
266 266 } ccsr_duart_t;
267 267 #endif
268 268  
269   -/* Local Bus Controller Registers */
270   -typedef struct ccsr_lbc {
271   - u32 br0; /* LBC Base 0 */
272   - u32 or0; /* LBC Options 0 */
273   - u32 br1; /* LBC Base 1 */
274   - u32 or1; /* LBC Options 1 */
275   - u32 br2; /* LBC Base 2 */
276   - u32 or2; /* LBC Options 2 */
277   - u32 br3; /* LBC Base 3 */
278   - u32 or3; /* LBC Options 3 */
279   - u32 br4; /* LBC Base 4 */
280   - u32 or4; /* LBC Options 4 */
281   - u32 br5; /* LBC Base 5 */
282   - u32 or5; /* LBC Options 5 */
283   - u32 br6; /* LBC Base 6 */
284   - u32 or6; /* LBC Options 6 */
285   - u32 br7; /* LBC Base 7 */
286   - u32 or7; /* LBC Options 7 */
287   - u8 res1[40];
288   - u32 mar; /* LBC UPM Addr */
289   - u8 res2[4];
290   - u32 mamr; /* LBC UPMA Mode */
291   - u32 mbmr; /* LBC UPMB Mode */
292   - u32 mcmr; /* LBC UPMC Mode */
293   - u8 res3[8];
294   - u32 mrtpr; /* LBC Memory Refresh Timer Prescaler */
295   - u32 mdr; /* LBC UPM Data */
296   - u8 res4[8];
297   - u32 lsdmr; /* LBC SDRAM Mode */
298   - u8 res5[8];
299   - u32 lurt; /* LBC UPM Refresh Timer */
300   - u32 lsrt; /* LBC SDRAM Refresh Timer */
301   - u8 res6[8];
302   - u32 ltesr; /* LBC Transfer Error Status */
303   - u32 ltedr; /* LBC Transfer Error Disable */
304   - u32 lteir; /* LBC Transfer Error IRQ */
305   - u32 lteatr; /* LBC Transfer Error Attrs */
306   - u32 ltear; /* LBC Transfer Error Addr */
307   - u8 res7[12];
308   - u32 lbcr; /* LBC Configuration */
309   - u32 lcrr; /* LBC Clock Ratio */
310   - u8 res8[3880];
311   -} ccsr_lbc_t;
312   -
313 269 /* eSPI Registers */
314 270 typedef struct ccsr_espi {
315 271 u32 mode; /* eSPI mode */
... ... @@ -2147,7 +2103,7 @@
2147 2103 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
2148 2104 #define CONFIG_SYS_MPC85xx_DDR2_ADDR \
2149 2105 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
2150   -#define CONFIG_SYS_MPC85xx_LBC_ADDR \
  2106 +#define CONFIG_SYS_LBC_ADDR \
2151 2107 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
2152 2108 #define CONFIG_SYS_MPC85xx_ESPI_ADDR \
2153 2109 (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET)
arch/powerpc/include/asm/immap_86xx.h
Diff comments   View file @ f51cdaf
... ... @@ -12,6 +12,7 @@
12 12  
13 13 #include <asm/types.h>
14 14 #include <asm/fsl_dma.h>
  15 +#include <asm/fsl_lbc.h>
15 16 #include <asm/fsl_i2c.h>
16 17  
17 18 /* Local-Access Registers and MCM Registers(0x0000-0x2000) */
... ... @@ -190,51 +191,6 @@
190 191 char res5[2543];
191 192 } ccsr_duart_t;
192 193  
193   -
194   -/* Local Bus Controller Registers(0x5000-0x6000) */
195   -typedef struct ccsr_lbc {
196   - uint br0; /* 0x5000 - LBC Base Register 0 */
197   - uint or0; /* 0x5004 - LBC Options Register 0 */
198   - uint br1; /* 0x5008 - LBC Base Register 1 */
199   - uint or1; /* 0x500c - LBC Options Register 1 */
200   - uint br2; /* 0x5010 - LBC Base Register 2 */
201   - uint or2; /* 0x5014 - LBC Options Register 2 */
202   - uint br3; /* 0x5018 - LBC Base Register 3 */
203   - uint or3; /* 0x501c - LBC Options Register 3 */
204   - uint br4; /* 0x5020 - LBC Base Register 4 */
205   - uint or4; /* 0x5024 - LBC Options Register 4 */
206   - uint br5; /* 0x5028 - LBC Base Register 5 */
207   - uint or5; /* 0x502c - LBC Options Register 5 */
208   - uint br6; /* 0x5030 - LBC Base Register 6 */
209   - uint or6; /* 0x5034 - LBC Options Register 6 */
210   - uint br7; /* 0x5038 - LBC Base Register 7 */
211   - uint or7; /* 0x503c - LBC Options Register 7 */
212   - char res1[40];
213   - uint mar; /* 0x5068 - LBC UPM Address Register */
214   - char res2[4];
215   - uint mamr; /* 0x5070 - LBC UPMA Mode Register */
216   - uint mbmr; /* 0x5074 - LBC UPMB Mode Register */
217   - uint mcmr; /* 0x5078 - LBC UPMC Mode Register */
218   - char res3[8];
219   - uint mrtpr; /* 0x5084 - LBC Memory Refresh Timer Prescaler Register */
220   - uint mdr; /* 0x5088 - LBC UPM Data Register */
221   - char res4[8];
222   - uint lsdmr; /* 0x5094 - LBC SDRAM Mode Register */
223   - char res5[8];
224   - uint lurt; /* 0x50a0 - LBC UPM Refresh Timer */
225   - uint lsrt; /* 0x50a4 - LBC SDRAM Refresh Timer */
226   - char res6[8];
227   - uint ltesr; /* 0x50b0 - LBC Transfer Error Status Register */
228   - uint ltedr; /* 0x50b4 - LBC Transfer Error Disable Register */
229   - uint lteir; /* 0x50b8 - LBC Transfer Error Interrupt Register */
230   - uint lteatr; /* 0x50bc - LBC Transfer Error Attributes Register */
231   - uint ltear; /* 0x50c0 - LBC Transfer Error Address Register */
232   - char res7[12];
233   - uint lbcr; /* 0x50d0 - LBC Configuration Register */
234   - uint lcrr; /* 0x50d4 - LBC Clock Ratio Register */
235   - char res8[3880];
236   -} ccsr_lbc_t;
237   -
238 194 /* PCI Express Registers(0x8000-0x9000) and (0x9000-0xA000) */
239 195 typedef struct ccsr_pex {
240 196 uint cfg_addr; /* 0x8000 - PEX Configuration Address Register */
... ... @@ -1270,7 +1226,7 @@
1270 1226 ccsr_ddr_t im_ddr1;
1271 1227 ccsr_i2c_t im_i2c;
1272 1228 ccsr_duart_t im_duart;
1273   - ccsr_lbc_t im_lbc;
  1229 + fsl_lbc_t im_lbc;
1274 1230 ccsr_ddr_t im_ddr2;
1275 1231 char res1[4096];
1276 1232 ccsr_pex_t im_pex1;
... ... @@ -1303,6 +1259,7 @@
1303 1259  
1304 1260 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
1305 1261 #define CONFIG_SYS_MDIO1_OFFSET 0x24000
  1262 +#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
1306 1263  
1307 1264 #define TSEC_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_TSEC1_OFFSET)
1308 1265 #define MDIO_BASE_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MDIO1_OFFSET)
board/atum8548/atum8548.c
Diff comments   View file @ f51cdaf
... ... @@ -47,7 +47,7 @@
47 47 int checkboard (void)
48 48 {
49 49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
50   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  50 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
51 51 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
52 52  
53 53 if ((uint)&gur->porpllsr != 0xe00e0000) {
board/esd/vme8349/vme8349.c
Diff comments   View file @ f51cdaf
... ... @@ -105,7 +105,7 @@
105 105 {
106 106 immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
107 107  
108   - clrsetbits_be32(&im->lbus.lcrr, LBCR_LDIS, 0);
  108 + clrsetbits_be32(&im->im_lbc.lcrr, LBCR_LDIS, 0);
109 109  
110 110 return 0;
111 111 }
board/freescale/mpc8313erdb/sdram.c
Diff comments   View file @ f51cdaf
... ... @@ -110,7 +110,7 @@
110 110 phys_size_t initdram(int board_type)
111 111 {
112 112 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
113   - volatile fsl_lbus_t *lbc = &im->lbus;
  113 + volatile fsl_lbc_t *lbc = &im->im_lbc;
114 114 u32 msize;
115 115  
116 116 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
board/freescale/mpc8349emds/mpc8349emds.c
Diff comments   View file @ f51cdaf
... ... @@ -192,7 +192,7 @@
192 192 void sdram_init(void)
193 193 {
194 194 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
195   - volatile fsl_lbus_t *lbc = &immap->lbus;
  195 + volatile fsl_lbc_t *lbc = &immap->im_lbc;
196 196 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
197 197  
198 198 /*
board/freescale/mpc8349itx/mpc8349itx.c
Diff comments   View file @ f51cdaf
... ... @@ -221,15 +221,14 @@
221 221 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
222 222 };
223 223 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
224   - volatile fsl_lbus_t *lbus = &immap->lbus;
225 224  
226   - lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
227   - lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
  225 + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
  226 + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
228 227  
229 228 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
230 229 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
231 230 */
232   - lbus->mamr = 0x08404440;
  231 + immap->im_lbc.mamr = 0x08404440;
233 232  
234 233 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
235 234  
board/freescale/mpc8360emds/mpc8360emds.c
Diff comments   View file @ f51cdaf
... ... @@ -280,7 +280,7 @@
280 280 static int sdram_init(unsigned int base)
281 281 {
282 282 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
283   - volatile fsl_lbus_t *lbc = &immap->lbus;
  283 + fsl_lbc_t *lbc = LBC_BASE_ADDR;
284 284 const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
285 285 int rem = base % sdram_size;
286 286 uint *sdram_addr;
... ... @@ -293,8 +293,8 @@
293 293 /*
294 294 * Setup SDRAM Base and Option Registers
295 295 */
296   - immap->lbus.bank[2].br = base | CONFIG_SYS_BR2;
297   - immap->lbus.bank[2].or = CONFIG_SYS_OR2;
  296 + set_lbc_br(2, base | CONFIG_SYS_BR2);
  297 + set_lbc_or(2, CONFIG_SYS_OR2);
298 298 immap->sysconf.lblaw[2].bar = base;
299 299 immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
300 300  
board/freescale/mpc8360erdk/nand.c
Diff comments   View file @ f51cdaf
... ... @@ -82,9 +82,9 @@
82 82  
83 83 int board_nand_init(struct nand_chip *nand)
84 84 {
85   - fun.upm.mxmr = &im->lbus.mamr;
86   - fun.upm.mdr = &im->lbus.mdr;
87   - fun.upm.mar = &im->lbus.mar;
  85 + fun.upm.mxmr = &im->im_lbc.mamr;
  86 + fun.upm.mdr = &im->im_lbc.mdr;
  87 + fun.upm.mar = &im->im_lbc.mar;
88 88  
89 89 upm_setup(&fun.upm);
90 90  
board/freescale/mpc8540ads/mpc8540ads.c
Diff comments   View file @ f51cdaf
... ... @@ -117,7 +117,7 @@
117 117 local_bus_init(void)
118 118 {
119 119 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
120   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  120 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
121 121  
122 122 uint clkdiv;
123 123 uint lbc_hz;
... ... @@ -176,7 +176,7 @@
176 176 void
177 177 sdram_init(void)
178 178 {
179   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  179 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
180 180 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
181 181  
182 182 puts(" SDRAM: ");
... ... @@ -185,8 +185,8 @@
185 185 /*
186 186 * Setup SDRAM Base and Option Registers
187 187 */
188   - lbc->or2 = CONFIG_SYS_OR2_PRELIM;
189   - lbc->br2 = CONFIG_SYS_BR2_PRELIM;
  188 + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  189 + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
190 190 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
191 191 asm("msync");
192 192  
board/freescale/mpc8541cds/mpc8541cds.c
Diff comments   View file @ f51cdaf
... ... @@ -291,7 +291,7 @@
291 291 local_bus_init(void)
292 292 {
293 293 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
294   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  294 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
295 295  
296 296 uint clkdiv;
297 297 uint lbc_hz;
... ... @@ -340,7 +340,7 @@
340 340 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
341 341  
342 342 uint idx;
343   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  343 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
344 344 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
345 345 uint cpu_board_rev;
346 346 uint lsdmr_common;
347 347  
... ... @@ -352,15 +352,10 @@
352 352 /*
353 353 * Setup SDRAM Base and Option Registers
354 354 */
355   - lbc->or2 = CONFIG_SYS_OR2_PRELIM;
356   - asm("msync");
357   -
358   - lbc->br2 = CONFIG_SYS_BR2_PRELIM;
359   - asm("msync");
360   -
  355 + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  356 + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
361 357 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
362 358 asm("msync");
363   -
364 359  
365 360 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
366 361 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
board/freescale/mpc8544ds/mpc8544ds.c
Diff comments   View file @ f51cdaf
... ... @@ -40,7 +40,7 @@
40 40 int checkboard (void)
41 41 {
42 42 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
43   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  43 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
44 44 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
45 45 u8 vboot;
46 46 u8 *pixis_base = (u8 *)PIXIS_BASE;
board/freescale/mpc8548cds/mpc8548cds.c
Diff comments   View file @ f51cdaf
... ... @@ -118,7 +118,7 @@
118 118 local_bus_init(void)
119 119 {
120 120 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
121   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  121 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
122 122  
123 123 uint clkdiv;
124 124 uint lbc_hz;
... ... @@ -154,7 +154,7 @@
154 154 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
155 155  
156 156 uint idx;
157   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  157 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
158 158 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
159 159 uint cpu_board_rev;
160 160 uint lsdmr_common;
161 161  
... ... @@ -166,15 +166,10 @@
166 166 /*
167 167 * Setup SDRAM Base and Option Registers
168 168 */
169   - lbc->or2 = CONFIG_SYS_OR2_PRELIM;
170   - asm("msync");
171   -
172   - lbc->br2 = CONFIG_SYS_BR2_PRELIM;
173   - asm("msync");
174   -
  169 + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  170 + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
175 171 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
176 172 asm("msync");
177   -
178 173  
179 174 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
180 175 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
board/freescale/mpc8555cds/mpc8555cds.c
Diff comments   View file @ f51cdaf
... ... @@ -291,7 +291,7 @@
291 291 local_bus_init(void)
292 292 {
293 293 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
294   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  294 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
295 295  
296 296 uint clkdiv;
297 297 uint lbc_hz;
... ... @@ -340,7 +340,7 @@
340 340 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
341 341  
342 342 uint idx;
343   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  343 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
344 344 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
345 345 uint cpu_board_rev;
346 346 uint lsdmr_common;
... ... @@ -352,12 +352,8 @@
352 352 /*
353 353 * Setup SDRAM Base and Option Registers
354 354 */
355   - lbc->or2 = CONFIG_SYS_OR2_PRELIM;
356   - asm("msync");
357   -
358   - lbc->br2 = CONFIG_SYS_BR2_PRELIM;
359   - asm("msync");
360   -
  355 + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  356 + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
361 357 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
362 358 asm("msync");
363 359  
board/freescale/mpc8560ads/mpc8560ads.c
Diff comments   View file @ f51cdaf
... ... @@ -322,7 +322,7 @@
322 322 local_bus_init(void)
323 323 {
324 324 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
325   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  325 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
326 326  
327 327 uint clkdiv;
328 328 uint lbc_hz;
... ... @@ -381,7 +381,7 @@
381 381 void
382 382 sdram_init(void)
383 383 {
384   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  384 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
385 385 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
386 386  
387 387 puts(" SDRAM: ");
... ... @@ -390,8 +390,8 @@
390 390 /*
391 391 * Setup SDRAM Base and Option Registers
392 392 */
393   - lbc->or2 = CONFIG_SYS_OR2_PRELIM;
394   - lbc->br2 = CONFIG_SYS_BR2_PRELIM;
  393 + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  394 + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
395 395 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
396 396 asm("msync");
397 397  
board/freescale/mpc8568mds/mpc8568mds.c
Diff comments   View file @ f51cdaf
... ... @@ -181,7 +181,7 @@
181 181 local_bus_init(void)
182 182 {
183 183 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
184   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  184 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
185 185  
186 186 uint clkdiv;
187 187 uint lbc_hz;
... ... @@ -214,7 +214,7 @@
214 214 #if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
215 215  
216 216 uint idx;
217   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  217 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
218 218 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
219 219 uint lsdmr_common;
220 220  
221 221  
222 222  
... ... @@ -225,15 +225,12 @@
225 225 /*
226 226 * Setup SDRAM Base and Option Registers
227 227 */
228   - lbc->or2 = CONFIG_SYS_OR2_PRELIM;
  228 + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM);
  229 + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
229 230 asm("msync");
230 231  
231   - lbc->br2 = CONFIG_SYS_BR2_PRELIM;
232   - asm("msync");
233   -
234 232 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
235 233 asm("msync");
236   -
237 234  
238 235 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
239 236 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
board/freescale/mpc8569mds/mpc8569mds.c
Diff comments   View file @ f51cdaf
... ... @@ -308,7 +308,7 @@
308 308 local_bus_init(void)
309 309 {
310 310 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
311   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  311 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
312 312  
313 313 uint clkdiv;
314 314 uint lbc_hz;
board/mpc8540eval/mpc8540eval.c
Diff comments   View file @ f51cdaf
... ... @@ -69,7 +69,7 @@
69 69 long dram_size = 0;
70 70  
71 71 #if !defined(CONFIG_RAM_AS_FLASH)
72   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  72 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
73 73 sys_info_t sysinfo;
74 74 uint temp_lbcdll = 0;
75 75 #endif
... ... @@ -110,8 +110,8 @@
110 110 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
111 111 asm("sync;isync;msync");
112 112 }
113   - lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
114   - lbc->br2 = CONFIG_SYS_BR2_PRELIM;
  113 + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
  114 + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
115 115 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
116 116 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
117 117 asm("sync");
... ... @@ -134,7 +134,7 @@
134 134 local_bus_init(void)
135 135 {
136 136 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
137   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  137 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
138 138  
139 139 uint clkdiv;
140 140 uint lbc_hz;
... ... @@ -290,7 +290,7 @@
290 290 local_bus_init(void)
291 291 {
292 292 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
293   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  293 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
294 294  
295 295 uint clkdiv;
296 296 uint lbc_hz;
board/sbc8349/sbc8349.c
Diff comments   View file @ f51cdaf
... ... @@ -160,7 +160,7 @@
160 160 void sdram_init(void)
161 161 {
162 162 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
163   - volatile fsl_lbus_t *lbc = &immap->lbus;
  163 + volatile fsl_lbc_t *lbc = &immap->im_lbc;
164 164 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
165 165  
166 166 puts("\n SDRAM on Local Bus: ");
board/sbc8548/sbc8548.c
Diff comments   View file @ f51cdaf
... ... @@ -116,7 +116,7 @@
116 116 local_bus_init(void)
117 117 {
118 118 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
119   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  119 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
120 120  
121 121 uint clkdiv;
122 122 uint lbc_hz;
... ... @@ -152,7 +152,7 @@
152 152 #if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
153 153  
154 154 uint idx;
155   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  155 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
156 156 uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
157 157 uint lsdmr_common;
158 158  
159 159  
160 160  
... ... @@ -163,21 +163,13 @@
163 163 /*
164 164 * Setup SDRAM Base and Option Registers
165 165 */
166   - out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
167   - asm("msync");
  166 + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
  167 + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
  168 + set_lbc_or(4, CONFIG_SYS_OR4_PRELIM);
  169 + set_lbc_br(4, CONFIG_SYS_BR4_PRELIM);
168 170  
169   - out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
170   - asm("msync");
171   -
172   - out_be32(&lbc->or4, CONFIG_SYS_OR4_PRELIM);
173   - asm("msync");
174   -
175   - out_be32(&lbc->br4, CONFIG_SYS_BR4_PRELIM);
176   - asm("msync");
177   -
178 171 out_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
179 172 asm("msync");
180   -
181 173  
182 174 out_be32(&lbc->lsrt, CONFIG_SYS_LBC_LSRT);
183 175 out_be32(&lbc->mrtpr, CONFIG_SYS_LBC_MRTPR);
board/sbc8560/sbc8560.c
Diff comments   View file @ f51cdaf
... ... @@ -269,7 +269,7 @@
269 269  
270 270 #if 0
271 271 #if !defined(CONFIG_RAM_AS_FLASH)
272   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  272 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
273 273 sys_info_t sysinfo;
274 274 uint temp_lbcdll = 0;
275 275 #endif
... ... @@ -310,8 +310,8 @@
310 310 gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
311 311 asm("sync;isync;msync");
312 312 }
313   - lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
314   - lbc->br2 = CONFIG_SYS_BR2_PRELIM;
  313 + set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */
  314 + set_lbc_br(2, CONFIG_SYS_BR2_PRELIM);
315 315 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
316 316 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
317 317 asm("sync");
board/sheldon/simpc8313/sdram.c
Diff comments   View file @ f51cdaf
... ... @@ -129,7 +129,7 @@
129 129 phys_size_t initdram(int board_type)
130 130 {
131 131 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
132   - volatile fsl_lbus_t *lbc= &im->lbus;
  132 + volatile fsl_lbc_t *lbc = &im->im_lbc;
133 133 u32 msize;
134 134  
135 135 if ((__raw_readl(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32) im)
board/sheldon/simpc8313/simpc8313.c
Diff comments   View file @ f51cdaf
... ... @@ -93,7 +93,7 @@
93 93 {
94 94 int rc = 0;
95 95 immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
96   - fsl_lbus_t *lbus = &immap->lbus;
  96 + fsl_lbc_t *lbus = &immap->im_lbc;
97 97 u32 *mxmr = &lbus->mamr; /* Pointer to mamr */
98 98  
99 99 /* UPM Table Configuration Code */
board/socrates/socrates.c
Diff comments   View file @ f51cdaf
... ... @@ -87,8 +87,6 @@
87 87  
88 88 int misc_init_r (void)
89 89 {
90   - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
91   -
92 90 /*
93 91 * Adjust flash start and offset to detected values
94 92 */
... ... @@ -99,8 +97,10 @@
99 97 * Check if boot FLASH isn't max size
100 98 */
101 99 if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
102   - memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
103   - memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
  100 + set_lbc_or(0, gd->bd->bi_flashstart |
  101 + (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
  102 + set_lbc_br(0, gd->bd->bi_flashstart |
  103 + (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
104 104  
105 105 /*
106 106 * Re-check to get correct base address
... ... @@ -112,8 +112,8 @@
112 112 * Check if only one FLASH bank is available
113 113 */
114 114 if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
115   - memctl->or1 = 0;
116   - memctl->br1 = 0;
  115 + set_lbc_or(1, 0);
  116 + set_lbc_br(1, 0);
117 117  
118 118 /*
119 119 * Re-do flash protection upon new addresses
... ... @@ -148,7 +148,7 @@
148 148 */
149 149 void local_bus_init (void)
150 150 {
151   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  151 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
152 152 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
153 153 sys_info_t sysinfo;
154 154 uint clkdiv;
155 155  
156 156  
157 157  
... ... @@ -299,26 +299,25 @@
299 299  
300 300 int lime_probe(void)
301 301 {
302   - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
303 302 uint cfg_br2;
304 303 uint cfg_or2;
305 304 int type;
306 305  
307   - cfg_br2 = memctl->br2;
308   - cfg_or2 = memctl->or2;
  306 + cfg_br2 = get_lbc_br(2);
  307 + cfg_or2 = get_lbc_or(2);
309 308  
310 309 /* Configure GPCM for CS2 */
311   - memctl->br2 = 0;
312   - memctl->or2 = 0xfc000410;
313   - memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
  310 + set_lbc_br(2, 0);
  311 + set_lbc_or(2, 0xfc000410);
  312 + set_lbc_br(2, (CONFIG_SYS_LIME_BASE) | 0x00001901);
314 313  
315 314 /* Get controller type */
316 315 type = mb862xx_probe(CONFIG_SYS_LIME_BASE);
317 316  
318 317 /* Restore previous CS2 configuration */
319   - memctl->br2 = 0;
320   - memctl->or2 = cfg_or2;
321   - memctl->br2 = cfg_br2;
  318 + set_lbc_br(2, 0);
  319 + set_lbc_or(2, cfg_or2);
  320 + set_lbc_br(2, cfg_br2);
322 321  
323 322 return (type == MB862XX_TYPE_LIME) ? 1 : 0;
324 323 }
board/tqc/tqm834x/tqm834x.c
Diff comments   View file @ f51cdaf
... ... @@ -253,10 +253,10 @@
253 253 debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
254 254  
255 255 /* set OR0 and BR0 */
256   - im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH |
257   - (-(total_size) & OR_GPCM_AM);
258   - im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) |
259   - (BR_MS_GPCM | BR_PS_32 | BR_V);
  256 + set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH |
  257 + (-(total_size) & OR_GPCM_AM));
  258 + set_lbc_br(0, (CONFIG_SYS_FLASH_BASE & BR_BA) |
  259 + (BR_MS_GPCM | BR_PS_32 | BR_V));
260 260  
261 261 return (0);
262 262 }
board/tqc/tqm85xx/nand.c
Diff comments   View file @ f51cdaf
... ... @@ -377,7 +377,7 @@
377 377 */
378 378 static void upmb_write (u_char addr, ulong val)
379 379 {
380   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  380 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
381 381  
382 382 out_be32 (&lbc->mdr, val);
383 383  
384 384  
... ... @@ -393,14 +393,14 @@
393 393 /*
394 394 * Initialize UPM for NAND flash access.
395 395 */
396   -static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
  396 +static void nand_upm_setup (volatile fsl_lbc_t *lbc)
397 397 {
398 398 uint i, j;
399 399 uint or3 = CONFIG_SYS_OR3_PRELIM;
400 400 uint clock = get_lbc_clock ();
401 401  
402   - out_be32 (&lbc->br3, 0); /* disable bank and reset all bits */
403   - out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
  402 + set_lbc_br(3, 0); /* disable bank and reset all bits */
  403 + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
404 404  
405 405 /*
406 406 * Search appropriate UPM table for bus clock.
... ... @@ -424,7 +424,7 @@
424 424 /* EAD must be set due to TQM8548 timing specification */
425 425 or3 |= OR_UPM_EAD;
426 426  
427   - out_be32 (&lbc->or3, or3);
  427 + set_lbc_or(3, or3);
428 428  
429 429 /* Assign address of table */
430 430 nand_upm_patt = upm_freq_table[i].upm_patt;
... ... @@ -458,7 +458,7 @@
458 458  
459 459 int board_nand_init (struct nand_chip *nand)
460 460 {
461   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  461 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
462 462  
463 463 if (!nand_upm_patt)
464 464 nand_upm_setup (lbc);
board/tqc/tqm85xx/tqm85xx.c
Diff comments   View file @ f51cdaf
... ... @@ -269,8 +269,6 @@
269 269  
270 270 int misc_init_r (void)
271 271 {
272   - volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
273   -
274 272 /*
275 273 * Adjust flash start and offset to detected values
276 274 */
277 275  
278 276  
... ... @@ -281,26 +279,27 @@
281 279 * Recalculate CS configuration if second FLASH bank is available
282 280 */
283 281 if (flash_info[0].size > 0) {
284   - memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
285   - (CONFIG_SYS_OR1_PRELIM & 0x00007fff);
286   - memctl->br1 = gd->bd->bi_flashstart |
287   - (CONFIG_SYS_BR1_PRELIM & 0x00007fff);
  282 + set_lbc_or(1, ((-flash_info[0].size) & 0xffff8000) |
  283 + (CONFIG_SYS_OR1_PRELIM & 0x00007fff));
  284 + set_lbc_br(1, gd->bd->bi_flashstart |
  285 + (CONFIG_SYS_BR1_PRELIM & 0x00007fff));
288 286 /*
289 287 * Re-check to get correct base address for bank 1
290 288 */
291 289 flash_get_size (gd->bd->bi_flashstart, 0);
292 290 } else {
293   - memctl->or1 = 0;
294   - memctl->br1 = 0;
  291 + set_lbc_or(1, 0);
  292 + set_lbc_br(1, 0);
295 293 }
296 294  
297 295 /*
298 296 * If bank 1 is equipped, bank 0 is mapped after bank 1
299 297 */
300   - memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
301   - (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
302   - memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
303   - (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
  298 + set_lbc_or(0, ((-flash_info[1].size) & 0xffff8000) |
  299 + (CONFIG_SYS_OR0_PRELIM & 0x00007fff));
  300 + set_lbc_br(0, gd->bd->bi_flashstart |
  301 + (CONFIG_SYS_BR0_PRELIM & 0x00007fff));
  302 +
304 303 /*
305 304 * Re-check to get correct base address for bank 0
306 305 */
... ... @@ -341,7 +340,7 @@
341 340 */
342 341 static void upmc_write (u_char addr, uint val)
343 342 {
344   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  343 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
345 344  
346 345 out_be32 (&lbc->mdr, val);
347 346  
... ... @@ -358,7 +357,7 @@
358 357  
359 358 uint get_lbc_clock (void)
360 359 {
361   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  360 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
362 361 sys_info_t sys_info;
363 362 ulong clkdiv = lbc->lcrr & LCRR_CLKDIV;
364 363  
... ... @@ -386,7 +385,7 @@
386 385 void local_bus_init (void)
387 386 {
388 387 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
389   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  388 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
390 389 uint lbc_mhz = get_lbc_clock () / 1000000;
391 390  
392 391 #ifdef CONFIG_MPC8548
393 392  
... ... @@ -502,10 +501,10 @@
502 501 * set if Local Bus Clock is > 83 MHz.
503 502 */
504 503 if (lbc_mhz > 83)
505   - out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
  504 + set_lbc_or(2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
506 505 else
507   - out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
508   - out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
  506 + set_lbc_or(2, CONFIG_SYS_OR2_CAN);
  507 + set_lbc_br(2, CONFIG_SYS_BR2_CAN);
509 508  
510 509 /* LGPL4 is UPWAIT */
511 510 out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
board/xes/xpedite5170/xpedite5170.c
Diff comments   View file @ f51cdaf
... ... @@ -56,8 +56,6 @@
56 56 */
57 57 static void flash_cs_fixup(void)
58 58 {
59   - immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
60   - ccsr_lbc_t *lbc = &immap->im_lbc;
61 59 int flash_sel;
62 60  
63 61 /*
64 62  
... ... @@ -70,11 +68,11 @@
70 68 printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
71 69  
72 70 if (flash_sel) {
73   - out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
74   - out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
  71 + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
  72 + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
75 73  
76   - out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
77   - out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
  74 + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
  75 + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
78 76 }
79 77 }
80 78  
board/xes/xpedite5200/xpedite5200.c
Diff comments   View file @ f51cdaf
... ... @@ -38,7 +38,7 @@
38 38  
39 39 int checkboard(void)
40 40 {
41   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
  41 + volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
42 42 volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
43 43 char *s;
44 44  
... ... @@ -65,7 +65,6 @@
65 65  
66 66 static void flash_cs_fixup(void)
67 67 {
68   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
69 68 int flash_sel;
70 69  
71 70 /*
72 71  
... ... @@ -78,11 +77,11 @@
78 77 printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
79 78  
80 79 if (flash_sel) {
81   - out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
82   - out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
  80 + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
  81 + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
83 82  
84   - out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
85   - out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
  83 + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
  84 + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
86 85 }
87 86 }
88 87  
board/xes/xpedite5370/xpedite5370.c
Diff comments   View file @ f51cdaf
... ... @@ -58,7 +58,6 @@
58 58  
59 59 static void flash_cs_fixup(void)
60 60 {
61   - volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
62 61 int flash_sel;
63 62  
64 63 /*
65 64  
... ... @@ -71,11 +70,11 @@
71 70 printf("FLASH: Executed from FLASH%d\n", flash_sel ? 2 : 1);
72 71  
73 72 if (flash_sel) {
74   - out_be32(&lbc->br0, CONFIG_SYS_BR1_PRELIM);
75   - out_be32(&lbc->or0, CONFIG_SYS_OR1_PRELIM);
  73 + set_lbc_br(0, CONFIG_SYS_BR1_PRELIM);
  74 + set_lbc_or(0, CONFIG_SYS_OR1_PRELIM);
76 75  
77   - out_be32(&lbc->br1, CONFIG_SYS_BR0_PRELIM);
78   - out_be32(&lbc->or1, CONFIG_SYS_OR0_PRELIM);
  76 + set_lbc_br(1, CONFIG_SYS_BR0_PRELIM);
  77 + set_lbc_or(1, CONFIG_SYS_OR0_PRELIM);
79 78 }
80 79 }
81 80  
drivers/mtd/nand/fsl_elbc_nand.c
Diff comments   View file @ f51cdaf
... ... @@ -75,7 +75,7 @@
75 75 struct fsl_elbc_mtd *chips[MAX_BANKS];
76 76  
77 77 /* device info */
78   - fsl_lbus_t *regs;
  78 + fsl_lbc_t *regs;
79 79 u8 __iomem *addr; /* Address of assigned FCM buffer */
80 80 unsigned int page; /* Last page written to / read from */
81 81 unsigned int read_bytes; /* Number of bytes read during command */
... ... @@ -171,7 +171,7 @@
171 171 struct nand_chip *chip = mtd->priv;
172 172 struct fsl_elbc_mtd *priv = chip->priv;
173 173 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
174   - fsl_lbus_t *lbc = ctrl->regs;
  174 + fsl_lbc_t *lbc = ctrl->regs;
175 175 int buf_num;
176 176  
177 177 ctrl->page = page_addr;
... ... @@ -211,7 +211,7 @@
211 211 struct nand_chip *chip = mtd->priv;
212 212 struct fsl_elbc_mtd *priv = chip->priv;
213 213 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
214   - fsl_lbus_t *lbc = ctrl->regs;
  214 + fsl_lbc_t *lbc = ctrl->regs;
215 215 long long end_tick;
216 216 u32 ltesr;
217 217  
... ... @@ -261,7 +261,7 @@
261 261 {
262 262 struct fsl_elbc_mtd *priv = chip->priv;
263 263 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
264   - fsl_lbus_t *lbc = ctrl->regs;
  264 + fsl_lbc_t *lbc = ctrl->regs;
265 265  
266 266 if (priv->page_size) {
267 267 out_be32(&lbc->fir,
... ... @@ -295,7 +295,7 @@
295 295 struct nand_chip *chip = mtd->priv;
296 296 struct fsl_elbc_mtd *priv = chip->priv;
297 297 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
298   - fsl_lbus_t *lbc = ctrl->regs;
  298 + fsl_lbc_t *lbc = ctrl->regs;
299 299  
300 300 ctrl->use_mdr = 0;
301 301  
... ... @@ -633,7 +633,7 @@
633 633 {
634 634 struct fsl_elbc_mtd *priv = chip->priv;
635 635 struct fsl_elbc_ctrl *ctrl = priv->ctrl;
636   - fsl_lbus_t *lbc = ctrl->regs;
  636 + fsl_lbc_t *lbc = ctrl->regs;
637 637  
638 638 if (ctrl->status != LTESR_CC)
639 639 return NAND_STATUS_FAIL;
... ... @@ -697,11 +697,7 @@
697 697 if (!elbc_ctrl)
698 698 return;
699 699  
700   -#ifdef CONFIG_MPC85xx
701   - elbc_ctrl->regs = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
702   -#else
703   - elbc_ctrl->regs = &((immap_t *)CONFIG_SYS_IMMR)->lbus;
704   -#endif
  700 + elbc_ctrl->regs = LBC_BASE_ADDR;
705 701  
706 702 /* clear event registers */
707 703 out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK);
... ... @@ -6,8 +6,6 @@
6 6 #ifndef __MPC85xx_H__
7 7 #define __MPC85xx_H__
8 8  
9   -#include <asm/fsl_lbc.h>
10   -
11 9 /* define for common ppc_asm.tmpl */
12 10 #define EXC_OFF_SYS_RESET 0x100 /* System reset */
13 11 #define _START_OFFSET 0
nand_spl/board/freescale/mpc8536ds/nand_boot.c
Diff comments   View file @ f51cdaf
... ... @@ -34,12 +34,11 @@
34 34 int px_spd;
35 35 u32 plat_ratio, bus_clk, sys_clk;
36 36 ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
37   - ccsr_lbc_t *lbc = (void *)CONFIG_SYS_MPC85xx_LBC_ADDR;
38 37  
39 38 #if defined(CONFIG_SYS_BR3_PRELIM) && defined(CONFIG_SYS_OR3_PRELIM)
40 39 /* for FPGA */
41   - out_be32(&lbc->br3, CONFIG_SYS_BR3_PRELIM);
42   - out_be32(&lbc->or3, CONFIG_SYS_OR3_PRELIM);
  40 + set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
  41 + set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
43 42 #else
44 43 #error CONFIG_SYS_BR3_PRELIM, CONFIG_SYS_OR3_PRELIM must be defined
45 44 #endif
nand_spl/nand_boot_fsl_elbc.c
Diff comments   View file @ f51cdaf
... ... @@ -32,7 +32,7 @@
32 32  
33 33 static void nand_wait(void)
34 34 {
35   - fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
  35 + fsl_lbc_t *regs = LBC_BASE_ADDR;
36 36  
37 37 for (;;) {
38 38 uint32_t status = in_be32(&regs->ltesr);
... ... @@ -49,7 +49,7 @@
49 49  
50 50 static void nand_load(unsigned int offs, int uboot_size, uchar *dst)
51 51 {
52   - fsl_lbus_t *regs = (fsl_lbus_t *)(CONFIG_SYS_IMMR + 0x5000);
  52 + fsl_lbc_t *regs = LBC_BASE_ADDR;
53 53 uchar *buf = (uchar *)CONFIG_SYS_NAND_BASE;
54 54 int large = in_be32(&regs->bank[0].or) & OR_FCM_PGS;
55 55 int block_shift = large ? 17 : 14;