Blame view
include/fsl_ddr.h
4.17 KB
58e5e9aff
|
1 |
/* |
34e026f9b
|
2 |
* Copyright 2008-2014 Freescale Semiconductor, Inc. |
58e5e9aff
|
3 4 5 6 7 8 9 10 |
* * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License * Version 2 as published by the Free Software Foundation. */ #ifndef FSL_DDR_MAIN_H #define FSL_DDR_MAIN_H |
34e026f9b
|
11 |
#include <fsl_ddrc_version.h> |
5614e71b4
|
12 13 |
#include <fsl_ddr_sdram.h> #include <fsl_ddr_dimm_params.h> |
58e5e9aff
|
14 |
|
5614e71b4
|
15 |
#include <common_timing_params.h> |
58e5e9aff
|
16 |
|
1d71efbb0
|
17 18 19 20 |
#ifndef CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS /* All controllers are for main memory */ #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS CONFIG_NUM_DDR_CONTROLLERS #endif |
4e5b1bd0d
|
21 22 23 24 25 26 27 |
#ifdef CONFIG_SYS_FSL_DDR_LE #define ddr_in32(a) in_le32(a) #define ddr_out32(a, v) out_le32(a, v) #else #define ddr_in32(a) in_be32(a) #define ddr_out32(a, v) out_be32(a, v) #endif |
34e026f9b
|
28 29 30 |
#define _DDR_ADDR CONFIG_SYS_FSL_DDR_ADDR u32 fsl_ddr_get_version(void); |
1b3e3c4f2
|
31 |
#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM) |
58e5e9aff
|
32 33 34 35 36 37 38 39 40 41 42 |
/* * Bind the main DDR setup driver's generic names * to this specific DDR technology. */ static __inline__ int compute_dimm_parameters(const generic_spd_eeprom_t *spd, dimm_params_t *pdimm, unsigned int dimm_number) { return ddr_compute_dimm_parameters(spd, pdimm, dimm_number); } |
1b3e3c4f2
|
43 |
#endif |
58e5e9aff
|
44 45 46 47 48 49 |
/* * Data Structures * * All data structures have to be on the stack */ |
6d0f6bcf3
|
50 51 |
#define CONFIG_SYS_NUM_DDR_CTLRS CONFIG_NUM_DDR_CONTROLLERS #define CONFIG_SYS_DIMM_SLOTS_PER_CTLR CONFIG_DIMM_SLOTS_PER_CTLR |
58e5e9aff
|
52 53 54 |
typedef struct { generic_spd_eeprom_t |
6d0f6bcf3
|
55 |
spd_installed_dimms[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; |
58e5e9aff
|
56 |
struct dimm_params_s |
6d0f6bcf3
|
57 58 59 60 |
dimm_params[CONFIG_SYS_NUM_DDR_CTLRS][CONFIG_SYS_DIMM_SLOTS_PER_CTLR]; memctl_options_t memctl_opts[CONFIG_SYS_NUM_DDR_CTLRS]; common_timing_params_t common_timing_params[CONFIG_SYS_NUM_DDR_CTLRS]; fsl_ddr_cfg_regs_t fsl_ddr_config_reg[CONFIG_SYS_NUM_DDR_CTLRS]; |
1d71efbb0
|
61 62 63 64 65 66 67 |
unsigned int first_ctrl; unsigned int num_ctrls; unsigned long long mem_base; unsigned int dimm_slots_per_ctrl; int (*board_need_mem_reset)(void); void (*board_mem_reset)(void); void (*board_mem_de_reset)(void); |
58e5e9aff
|
68 69 70 71 72 73 74 75 76 77 78 |
} fsl_ddr_info_t; /* Compute steps */ #define STEP_GET_SPD (1 << 0) #define STEP_COMPUTE_DIMM_PARMS (1 << 1) #define STEP_COMPUTE_COMMON_PARMS (1 << 2) #define STEP_GATHER_OPTS (1 << 3) #define STEP_ASSIGN_ADDRESSES (1 << 4) #define STEP_COMPUTE_REGS (1 << 5) #define STEP_PROGRAM_REGS (1 << 6) #define STEP_ALL 0xFFF |
6f5e1dc53
|
79 |
unsigned long long |
fc0c2b6fc
|
80 81 |
fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step, unsigned int size_only); |
6f5e1dc53
|
82 |
const char *step_to_string(unsigned int step); |
58e5e9aff
|
83 |
|
6f5e1dc53
|
84 |
unsigned int compute_fsl_memctl_config_regs(const memctl_options_t *popts, |
58e5e9aff
|
85 86 87 |
fsl_ddr_cfg_regs_t *ddr, const common_timing_params_t *common_dimm, const dimm_params_t *dimm_parameters, |
fc0c2b6fc
|
88 89 |
unsigned int dbw_capacity_adjust, unsigned int size_only); |
6f5e1dc53
|
90 91 92 93 |
unsigned int compute_lowest_common_dimm_parameters( const dimm_params_t *dimm_params, common_timing_params_t *outpdimm, unsigned int number_of_dimms); |
0dd38a35f
|
94 |
unsigned int populate_memctl_options(int all_dimms_registered, |
58e5e9aff
|
95 |
memctl_options_t *popts, |
dfb49108e
|
96 |
dimm_params_t *pdimm, |
58e5e9aff
|
97 |
unsigned int ctrl_num); |
6f5e1dc53
|
98 |
void check_interleaving_options(fsl_ddr_info_t *pinfo); |
58e5e9aff
|
99 |
|
6f5e1dc53
|
100 101 102 103 104 105 106 |
unsigned int mclk_to_picos(unsigned int mclk); unsigned int get_memory_clk_period_ps(void); unsigned int picos_to_mclk(unsigned int picos); void fsl_ddr_set_lawbar( const common_timing_params_t *memctl_common_params, unsigned int memctl_interleaved, unsigned int ctrl_num); |
e8ba6c503
|
107 108 |
int fsl_ddr_interactive_env_var_exists(void); unsigned long long fsl_ddr_interactive(fsl_ddr_info_t *pinfo, int var_is_set); |
6f5e1dc53
|
109 |
void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd, |
1d71efbb0
|
110 |
unsigned int ctrl_num, unsigned int dimm_slots_per_ctrl); |
6f5e1dc53
|
111 112 113 |
int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); unsigned int check_fsl_memctl_config_regs(const fsl_ddr_cfg_regs_t *ddr); |
4e5b1bd0d
|
114 |
void board_add_ram_info(int use_default); |
6f5e1dc53
|
115 116 117 |
/* processor specific function */ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, |
c63e13701
|
118 |
unsigned int ctrl_num, int step); |
1b3e3c4f2
|
119 120 121 122 123 |
/* board specific function */ int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, unsigned int controller_number, unsigned int dimm_number); |
58e5e9aff
|
124 |
#endif |