powerpc/mpc8xxx: Enable calculation for fixed DDR chips

We used to have fixed parameters for soldered DDR chips. This patch introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR chip datasheet, implemneted in board-specific files or header files. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

powerpc/mpc8xxx: Enable calculation for fixed DDR chips
We used to have fixed parameters for soldered DDR chips. This patch introduces CONFIG_SYS_DDR_RAW_TIMING to enable calculation based on timing data from DDR chip datasheet, implemneted in board-specific files or header files. Signed-off-by: York Sun <yorksun@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
York Sun · Kumar Gala
1 parent aeb6716a12
Showing 5 changed files with 39 additions and 3 deletions Side-by-side Diff
README
arch/powerpc/cpu/mpc85xx/cpu.c
arch/powerpc/cpu/mpc8xxx/ddr/Makefile
arch/powerpc/cpu/mpc8xxx/ddr/ddr.h
arch/powerpc/cpu/mpc8xxx/ddr/main.c
@@ -2948,6 +2948,12 @@
 		one, specify here. Note that the value must resolve
 		to something your driver can deal with.
  
+- CONFIG_SYS_DDR_RAW_TIMING
+		Get DDR timing information from other than SPD. Common with
+		soldered DDR chips onboard without SPD. DDR raw timing
+		parameters are extracted from datasheet and hard-coded into
+		header files or board specific files.
+
 - CONFIG_SYS_83XX_DDR_USES_CS0
 		Only for 83xx systems. If specified, then DDR should
 		be configured using CS0 and CS1 instead of CS2 and CS3.
@@ -336,7 +336,9 @@
 	}
 #endif
  
-#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD)
+#if	defined(CONFIG_SPD_EEPROM)	|| \
+	defined(CONFIG_DDR_SPD)		|| \
+	defined(CONFIG_SYS_DDR_RAW_TIMING)
 	dram_size = fsl_ddr_sdram();
 #else
 	dram_size = fixed_sdram();
@@ -12,15 +12,24 @@
  
 COBJS-$(CONFIG_FSL_DDR1)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR1)	+= ddr1_dimm_params.o
  
 COBJS-$(CONFIG_FSL_DDR2)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
-COBJS-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
  
 COBJS-$(CONFIG_FSL_DDR3)	+= main.o util.o ctrl_regs.o options.o \
 				   lc_common_dimm_params.o
+ifdef CONFIG_DDR_SPD
+SPD := y
+endif
+ifdef CONFIG_SPD_EEPROM
+SPD := y
+endif
+ifdef SPD
+COBJS-$(CONFIG_FSL_DDR1)	+= ddr1_dimm_params.o
+COBJS-$(CONFIG_FSL_DDR2)	+= ddr2_dimm_params.o
 COBJS-$(CONFIG_FSL_DDR3)	+= ddr3_dimm_params.o
+endif
+
  
 SRCS	:= $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
 OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
@@ -14,6 +14,7 @@
  
 #include "common_timing_params.h"
  
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 /*
  * Bind the main DDR setup driver's generic names
  * to this specific DDR technology.
@@ -25,6 +26,7 @@
 {
 	return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
 }
+#endif
  
 /*
  * Data Structures
@@ -80,5 +82,10 @@
 extern unsigned int mclk_to_picos(unsigned int mclk);
 extern unsigned int get_memory_clk_period_ps(void);
 extern unsigned int picos_to_mclk(unsigned int picos);
+
+/* board specific function */
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+			unsigned int controller_number,
+			unsigned int dimm_number);
 #endif
@@ -325,6 +325,7 @@
  
 	switch (start_step) {
 	case STEP_GET_SPD:
+#if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 		/* STEP 1:  Gather all DIMM SPD data */
 		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 			fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
@@ -356,6 +357,17 @@
 			}
 		}
  
+#else
+	case STEP_COMPUTE_DIMM_PARMS:
+		for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
+			for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
+				dimm_params_t *pdimm =
+					&(pinfo->dimm_params[i][j]);
+				fsl_ddr_get_dimm_params(pdimm, i, j);
+			}
+		}
+		debug("Filling dimm parameters from board specific file\n");
+#endif
 	case STEP_COMPUTE_COMMON_PARMS:
 		/*
 		 * STEP 3: Compute a common set of timing parameters
...	...	@@ -2948,6 +2948,12 @@
2948	2948	one, specify here. Note that the value must resolve
2949	2949	to something your driver can deal with.
2950	2950
	2951	+- CONFIG_SYS_DDR_RAW_TIMING
	2952	+ Get DDR timing information from other than SPD. Common with
	2953	+ soldered DDR chips onboard without SPD. DDR raw timing
	2954	+ parameters are extracted from datasheet and hard-coded into
	2955	+ header files or board specific files.
	2956	+
2951	2957	- CONFIG_SYS_83XX_DDR_USES_CS0
2952	2958	Only for 83xx systems. If specified, then DDR should
2953	2959	be configured using CS0 and CS1 instead of CS2 and CS3.
...	...	@@ -336,7 +336,9 @@
336	336	}
337	337	#endif
338	338
339		-#if defined(CONFIG_SPD_EEPROM) \|\| defined(CONFIG_DDR_SPD)
	339	+#if defined(CONFIG_SPD_EEPROM) \|\| \
	340	+ defined(CONFIG_DDR_SPD) \|\| \
	341	+ defined(CONFIG_SYS_DDR_RAW_TIMING)
340	342	dram_size = fsl_ddr_sdram();
341	343	#else
342	344	dram_size = fixed_sdram();
...	...	@@ -12,15 +12,24 @@
12	12
13	13	COBJS-$(CONFIG_FSL_DDR1) += main.o util.o ctrl_regs.o options.o \
14	14	lc_common_dimm_params.o
15		-COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
16	15
17	16	COBJS-$(CONFIG_FSL_DDR2) += main.o util.o ctrl_regs.o options.o \
18	17	lc_common_dimm_params.o
19		-COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
20	18
21	19	COBJS-$(CONFIG_FSL_DDR3) += main.o util.o ctrl_regs.o options.o \
22	20	lc_common_dimm_params.o
	21	+ifdef CONFIG_DDR_SPD
	22	+SPD := y
	23	+endif
	24	+ifdef CONFIG_SPD_EEPROM
	25	+SPD := y
	26	+endif
	27	+ifdef SPD
	28	+COBJS-$(CONFIG_FSL_DDR1) += ddr1_dimm_params.o
	29	+COBJS-$(CONFIG_FSL_DDR2) += ddr2_dimm_params.o
23	30	COBJS-$(CONFIG_FSL_DDR3) += ddr3_dimm_params.o
	31	+endif
	32	+
24	33
25	34	SRCS := $(START:.o=.S) $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
26	35	OBJS := $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
...	...	@@ -14,6 +14,7 @@
14	14
15	15	#include "common_timing_params.h"
16	16
	17	+#if defined(CONFIG_DDR_SPD) \|\| defined(CONFIG_SPD_EEPROM)
17	18	/*
18	19	* Bind the main DDR setup driver's generic names
19	20	* to this specific DDR technology.
...	...	@@ -25,6 +26,7 @@
25	26	{
26	27	return ddr_compute_dimm_parameters(spd, pdimm, dimm_number);
27	28	}
	29	+#endif
28	30
29	31	/*
30	32	* Data Structures
...	...	@@ -80,5 +82,10 @@
80	82	extern unsigned int mclk_to_picos(unsigned int mclk);
81	83	extern unsigned int get_memory_clk_period_ps(void);
82	84	extern unsigned int picos_to_mclk(unsigned int picos);
	85	+
	86	+/* board specific function */
	87	+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
	88	+ unsigned int controller_number,
	89	+ unsigned int dimm_number);
83	90	#endif
...	...	@@ -325,6 +325,7 @@
325	325
326	326	switch (start_step) {
327	327	case STEP_GET_SPD:
	328	+#if defined(CONFIG_DDR_SPD) \|\| defined(CONFIG_SPD_EEPROM)
328	329	/* STEP 1: Gather all DIMM SPD data */
329	330	for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
330	331	fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
...	...	@@ -356,6 +357,17 @@
356	357	}
357	358	}
358	359
	360	+#else
	361	+ case STEP_COMPUTE_DIMM_PARMS:
	362	+ for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
	363	+ for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
	364	+ dimm_params_t *pdimm =
	365	+ &(pinfo->dimm_params[i][j]);
	366	+ fsl_ddr_get_dimm_params(pdimm, i, j);
	367	+ }
	368	+ }
	369	+ debug("Filling dimm parameters from board specific file\n");
	370	+#endif
359	371	case STEP_COMPUTE_COMMON_PARMS:
360	372	/*
361	373	* STEP 3: Compute a common set of timing parameters