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include/configs/imx8qxp_arm2.h
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/* * Copyright 2017-2018 NXP * * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __IMX8QXP_ARM2_H #define __IMX8QXP_ARM2_H #include <linux/sizes.h> #include <asm/arch/imx-regs.h> |
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#include "imx_env.h" |
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#ifdef CONFIG_SPL_BUILD |
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#define CONFIG_PARSE_CONTAINER |
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#ifdef CONFIG_QSPI_BOOT #define CONFIG_SPL_SPI_LOAD #endif #define CONFIG_SPL_TEXT_BASE 0x0 #define CONFIG_SPL_MAX_SIZE (124 * 1024) #define CONFIG_SYS_MONITOR_LEN (1024 * 1024) |
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#ifdef CONFIG_NAND_BOOT |
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#ifndef CONFIG_PARSE_CONTAINER |
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#define CONFIG_SPL_NAND_RAW_ONLY |
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#endif |
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#define CONFIG_SPL_NAND_SUPPORT #define CONFIG_SPL_DMA_SUPPORT #define CONFIG_SPL_NAND_MXS |
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#define CONFIG_SYS_NAND_U_BOOT_OFFS (0x8000000) /*Put the FIT out of first 128MB boot area */ |
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#define CONFIG_SPL_NAND_BOOT #define CONFIG_SYS_NAND_U_BOOT_DST 0x80000000 #define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 * 1024 ) #define CONFIG_SYS_NAND_U_BOOT_START 0x80000000 #endif |
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#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x1040 /* (32K + 2Mb)/sector_size */ #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 0 #define CONFIG_SPL_WATCHDOG_SUPPORT #define CONFIG_SPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" #define CONFIG_SPL_STACK 0x013E000 #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT #define CONFIG_SPL_SERIAL_SUPPORT |
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#define CONFIG_SPL_BSS_START_ADDR 0x00138000 #define CONFIG_SPL_BSS_MAX_SIZE 0x8000 /* 20 KB */ |
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#define CONFIG_SYS_SPL_MALLOC_START 0x00120000 |
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#define CONFIG_SYS_SPL_MALLOC_SIZE 0x18000 /* 60 KB */ |
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#define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_SYS_ICACHE_OFF #define CONFIG_SYS_DCACHE_OFF #define CONFIG_MALLOC_F_ADDR 0x00120000 /* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ #define CONFIG_SPL_RAW_IMAGE_ARM_TRUSTED_FIRMWARE #define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ #define CONFIG_OF_EMBED #define CONFIG_ATF_TEXT_BASE 0x80000000 #define CONFIG_SYS_ATF_START 0x80000000 /* #define CONFIG_FIT */ /* Since the SPL runs before ATF, MU1 will not be started yet, so use MU0 */ #define SC_IPC_CH SC_IPC_AP_CH0 #endif |
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#define CONFIG_REMAKE_ELF #define CONFIG_BOARD_EARLY_INIT_F #define CONFIG_ARCH_MISC_INIT /* Flat Device Tree Definitions */ #define CONFIG_OF_BOARD_SETUP #undef CONFIG_CMD_EXPORTENV #undef CONFIG_CMD_IMPORTENV #undef CONFIG_CMD_IMLS #undef CONFIG_CMD_CRC32 #undef CONFIG_BOOTM_NETBSD #define CONFIG_FSL_ESDHC #define CONFIG_FSL_USDHC #define CONFIG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 #define CONFIG_SUPPORT_EMMC_BOOT /* eMMC specific */ #define CONFIG_ENV_OVERWRITE #define CONFIG_FSL_HSIO #ifdef CONFIG_FSL_HSIO #define CONFIG_PCIE_IMX8X #define CONFIG_CMD_PCI #define CONFIG_PCI #define CONFIG_PCI_PNP #define CONFIG_PCI_SCAN_SHOW #endif #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG /* FUSE command */ #define CONFIG_CMD_FUSE /* GPIO configs */ #define CONFIG_MXC_GPIO /* ENET Config */ #define CONFIG_MII #define CONFIG_FEC_MXC #define CONFIG_FEC_XCV_TYPE RGMII #define FEC_QUIRK_ENET_MAC #define CONFIG_PHY_GIGE /* Support for 1000BASE-X */ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS /* ENET0 connects AR8031 on CPU board, ENET1 connects to base board and MUX with ESAI, default is ESAI */ #define CONFIG_FEC_ENET_DEV 0 #if (CONFIG_FEC_ENET_DEV == 0) #define IMX_FEC_BASE 0x5B040000 #define CONFIG_FEC_MXC_PHYADDR 0x0 #define CONFIG_ETHPRIME "eth0" #elif (CONFIG_FEC_ENET_DEV == 1) #define IMX_FEC_BASE 0x5B050000 #define CONFIG_FEC_MXC_PHYADDR 0x1 #define CONFIG_FEC_ENABLE_MAX7322 #define CONFIG_ETHPRIME "eth1" #endif /* ENET0 MDIO are shared */ #define CONFIG_FEC_MXC_MDIO_BASE 0x5B040000 #define CONFIG_LIB_RAND #define CONFIG_NET_RANDOM_ETHADDR /* MAX7322 */ #ifdef CONFIG_FEC_ENABLE_MAX7322 #define CONFIG_MAX7322_I2C_ADDR 0x68 #define CONFIG_MAX7322_I2C_BUS 0 /* I2C1 */ #endif |
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#ifdef CONFIG_AHAB_BOOT #define AHAB_ENV "sec_boot=yes\0" #else #define AHAB_ENV "sec_boot=no\0" #endif |
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/* Boot M4 */ #define M4_BOOT_ENV \ "m4_0_image=m4_0.bin\0" \ "loadm4image_0=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4_0_image}\0" \ "m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \ #ifdef CONFIG_NAND_BOOT |
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#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) " |
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#endif #define CONFIG_MFG_ENV_SETTINGS \ |
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CONFIG_MFG_ENV_SETTINGS_DEFAULT \ "clk_ignore_unused "\ "\0" \ |
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"initrd_addr=0x83100000\0" \ |
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"initrd_high=0xffffffffffffffff\0" \ |
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"emmc_dev=0\0" \ "sd_dev=1\0" \ |
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/* Initial environment variables */ |
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#ifdef CONFIG_NAND_BOOT #define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ |
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"bootargs=console=ttyLP0,115200 ubi.mtd=6 " \ |
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"root=ubi0:nandrootfs rootfstype=ubifs " \ MFG_NAND_PARTITION \ "\0"\ |
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"console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \ |
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"mtdparts=" MFG_NAND_PARTITION "\0" \ |
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"fdt_addr=0x83000000\0" #else |
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#define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_MFG_ENV_SETTINGS \ M4_BOOT_ENV \ |
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AHAB_ENV \ |
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"script=boot.scr\0" \ "image=Image\0" \ "panel=NULL\0" \ |
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"console=ttyLP0\0" \ "earlycon=lpuart32,0x5a060000\0" \ |
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"fdt_addr=0x83000000\0" \ "fdt_high=0xffffffffffffffff\0" \ |
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"cntr_addr=0x98000000\0" \ |
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"cntr_file=os_cntr_signed.bin\0" \ |
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"boot_fdt=try\0" \ |
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"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ |
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"mmcdev="__stringify(CONFIG_SYS_MMC_ENV_DEV)"\0" \ "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcautodetect=yes\0" \ |
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"mmcargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} root=${mmcroot}\0 " \ |
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"loadbootscript=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ |
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"loadcntr=fatload mmc ${mmcdev}:${mmcpart} ${cntr_addr} ${cntr_file}\0" \ "auth_os=auth_cntr ${cntr_addr}\0" \ |
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"mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ |
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"if test ${sec_boot} = yes; then " \ "if run auth_os; then " \ |
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"booti ${loadaddr} - ${fdt_addr}; " \ "else " \ |
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"echo ERR: failed to authenticate; " \ |
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"fi; " \ "else " \ |
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"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ "booti ${loadaddr} - ${fdt_addr}; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "else " \ "echo wait for boot; " \ "fi;" \ |
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"fi;\0" \ |
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"netargs=setenv bootargs console=${console},${baudrate} earlycon=${earlycon},${baudrate} " \ |
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"root=/dev/nfs " \ "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ "netboot=echo Booting from net ...; " \ "run netargs; " \ "if test ${ip_dyn} = yes; then " \ "setenv get_cmd dhcp; " \ "else " \ "setenv get_cmd tftp; " \ "fi; " \ |
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"if test ${sec_boot} = yes; then " \ "${get_cmd} ${cntr_addr} ${cntr_file}; " \ "if run auth_os; then " \ |
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"booti ${loadaddr} - ${fdt_addr}; " \ "else " \ |
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"echo ERR: failed to authenticate; " \ |
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"fi; " \ "else " \ |
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"${get_cmd} ${loadaddr} ${image}; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ "booti ${loadaddr} - ${fdt_addr}; " \ "else " \ "echo WARN: Cannot load the DT; " \ "fi; " \ "else " \ "booti; " \ "fi;" \ |
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"fi;\0" |
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#endif |
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#ifdef CONFIG_NAND_BOOT #define CONFIG_BOOTCOMMAND \ |
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"nand read ${loadaddr} 0x9000000 0x2000000;"\ "nand read ${fdt_addr} 0xB000000 0x100000;"\ |
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"booti ${loadaddr} - ${fdt_addr}" #else |
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#define CONFIG_BOOTCOMMAND \ "mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ "run bootscript; " \ "else " \ |
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"if test ${sec_boot} = yes; then " \ "if run loadcntr; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ "else " \ "if run loadimage; then " \ "run mmcboot; " \ "else run netboot; " \ "fi; " \ "fi; " \ |
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"fi; " \ "else booti ${loadaddr} - ${fdt_addr}; fi" |
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#endif |
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/* Link Definitions */ #define CONFIG_LOADADDR 0x80280000 #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR #define CONFIG_SYS_INIT_SP_ADDR 0x80200000 /* Default environment is in SD */ |
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#define CONFIG_ENV_SIZE 0x2000 |
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#ifdef CONFIG_NAND_BOOT #define CONFIG_ENV_OFFSET (120 << 20) #elif defined(CONFIG_QSPI_BOOT) |
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#define CONFIG_ENV_OFFSET (4 * 1024 * 1024) #define CONFIG_ENV_SECT_SIZE (128 * 1024) #define CONFIG_ENV_SPI_BUS CONFIG_SF_DEFAULT_BUS #define CONFIG_ENV_SPI_CS CONFIG_SF_DEFAULT_CS #define CONFIG_ENV_SPI_MODE CONFIG_SF_DEFAULT_MODE #define CONFIG_ENV_SPI_MAX_HZ CONFIG_SF_DEFAULT_SPEED #else #define CONFIG_ENV_OFFSET (64 * SZ_64K) #define CONFIG_SYS_MMC_ENV_PART 0 /* user area */ #endif #define CONFIG_SYS_MMC_IMG_LOAD_PART 1 /* On LPDDR4 board, USDHC1 is for eMMC, USDHC2 is for SD on CPU board */ |
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#ifdef CONFIG_TARGET_IMX8X_17X17_VAL |
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#define CONFIG_SYS_MMC_ENV_DEV 0 /* USDHC1 */ #define CONFIG_MMCROOT "/dev/mmcblk0p2" /* USDHC1 */ #define CONFIG_SYS_FSL_USDHC_NUM 1 #else |
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#define CONFIG_SYS_MMC_ENV_DEV 1 /* USDHC2 */ #define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ #define CONFIG_SYS_FSL_USDHC_NUM 2 |
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#endif |
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/* Size of malloc() pool */ #define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (32*1024)) * 1024) #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
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#define CONFIG_NR_DRAM_BANKS 4 |
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#define PHYS_SDRAM_1 0x80000000 #define PHYS_SDRAM_2 0x880000000 |
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#if defined(CONFIG_TARGET_IMX8QXP_DDR3_ARM2) || defined(CONFIG_TARGET_IMX8X_17X17_VAL) #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1 GB totally */ |
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#define PHYS_SDRAM_2_SIZE 0x00000000 #else #define PHYS_SDRAM_1_SIZE 0x80000000 /* 2 GB */ /* LPDDR4 board total DDR is 3GB */ #define PHYS_SDRAM_2_SIZE 0x40000000 /* 1 GB */ #endif |
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#define CONFIG_SYS_MEMTEST_START 0xA0000000 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (PHYS_SDRAM_1_SIZE >> 2)) |
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/* Serial */ #define CONFIG_BAUDRATE 115200 /* Monitor Command Prompt */ #define CONFIG_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_CBSIZE 1024 #define CONFIG_SYS_MAXARGS 64 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ sizeof(CONFIG_SYS_PROMPT) + 16) /* Generic Timer Definitions */ #define COUNTER_FREQUENCY 8000000 /* 8MHz */ #ifndef CONFIG_DM_PCA953X #define CONFIG_PCA953X #define CONFIG_CMD_PCA953X #define CONFIG_CMD_PCA953X_INFO #endif #define CONFIG_IMX_SMMU /* MT35XU512ABA1G12 has only one Die, so QSPI0 B won't work */ #ifdef CONFIG_FSL_FSPI #define CONFIG_SF_DEFAULT_BUS 0 #define CONFIG_SF_DEFAULT_CS 0 #define CONFIG_SF_DEFAULT_SPEED 40000000 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #define FSL_FSPI_FLASH_SIZE SZ_64M #define FSL_FSPI_FLASH_NUM 1 #define FSPI0_BASE_ADDR 0x5d120000 #define FSPI0_AMBA_BASE 0 #define CONFIG_SYS_FSL_FSPI_AHB #endif |
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#ifdef CONFIG_CMD_NAND #define CONFIG_NAND_MXS #define CONFIG_CMD_NAND_TRIMFFS /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_ONFI_DETECTION /* DMA stuff, needed for GPMI/MXS NAND support */ #define CONFIG_APBH_DMA #define CONFIG_APBH_DMA_BURST #define CONFIG_APBH_DMA_BURST8 #endif |
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/* USB Config */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* USB OTG controller configs */ #ifdef CONFIG_USB_EHCI_HCD #define CONFIG_USB_HOST_ETHER #define CONFIG_USB_ETHER_ASIX #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #endif #endif /* CONFIG_CMD_USB */ #ifdef CONFIG_USB_GADGET #define CONFIG_USBD_HS #endif |
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#if defined(CONFIG_ANDROID_SUPPORT) #include "imx8qxp_arm2_android.h" #endif |
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/* Framebuffer */ #ifdef CONFIG_VIDEO #define CONFIG_VIDEO_IMXDPUV1 #define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN #define CONFIG_BMP_16BPP #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO #define CONFIG_IMX_VIDEO_SKIP #endif #define CONFIG_OF_SYSTEM_SETUP |
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#define CONFIG_CMD_READ #define CONFIG_SERIAL_TAG |
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#endif /* __IMX8QXP_ARM2_H */ |