MLK-20664-1 imx8qxp: spl: Enable SPL container support for NAND

Add the NAND support to SPL container parser and enable it for imx8qxp arm2 nand reworked board. The SPL NAND will read from nandfit mtdpart (128MB offset) to parsing the entire boot image and get the 3rd container from it. This requires burning tool (uuu) to program the entire boot image into nandfit. Signed-off-by: Ye Li <ye.li@nxp.com>

MLK-20664-1 imx8qxp: spl: Enable SPL container support for NAND
Add the NAND support to SPL container parser and enable it for imx8qxp arm2 nand reworked board. The SPL NAND will read from nandfit mtdpart (128MB offset) to parsing the entire boot image and get the 3rd container from it. This requires burning tool (uuu) to program the entire boot image into nandfit. Signed-off-by: Ye Li <ye.li@nxp.com>
Ye Li · Eric Lee · Eric Lee
1 parent cf2acc5b7c
Showing 4 changed files with 53 additions and 12 deletions Side-by-side Diff
arch/arm/include/asm/arch-imx8/image.h
arch/arm/mach-imx/imx8/parser.c
common/spl/spl_nand.c
include/configs/imx8qxp_arm2.h
@@ -10,7 +10,7 @@
 #define CONTAINER_HDR_EMMC_OFFSET 0
 #define CONTAINER_HDR_MMCSD_OFFSET SZ_32K
 #define CONTAINER_HDR_QSPI_OFFSET SZ_4K
-#define CONTAINER_HDR_NAND_OFFSET SZ_64M
+#define CONTAINER_HDR_NAND_OFFSET SZ_128M
  
  struct container_hdr{
 	 uint8_t version;
@@ -9,6 +9,7 @@
 #include <dm.h>
 #include <mmc.h>
 #include <spi_flash.h>
+#include <nand.h>
 #include <asm/arch/image.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/sci/sci.h>
@@ -16,7 +17,8 @@
  
 #define MMC_DEV		0
 #define QSPI_DEV	1
-#define RAM_DEV	3
+#define NAND_DEV	2
+#define RAM_DEV		3
  
 #define SEC_SECURE_RAM_BASE			(0x31800000UL)
 #define SEC_SECURE_RAM_END_BASE			(SEC_SECURE_RAM_BASE + 0xFFFFUL)
@@ -39,7 +41,8 @@
 {
 	int ret = -ENODEV;
  
-	if (!device && current_dev_type != RAM_DEV) {
+	if (current_dev_type != NAND_DEV && current_dev_type != RAM_DEV
+		&& !device) {
 		debug("No device selected\n");
 		return ret;
 	}
@@ -73,6 +76,15 @@
 		}
 	}
 #endif
+#ifdef CONFIG_SPL_NAND_SUPPORT
+	if (current_dev_type == NAND_DEV) {
+		ret = nand_spl_load_image(start, len, load_addr);
+		if (ret != 0) {
+			debug("Read container image from NAND failed\n");
+			return -EIO;
+		}
+	}
+#endif
  
 	if (current_dev_type == RAM_DEV) {
 		memcpy(load_addr, (const void *)(ulong)start, len);
@@ -257,6 +269,21 @@
  
 	current_dev_type = QSPI_DEV;
 	device = flash;
+
+	start_offset = offset;
+
+	ret = read_auth_container(spl_image);
+
+	return ret;
+}
+
+int nand_load_image_parse_container(struct spl_image_info *spl_image,
+				   unsigned long offset)
+{
+	int ret = 0;
+
+	current_dev_type = NAND_DEV;
+	device = NULL;
  
 	start_offset = offset;
  
@@ -12,12 +12,20 @@
 #include <linux/libfdt_env.h>
 #include <fdt.h>
  
-#if defined(CONFIG_SPL_NAND_RAW_ONLY)
+#ifdef CONFIG_PARSE_CONTAINER
+int __weak nand_load_image_parse_container(struct spl_image_info *spl_image,
+				   unsigned long offset)
+{
+	return -EINVAL;
+}
+#endif
+
 uint32_t __weak spl_nand_get_uboot_raw_page(void)
 {
        return CONFIG_SYS_NAND_U_BOOT_OFFS;
 }
  
+#if defined(CONFIG_SPL_NAND_RAW_ONLY)
 int spl_nand_load_image(struct spl_image_info *spl_image,
 			struct spl_boot_device *bootdev)
 {
  
@@ -69,11 +77,15 @@
 		load.read = spl_nand_fit_read;
 		return spl_load_simple_fit(spl_image, &load, offset, header);
 	} else {
+#ifdef CONFIG_PARSE_CONTAINER
+		return nand_load_image_parse_container(spl_image, offset);
+#else
 		err = spl_parse_image_header(spl_image, header);
 		if (err)
 			return err;
 		return nand_spl_load_image(offset, spl_image->size,
 					   (void *)(ulong)spl_image->load_addr);
+#endif
 	}
 }
  
@@ -144,7 +156,7 @@
 #endif
 #endif
 	/* Load u-boot */
-	err = spl_nand_load_element(spl_image, CONFIG_SYS_NAND_U_BOOT_OFFS,
+	err = spl_nand_load_element(spl_image, spl_nand_get_uboot_raw_page(),
 				    header);
 #ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
 #if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
@@ -14,6 +14,8 @@
  
 #ifdef CONFIG_SPL_BUILD
  
+#define CONFIG_PARSE_CONTAINER
+
 #ifdef CONFIG_QSPI_BOOT
 #define CONFIG_SPL_SPI_LOAD
 #endif
  
  
@@ -23,11 +25,13 @@
 #define CONFIG_SYS_MONITOR_LEN          (1024 * 1024)
  
 #ifdef CONFIG_NAND_BOOT
+#ifndef CONFIG_PARSE_CONTAINER
 #define CONFIG_SPL_NAND_RAW_ONLY
+#endif
 #define CONFIG_SPL_NAND_SUPPORT
 #define CONFIG_SPL_DMA_SUPPORT
 #define CONFIG_SPL_NAND_MXS
-#define CONFIG_SYS_NAND_U_BOOT_OFFS     (0x4000000)  /*Put the FIT out of first 64MB boot area */
+#define CONFIG_SYS_NAND_U_BOOT_OFFS     (0x8000000)  /*Put the FIT out of first 128MB boot area */
 #define CONFIG_SPL_NAND_BOOT
 #define CONFIG_SYS_NAND_U_BOOT_DST		0x80000000
 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (1024 * 1024 )
@@ -162,9 +166,7 @@
 	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
  
 #ifdef CONFIG_NAND_BOOT
-#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
-#else
-#define MFG_NAND_PARTITION ""
+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
 #endif
  
 #define CONFIG_MFG_ENV_SETTINGS \
@@ -175,7 +177,6 @@
 	"initrd_high=0xffffffffffffffff\0" \
 	"emmc_dev=0\0" \
 	"sd_dev=1\0" \
-	"mtdparts=mtdparts=gpmi-nand:128m(nandboot),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)\0"
  
 /* Initial environment variables */
 #ifdef CONFIG_NAND_BOOT
@@ -186,6 +187,7 @@
 		MFG_NAND_PARTITION \
 		"\0"\
 	"console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \
+	"mtdparts=" MFG_NAND_PARTITION "\0" \
 	"fdt_addr=0x83000000\0"
 #else
 #define CONFIG_EXTRA_ENV_SETTINGS		\
@@ -267,8 +269,8 @@
  
 #ifdef CONFIG_NAND_BOOT
 #define CONFIG_BOOTCOMMAND \
-	"nand read ${loadaddr} 0x8000000 0x2000000;"\
-	"nand read ${fdt_addr} 0xA000000 0x100000;"\
+	"nand read ${loadaddr} 0x9000000 0x2000000;"\
+	"nand read ${fdt_addr} 0xB000000 0x100000;"\
 	"booti ${loadaddr} - ${fdt_addr}"
 #else
 #define CONFIG_BOOTCOMMAND \
...	...	@@ -10,7 +10,7 @@
10	10	#define CONTAINER_HDR_EMMC_OFFSET 0
11	11	#define CONTAINER_HDR_MMCSD_OFFSET SZ_32K
12	12	#define CONTAINER_HDR_QSPI_OFFSET SZ_4K
13		-#define CONTAINER_HDR_NAND_OFFSET SZ_64M
	13	+#define CONTAINER_HDR_NAND_OFFSET SZ_128M
14	14
15	15	struct container_hdr{
16	16	uint8_t version;
...	...	@@ -9,6 +9,7 @@
9	9	#include <dm.h>
10	10	#include <mmc.h>
11	11	#include <spi_flash.h>
	12	+#include <nand.h>
12	13	#include <asm/arch/image.h>
13	14	#include <asm/arch/sys_proto.h>
14	15	#include <asm/mach-imx/sci/sci.h>
...	...	@@ -16,7 +17,8 @@
16	17
17	18	#define MMC_DEV 0
18	19	#define QSPI_DEV 1
19		-#define RAM_DEV 3
	20	+#define NAND_DEV 2
	21	+#define RAM_DEV 3
20	22
21	23	#define SEC_SECURE_RAM_BASE (0x31800000UL)
22	24	#define SEC_SECURE_RAM_END_BASE (SEC_SECURE_RAM_BASE + 0xFFFFUL)
...	...	@@ -39,7 +41,8 @@
39	41	{
40	42	int ret = -ENODEV;
41	43
42		- if (!device && current_dev_type != RAM_DEV) {
	44	+ if (current_dev_type != NAND_DEV && current_dev_type != RAM_DEV
	45	+ && !device) {
43	46	debug("No device selected\n");
44	47	return ret;
45	48	}
...	...	@@ -73,6 +76,15 @@
73	76	}
74	77	}
75	78	#endif
	79	+#ifdef CONFIG_SPL_NAND_SUPPORT
	80	+ if (current_dev_type == NAND_DEV) {
	81	+ ret = nand_spl_load_image(start, len, load_addr);
	82	+ if (ret != 0) {
	83	+ debug("Read container image from NAND failed\n");
	84	+ return -EIO;
	85	+ }
	86	+ }
	87	+#endif
76	88
77	89	if (current_dev_type == RAM_DEV) {
78	90	memcpy(load_addr, (const void *)(ulong)start, len);
...	...	@@ -257,6 +269,21 @@
257	269
258	270	current_dev_type = QSPI_DEV;
259	271	device = flash;
	272	+
	273	+ start_offset = offset;
	274	+
	275	+ ret = read_auth_container(spl_image);
	276	+
	277	+ return ret;
	278	+}
	279	+
	280	+int nand_load_image_parse_container(struct spl_image_info *spl_image,
	281	+ unsigned long offset)
	282	+{
	283	+ int ret = 0;
	284	+
	285	+ current_dev_type = NAND_DEV;
	286	+ device = NULL;
260	287
261	288	start_offset = offset;
262	289
...	...	@@ -12,12 +12,20 @@
12	12	#include <linux/libfdt_env.h>
13	13	#include <fdt.h>
14	14
15		-#if defined(CONFIG_SPL_NAND_RAW_ONLY)
	15	+#ifdef CONFIG_PARSE_CONTAINER
	16	+int __weak nand_load_image_parse_container(struct spl_image_info *spl_image,
	17	+ unsigned long offset)
	18	+{
	19	+ return -EINVAL;
	20	+}
	21	+#endif
	22	+
16	23	uint32_t __weak spl_nand_get_uboot_raw_page(void)
17	24	{
18	25	return CONFIG_SYS_NAND_U_BOOT_OFFS;
19	26	}
20	27
	28	+#if defined(CONFIG_SPL_NAND_RAW_ONLY)
21	29	int spl_nand_load_image(struct spl_image_info *spl_image,
22	30	struct spl_boot_device *bootdev)
23	31	{
24	32
...	...	@@ -69,11 +77,15 @@
69	77	load.read = spl_nand_fit_read;
70	78	return spl_load_simple_fit(spl_image, &load, offset, header);
71	79	} else {
	80	+#ifdef CONFIG_PARSE_CONTAINER
	81	+ return nand_load_image_parse_container(spl_image, offset);
	82	+#else
72	83	err = spl_parse_image_header(spl_image, header);
73	84	if (err)
74	85	return err;
75	86	return nand_spl_load_image(offset, spl_image->size,
76	87	(void *)(ulong)spl_image->load_addr);
	88	+#endif
77	89	}
78	90	}
79	91
...	...	@@ -144,7 +156,7 @@
144	156	#endif
145	157	#endif
146	158	/* Load u-boot */
147		- err = spl_nand_load_element(spl_image, CONFIG_SYS_NAND_U_BOOT_OFFS,
	159	+ err = spl_nand_load_element(spl_image, spl_nand_get_uboot_raw_page(),
148	160	header);
149	161	#ifdef CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
150	162	#if CONFIG_SYS_NAND_U_BOOT_OFFS != CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND
...	...	@@ -14,6 +14,8 @@
14	14
15	15	#ifdef CONFIG_SPL_BUILD
16	16
	17	+#define CONFIG_PARSE_CONTAINER
	18	+
17	19	#ifdef CONFIG_QSPI_BOOT
18	20	#define CONFIG_SPL_SPI_LOAD
19	21	#endif
20	22
21	23
...	...	@@ -23,11 +25,13 @@
23	25	#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
24	26
25	27	#ifdef CONFIG_NAND_BOOT
	28	+#ifndef CONFIG_PARSE_CONTAINER
26	29	#define CONFIG_SPL_NAND_RAW_ONLY
	30	+#endif
27	31	#define CONFIG_SPL_NAND_SUPPORT
28	32	#define CONFIG_SPL_DMA_SUPPORT
29	33	#define CONFIG_SPL_NAND_MXS
30		-#define CONFIG_SYS_NAND_U_BOOT_OFFS (0x4000000) /Put the FIT out of first 64MB boot area /
	34	+#define CONFIG_SYS_NAND_U_BOOT_OFFS (0x8000000) /Put the FIT out of first 128MB boot area /
31	35	#define CONFIG_SPL_NAND_BOOT
32	36	#define CONFIG_SYS_NAND_U_BOOT_DST 0x80000000
33	37	#define CONFIG_SYS_NAND_U_BOOT_SIZE (1024 * 1024 )
...	...	@@ -162,9 +166,7 @@
162	166	"m4boot_0=run loadm4image_0; dcache flush; bootaux ${loadaddr} 0\0" \
163	167
164	168	#ifdef CONFIG_NAND_BOOT
165		-#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
166		-#else
167		-#define MFG_NAND_PARTITION ""
	169	+#define MFG_NAND_PARTITION "mtdparts=gpmi-nand:128m(nandboot),16m(nandfit),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs) "
168	170	#endif
169	171
170	172	#define CONFIG_MFG_ENV_SETTINGS \
...	...	@@ -175,7 +177,6 @@
175	177	"initrd_high=0xffffffffffffffff\0" \
176	178	"emmc_dev=0\0" \
177	179	"sd_dev=1\0" \
178		- "mtdparts=mtdparts=gpmi-nand:128m(nandboot),32m(nandkernel),16m(nanddtb),8m(nandtee),-(nandrootfs)\0"
179	180
180	181	/* Initial environment variables */
181	182	#ifdef CONFIG_NAND_BOOT
...	...	@@ -186,6 +187,7 @@
186	187	MFG_NAND_PARTITION \
187	188	"\0"\
188	189	"console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200\0" \
	190	+ "mtdparts=" MFG_NAND_PARTITION "\0" \
189	191	"fdt_addr=0x83000000\0"
190	192	#else
191	193	#define CONFIG_EXTRA_ENV_SETTINGS \
...	...	@@ -267,8 +269,8 @@
267	269
268	270	#ifdef CONFIG_NAND_BOOT
269	271	#define CONFIG_BOOTCOMMAND \
270		- "nand read ${loadaddr} 0x8000000 0x2000000;"\
271		- "nand read ${fdt_addr} 0xA000000 0x100000;"\
	272	+ "nand read ${loadaddr} 0x9000000 0x2000000;"\
	273	+ "nand read ${fdt_addr} 0xB000000 0x100000;"\
272	274	"booti ${loadaddr} - ${fdt_addr}"
273	275	#else
274	276	#define CONFIG_BOOTCOMMAND \