phy-rcar-gen2.c
4.32 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
// SPDX-License-Identifier: GPL-2.0
/*
* Renesas RCar Gen2 USB PHY driver
*
* Copyright (C) 2018 Marek Vasut <marek.vasut@gmail.com>
*/
#include <common.h>
#include <clk.h>
#include <div64.h>
#include <dm.h>
#include <fdtdec.h>
#include <generic-phy.h>
#include <reset.h>
#include <syscon.h>
#include <usb.h>
#include <asm/io.h>
#include <linux/bitops.h>
#include <power/regulator.h>
#define USBHS_LPSTS 0x02
#define USBHS_UGCTRL 0x80
#define USBHS_UGCTRL2 0x84
#define USBHS_UGSTS 0x88 /* From technical update */
/* Low Power Status register (LPSTS) */
#define USBHS_LPSTS_SUSPM 0x4000
/* USB General control register (UGCTRL) */
#define USBHS_UGCTRL_CONNECT BIT(2)
#define USBHS_UGCTRL_PLLRESET BIT(0)
/* USB General control register 2 (UGCTRL2) */
#define USBHS_UGCTRL2_USB2SEL 0x80000000
#define USBHS_UGCTRL2_USB2SEL_PCI 0x00000000
#define USBHS_UGCTRL2_USB2SEL_USB30 0x80000000
#define USBHS_UGCTRL2_USB0SEL 0x00000030
#define USBHS_UGCTRL2_USB0SEL_PCI 0x00000010
#define USBHS_UGCTRL2_USB0SEL_HS_USB 0x00000030
/* USB General status register (UGSTS) */
#define USBHS_UGSTS_LOCK 0x00000100 /* From technical update */
#define PHYS_PER_CHANNEL 2
struct rcar_gen2_phy {
fdt_addr_t regs;
struct clk clk;
};
static int rcar_gen2_phy_phy_init(struct phy *phy)
{
struct rcar_gen2_phy *priv = dev_get_priv(phy->dev);
u16 chan = phy->id & 0xffff;
u16 mode = (phy->id >> 16) & 0xffff;
u32 clrmask, setmask;
if (chan == 0) {
clrmask = USBHS_UGCTRL2_USB0SEL;
setmask = mode ? USBHS_UGCTRL2_USB0SEL_HS_USB :
USBHS_UGCTRL2_USB0SEL_PCI;
} else {
clrmask = USBHS_UGCTRL2_USB2SEL;
setmask = mode ? USBHS_UGCTRL2_USB2SEL_USB30 :
USBHS_UGCTRL2_USB2SEL_PCI;
}
clrsetbits_le32(priv->regs + USBHS_UGCTRL2, clrmask, setmask);
return 0;
}
static int rcar_gen2_phy_phy_power_on(struct phy *phy)
{
struct rcar_gen2_phy *priv = dev_get_priv(phy->dev);
int i;
u32 value;
/* Power on USBHS PHY */
clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET);
setbits_le16(priv->regs + USBHS_LPSTS, USBHS_LPSTS_SUSPM);
for (i = 0; i < 20; i++) {
value = readl(priv->regs + USBHS_UGSTS);
if ((value & USBHS_UGSTS_LOCK) == USBHS_UGSTS_LOCK) {
setbits_le32(priv->regs + USBHS_UGCTRL,
USBHS_UGCTRL_CONNECT);
return 0;
}
udelay(1);
}
return -ETIMEDOUT;
}
static int rcar_gen2_phy_phy_power_off(struct phy *phy)
{
struct rcar_gen2_phy *priv = dev_get_priv(phy->dev);
/* Power off USBHS PHY */
clrbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_CONNECT);
clrbits_le16(priv->regs + USBHS_LPSTS, USBHS_LPSTS_SUSPM);
setbits_le32(priv->regs + USBHS_UGCTRL, USBHS_UGCTRL_PLLRESET);
return 0;
}
static int rcar_gen2_phy_of_xlate(struct phy *phy,
struct ofnode_phandle_args *args)
{
if (args->args_count != 2) {
dev_err(phy->dev, "Invalid DT PHY argument count: %d\n",
args->args_count);
return -EINVAL;
}
if (args->args[0] != 0 && args->args[0] != 2) {
dev_err(phy->dev, "Invalid DT PHY channel: %d\n",
args->args[0]);
return -EINVAL;
}
if (args->args[1] != 0 && args->args[1] != 1) {
dev_err(phy->dev, "Invalid DT PHY mode: %d\n",
args->args[1]);
return -EINVAL;
}
if (args->args_count)
phy->id = args->args[0] | (args->args[1] << 16);
else
phy->id = 0;
return 0;
}
static const struct phy_ops rcar_gen2_phy_phy_ops = {
.init = rcar_gen2_phy_phy_init,
.power_on = rcar_gen2_phy_phy_power_on,
.power_off = rcar_gen2_phy_phy_power_off,
.of_xlate = rcar_gen2_phy_of_xlate,
};
static int rcar_gen2_phy_probe(struct udevice *dev)
{
struct rcar_gen2_phy *priv = dev_get_priv(dev);
int ret;
priv->regs = dev_read_addr(dev);
if (priv->regs == FDT_ADDR_T_NONE)
return -EINVAL;
/* Enable clock */
ret = clk_get_by_index(dev, 0, &priv->clk);
if (ret)
return ret;
ret = clk_enable(&priv->clk);
if (ret)
return ret;
return 0;
}
static int rcar_gen2_phy_remove(struct udevice *dev)
{
struct rcar_gen2_phy *priv = dev_get_priv(dev);
clk_disable(&priv->clk);
clk_free(&priv->clk);
return 0;
}
static const struct udevice_id rcar_gen2_phy_of_match[] = {
{ .compatible = "renesas,rcar-gen2-usb-phy", },
{ },
};
U_BOOT_DRIVER(rcar_gen2_phy) = {
.name = "rcar-gen2-phy",
.id = UCLASS_PHY,
.of_match = rcar_gen2_phy_of_match,
.ops = &rcar_gen2_phy_phy_ops,
.probe = rcar_gen2_phy_probe,
.remove = rcar_gen2_phy_remove,
.priv_auto_alloc_size = sizeof(struct rcar_gen2_phy),
};