ramtest.c
1.36 KB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
/*
* Copyright (c) 2014 Google, Inc
*
* From Coreboot src/lib/ramtest.c
*
* SPDX-License-Identifier: GPL-2.0
*/
#include <common.h>
#include <asm/io.h>
#include <asm/post.h>
static void write_phys(unsigned long addr, u32 value)
{
#if CONFIG_SSE2
asm volatile(
"movnti %1, (%0)"
: /* outputs */
: "r" (addr), "r" (value) /* inputs */
: /* clobbers */
);
#else
writel(value, addr);
#endif
}
static u32 read_phys(unsigned long addr)
{
return readl(addr);
}
static void phys_memory_barrier(void)
{
#if CONFIG_SSE2
/* Needed for movnti */
asm volatile(
"sfence"
:
:
: "memory"
);
#else
asm volatile(""
:
:
: "memory");
#endif
}
void quick_ram_check(void)
{
int fail = 0;
u32 backup;
backup = read_phys(CONFIG_RAMBASE);
write_phys(CONFIG_RAMBASE, 0x55555555);
phys_memory_barrier();
if (read_phys(CONFIG_RAMBASE) != 0x55555555)
fail = 1;
write_phys(CONFIG_RAMBASE, 0xaaaaaaaa);
phys_memory_barrier();
if (read_phys(CONFIG_RAMBASE) != 0xaaaaaaaa)
fail = 1;
write_phys(CONFIG_RAMBASE, 0x00000000);
phys_memory_barrier();
if (read_phys(CONFIG_RAMBASE) != 0x00000000)
fail = 1;
write_phys(CONFIG_RAMBASE, 0xffffffff);
phys_memory_barrier();
if (read_phys(CONFIG_RAMBASE) != 0xffffffff)
fail = 1;
write_phys(CONFIG_RAMBASE, backup);
if (fail) {
post_code(POST_RAM_FAILURE);
panic("RAM INIT FAILURE!\n");
}
phys_memory_barrier();
}