Commit 004425871380ffe110142b149d71bf32d0607720
1 parent
53644801c5
Exists in
smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga
and in
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Remove redundant files
Showing 5 changed files with 0 additions and 4522 deletions Inline Diff
board/embedian/embedian/smarcimx8mq/Kconfig
| 1 | if TARGET_SMARCIMX8MQ | File was deleted | |
| 2 | |||
| 3 | config SYS_BOARD | ||
| 4 | default "smarcimx8mq" | ||
| 5 | |||
| 6 | config SYS_VENDOR | ||
| 7 | default "embedian" | ||
| 8 | |||
| 9 | config SYS_CONFIG_NAME | ||
| 10 | default "smarcimx8mq" | ||
| 11 | |||
| 12 | endif | ||
| 13 | 1 | if TARGET_SMARCIMX8MQ |
board/embedian/embedian/smarcimx8mq/Makefile
| 1 | # | File was deleted | |
| 2 | # Copyright 2016 Freescale Semiconductor | ||
| 3 | # | ||
| 4 | # SPDX-License-Identifier: GPL-2.0+ | ||
| 5 | # | ||
| 6 | |||
| 7 | obj-y += smarcimx8mq.o | ||
| 8 | |||
| 9 | obj-$(CONFIG_POWER_PFUZE100) += ../../freescale/common/pfuze.o | ||
| 10 | |||
| 11 | ifdef CONFIG_SPL_BUILD | ||
| 12 | obj-y += spl.o | ||
| 13 | obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o | ||
| 14 | endif | ||
| 15 | 1 | # |
board/embedian/embedian/smarcimx8mq/lpddr4_timing.c
| 1 | /* | File was deleted | |
| 2 | * Copyright 2018 NXP | ||
| 3 | * | ||
| 4 | * SPDX-License-Identifier: GPL-2.0+ | ||
| 5 | * | ||
| 6 | * Generated code from MX8M_DDR_tool | ||
| 7 | * Align with uboot-imx_v2018.03_4.14.78_1.0.0_ga | ||
| 8 | */ | ||
| 9 | |||
| 10 | #include <linux/kernel.h> | ||
| 11 | #include <asm/arch/imx8m_ddr.h> | ||
| 12 | #include <common.h> | ||
| 13 | #if defined(CONFIG_2GB_LPDDR4) | ||
| 14 | struct dram_cfg_param ddr_ddrc_cfg[] = { | ||
| 15 | /** Initialize DDRC registers **/ | ||
| 16 | {0x3d400304,0x1}, | ||
| 17 | {0x3d400030,0x1}, | ||
| 18 | {0x3d400000,0xa1080020}, | ||
| 19 | {0x3d400028,0x0}, | ||
| 20 | {0x3d400020,0x203}, | ||
| 21 | {0x3d400024,0x3e800}, | ||
| 22 | {0x3d400064,0x6100e0}, | ||
| 23 | {0x3d4000d0,0xc003061c}, | ||
| 24 | {0x3d4000d4,0x9e0000}, | ||
| 25 | {0x3d4000dc,0xd4002d}, | ||
| 26 | {0x3d4000e0,0x310008}, | ||
| 27 | {0x3d4000e8,0x66004a}, | ||
| 28 | {0x3d4000ec,0x16004a}, | ||
| 29 | {0x3d400100,0x1a201b22}, | ||
| 30 | {0x3d400104,0x60633}, | ||
| 31 | {0x3d40010c,0xc0c000}, | ||
| 32 | {0x3d400110,0xf04080f}, | ||
| 33 | {0x3d400114,0x2040c0c}, | ||
| 34 | {0x3d400118,0x1010007}, | ||
| 35 | {0x3d40011c,0x401}, | ||
| 36 | {0x3d400130,0x20600}, | ||
| 37 | {0x3d400134,0xc100002}, | ||
| 38 | {0x3d400138,0xe6}, | ||
| 39 | {0x3d400144,0xa00050}, | ||
| 40 | {0x3d400180,0xc3200018}, | ||
| 41 | {0x3d400184,0x28061a8}, | ||
| 42 | {0x3d400188,0x0}, | ||
| 43 | {0x3d400190,0x497820a}, | ||
| 44 | {0x3d400194,0x80303}, | ||
| 45 | {0x3d4001a0,0xe0400018}, | ||
| 46 | {0x3d4001a4,0xdf00e4}, | ||
| 47 | {0x3d4001a8,0x80000000}, | ||
| 48 | {0x3d4001b0,0x11}, | ||
| 49 | {0x3d4001b4,0x170a}, | ||
| 50 | {0x3d4001c0,0x1}, | ||
| 51 | {0x3d4001c4,0x1}, | ||
| 52 | {0x3d4000f4,0x639}, | ||
| 53 | {0x3d400108,0x70e1617}, | ||
| 54 | {0x3d400200,0x1f}, | ||
| 55 | {0x3d40020c,0x0}, | ||
| 56 | {0x3d400210,0x1f1f}, | ||
| 57 | {0x3d400204,0x80808}, | ||
| 58 | {0x3d400214,0x7070707}, | ||
| 59 | {0x3d400218,0x7070707}, | ||
| 60 | {0x3d402020,0x1}, | ||
| 61 | {0x3d402024,0xd0c0}, | ||
| 62 | {0x3d402050,0x20d040}, | ||
| 63 | {0x3d402064,0x14002f}, | ||
| 64 | {0x3d4020dc,0x940009}, | ||
| 65 | {0x3d4020e0,0x310000}, | ||
| 66 | {0x3d4020e8,0x66004a}, | ||
| 67 | {0x3d4020ec,0x16004a}, | ||
| 68 | {0x3d402100,0xb070508}, | ||
| 69 | {0x3d402104,0x3040b}, | ||
| 70 | {0x3d402108,0x305090c}, | ||
| 71 | {0x3d40210c,0x505000}, | ||
| 72 | {0x3d402110,0x4040204}, | ||
| 73 | {0x3d402114,0x2030303}, | ||
| 74 | {0x3d402118,0x1010004}, | ||
| 75 | {0x3d40211c,0x301}, | ||
| 76 | {0x3d402130,0x20300}, | ||
| 77 | {0x3d402134,0xa100002}, | ||
| 78 | {0x3d402138,0x31}, | ||
| 79 | {0x3d402144,0x220011}, | ||
| 80 | {0x3d402180,0xc0a70006}, | ||
| 81 | {0x3d402190,0x3858202}, | ||
| 82 | {0x3d402194,0x80303}, | ||
| 83 | {0x3d4021b4,0x502}, | ||
| 84 | {0x3d400244,0x0}, | ||
| 85 | {0x3d400250,0x29001505}, | ||
| 86 | {0x3d400254,0x2c}, | ||
| 87 | {0x3d40025c,0x5900575b}, | ||
| 88 | {0x3d400264,0x90000096}, | ||
| 89 | {0x3d40026c,0x1000012c}, | ||
| 90 | {0x3d400300,0x16}, | ||
| 91 | {0x3d400304,0x0}, | ||
| 92 | {0x3d40030c,0x0}, | ||
| 93 | {0x3d400320,0x1}, | ||
| 94 | {0x3d40036c,0x11}, | ||
| 95 | {0x3d400400,0x111}, | ||
| 96 | {0x3d400404,0x10f3}, | ||
| 97 | {0x3d400408,0x72ff}, | ||
| 98 | {0x3d400490,0x1}, | ||
| 99 | {0x3d400494,0xe00}, | ||
| 100 | {0x3d400498,0x62ffff}, | ||
| 101 | {0x3d40049c,0xe00}, | ||
| 102 | {0x3d4004a0,0xffff}, | ||
| 103 | }; | ||
| 104 | |||
| 105 | /* PHY Initialize Configuration */ | ||
| 106 | struct dram_cfg_param ddr_ddrphy_cfg[] = { | ||
| 107 | {0x100a0,0x0}, | ||
| 108 | {0x100a1,0x1}, | ||
| 109 | {0x100a2,0x2}, | ||
| 110 | {0x100a3,0x3}, | ||
| 111 | {0x100a4,0x4}, | ||
| 112 | {0x100a5,0x5}, | ||
| 113 | {0x100a6,0x6}, | ||
| 114 | {0x100a7,0x7}, | ||
| 115 | {0x110a0,0x0}, | ||
| 116 | {0x110a1,0x1}, | ||
| 117 | {0x110a2,0x2}, | ||
| 118 | {0x110a3,0x3}, | ||
| 119 | {0x110a4,0x4}, | ||
| 120 | {0x110a5,0x7}, | ||
| 121 | {0x110a6,0x6}, | ||
| 122 | {0x110a7,0x5}, | ||
| 123 | {0x120a0,0x0}, | ||
| 124 | {0x120a1,0x1}, | ||
| 125 | {0x120a2,0x2}, | ||
| 126 | {0x120a3,0x3}, | ||
| 127 | {0x120a4,0x4}, | ||
| 128 | {0x120a5,0x5}, | ||
| 129 | {0x120a6,0x6}, | ||
| 130 | {0x120a7,0x7}, | ||
| 131 | {0x130a0,0x0}, | ||
| 132 | {0x130a1,0x1}, | ||
| 133 | {0x130a2,0x2}, | ||
| 134 | {0x130a3,0x3}, | ||
| 135 | {0x130a4,0x4}, | ||
| 136 | {0x130a5,0x5}, | ||
| 137 | {0x130a6,0x6}, | ||
| 138 | {0x130a7,0x7}, | ||
| 139 | {0x20110,0x2}, | ||
| 140 | {0x20111,0x3}, | ||
| 141 | {0x20112,0x4}, | ||
| 142 | {0x20113,0x5}, | ||
| 143 | {0x20114,0x0}, | ||
| 144 | {0x20115,0x1}, | ||
| 145 | {0x1005f,0x1ff}, | ||
| 146 | {0x1015f,0x1ff}, | ||
| 147 | {0x1105f,0x1ff}, | ||
| 148 | {0x1115f,0x1ff}, | ||
| 149 | {0x1205f,0x1ff}, | ||
| 150 | {0x1215f,0x1ff}, | ||
| 151 | {0x1305f,0x1ff}, | ||
| 152 | {0x1315f,0x1ff}, | ||
| 153 | {0x11005f,0x1ff}, | ||
| 154 | {0x11015f,0x1ff}, | ||
| 155 | {0x11105f,0x1ff}, | ||
| 156 | {0x11115f,0x1ff}, | ||
| 157 | {0x11205f,0x1ff}, | ||
| 158 | {0x11215f,0x1ff}, | ||
| 159 | {0x11305f,0x1ff}, | ||
| 160 | {0x11315f,0x1ff}, | ||
| 161 | {0x55,0x1ff}, | ||
| 162 | {0x1055,0x1ff}, | ||
| 163 | {0x2055,0x1ff}, | ||
| 164 | {0x3055,0x1ff}, | ||
| 165 | {0x4055,0x1ff}, | ||
| 166 | {0x5055,0x1ff}, | ||
| 167 | {0x6055,0x1ff}, | ||
| 168 | {0x7055,0x1ff}, | ||
| 169 | {0x8055,0x1ff}, | ||
| 170 | {0x9055,0x1ff}, | ||
| 171 | {0x200c5,0x19}, | ||
| 172 | {0x1200c5,0x7}, | ||
| 173 | {0x2002e,0x2}, | ||
| 174 | {0x12002e,0x1}, | ||
| 175 | {0x90204,0x0}, | ||
| 176 | {0x190204,0x0}, | ||
| 177 | {0x20024,0x1ab}, | ||
| 178 | {0x2003a,0x0}, | ||
| 179 | {0x120024,0x1ab}, | ||
| 180 | {0x2003a,0x0}, | ||
| 181 | {0x20056,0x3}, | ||
| 182 | {0x120056,0xa}, | ||
| 183 | {0x1004d,0xe00}, | ||
| 184 | {0x1014d,0xe00}, | ||
| 185 | {0x1104d,0xe00}, | ||
| 186 | {0x1114d,0xe00}, | ||
| 187 | {0x1204d,0xe00}, | ||
| 188 | {0x1214d,0xe00}, | ||
| 189 | {0x1304d,0xe00}, | ||
| 190 | {0x1314d,0xe00}, | ||
| 191 | {0x11004d,0xe00}, | ||
| 192 | {0x11014d,0xe00}, | ||
| 193 | {0x11104d,0xe00}, | ||
| 194 | {0x11114d,0xe00}, | ||
| 195 | {0x11204d,0xe00}, | ||
| 196 | {0x11214d,0xe00}, | ||
| 197 | {0x11304d,0xe00}, | ||
| 198 | {0x11314d,0xe00}, | ||
| 199 | {0x10049,0xeba}, | ||
| 200 | {0x10149,0xeba}, | ||
| 201 | {0x11049,0xeba}, | ||
| 202 | {0x11149,0xeba}, | ||
| 203 | {0x12049,0xeba}, | ||
| 204 | {0x12149,0xeba}, | ||
| 205 | {0x13049,0xeba}, | ||
| 206 | {0x13149,0xeba}, | ||
| 207 | {0x110049,0xeba}, | ||
| 208 | {0x110149,0xeba}, | ||
| 209 | {0x111049,0xeba}, | ||
| 210 | {0x111149,0xeba}, | ||
| 211 | {0x112049,0xeba}, | ||
| 212 | {0x112149,0xeba}, | ||
| 213 | {0x113049,0xeba}, | ||
| 214 | {0x113149,0xeba}, | ||
| 215 | {0x43,0x63}, | ||
| 216 | {0x1043,0x63}, | ||
| 217 | {0x2043,0x63}, | ||
| 218 | {0x3043,0x63}, | ||
| 219 | {0x4043,0x63}, | ||
| 220 | {0x5043,0x63}, | ||
| 221 | {0x6043,0x63}, | ||
| 222 | {0x7043,0x63}, | ||
| 223 | {0x8043,0x63}, | ||
| 224 | {0x9043,0x63}, | ||
| 225 | {0x20018,0x3}, | ||
| 226 | {0x20075,0x4}, | ||
| 227 | {0x20050,0x0}, | ||
| 228 | {0x20008,0x320}, | ||
| 229 | {0x120008,0xa7}, | ||
| 230 | {0x20088,0x9}, | ||
| 231 | {0x200b2,0xdc}, | ||
| 232 | {0x10043,0x5a1}, | ||
| 233 | {0x10143,0x5a1}, | ||
| 234 | {0x11043,0x5a1}, | ||
| 235 | {0x11143,0x5a1}, | ||
| 236 | {0x12043,0x5a1}, | ||
| 237 | {0x12143,0x5a1}, | ||
| 238 | {0x13043,0x5a1}, | ||
| 239 | {0x13143,0x5a1}, | ||
| 240 | {0x1200b2,0xdc}, | ||
| 241 | {0x110043,0x5a1}, | ||
| 242 | {0x110143,0x5a1}, | ||
| 243 | {0x111043,0x5a1}, | ||
| 244 | {0x111143,0x5a1}, | ||
| 245 | {0x112043,0x5a1}, | ||
| 246 | {0x112143,0x5a1}, | ||
| 247 | {0x113043,0x5a1}, | ||
| 248 | {0x113143,0x5a1}, | ||
| 249 | {0x200fa,0x1}, | ||
| 250 | {0x1200fa,0x1}, | ||
| 251 | {0x20019,0x1}, | ||
| 252 | {0x120019,0x1}, | ||
| 253 | {0x200f0,0x0}, | ||
| 254 | {0x200f1,0x0}, | ||
| 255 | {0x200f2,0x4444}, | ||
| 256 | {0x200f3,0x8888}, | ||
| 257 | {0x200f4,0x5555}, | ||
| 258 | {0x200f5,0x0}, | ||
| 259 | {0x200f6,0x0}, | ||
| 260 | {0x200f7,0xf000}, | ||
| 261 | {0x20025,0x0}, | ||
| 262 | {0x2002d,0x0}, | ||
| 263 | {0x12002d,0x0}, | ||
| 264 | {0x200c7,0x80}, | ||
| 265 | {0x1200c7,0x80}, | ||
| 266 | {0x200ca,0x106}, | ||
| 267 | {0x1200ca,0x106}, | ||
| 268 | }; | ||
| 269 | |||
| 270 | /* ddr phy trained csr */ | ||
| 271 | struct dram_cfg_param ddr_ddrphy_trained_csr[] = { | ||
| 272 | { 0x200b2, 0x0 }, | ||
| 273 | { 0x1200b2, 0x0 }, | ||
| 274 | { 0x2200b2, 0x0 }, | ||
| 275 | { 0x200cb, 0x0 }, | ||
| 276 | { 0x10043, 0x0 }, | ||
| 277 | { 0x110043, 0x0 }, | ||
| 278 | { 0x210043, 0x0 }, | ||
| 279 | { 0x10143, 0x0 }, | ||
| 280 | { 0x110143, 0x0 }, | ||
| 281 | { 0x210143, 0x0 }, | ||
| 282 | { 0x11043, 0x0 }, | ||
| 283 | { 0x111043, 0x0 }, | ||
| 284 | { 0x211043, 0x0 }, | ||
| 285 | { 0x11143, 0x0 }, | ||
| 286 | { 0x111143, 0x0 }, | ||
| 287 | { 0x211143, 0x0 }, | ||
| 288 | { 0x12043, 0x0 }, | ||
| 289 | { 0x112043, 0x0 }, | ||
| 290 | { 0x212043, 0x0 }, | ||
| 291 | { 0x12143, 0x0 }, | ||
| 292 | { 0x112143, 0x0 }, | ||
| 293 | { 0x212143, 0x0 }, | ||
| 294 | { 0x13043, 0x0 }, | ||
| 295 | { 0x113043, 0x0 }, | ||
| 296 | { 0x213043, 0x0 }, | ||
| 297 | { 0x13143, 0x0 }, | ||
| 298 | { 0x113143, 0x0 }, | ||
| 299 | { 0x213143, 0x0 }, | ||
| 300 | { 0x80, 0x0 }, | ||
| 301 | { 0x100080, 0x0 }, | ||
| 302 | { 0x200080, 0x0 }, | ||
| 303 | { 0x1080, 0x0 }, | ||
| 304 | { 0x101080, 0x0 }, | ||
| 305 | { 0x201080, 0x0 }, | ||
| 306 | { 0x2080, 0x0 }, | ||
| 307 | { 0x102080, 0x0 }, | ||
| 308 | { 0x202080, 0x0 }, | ||
| 309 | { 0x3080, 0x0 }, | ||
| 310 | { 0x103080, 0x0 }, | ||
| 311 | { 0x203080, 0x0 }, | ||
| 312 | { 0x4080, 0x0 }, | ||
| 313 | { 0x104080, 0x0 }, | ||
| 314 | { 0x204080, 0x0 }, | ||
| 315 | { 0x5080, 0x0 }, | ||
| 316 | { 0x105080, 0x0 }, | ||
| 317 | { 0x205080, 0x0 }, | ||
| 318 | { 0x6080, 0x0 }, | ||
| 319 | { 0x106080, 0x0 }, | ||
| 320 | { 0x206080, 0x0 }, | ||
| 321 | { 0x7080, 0x0 }, | ||
| 322 | { 0x107080, 0x0 }, | ||
| 323 | { 0x207080, 0x0 }, | ||
| 324 | { 0x8080, 0x0 }, | ||
| 325 | { 0x108080, 0x0 }, | ||
| 326 | { 0x208080, 0x0 }, | ||
| 327 | { 0x9080, 0x0 }, | ||
| 328 | { 0x109080, 0x0 }, | ||
| 329 | { 0x209080, 0x0 }, | ||
| 330 | { 0x10080, 0x0 }, | ||
| 331 | { 0x110080, 0x0 }, | ||
| 332 | { 0x210080, 0x0 }, | ||
| 333 | { 0x10180, 0x0 }, | ||
| 334 | { 0x110180, 0x0 }, | ||
| 335 | { 0x210180, 0x0 }, | ||
| 336 | { 0x11080, 0x0 }, | ||
| 337 | { 0x111080, 0x0 }, | ||
| 338 | { 0x211080, 0x0 }, | ||
| 339 | { 0x11180, 0x0 }, | ||
| 340 | { 0x111180, 0x0 }, | ||
| 341 | { 0x211180, 0x0 }, | ||
| 342 | { 0x12080, 0x0 }, | ||
| 343 | { 0x112080, 0x0 }, | ||
| 344 | { 0x212080, 0x0 }, | ||
| 345 | { 0x12180, 0x0 }, | ||
| 346 | { 0x112180, 0x0 }, | ||
| 347 | { 0x212180, 0x0 }, | ||
| 348 | { 0x13080, 0x0 }, | ||
| 349 | { 0x113080, 0x0 }, | ||
| 350 | { 0x213080, 0x0 }, | ||
| 351 | { 0x13180, 0x0 }, | ||
| 352 | { 0x113180, 0x0 }, | ||
| 353 | { 0x213180, 0x0 }, | ||
| 354 | { 0x10081, 0x0 }, | ||
| 355 | { 0x110081, 0x0 }, | ||
| 356 | { 0x210081, 0x0 }, | ||
| 357 | { 0x10181, 0x0 }, | ||
| 358 | { 0x110181, 0x0 }, | ||
| 359 | { 0x210181, 0x0 }, | ||
| 360 | { 0x11081, 0x0 }, | ||
| 361 | { 0x111081, 0x0 }, | ||
| 362 | { 0x211081, 0x0 }, | ||
| 363 | { 0x11181, 0x0 }, | ||
| 364 | { 0x111181, 0x0 }, | ||
| 365 | { 0x211181, 0x0 }, | ||
| 366 | { 0x12081, 0x0 }, | ||
| 367 | { 0x112081, 0x0 }, | ||
| 368 | { 0x212081, 0x0 }, | ||
| 369 | { 0x12181, 0x0 }, | ||
| 370 | { 0x112181, 0x0 }, | ||
| 371 | { 0x212181, 0x0 }, | ||
| 372 | { 0x13081, 0x0 }, | ||
| 373 | { 0x113081, 0x0 }, | ||
| 374 | { 0x213081, 0x0 }, | ||
| 375 | { 0x13181, 0x0 }, | ||
| 376 | { 0x113181, 0x0 }, | ||
| 377 | { 0x213181, 0x0 }, | ||
| 378 | { 0x100d0, 0x0 }, | ||
| 379 | { 0x1100d0, 0x0 }, | ||
| 380 | { 0x2100d0, 0x0 }, | ||
| 381 | { 0x101d0, 0x0 }, | ||
| 382 | { 0x1101d0, 0x0 }, | ||
| 383 | { 0x2101d0, 0x0 }, | ||
| 384 | { 0x110d0, 0x0 }, | ||
| 385 | { 0x1110d0, 0x0 }, | ||
| 386 | { 0x2110d0, 0x0 }, | ||
| 387 | { 0x111d0, 0x0 }, | ||
| 388 | { 0x1111d0, 0x0 }, | ||
| 389 | { 0x2111d0, 0x0 }, | ||
| 390 | { 0x120d0, 0x0 }, | ||
| 391 | { 0x1120d0, 0x0 }, | ||
| 392 | { 0x2120d0, 0x0 }, | ||
| 393 | { 0x121d0, 0x0 }, | ||
| 394 | { 0x1121d0, 0x0 }, | ||
| 395 | { 0x2121d0, 0x0 }, | ||
| 396 | { 0x130d0, 0x0 }, | ||
| 397 | { 0x1130d0, 0x0 }, | ||
| 398 | { 0x2130d0, 0x0 }, | ||
| 399 | { 0x131d0, 0x0 }, | ||
| 400 | { 0x1131d0, 0x0 }, | ||
| 401 | { 0x2131d0, 0x0 }, | ||
| 402 | { 0x100d1, 0x0 }, | ||
| 403 | { 0x1100d1, 0x0 }, | ||
| 404 | { 0x2100d1, 0x0 }, | ||
| 405 | { 0x101d1, 0x0 }, | ||
| 406 | { 0x1101d1, 0x0 }, | ||
| 407 | { 0x2101d1, 0x0 }, | ||
| 408 | { 0x110d1, 0x0 }, | ||
| 409 | { 0x1110d1, 0x0 }, | ||
| 410 | { 0x2110d1, 0x0 }, | ||
| 411 | { 0x111d1, 0x0 }, | ||
| 412 | { 0x1111d1, 0x0 }, | ||
| 413 | { 0x2111d1, 0x0 }, | ||
| 414 | { 0x120d1, 0x0 }, | ||
| 415 | { 0x1120d1, 0x0 }, | ||
| 416 | { 0x2120d1, 0x0 }, | ||
| 417 | { 0x121d1, 0x0 }, | ||
| 418 | { 0x1121d1, 0x0 }, | ||
| 419 | { 0x2121d1, 0x0 }, | ||
| 420 | { 0x130d1, 0x0 }, | ||
| 421 | { 0x1130d1, 0x0 }, | ||
| 422 | { 0x2130d1, 0x0 }, | ||
| 423 | { 0x131d1, 0x0 }, | ||
| 424 | { 0x1131d1, 0x0 }, | ||
| 425 | { 0x2131d1, 0x0 }, | ||
| 426 | { 0x10068, 0x0 }, | ||
| 427 | { 0x10168, 0x0 }, | ||
| 428 | { 0x10268, 0x0 }, | ||
| 429 | { 0x10368, 0x0 }, | ||
| 430 | { 0x10468, 0x0 }, | ||
| 431 | { 0x10568, 0x0 }, | ||
| 432 | { 0x10668, 0x0 }, | ||
| 433 | { 0x10768, 0x0 }, | ||
| 434 | { 0x10868, 0x0 }, | ||
| 435 | { 0x11068, 0x0 }, | ||
| 436 | { 0x11168, 0x0 }, | ||
| 437 | { 0x11268, 0x0 }, | ||
| 438 | { 0x11368, 0x0 }, | ||
| 439 | { 0x11468, 0x0 }, | ||
| 440 | { 0x11568, 0x0 }, | ||
| 441 | { 0x11668, 0x0 }, | ||
| 442 | { 0x11768, 0x0 }, | ||
| 443 | { 0x11868, 0x0 }, | ||
| 444 | { 0x12068, 0x0 }, | ||
| 445 | { 0x12168, 0x0 }, | ||
| 446 | { 0x12268, 0x0 }, | ||
| 447 | { 0x12368, 0x0 }, | ||
| 448 | { 0x12468, 0x0 }, | ||
| 449 | { 0x12568, 0x0 }, | ||
| 450 | { 0x12668, 0x0 }, | ||
| 451 | { 0x12768, 0x0 }, | ||
| 452 | { 0x12868, 0x0 }, | ||
| 453 | { 0x13068, 0x0 }, | ||
| 454 | { 0x13168, 0x0 }, | ||
| 455 | { 0x13268, 0x0 }, | ||
| 456 | { 0x13368, 0x0 }, | ||
| 457 | { 0x13468, 0x0 }, | ||
| 458 | { 0x13568, 0x0 }, | ||
| 459 | { 0x13668, 0x0 }, | ||
| 460 | { 0x13768, 0x0 }, | ||
| 461 | { 0x13868, 0x0 }, | ||
| 462 | { 0x10069, 0x0 }, | ||
| 463 | { 0x10169, 0x0 }, | ||
| 464 | { 0x10269, 0x0 }, | ||
| 465 | { 0x10369, 0x0 }, | ||
| 466 | { 0x10469, 0x0 }, | ||
| 467 | { 0x10569, 0x0 }, | ||
| 468 | { 0x10669, 0x0 }, | ||
| 469 | { 0x10769, 0x0 }, | ||
| 470 | { 0x10869, 0x0 }, | ||
| 471 | { 0x11069, 0x0 }, | ||
| 472 | { 0x11169, 0x0 }, | ||
| 473 | { 0x11269, 0x0 }, | ||
| 474 | { 0x11369, 0x0 }, | ||
| 475 | { 0x11469, 0x0 }, | ||
| 476 | { 0x11569, 0x0 }, | ||
| 477 | { 0x11669, 0x0 }, | ||
| 478 | { 0x11769, 0x0 }, | ||
| 479 | { 0x11869, 0x0 }, | ||
| 480 | { 0x12069, 0x0 }, | ||
| 481 | { 0x12169, 0x0 }, | ||
| 482 | { 0x12269, 0x0 }, | ||
| 483 | { 0x12369, 0x0 }, | ||
| 484 | { 0x12469, 0x0 }, | ||
| 485 | { 0x12569, 0x0 }, | ||
| 486 | { 0x12669, 0x0 }, | ||
| 487 | { 0x12769, 0x0 }, | ||
| 488 | { 0x12869, 0x0 }, | ||
| 489 | { 0x13069, 0x0 }, | ||
| 490 | { 0x13169, 0x0 }, | ||
| 491 | { 0x13269, 0x0 }, | ||
| 492 | { 0x13369, 0x0 }, | ||
| 493 | { 0x13469, 0x0 }, | ||
| 494 | { 0x13569, 0x0 }, | ||
| 495 | { 0x13669, 0x0 }, | ||
| 496 | { 0x13769, 0x0 }, | ||
| 497 | { 0x13869, 0x0 }, | ||
| 498 | { 0x1008c, 0x0 }, | ||
| 499 | { 0x11008c, 0x0 }, | ||
| 500 | { 0x21008c, 0x0 }, | ||
| 501 | { 0x1018c, 0x0 }, | ||
| 502 | { 0x11018c, 0x0 }, | ||
| 503 | { 0x21018c, 0x0 }, | ||
| 504 | { 0x1108c, 0x0 }, | ||
| 505 | { 0x11108c, 0x0 }, | ||
| 506 | { 0x21108c, 0x0 }, | ||
| 507 | { 0x1118c, 0x0 }, | ||
| 508 | { 0x11118c, 0x0 }, | ||
| 509 | { 0x21118c, 0x0 }, | ||
| 510 | { 0x1208c, 0x0 }, | ||
| 511 | { 0x11208c, 0x0 }, | ||
| 512 | { 0x21208c, 0x0 }, | ||
| 513 | { 0x1218c, 0x0 }, | ||
| 514 | { 0x11218c, 0x0 }, | ||
| 515 | { 0x21218c, 0x0 }, | ||
| 516 | { 0x1308c, 0x0 }, | ||
| 517 | { 0x11308c, 0x0 }, | ||
| 518 | { 0x21308c, 0x0 }, | ||
| 519 | { 0x1318c, 0x0 }, | ||
| 520 | { 0x11318c, 0x0 }, | ||
| 521 | { 0x21318c, 0x0 }, | ||
| 522 | { 0x1008d, 0x0 }, | ||
| 523 | { 0x11008d, 0x0 }, | ||
| 524 | { 0x21008d, 0x0 }, | ||
| 525 | { 0x1018d, 0x0 }, | ||
| 526 | { 0x11018d, 0x0 }, | ||
| 527 | { 0x21018d, 0x0 }, | ||
| 528 | { 0x1108d, 0x0 }, | ||
| 529 | { 0x11108d, 0x0 }, | ||
| 530 | { 0x21108d, 0x0 }, | ||
| 531 | { 0x1118d, 0x0 }, | ||
| 532 | { 0x11118d, 0x0 }, | ||
| 533 | { 0x21118d, 0x0 }, | ||
| 534 | { 0x1208d, 0x0 }, | ||
| 535 | { 0x11208d, 0x0 }, | ||
| 536 | { 0x21208d, 0x0 }, | ||
| 537 | { 0x1218d, 0x0 }, | ||
| 538 | { 0x11218d, 0x0 }, | ||
| 539 | { 0x21218d, 0x0 }, | ||
| 540 | { 0x1308d, 0x0 }, | ||
| 541 | { 0x11308d, 0x0 }, | ||
| 542 | { 0x21308d, 0x0 }, | ||
| 543 | { 0x1318d, 0x0 }, | ||
| 544 | { 0x11318d, 0x0 }, | ||
| 545 | { 0x21318d, 0x0 }, | ||
| 546 | { 0x100c0, 0x0 }, | ||
| 547 | { 0x1100c0, 0x0 }, | ||
| 548 | { 0x2100c0, 0x0 }, | ||
| 549 | { 0x101c0, 0x0 }, | ||
| 550 | { 0x1101c0, 0x0 }, | ||
| 551 | { 0x2101c0, 0x0 }, | ||
| 552 | { 0x102c0, 0x0 }, | ||
| 553 | { 0x1102c0, 0x0 }, | ||
| 554 | { 0x2102c0, 0x0 }, | ||
| 555 | { 0x103c0, 0x0 }, | ||
| 556 | { 0x1103c0, 0x0 }, | ||
| 557 | { 0x2103c0, 0x0 }, | ||
| 558 | { 0x104c0, 0x0 }, | ||
| 559 | { 0x1104c0, 0x0 }, | ||
| 560 | { 0x2104c0, 0x0 }, | ||
| 561 | { 0x105c0, 0x0 }, | ||
| 562 | { 0x1105c0, 0x0 }, | ||
| 563 | { 0x2105c0, 0x0 }, | ||
| 564 | { 0x106c0, 0x0 }, | ||
| 565 | { 0x1106c0, 0x0 }, | ||
| 566 | { 0x2106c0, 0x0 }, | ||
| 567 | { 0x107c0, 0x0 }, | ||
| 568 | { 0x1107c0, 0x0 }, | ||
| 569 | { 0x2107c0, 0x0 }, | ||
| 570 | { 0x108c0, 0x0 }, | ||
| 571 | { 0x1108c0, 0x0 }, | ||
| 572 | { 0x2108c0, 0x0 }, | ||
| 573 | { 0x110c0, 0x0 }, | ||
| 574 | { 0x1110c0, 0x0 }, | ||
| 575 | { 0x2110c0, 0x0 }, | ||
| 576 | { 0x111c0, 0x0 }, | ||
| 577 | { 0x1111c0, 0x0 }, | ||
| 578 | { 0x2111c0, 0x0 }, | ||
| 579 | { 0x112c0, 0x0 }, | ||
| 580 | { 0x1112c0, 0x0 }, | ||
| 581 | { 0x2112c0, 0x0 }, | ||
| 582 | { 0x113c0, 0x0 }, | ||
| 583 | { 0x1113c0, 0x0 }, | ||
| 584 | { 0x2113c0, 0x0 }, | ||
| 585 | { 0x114c0, 0x0 }, | ||
| 586 | { 0x1114c0, 0x0 }, | ||
| 587 | { 0x2114c0, 0x0 }, | ||
| 588 | { 0x115c0, 0x0 }, | ||
| 589 | { 0x1115c0, 0x0 }, | ||
| 590 | { 0x2115c0, 0x0 }, | ||
| 591 | { 0x116c0, 0x0 }, | ||
| 592 | { 0x1116c0, 0x0 }, | ||
| 593 | { 0x2116c0, 0x0 }, | ||
| 594 | { 0x117c0, 0x0 }, | ||
| 595 | { 0x1117c0, 0x0 }, | ||
| 596 | { 0x2117c0, 0x0 }, | ||
| 597 | { 0x118c0, 0x0 }, | ||
| 598 | { 0x1118c0, 0x0 }, | ||
| 599 | { 0x2118c0, 0x0 }, | ||
| 600 | { 0x120c0, 0x0 }, | ||
| 601 | { 0x1120c0, 0x0 }, | ||
| 602 | { 0x2120c0, 0x0 }, | ||
| 603 | { 0x121c0, 0x0 }, | ||
| 604 | { 0x1121c0, 0x0 }, | ||
| 605 | { 0x2121c0, 0x0 }, | ||
| 606 | { 0x122c0, 0x0 }, | ||
| 607 | { 0x1122c0, 0x0 }, | ||
| 608 | { 0x2122c0, 0x0 }, | ||
| 609 | { 0x123c0, 0x0 }, | ||
| 610 | { 0x1123c0, 0x0 }, | ||
| 611 | { 0x2123c0, 0x0 }, | ||
| 612 | { 0x124c0, 0x0 }, | ||
| 613 | { 0x1124c0, 0x0 }, | ||
| 614 | { 0x2124c0, 0x0 }, | ||
| 615 | { 0x125c0, 0x0 }, | ||
| 616 | { 0x1125c0, 0x0 }, | ||
| 617 | { 0x2125c0, 0x0 }, | ||
| 618 | { 0x126c0, 0x0 }, | ||
| 619 | { 0x1126c0, 0x0 }, | ||
| 620 | { 0x2126c0, 0x0 }, | ||
| 621 | { 0x127c0, 0x0 }, | ||
| 622 | { 0x1127c0, 0x0 }, | ||
| 623 | { 0x2127c0, 0x0 }, | ||
| 624 | { 0x128c0, 0x0 }, | ||
| 625 | { 0x1128c0, 0x0 }, | ||
| 626 | { 0x2128c0, 0x0 }, | ||
| 627 | { 0x130c0, 0x0 }, | ||
| 628 | { 0x1130c0, 0x0 }, | ||
| 629 | { 0x2130c0, 0x0 }, | ||
| 630 | { 0x131c0, 0x0 }, | ||
| 631 | { 0x1131c0, 0x0 }, | ||
| 632 | { 0x2131c0, 0x0 }, | ||
| 633 | { 0x132c0, 0x0 }, | ||
| 634 | { 0x1132c0, 0x0 }, | ||
| 635 | { 0x2132c0, 0x0 }, | ||
| 636 | { 0x133c0, 0x0 }, | ||
| 637 | { 0x1133c0, 0x0 }, | ||
| 638 | { 0x2133c0, 0x0 }, | ||
| 639 | { 0x134c0, 0x0 }, | ||
| 640 | { 0x1134c0, 0x0 }, | ||
| 641 | { 0x2134c0, 0x0 }, | ||
| 642 | { 0x135c0, 0x0 }, | ||
| 643 | { 0x1135c0, 0x0 }, | ||
| 644 | { 0x2135c0, 0x0 }, | ||
| 645 | { 0x136c0, 0x0 }, | ||
| 646 | { 0x1136c0, 0x0 }, | ||
| 647 | { 0x2136c0, 0x0 }, | ||
| 648 | { 0x137c0, 0x0 }, | ||
| 649 | { 0x1137c0, 0x0 }, | ||
| 650 | { 0x2137c0, 0x0 }, | ||
| 651 | { 0x138c0, 0x0 }, | ||
| 652 | { 0x1138c0, 0x0 }, | ||
| 653 | { 0x2138c0, 0x0 }, | ||
| 654 | { 0x100c1, 0x0 }, | ||
| 655 | { 0x1100c1, 0x0 }, | ||
| 656 | { 0x2100c1, 0x0 }, | ||
| 657 | { 0x101c1, 0x0 }, | ||
| 658 | { 0x1101c1, 0x0 }, | ||
| 659 | { 0x2101c1, 0x0 }, | ||
| 660 | { 0x102c1, 0x0 }, | ||
| 661 | { 0x1102c1, 0x0 }, | ||
| 662 | { 0x2102c1, 0x0 }, | ||
| 663 | { 0x103c1, 0x0 }, | ||
| 664 | { 0x1103c1, 0x0 }, | ||
| 665 | { 0x2103c1, 0x0 }, | ||
| 666 | { 0x104c1, 0x0 }, | ||
| 667 | { 0x1104c1, 0x0 }, | ||
| 668 | { 0x2104c1, 0x0 }, | ||
| 669 | { 0x105c1, 0x0 }, | ||
| 670 | { 0x1105c1, 0x0 }, | ||
| 671 | { 0x2105c1, 0x0 }, | ||
| 672 | { 0x106c1, 0x0 }, | ||
| 673 | { 0x1106c1, 0x0 }, | ||
| 674 | { 0x2106c1, 0x0 }, | ||
| 675 | { 0x107c1, 0x0 }, | ||
| 676 | { 0x1107c1, 0x0 }, | ||
| 677 | { 0x2107c1, 0x0 }, | ||
| 678 | { 0x108c1, 0x0 }, | ||
| 679 | { 0x1108c1, 0x0 }, | ||
| 680 | { 0x2108c1, 0x0 }, | ||
| 681 | { 0x110c1, 0x0 }, | ||
| 682 | { 0x1110c1, 0x0 }, | ||
| 683 | { 0x2110c1, 0x0 }, | ||
| 684 | { 0x111c1, 0x0 }, | ||
| 685 | { 0x1111c1, 0x0 }, | ||
| 686 | { 0x2111c1, 0x0 }, | ||
| 687 | { 0x112c1, 0x0 }, | ||
| 688 | { 0x1112c1, 0x0 }, | ||
| 689 | { 0x2112c1, 0x0 }, | ||
| 690 | { 0x113c1, 0x0 }, | ||
| 691 | { 0x1113c1, 0x0 }, | ||
| 692 | { 0x2113c1, 0x0 }, | ||
| 693 | { 0x114c1, 0x0 }, | ||
| 694 | { 0x1114c1, 0x0 }, | ||
| 695 | { 0x2114c1, 0x0 }, | ||
| 696 | { 0x115c1, 0x0 }, | ||
| 697 | { 0x1115c1, 0x0 }, | ||
| 698 | { 0x2115c1, 0x0 }, | ||
| 699 | { 0x116c1, 0x0 }, | ||
| 700 | { 0x1116c1, 0x0 }, | ||
| 701 | { 0x2116c1, 0x0 }, | ||
| 702 | { 0x117c1, 0x0 }, | ||
| 703 | { 0x1117c1, 0x0 }, | ||
| 704 | { 0x2117c1, 0x0 }, | ||
| 705 | { 0x118c1, 0x0 }, | ||
| 706 | { 0x1118c1, 0x0 }, | ||
| 707 | { 0x2118c1, 0x0 }, | ||
| 708 | { 0x120c1, 0x0 }, | ||
| 709 | { 0x1120c1, 0x0 }, | ||
| 710 | { 0x2120c1, 0x0 }, | ||
| 711 | { 0x121c1, 0x0 }, | ||
| 712 | { 0x1121c1, 0x0 }, | ||
| 713 | { 0x2121c1, 0x0 }, | ||
| 714 | { 0x122c1, 0x0 }, | ||
| 715 | { 0x1122c1, 0x0 }, | ||
| 716 | { 0x2122c1, 0x0 }, | ||
| 717 | { 0x123c1, 0x0 }, | ||
| 718 | { 0x1123c1, 0x0 }, | ||
| 719 | { 0x2123c1, 0x0 }, | ||
| 720 | { 0x124c1, 0x0 }, | ||
| 721 | { 0x1124c1, 0x0 }, | ||
| 722 | { 0x2124c1, 0x0 }, | ||
| 723 | { 0x125c1, 0x0 }, | ||
| 724 | { 0x1125c1, 0x0 }, | ||
| 725 | { 0x2125c1, 0x0 }, | ||
| 726 | { 0x126c1, 0x0 }, | ||
| 727 | { 0x1126c1, 0x0 }, | ||
| 728 | { 0x2126c1, 0x0 }, | ||
| 729 | { 0x127c1, 0x0 }, | ||
| 730 | { 0x1127c1, 0x0 }, | ||
| 731 | { 0x2127c1, 0x0 }, | ||
| 732 | { 0x128c1, 0x0 }, | ||
| 733 | { 0x1128c1, 0x0 }, | ||
| 734 | { 0x2128c1, 0x0 }, | ||
| 735 | { 0x130c1, 0x0 }, | ||
| 736 | { 0x1130c1, 0x0 }, | ||
| 737 | { 0x2130c1, 0x0 }, | ||
| 738 | { 0x131c1, 0x0 }, | ||
| 739 | { 0x1131c1, 0x0 }, | ||
| 740 | { 0x2131c1, 0x0 }, | ||
| 741 | { 0x132c1, 0x0 }, | ||
| 742 | { 0x1132c1, 0x0 }, | ||
| 743 | { 0x2132c1, 0x0 }, | ||
| 744 | { 0x133c1, 0x0 }, | ||
| 745 | { 0x1133c1, 0x0 }, | ||
| 746 | { 0x2133c1, 0x0 }, | ||
| 747 | { 0x134c1, 0x0 }, | ||
| 748 | { 0x1134c1, 0x0 }, | ||
| 749 | { 0x2134c1, 0x0 }, | ||
| 750 | { 0x135c1, 0x0 }, | ||
| 751 | { 0x1135c1, 0x0 }, | ||
| 752 | { 0x2135c1, 0x0 }, | ||
| 753 | { 0x136c1, 0x0 }, | ||
| 754 | { 0x1136c1, 0x0 }, | ||
| 755 | { 0x2136c1, 0x0 }, | ||
| 756 | { 0x137c1, 0x0 }, | ||
| 757 | { 0x1137c1, 0x0 }, | ||
| 758 | { 0x2137c1, 0x0 }, | ||
| 759 | { 0x138c1, 0x0 }, | ||
| 760 | { 0x1138c1, 0x0 }, | ||
| 761 | { 0x2138c1, 0x0 }, | ||
| 762 | { 0x10020, 0x0 }, | ||
| 763 | { 0x110020, 0x0 }, | ||
| 764 | { 0x210020, 0x0 }, | ||
| 765 | { 0x11020, 0x0 }, | ||
| 766 | { 0x111020, 0x0 }, | ||
| 767 | { 0x211020, 0x0 }, | ||
| 768 | { 0x12020, 0x0 }, | ||
| 769 | { 0x112020, 0x0 }, | ||
| 770 | { 0x212020, 0x0 }, | ||
| 771 | { 0x13020, 0x0 }, | ||
| 772 | { 0x113020, 0x0 }, | ||
| 773 | { 0x213020, 0x0 }, | ||
| 774 | { 0x20072, 0x0 }, | ||
| 775 | { 0x20073, 0x0 }, | ||
| 776 | { 0x20074, 0x0 }, | ||
| 777 | { 0x100aa, 0x0 }, | ||
| 778 | { 0x110aa, 0x0 }, | ||
| 779 | { 0x120aa, 0x0 }, | ||
| 780 | { 0x130aa, 0x0 }, | ||
| 781 | { 0x20010, 0x0 }, | ||
| 782 | { 0x120010, 0x0 }, | ||
| 783 | { 0x220010, 0x0 }, | ||
| 784 | { 0x20011, 0x0 }, | ||
| 785 | { 0x120011, 0x0 }, | ||
| 786 | { 0x220011, 0x0 }, | ||
| 787 | { 0x100ae, 0x0 }, | ||
| 788 | { 0x1100ae, 0x0 }, | ||
| 789 | { 0x2100ae, 0x0 }, | ||
| 790 | { 0x100af, 0x0 }, | ||
| 791 | { 0x1100af, 0x0 }, | ||
| 792 | { 0x2100af, 0x0 }, | ||
| 793 | { 0x110ae, 0x0 }, | ||
| 794 | { 0x1110ae, 0x0 }, | ||
| 795 | { 0x2110ae, 0x0 }, | ||
| 796 | { 0x110af, 0x0 }, | ||
| 797 | { 0x1110af, 0x0 }, | ||
| 798 | { 0x2110af, 0x0 }, | ||
| 799 | { 0x120ae, 0x0 }, | ||
| 800 | { 0x1120ae, 0x0 }, | ||
| 801 | { 0x2120ae, 0x0 }, | ||
| 802 | { 0x120af, 0x0 }, | ||
| 803 | { 0x1120af, 0x0 }, | ||
| 804 | { 0x2120af, 0x0 }, | ||
| 805 | { 0x130ae, 0x0 }, | ||
| 806 | { 0x1130ae, 0x0 }, | ||
| 807 | { 0x2130ae, 0x0 }, | ||
| 808 | { 0x130af, 0x0 }, | ||
| 809 | { 0x1130af, 0x0 }, | ||
| 810 | { 0x2130af, 0x0 }, | ||
| 811 | { 0x20020, 0x0 }, | ||
| 812 | { 0x120020, 0x0 }, | ||
| 813 | { 0x220020, 0x0 }, | ||
| 814 | { 0x100a0, 0x0 }, | ||
| 815 | { 0x100a1, 0x0 }, | ||
| 816 | { 0x100a2, 0x0 }, | ||
| 817 | { 0x100a3, 0x0 }, | ||
| 818 | { 0x100a4, 0x0 }, | ||
| 819 | { 0x100a5, 0x0 }, | ||
| 820 | { 0x100a6, 0x0 }, | ||
| 821 | { 0x100a7, 0x0 }, | ||
| 822 | { 0x110a0, 0x0 }, | ||
| 823 | { 0x110a1, 0x0 }, | ||
| 824 | { 0x110a2, 0x0 }, | ||
| 825 | { 0x110a3, 0x0 }, | ||
| 826 | { 0x110a4, 0x0 }, | ||
| 827 | { 0x110a5, 0x0 }, | ||
| 828 | { 0x110a6, 0x0 }, | ||
| 829 | { 0x110a7, 0x0 }, | ||
| 830 | { 0x120a0, 0x0 }, | ||
| 831 | { 0x120a1, 0x0 }, | ||
| 832 | { 0x120a2, 0x0 }, | ||
| 833 | { 0x120a3, 0x0 }, | ||
| 834 | { 0x120a4, 0x0 }, | ||
| 835 | { 0x120a5, 0x0 }, | ||
| 836 | { 0x120a6, 0x0 }, | ||
| 837 | { 0x120a7, 0x0 }, | ||
| 838 | { 0x130a0, 0x0 }, | ||
| 839 | { 0x130a1, 0x0 }, | ||
| 840 | { 0x130a2, 0x0 }, | ||
| 841 | { 0x130a3, 0x0 }, | ||
| 842 | { 0x130a4, 0x0 }, | ||
| 843 | { 0x130a5, 0x0 }, | ||
| 844 | { 0x130a6, 0x0 }, | ||
| 845 | { 0x130a7, 0x0 }, | ||
| 846 | { 0x2007c, 0x0 }, | ||
| 847 | { 0x12007c, 0x0 }, | ||
| 848 | { 0x22007c, 0x0 }, | ||
| 849 | { 0x2007d, 0x0 }, | ||
| 850 | { 0x12007d, 0x0 }, | ||
| 851 | { 0x22007d, 0x0 }, | ||
| 852 | { 0x400fd, 0x0 }, | ||
| 853 | { 0x400c0, 0x0 }, | ||
| 854 | { 0x90201, 0x0 }, | ||
| 855 | { 0x190201, 0x0 }, | ||
| 856 | { 0x290201, 0x0 }, | ||
| 857 | { 0x90202, 0x0 }, | ||
| 858 | { 0x190202, 0x0 }, | ||
| 859 | { 0x290202, 0x0 }, | ||
| 860 | { 0x90203, 0x0 }, | ||
| 861 | { 0x190203, 0x0 }, | ||
| 862 | { 0x290203, 0x0 }, | ||
| 863 | { 0x90204, 0x0 }, | ||
| 864 | { 0x190204, 0x0 }, | ||
| 865 | { 0x290204, 0x0 }, | ||
| 866 | { 0x90205, 0x0 }, | ||
| 867 | { 0x190205, 0x0 }, | ||
| 868 | { 0x290205, 0x0 }, | ||
| 869 | { 0x90206, 0x0 }, | ||
| 870 | { 0x190206, 0x0 }, | ||
| 871 | { 0x290206, 0x0 }, | ||
| 872 | { 0x90207, 0x0 }, | ||
| 873 | { 0x190207, 0x0 }, | ||
| 874 | { 0x290207, 0x0 }, | ||
| 875 | { 0x90208, 0x0 }, | ||
| 876 | { 0x190208, 0x0 }, | ||
| 877 | { 0x290208, 0x0 }, | ||
| 878 | { 0x10062, 0x0 }, | ||
| 879 | { 0x10162, 0x0 }, | ||
| 880 | { 0x10262, 0x0 }, | ||
| 881 | { 0x10362, 0x0 }, | ||
| 882 | { 0x10462, 0x0 }, | ||
| 883 | { 0x10562, 0x0 }, | ||
| 884 | { 0x10662, 0x0 }, | ||
| 885 | { 0x10762, 0x0 }, | ||
| 886 | { 0x10862, 0x0 }, | ||
| 887 | { 0x11062, 0x0 }, | ||
| 888 | { 0x11162, 0x0 }, | ||
| 889 | { 0x11262, 0x0 }, | ||
| 890 | { 0x11362, 0x0 }, | ||
| 891 | { 0x11462, 0x0 }, | ||
| 892 | { 0x11562, 0x0 }, | ||
| 893 | { 0x11662, 0x0 }, | ||
| 894 | { 0x11762, 0x0 }, | ||
| 895 | { 0x11862, 0x0 }, | ||
| 896 | { 0x12062, 0x0 }, | ||
| 897 | { 0x12162, 0x0 }, | ||
| 898 | { 0x12262, 0x0 }, | ||
| 899 | { 0x12362, 0x0 }, | ||
| 900 | { 0x12462, 0x0 }, | ||
| 901 | { 0x12562, 0x0 }, | ||
| 902 | { 0x12662, 0x0 }, | ||
| 903 | { 0x12762, 0x0 }, | ||
| 904 | { 0x12862, 0x0 }, | ||
| 905 | { 0x13062, 0x0 }, | ||
| 906 | { 0x13162, 0x0 }, | ||
| 907 | { 0x13262, 0x0 }, | ||
| 908 | { 0x13362, 0x0 }, | ||
| 909 | { 0x13462, 0x0 }, | ||
| 910 | { 0x13562, 0x0 }, | ||
| 911 | { 0x13662, 0x0 }, | ||
| 912 | { 0x13762, 0x0 }, | ||
| 913 | { 0x13862, 0x0 }, | ||
| 914 | { 0x20077, 0x0 }, | ||
| 915 | { 0x10001, 0x0 }, | ||
| 916 | { 0x11001, 0x0 }, | ||
| 917 | { 0x12001, 0x0 }, | ||
| 918 | { 0x13001, 0x0 }, | ||
| 919 | { 0x10040, 0x0 }, | ||
| 920 | { 0x10140, 0x0 }, | ||
| 921 | { 0x10240, 0x0 }, | ||
| 922 | { 0x10340, 0x0 }, | ||
| 923 | { 0x10440, 0x0 }, | ||
| 924 | { 0x10540, 0x0 }, | ||
| 925 | { 0x10640, 0x0 }, | ||
| 926 | { 0x10740, 0x0 }, | ||
| 927 | { 0x10840, 0x0 }, | ||
| 928 | { 0x10030, 0x0 }, | ||
| 929 | { 0x10130, 0x0 }, | ||
| 930 | { 0x10230, 0x0 }, | ||
| 931 | { 0x10330, 0x0 }, | ||
| 932 | { 0x10430, 0x0 }, | ||
| 933 | { 0x10530, 0x0 }, | ||
| 934 | { 0x10630, 0x0 }, | ||
| 935 | { 0x10730, 0x0 }, | ||
| 936 | { 0x10830, 0x0 }, | ||
| 937 | { 0x11040, 0x0 }, | ||
| 938 | { 0x11140, 0x0 }, | ||
| 939 | { 0x11240, 0x0 }, | ||
| 940 | { 0x11340, 0x0 }, | ||
| 941 | { 0x11440, 0x0 }, | ||
| 942 | { 0x11540, 0x0 }, | ||
| 943 | { 0x11640, 0x0 }, | ||
| 944 | { 0x11740, 0x0 }, | ||
| 945 | { 0x11840, 0x0 }, | ||
| 946 | { 0x11030, 0x0 }, | ||
| 947 | { 0x11130, 0x0 }, | ||
| 948 | { 0x11230, 0x0 }, | ||
| 949 | { 0x11330, 0x0 }, | ||
| 950 | { 0x11430, 0x0 }, | ||
| 951 | { 0x11530, 0x0 }, | ||
| 952 | { 0x11630, 0x0 }, | ||
| 953 | { 0x11730, 0x0 }, | ||
| 954 | { 0x11830, 0x0 }, | ||
| 955 | { 0x12040, 0x0 }, | ||
| 956 | { 0x12140, 0x0 }, | ||
| 957 | { 0x12240, 0x0 }, | ||
| 958 | { 0x12340, 0x0 }, | ||
| 959 | { 0x12440, 0x0 }, | ||
| 960 | { 0x12540, 0x0 }, | ||
| 961 | { 0x12640, 0x0 }, | ||
| 962 | { 0x12740, 0x0 }, | ||
| 963 | { 0x12840, 0x0 }, | ||
| 964 | { 0x12030, 0x0 }, | ||
| 965 | { 0x12130, 0x0 }, | ||
| 966 | { 0x12230, 0x0 }, | ||
| 967 | { 0x12330, 0x0 }, | ||
| 968 | { 0x12430, 0x0 }, | ||
| 969 | { 0x12530, 0x0 }, | ||
| 970 | { 0x12630, 0x0 }, | ||
| 971 | { 0x12730, 0x0 }, | ||
| 972 | { 0x12830, 0x0 }, | ||
| 973 | { 0x13040, 0x0 }, | ||
| 974 | { 0x13140, 0x0 }, | ||
| 975 | { 0x13240, 0x0 }, | ||
| 976 | { 0x13340, 0x0 }, | ||
| 977 | { 0x13440, 0x0 }, | ||
| 978 | { 0x13540, 0x0 }, | ||
| 979 | { 0x13640, 0x0 }, | ||
| 980 | { 0x13740, 0x0 }, | ||
| 981 | { 0x13840, 0x0 }, | ||
| 982 | { 0x13030, 0x0 }, | ||
| 983 | { 0x13130, 0x0 }, | ||
| 984 | { 0x13230, 0x0 }, | ||
| 985 | { 0x13330, 0x0 }, | ||
| 986 | { 0x13430, 0x0 }, | ||
| 987 | { 0x13530, 0x0 }, | ||
| 988 | { 0x13630, 0x0 }, | ||
| 989 | { 0x13730, 0x0 }, | ||
| 990 | { 0x13830, 0x0 }, | ||
| 991 | }; | ||
| 992 | /* P0 message block paremeter for training firmware */ | ||
| 993 | struct dram_cfg_param ddr_fsp0_cfg[] = { | ||
| 994 | {0xd0000, 0x0}, | ||
| 995 | {0x54003,0xc80}, | ||
| 996 | {0x54004,0x2}, | ||
| 997 | {0x54005,0x2228}, | ||
| 998 | {0x54006,0x11}, | ||
| 999 | {0x54008,0x131f}, | ||
| 1000 | {0x54009,0xc8}, | ||
| 1001 | {0x5400b,0x2}, | ||
| 1002 | {0x5400d,0x100}, | ||
| 1003 | {0x54012,0x110}, | ||
| 1004 | {0x54019,0x2dd4}, | ||
| 1005 | {0x5401a,0x31}, | ||
| 1006 | {0x5401b,0x4a66}, | ||
| 1007 | {0x5401c,0x4a08}, | ||
| 1008 | {0x5401e,0x16}, | ||
| 1009 | {0x5401f,0x2dd4}, | ||
| 1010 | {0x54020,0x31}, | ||
| 1011 | {0x54021,0x4a66}, | ||
| 1012 | {0x54022,0x4a08}, | ||
| 1013 | {0x54024,0x16}, | ||
| 1014 | {0x5402b,0x1000}, | ||
| 1015 | {0x5402c,0x1}, | ||
| 1016 | {0x54032,0xd400}, | ||
| 1017 | {0x54033,0x312d}, | ||
| 1018 | {0x54034,0x6600}, | ||
| 1019 | {0x54035,0x84a}, | ||
| 1020 | {0x54036,0x4a}, | ||
| 1021 | {0x54037,0x1600}, | ||
| 1022 | {0x54038,0xd400}, | ||
| 1023 | {0x54039,0x312d}, | ||
| 1024 | {0x5403a,0x6600}, | ||
| 1025 | {0x5403b,0x84a}, | ||
| 1026 | {0x5403c,0x4a}, | ||
| 1027 | {0x5403d,0x1600}, | ||
| 1028 | {0xd0000, 0x1}, | ||
| 1029 | }; | ||
| 1030 | |||
| 1031 | |||
| 1032 | /* P1 message block paremeter for training firmware */ | ||
| 1033 | struct dram_cfg_param ddr_fsp1_cfg[] = { | ||
| 1034 | {0xd0000, 0x0}, | ||
| 1035 | {0x54002,0x1}, | ||
| 1036 | {0x54003,0x29c}, | ||
| 1037 | {0x54004,0x2}, | ||
| 1038 | {0x54005,0x2228}, | ||
| 1039 | {0x54006,0x11}, | ||
| 1040 | {0x54008,0x121f}, | ||
| 1041 | {0x54009,0xc8}, | ||
| 1042 | {0x5400b,0x2}, | ||
| 1043 | {0x5400d,0x100}, | ||
| 1044 | {0x54012,0x110}, | ||
| 1045 | {0x54019,0x994}, | ||
| 1046 | {0x5401a,0x31}, | ||
| 1047 | {0x5401b,0x4a66}, | ||
| 1048 | {0x5401c,0x4a08}, | ||
| 1049 | {0x5401e,0x16}, | ||
| 1050 | {0x5401f,0x994}, | ||
| 1051 | {0x54020,0x31}, | ||
| 1052 | {0x54021,0x4a66}, | ||
| 1053 | {0x54022,0x4a08}, | ||
| 1054 | {0x54024,0x16}, | ||
| 1055 | {0x5402b,0x1000}, | ||
| 1056 | {0x5402c,0x1}, | ||
| 1057 | {0x54032,0x9400}, | ||
| 1058 | {0x54033,0x3109}, | ||
| 1059 | {0x54034,0x6600}, | ||
| 1060 | {0x54035,0x84a}, | ||
| 1061 | {0x54036,0x4a}, | ||
| 1062 | {0x54037,0x1600}, | ||
| 1063 | {0x54038,0x9400}, | ||
| 1064 | {0x54039,0x3109}, | ||
| 1065 | {0x5403a,0x6600}, | ||
| 1066 | {0x5403b,0x84a}, | ||
| 1067 | {0x5403c,0x4a}, | ||
| 1068 | {0x5403d,0x1600}, | ||
| 1069 | {0xd0000, 0x1}, | ||
| 1070 | }; | ||
| 1071 | |||
| 1072 | |||
| 1073 | /* P0 2D message block paremeter for training firmware */ | ||
| 1074 | struct dram_cfg_param ddr_fsp0_2d_cfg[] = { | ||
| 1075 | {0xd0000, 0x0}, | ||
| 1076 | {0x54003,0xc80}, | ||
| 1077 | {0x54004,0x2}, | ||
| 1078 | {0x54005,0x2228}, | ||
| 1079 | {0x54006,0x11}, | ||
| 1080 | {0x54008,0x61}, | ||
| 1081 | {0x54009,0xc8}, | ||
| 1082 | {0x5400b,0x2}, | ||
| 1083 | {0x5400f,0x100}, | ||
| 1084 | {0x54010,0x1f7f}, | ||
| 1085 | {0x54012,0x110}, | ||
| 1086 | {0x54019,0x2dd4}, | ||
| 1087 | {0x5401a,0x31}, | ||
| 1088 | {0x5401b,0x4a66}, | ||
| 1089 | {0x5401c,0x4a08}, | ||
| 1090 | {0x5401e,0x16}, | ||
| 1091 | {0x5401f,0x2dd4}, | ||
| 1092 | {0x54020,0x31}, | ||
| 1093 | {0x54021,0x4a66}, | ||
| 1094 | {0x54022,0x4a08}, | ||
| 1095 | {0x54024,0x16}, | ||
| 1096 | {0x5402b,0x1000}, | ||
| 1097 | {0x5402c,0x1}, | ||
| 1098 | {0x54032,0xd400}, | ||
| 1099 | {0x54033,0x312d}, | ||
| 1100 | {0x54034,0x6600}, | ||
| 1101 | {0x54035,0x84a}, | ||
| 1102 | {0x54036,0x4a}, | ||
| 1103 | {0x54037,0x1600}, | ||
| 1104 | {0x54038,0xd400}, | ||
| 1105 | {0x54039,0x312d}, | ||
| 1106 | {0x5403a,0x6600}, | ||
| 1107 | {0x5403b,0x84a}, | ||
| 1108 | {0x5403c,0x4a}, | ||
| 1109 | {0x5403d,0x1600}, | ||
| 1110 | { 0xd0000, 0x1 }, | ||
| 1111 | }; | ||
| 1112 | |||
| 1113 | /* DRAM PHY init engine image */ | ||
| 1114 | struct dram_cfg_param ddr_phy_pie[] = { | ||
| 1115 | {0xd0000, 0x0}, | ||
| 1116 | {0x90000,0x10}, | ||
| 1117 | {0x90001,0x400}, | ||
| 1118 | {0x90002,0x10e}, | ||
| 1119 | {0x90003,0x0}, | ||
| 1120 | {0x90004,0x0}, | ||
| 1121 | {0x90005,0x8}, | ||
| 1122 | {0x90029,0xb}, | ||
| 1123 | {0x9002a,0x480}, | ||
| 1124 | {0x9002b,0x109}, | ||
| 1125 | {0x9002c,0x8}, | ||
| 1126 | {0x9002d,0x448}, | ||
| 1127 | {0x9002e,0x139}, | ||
| 1128 | {0x9002f,0x8}, | ||
| 1129 | {0x90030,0x478}, | ||
| 1130 | {0x90031,0x109}, | ||
| 1131 | {0x90032,0x0}, | ||
| 1132 | {0x90033,0xe8}, | ||
| 1133 | {0x90034,0x109}, | ||
| 1134 | {0x90035,0x2}, | ||
| 1135 | {0x90036,0x10}, | ||
| 1136 | {0x90037,0x139}, | ||
| 1137 | {0x90038,0xf}, | ||
| 1138 | {0x90039,0x7c0}, | ||
| 1139 | {0x9003a,0x139}, | ||
| 1140 | {0x9003b,0x44}, | ||
| 1141 | {0x9003c,0x630}, | ||
| 1142 | {0x9003d,0x159}, | ||
| 1143 | {0x9003e,0x14f}, | ||
| 1144 | {0x9003f,0x630}, | ||
| 1145 | {0x90040,0x159}, | ||
| 1146 | {0x90041,0x47}, | ||
| 1147 | {0x90042,0x630}, | ||
| 1148 | {0x90043,0x149}, | ||
| 1149 | {0x90044,0x4f}, | ||
| 1150 | {0x90045,0x630}, | ||
| 1151 | {0x90046,0x179}, | ||
| 1152 | {0x90047,0x8}, | ||
| 1153 | {0x90048,0xe0}, | ||
| 1154 | {0x90049,0x109}, | ||
| 1155 | {0x9004a,0x0}, | ||
| 1156 | {0x9004b,0x7c8}, | ||
| 1157 | {0x9004c,0x109}, | ||
| 1158 | {0x9004d,0x0}, | ||
| 1159 | {0x9004e,0x1}, | ||
| 1160 | {0x9004f,0x8}, | ||
| 1161 | {0x90050,0x0}, | ||
| 1162 | {0x90051,0x45a}, | ||
| 1163 | {0x90052,0x9}, | ||
| 1164 | {0x90053,0x0}, | ||
| 1165 | {0x90054,0x448}, | ||
| 1166 | {0x90055,0x109}, | ||
| 1167 | {0x90056,0x40}, | ||
| 1168 | {0x90057,0x630}, | ||
| 1169 | {0x90058,0x179}, | ||
| 1170 | {0x90059,0x1}, | ||
| 1171 | {0x9005a,0x618}, | ||
| 1172 | {0x9005b,0x109}, | ||
| 1173 | {0x9005c,0x40c0}, | ||
| 1174 | {0x9005d,0x630}, | ||
| 1175 | {0x9005e,0x149}, | ||
| 1176 | {0x9005f,0x8}, | ||
| 1177 | {0x90060,0x4}, | ||
| 1178 | {0x90061,0x48}, | ||
| 1179 | {0x90062,0x4040}, | ||
| 1180 | {0x90063,0x630}, | ||
| 1181 | {0x90064,0x149}, | ||
| 1182 | {0x90065,0x0}, | ||
| 1183 | {0x90066,0x4}, | ||
| 1184 | {0x90067,0x48}, | ||
| 1185 | {0x90068,0x40}, | ||
| 1186 | {0x90069,0x630}, | ||
| 1187 | {0x9006a,0x149}, | ||
| 1188 | {0x9006b,0x10}, | ||
| 1189 | {0x9006c,0x4}, | ||
| 1190 | {0x9006d,0x18}, | ||
| 1191 | {0x9006e,0x0}, | ||
| 1192 | {0x9006f,0x4}, | ||
| 1193 | {0x90070,0x78}, | ||
| 1194 | {0x90071,0x549}, | ||
| 1195 | {0x90072,0x630}, | ||
| 1196 | {0x90073,0x159}, | ||
| 1197 | {0x90074,0xd49}, | ||
| 1198 | {0x90075,0x630}, | ||
| 1199 | {0x90076,0x159}, | ||
| 1200 | {0x90077,0x94a}, | ||
| 1201 | {0x90078,0x630}, | ||
| 1202 | {0x90079,0x159}, | ||
| 1203 | {0x9007a,0x441}, | ||
| 1204 | {0x9007b,0x630}, | ||
| 1205 | {0x9007c,0x149}, | ||
| 1206 | {0x9007d,0x42}, | ||
| 1207 | {0x9007e,0x630}, | ||
| 1208 | {0x9007f,0x149}, | ||
| 1209 | {0x90080,0x1}, | ||
| 1210 | {0x90081,0x630}, | ||
| 1211 | {0x90082,0x149}, | ||
| 1212 | {0x90083,0x0}, | ||
| 1213 | {0x90084,0xe0}, | ||
| 1214 | {0x90085,0x109}, | ||
| 1215 | {0x90086,0xa}, | ||
| 1216 | {0x90087,0x10}, | ||
| 1217 | {0x90088,0x109}, | ||
| 1218 | {0x90089,0x9}, | ||
| 1219 | {0x9008a,0x3c0}, | ||
| 1220 | {0x9008b,0x149}, | ||
| 1221 | {0x9008c,0x9}, | ||
| 1222 | {0x9008d,0x3c0}, | ||
| 1223 | {0x9008e,0x159}, | ||
| 1224 | {0x9008f,0x18}, | ||
| 1225 | {0x90090,0x10}, | ||
| 1226 | {0x90091,0x109}, | ||
| 1227 | {0x90092,0x0}, | ||
| 1228 | {0x90093,0x3c0}, | ||
| 1229 | {0x90094,0x109}, | ||
| 1230 | {0x90095,0x18}, | ||
| 1231 | {0x90096,0x4}, | ||
| 1232 | {0x90097,0x48}, | ||
| 1233 | {0x90098,0x18}, | ||
| 1234 | {0x90099,0x4}, | ||
| 1235 | {0x9009a,0x58}, | ||
| 1236 | {0x9009b,0xa}, | ||
| 1237 | {0x9009c,0x10}, | ||
| 1238 | {0x9009d,0x109}, | ||
| 1239 | {0x9009e,0x2}, | ||
| 1240 | {0x9009f,0x10}, | ||
| 1241 | {0x900a0,0x109}, | ||
| 1242 | {0x900a1,0x5}, | ||
| 1243 | {0x900a2,0x7c0}, | ||
| 1244 | {0x900a3,0x109}, | ||
| 1245 | {0x900a4,0x10}, | ||
| 1246 | {0x900a5,0x10}, | ||
| 1247 | {0x900a6,0x109}, | ||
| 1248 | {0x40000,0x811}, | ||
| 1249 | {0x40020,0x880}, | ||
| 1250 | {0x40040,0x0}, | ||
| 1251 | {0x40060,0x0}, | ||
| 1252 | {0x40001,0x4008}, | ||
| 1253 | {0x40021,0x83}, | ||
| 1254 | {0x40041,0x4f}, | ||
| 1255 | {0x40061,0x0}, | ||
| 1256 | {0x40002,0x4040}, | ||
| 1257 | {0x40022,0x83}, | ||
| 1258 | {0x40042,0x51}, | ||
| 1259 | {0x40062,0x0}, | ||
| 1260 | {0x40003,0x811}, | ||
| 1261 | {0x40023,0x880}, | ||
| 1262 | {0x40043,0x0}, | ||
| 1263 | {0x40063,0x0}, | ||
| 1264 | {0x40004,0x720}, | ||
| 1265 | {0x40024,0xf}, | ||
| 1266 | {0x40044,0x1740}, | ||
| 1267 | {0x40064,0x0}, | ||
| 1268 | {0x40005,0x16}, | ||
| 1269 | {0x40025,0x83}, | ||
| 1270 | {0x40045,0x4b}, | ||
| 1271 | {0x40065,0x0}, | ||
| 1272 | {0x40006,0x716}, | ||
| 1273 | {0x40026,0xf}, | ||
| 1274 | {0x40046,0x2001}, | ||
| 1275 | {0x40066,0x0}, | ||
| 1276 | {0x40007,0x716}, | ||
| 1277 | {0x40027,0xf}, | ||
| 1278 | {0x40047,0x2800}, | ||
| 1279 | {0x40067,0x0}, | ||
| 1280 | {0x40008,0x716}, | ||
| 1281 | {0x40028,0xf}, | ||
| 1282 | {0x40048,0xf00}, | ||
| 1283 | {0x40068,0x0}, | ||
| 1284 | {0x40009,0x720}, | ||
| 1285 | {0x40029,0xf}, | ||
| 1286 | {0x40049,0x1400}, | ||
| 1287 | {0x40069,0x0}, | ||
| 1288 | {0x4000a,0xe08}, | ||
| 1289 | {0x4002a,0xc15}, | ||
| 1290 | {0x4004a,0x0}, | ||
| 1291 | {0x4006a,0x0}, | ||
| 1292 | {0x4000b,0x623}, | ||
| 1293 | {0x4002b,0x15}, | ||
| 1294 | {0x4004b,0x0}, | ||
| 1295 | {0x4006b,0x0}, | ||
| 1296 | {0x4000c,0x4028}, | ||
| 1297 | {0x4002c,0x80}, | ||
| 1298 | {0x4004c,0x0}, | ||
| 1299 | {0x4006c,0x0}, | ||
| 1300 | {0x4000d,0xe08}, | ||
| 1301 | {0x4002d,0xc1a}, | ||
| 1302 | {0x4004d,0x0}, | ||
| 1303 | {0x4006d,0x0}, | ||
| 1304 | {0x4000e,0x623}, | ||
| 1305 | {0x4002e,0x1a}, | ||
| 1306 | {0x4004e,0x0}, | ||
| 1307 | {0x4006e,0x0}, | ||
| 1308 | {0x4000f,0x4040}, | ||
| 1309 | {0x4002f,0x80}, | ||
| 1310 | {0x4004f,0x0}, | ||
| 1311 | {0x4006f,0x0}, | ||
| 1312 | {0x40010,0x2604}, | ||
| 1313 | {0x40030,0x15}, | ||
| 1314 | {0x40050,0x0}, | ||
| 1315 | {0x40070,0x0}, | ||
| 1316 | {0x40011,0x708}, | ||
| 1317 | {0x40031,0x5}, | ||
| 1318 | {0x40051,0x0}, | ||
| 1319 | {0x40071,0x2002}, | ||
| 1320 | {0x40012,0x8}, | ||
| 1321 | {0x40032,0x80}, | ||
| 1322 | {0x40052,0x0}, | ||
| 1323 | {0x40072,0x0}, | ||
| 1324 | {0x40013,0x2604}, | ||
| 1325 | {0x40033,0x1a}, | ||
| 1326 | {0x40053,0x0}, | ||
| 1327 | {0x40073,0x0}, | ||
| 1328 | {0x40014,0x708}, | ||
| 1329 | {0x40034,0xa}, | ||
| 1330 | {0x40054,0x0}, | ||
| 1331 | {0x40074,0x2002}, | ||
| 1332 | {0x40015,0x4040}, | ||
| 1333 | {0x40035,0x80}, | ||
| 1334 | {0x40055,0x0}, | ||
| 1335 | {0x40075,0x0}, | ||
| 1336 | {0x40016,0x60a}, | ||
| 1337 | {0x40036,0x15}, | ||
| 1338 | {0x40056,0x1200}, | ||
| 1339 | {0x40076,0x0}, | ||
| 1340 | {0x40017,0x61a}, | ||
| 1341 | {0x40037,0x15}, | ||
| 1342 | {0x40057,0x1300}, | ||
| 1343 | {0x40077,0x0}, | ||
| 1344 | {0x40018,0x60a}, | ||
| 1345 | {0x40038,0x1a}, | ||
| 1346 | {0x40058,0x1200}, | ||
| 1347 | {0x40078,0x0}, | ||
| 1348 | {0x40019,0x642}, | ||
| 1349 | {0x40039,0x1a}, | ||
| 1350 | {0x40059,0x1300}, | ||
| 1351 | {0x40079,0x0}, | ||
| 1352 | {0x4001a,0x4808}, | ||
| 1353 | {0x4003a,0x880}, | ||
| 1354 | {0x4005a,0x0}, | ||
| 1355 | {0x4007a,0x0}, | ||
| 1356 | {0x900a7,0x0}, | ||
| 1357 | {0x900a8,0x790}, | ||
| 1358 | {0x900a9,0x11a}, | ||
| 1359 | {0x900aa,0x8}, | ||
| 1360 | {0x900ab,0x7aa}, | ||
| 1361 | {0x900ac,0x2a}, | ||
| 1362 | {0x900ad,0x10}, | ||
| 1363 | {0x900ae,0x7b2}, | ||
| 1364 | {0x900af,0x2a}, | ||
| 1365 | {0x900b0,0x0}, | ||
| 1366 | {0x900b1,0x7c8}, | ||
| 1367 | {0x900b2,0x109}, | ||
| 1368 | {0x900b3,0x10}, | ||
| 1369 | {0x900b4,0x2a8}, | ||
| 1370 | {0x900b5,0x129}, | ||
| 1371 | {0x900b6,0x8}, | ||
| 1372 | {0x900b7,0x370}, | ||
| 1373 | {0x900b8,0x129}, | ||
| 1374 | {0x900b9,0xa}, | ||
| 1375 | {0x900ba,0x3c8}, | ||
| 1376 | {0x900bb,0x1a9}, | ||
| 1377 | {0x900bc,0xc}, | ||
| 1378 | {0x900bd,0x408}, | ||
| 1379 | {0x900be,0x199}, | ||
| 1380 | {0x900bf,0x14}, | ||
| 1381 | {0x900c0,0x790}, | ||
| 1382 | {0x900c1,0x11a}, | ||
| 1383 | {0x900c2,0x8}, | ||
| 1384 | {0x900c3,0x4}, | ||
| 1385 | {0x900c4,0x18}, | ||
| 1386 | {0x900c5,0xe}, | ||
| 1387 | {0x900c6,0x408}, | ||
| 1388 | {0x900c7,0x199}, | ||
| 1389 | {0x900c8,0x8}, | ||
| 1390 | {0x900c9,0x8568}, | ||
| 1391 | {0x900ca,0x108}, | ||
| 1392 | {0x900cb,0x18}, | ||
| 1393 | {0x900cc,0x790}, | ||
| 1394 | {0x900cd,0x16a}, | ||
| 1395 | {0x900ce,0x8}, | ||
| 1396 | {0x900cf,0x1d8}, | ||
| 1397 | {0x900d0,0x169}, | ||
| 1398 | {0x900d1,0x10}, | ||
| 1399 | {0x900d2,0x8558}, | ||
| 1400 | {0x900d3,0x168}, | ||
| 1401 | {0x900d4,0x70}, | ||
| 1402 | {0x900d5,0x788}, | ||
| 1403 | {0x900d6,0x16a}, | ||
| 1404 | {0x900d7,0x1ff8}, | ||
| 1405 | {0x900d8,0x85a8}, | ||
| 1406 | {0x900d9,0x1e8}, | ||
| 1407 | {0x900da,0x50}, | ||
| 1408 | {0x900db,0x798}, | ||
| 1409 | {0x900dc,0x16a}, | ||
| 1410 | {0x900dd,0x60}, | ||
| 1411 | {0x900de,0x7a0}, | ||
| 1412 | {0x900df,0x16a}, | ||
| 1413 | {0x900e0,0x8}, | ||
| 1414 | {0x900e1,0x8310}, | ||
| 1415 | {0x900e2,0x168}, | ||
| 1416 | {0x900e3,0x8}, | ||
| 1417 | {0x900e4,0xa310}, | ||
| 1418 | {0x900e5,0x168}, | ||
| 1419 | {0x900e6,0xa}, | ||
| 1420 | {0x900e7,0x408}, | ||
| 1421 | {0x900e8,0x169}, | ||
| 1422 | {0x900e9,0x6e}, | ||
| 1423 | {0x900ea,0x0}, | ||
| 1424 | {0x900eb,0x68}, | ||
| 1425 | {0x900ec,0x0}, | ||
| 1426 | {0x900ed,0x408}, | ||
| 1427 | {0x900ee,0x169}, | ||
| 1428 | {0x900ef,0x0}, | ||
| 1429 | {0x900f0,0x8310}, | ||
| 1430 | {0x900f1,0x168}, | ||
| 1431 | {0x900f2,0x0}, | ||
| 1432 | {0x900f3,0xa310}, | ||
| 1433 | {0x900f4,0x168}, | ||
| 1434 | {0x900f5,0x1ff8}, | ||
| 1435 | {0x900f6,0x85a8}, | ||
| 1436 | {0x900f7,0x1e8}, | ||
| 1437 | {0x900f8,0x68}, | ||
| 1438 | {0x900f9,0x798}, | ||
| 1439 | {0x900fa,0x16a}, | ||
| 1440 | {0x900fb,0x78}, | ||
| 1441 | {0x900fc,0x7a0}, | ||
| 1442 | {0x900fd,0x16a}, | ||
| 1443 | {0x900fe,0x68}, | ||
| 1444 | {0x900ff,0x790}, | ||
| 1445 | {0x90100,0x16a}, | ||
| 1446 | {0x90101,0x8}, | ||
| 1447 | {0x90102,0x8b10}, | ||
| 1448 | {0x90103,0x168}, | ||
| 1449 | {0x90104,0x8}, | ||
| 1450 | {0x90105,0xab10}, | ||
| 1451 | {0x90106,0x168}, | ||
| 1452 | {0x90107,0xa}, | ||
| 1453 | {0x90108,0x408}, | ||
| 1454 | {0x90109,0x169}, | ||
| 1455 | {0x9010a,0x58}, | ||
| 1456 | {0x9010b,0x0}, | ||
| 1457 | {0x9010c,0x68}, | ||
| 1458 | {0x9010d,0x0}, | ||
| 1459 | {0x9010e,0x408}, | ||
| 1460 | {0x9010f,0x169}, | ||
| 1461 | {0x90110,0x0}, | ||
| 1462 | {0x90111,0x8b10}, | ||
| 1463 | {0x90112,0x168}, | ||
| 1464 | {0x90113,0x0}, | ||
| 1465 | {0x90114,0xab10}, | ||
| 1466 | {0x90115,0x168}, | ||
| 1467 | {0x90116,0x0}, | ||
| 1468 | {0x90117,0x1d8}, | ||
| 1469 | {0x90118,0x169}, | ||
| 1470 | {0x90119,0x80}, | ||
| 1471 | {0x9011a,0x790}, | ||
| 1472 | {0x9011b,0x16a}, | ||
| 1473 | {0x9011c,0x18}, | ||
| 1474 | {0x9011d,0x7aa}, | ||
| 1475 | {0x9011e,0x6a}, | ||
| 1476 | {0x9011f,0xa}, | ||
| 1477 | {0x90120,0x0}, | ||
| 1478 | {0x90121,0x1e9}, | ||
| 1479 | {0x90122,0x8}, | ||
| 1480 | {0x90123,0x8080}, | ||
| 1481 | {0x90124,0x108}, | ||
| 1482 | {0x90125,0xf}, | ||
| 1483 | {0x90126,0x408}, | ||
| 1484 | {0x90127,0x169}, | ||
| 1485 | {0x90128,0xc}, | ||
| 1486 | {0x90129,0x0}, | ||
| 1487 | {0x9012a,0x68}, | ||
| 1488 | {0x9012b,0x9}, | ||
| 1489 | {0x9012c,0x0}, | ||
| 1490 | {0x9012d,0x1a9}, | ||
| 1491 | {0x9012e,0x0}, | ||
| 1492 | {0x9012f,0x408}, | ||
| 1493 | {0x90130,0x169}, | ||
| 1494 | {0x90131,0x0}, | ||
| 1495 | {0x90132,0x8080}, | ||
| 1496 | {0x90133,0x108}, | ||
| 1497 | {0x90134,0x8}, | ||
| 1498 | {0x90135,0x7aa}, | ||
| 1499 | {0x90136,0x6a}, | ||
| 1500 | {0x90137,0x0}, | ||
| 1501 | {0x90138,0x8568}, | ||
| 1502 | {0x90139,0x108}, | ||
| 1503 | {0x9013a,0xb7}, | ||
| 1504 | {0x9013b,0x790}, | ||
| 1505 | {0x9013c,0x16a}, | ||
| 1506 | {0x9013d,0x1f}, | ||
| 1507 | {0x9013e,0x0}, | ||
| 1508 | {0x9013f,0x68}, | ||
| 1509 | {0x90140,0x8}, | ||
| 1510 | {0x90141,0x8558}, | ||
| 1511 | {0x90142,0x168}, | ||
| 1512 | {0x90143,0xf}, | ||
| 1513 | {0x90144,0x408}, | ||
| 1514 | {0x90145,0x169}, | ||
| 1515 | {0x90146,0xc}, | ||
| 1516 | {0x90147,0x0}, | ||
| 1517 | {0x90148,0x68}, | ||
| 1518 | {0x90149,0x0}, | ||
| 1519 | {0x9014a,0x408}, | ||
| 1520 | {0x9014b,0x169}, | ||
| 1521 | {0x9014c,0x0}, | ||
| 1522 | {0x9014d,0x8558}, | ||
| 1523 | {0x9014e,0x168}, | ||
| 1524 | {0x9014f,0x8}, | ||
| 1525 | {0x90150,0x3c8}, | ||
| 1526 | {0x90151,0x1a9}, | ||
| 1527 | {0x90152,0x3}, | ||
| 1528 | {0x90153,0x370}, | ||
| 1529 | {0x90154,0x129}, | ||
| 1530 | {0x90155,0x20}, | ||
| 1531 | {0x90156,0x2aa}, | ||
| 1532 | {0x90157,0x9}, | ||
| 1533 | {0x90158,0x0}, | ||
| 1534 | {0x90159,0x400}, | ||
| 1535 | {0x9015a,0x10e}, | ||
| 1536 | {0x9015b,0x8}, | ||
| 1537 | {0x9015c,0xe8}, | ||
| 1538 | {0x9015d,0x109}, | ||
| 1539 | {0x9015e,0x0}, | ||
| 1540 | {0x9015f,0x8140}, | ||
| 1541 | {0x90160,0x10c}, | ||
| 1542 | {0x90161,0x10}, | ||
| 1543 | {0x90162,0x8138}, | ||
| 1544 | {0x90163,0x10c}, | ||
| 1545 | {0x90164,0x8}, | ||
| 1546 | {0x90165,0x7c8}, | ||
| 1547 | {0x90166,0x101}, | ||
| 1548 | {0x90167,0x8}, | ||
| 1549 | {0x90168,0x0}, | ||
| 1550 | {0x90169,0x8}, | ||
| 1551 | {0x9016a,0x8}, | ||
| 1552 | {0x9016b,0x448}, | ||
| 1553 | {0x9016c,0x109}, | ||
| 1554 | {0x9016d,0xf}, | ||
| 1555 | {0x9016e,0x7c0}, | ||
| 1556 | {0x9016f,0x109}, | ||
| 1557 | {0x90170,0x0}, | ||
| 1558 | {0x90171,0xe8}, | ||
| 1559 | {0x90172,0x109}, | ||
| 1560 | {0x90173,0x47}, | ||
| 1561 | {0x90174,0x630}, | ||
| 1562 | {0x90175,0x109}, | ||
| 1563 | {0x90176,0x8}, | ||
| 1564 | {0x90177,0x618}, | ||
| 1565 | {0x90178,0x109}, | ||
| 1566 | {0x90179,0x8}, | ||
| 1567 | {0x9017a,0xe0}, | ||
| 1568 | {0x9017b,0x109}, | ||
| 1569 | {0x9017c,0x0}, | ||
| 1570 | {0x9017d,0x7c8}, | ||
| 1571 | {0x9017e,0x109}, | ||
| 1572 | {0x9017f,0x8}, | ||
| 1573 | {0x90180,0x8140}, | ||
| 1574 | {0x90181,0x10c}, | ||
| 1575 | {0x90182,0x0}, | ||
| 1576 | {0x90183,0x1}, | ||
| 1577 | {0x90184,0x8}, | ||
| 1578 | {0x90185,0x8}, | ||
| 1579 | {0x90186,0x4}, | ||
| 1580 | {0x90187,0x8}, | ||
| 1581 | {0x90188,0x8}, | ||
| 1582 | {0x90189,0x7c8}, | ||
| 1583 | {0x9018a,0x101}, | ||
| 1584 | {0x90006,0x0}, | ||
| 1585 | {0x90007,0x0}, | ||
| 1586 | {0x90008,0x8}, | ||
| 1587 | {0x90009,0x0}, | ||
| 1588 | {0x9000a,0x0}, | ||
| 1589 | {0x9000b,0x0}, | ||
| 1590 | {0xd00e7,0x400}, | ||
| 1591 | {0x90017,0x0}, | ||
| 1592 | {0x9001f,0x2a}, | ||
| 1593 | {0x90026,0x6a}, | ||
| 1594 | {0x400d0,0x0}, | ||
| 1595 | {0x400d1,0x101}, | ||
| 1596 | {0x400d2,0x105}, | ||
| 1597 | {0x400d3,0x107}, | ||
| 1598 | {0x400d4,0x10f}, | ||
| 1599 | {0x400d5,0x202}, | ||
| 1600 | {0x400d6,0x20a}, | ||
| 1601 | {0x400d7,0x20b}, | ||
| 1602 | {0x2003a,0x2}, | ||
| 1603 | {0x2000b,0x64}, | ||
| 1604 | {0x2000c,0xc8}, | ||
| 1605 | {0x2000d,0x7d0}, | ||
| 1606 | {0x2000e,0x2c}, | ||
| 1607 | {0x12000b,0x14}, | ||
| 1608 | {0x12000c,0x29}, | ||
| 1609 | {0x12000d,0x1a1}, | ||
| 1610 | {0x12000e,0x10}, | ||
| 1611 | {0x9000c,0x0}, | ||
| 1612 | {0x9000d,0x173}, | ||
| 1613 | {0x9000e,0x60}, | ||
| 1614 | {0x9000f,0x6110}, | ||
| 1615 | {0x90010,0x2152}, | ||
| 1616 | {0x90011,0xdfbd}, | ||
| 1617 | {0x90012,0x60}, | ||
| 1618 | {0x90013,0x6152}, | ||
| 1619 | {0x20010,0x5a}, | ||
| 1620 | {0x20011,0x3}, | ||
| 1621 | {0x120010,0x5a}, | ||
| 1622 | {0x120011,0x3}, | ||
| 1623 | {0x40080,0xe0}, | ||
| 1624 | {0x40081,0x12}, | ||
| 1625 | {0x40082,0xe0}, | ||
| 1626 | {0x40083,0x12}, | ||
| 1627 | {0x40084,0xe0}, | ||
| 1628 | {0x40085,0x12}, | ||
| 1629 | {0x140080,0xe0}, | ||
| 1630 | {0x140081,0x12}, | ||
| 1631 | {0x140082,0xe0}, | ||
| 1632 | {0x140083,0x12}, | ||
| 1633 | {0x140084,0xe0}, | ||
| 1634 | {0x140085,0x12}, | ||
| 1635 | {0x400fd,0xf}, | ||
| 1636 | {0x10011,0x1}, | ||
| 1637 | {0x10012,0x1}, | ||
| 1638 | {0x10013,0x180}, | ||
| 1639 | {0x10018,0x1}, | ||
| 1640 | {0x10002,0x6209}, | ||
| 1641 | {0x100b2,0x1}, | ||
| 1642 | {0x101b4,0x1}, | ||
| 1643 | {0x102b4,0x1}, | ||
| 1644 | {0x103b4,0x1}, | ||
| 1645 | {0x104b4,0x1}, | ||
| 1646 | {0x105b4,0x1}, | ||
| 1647 | {0x106b4,0x1}, | ||
| 1648 | {0x107b4,0x1}, | ||
| 1649 | {0x108b4,0x1}, | ||
| 1650 | {0x11011,0x1}, | ||
| 1651 | {0x11012,0x1}, | ||
| 1652 | {0x11013,0x180}, | ||
| 1653 | {0x11018,0x1}, | ||
| 1654 | {0x11002,0x6209}, | ||
| 1655 | {0x110b2,0x1}, | ||
| 1656 | {0x111b4,0x1}, | ||
| 1657 | {0x112b4,0x1}, | ||
| 1658 | {0x113b4,0x1}, | ||
| 1659 | {0x114b4,0x1}, | ||
| 1660 | {0x115b4,0x1}, | ||
| 1661 | {0x116b4,0x1}, | ||
| 1662 | {0x117b4,0x1}, | ||
| 1663 | {0x118b4,0x1}, | ||
| 1664 | {0x12011,0x1}, | ||
| 1665 | {0x12012,0x1}, | ||
| 1666 | {0x12013,0x180}, | ||
| 1667 | {0x12018,0x1}, | ||
| 1668 | {0x12002,0x6209}, | ||
| 1669 | {0x120b2,0x1}, | ||
| 1670 | {0x121b4,0x1}, | ||
| 1671 | {0x122b4,0x1}, | ||
| 1672 | {0x123b4,0x1}, | ||
| 1673 | {0x124b4,0x1}, | ||
| 1674 | {0x125b4,0x1}, | ||
| 1675 | {0x126b4,0x1}, | ||
| 1676 | {0x127b4,0x1}, | ||
| 1677 | {0x128b4,0x1}, | ||
| 1678 | {0x13011,0x1}, | ||
| 1679 | {0x13012,0x1}, | ||
| 1680 | {0x13013,0x180}, | ||
| 1681 | {0x13018,0x1}, | ||
| 1682 | {0x13002,0x6209}, | ||
| 1683 | {0x130b2,0x1}, | ||
| 1684 | {0x131b4,0x1}, | ||
| 1685 | {0x132b4,0x1}, | ||
| 1686 | {0x133b4,0x1}, | ||
| 1687 | {0x134b4,0x1}, | ||
| 1688 | {0x135b4,0x1}, | ||
| 1689 | {0x136b4,0x1}, | ||
| 1690 | {0x137b4,0x1}, | ||
| 1691 | {0x138b4,0x1}, | ||
| 1692 | {0x2003a,0x2}, | ||
| 1693 | {0xc0080,0x2}, | ||
| 1694 | {0xd0000, 0x1} | ||
| 1695 | }; | ||
| 1696 | |||
| 1697 | struct dram_fsp_msg ddr_dram_fsp_msg[] = { | ||
| 1698 | { | ||
| 1699 | /* P0 3200mts 1D */ | ||
| 1700 | .drate = 3200, | ||
| 1701 | .fw_type = FW_1D_IMAGE, | ||
| 1702 | .fsp_cfg = ddr_fsp0_cfg, | ||
| 1703 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), | ||
| 1704 | }, | ||
| 1705 | { | ||
| 1706 | /* P1 667mts 1D */ | ||
| 1707 | .drate = 667, | ||
| 1708 | .fw_type = FW_1D_IMAGE, | ||
| 1709 | .fsp_cfg = ddr_fsp1_cfg, | ||
| 1710 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), | ||
| 1711 | }, | ||
| 1712 | { | ||
| 1713 | /* P0 3200mts 2D */ | ||
| 1714 | .drate = 3200, | ||
| 1715 | .fw_type = FW_2D_IMAGE, | ||
| 1716 | .fsp_cfg = ddr_fsp0_2d_cfg, | ||
| 1717 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), | ||
| 1718 | }, | ||
| 1719 | }; | ||
| 1720 | |||
| 1721 | /* ddr timing config params */ | ||
| 1722 | struct dram_timing_info dram_timing = { | ||
| 1723 | .ddrc_cfg = ddr_ddrc_cfg, | ||
| 1724 | .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), | ||
| 1725 | .ddrphy_cfg = ddr_ddrphy_cfg, | ||
| 1726 | .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), | ||
| 1727 | .fsp_msg = ddr_dram_fsp_msg, | ||
| 1728 | .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), | ||
| 1729 | .ddrphy_trained_csr = ddr_ddrphy_trained_csr, | ||
| 1730 | .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), | ||
| 1731 | .ddrphy_pie = ddr_phy_pie, | ||
| 1732 | .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), | ||
| 1733 | .fsp_table = { 3200, 667, }, | ||
| 1734 | }; | ||
| 1735 | #elif defined(CONFIG_4GB_LPDDR4) | ||
| 1736 | struct dram_cfg_param ddr_ddrc_cfg[] = { | ||
| 1737 | /** Initialize DDRC registers **/ | ||
| 1738 | {0x3d400304,0x1}, | ||
| 1739 | {0x3d400030,0x1}, | ||
| 1740 | {0x3d400000,0xa3080020}, | ||
| 1741 | {0x3d400028,0x0}, | ||
| 1742 | {0x3d400020,0x203}, | ||
| 1743 | {0x3d400024,0x3e800}, | ||
| 1744 | {0x3d400064,0x6100e0}, | ||
| 1745 | {0x3d4000d0,0xc003061c}, | ||
| 1746 | {0x3d4000d4,0x9e0000}, | ||
| 1747 | {0x3d4000dc,0xd4002d}, | ||
| 1748 | {0x3d4000e0,0x310008}, | ||
| 1749 | {0x3d4000e8,0x66004a}, | ||
| 1750 | {0x3d4000ec,0x16004a}, | ||
| 1751 | {0x3d400100,0x1a201b22}, | ||
| 1752 | {0x3d400104,0x60633}, | ||
| 1753 | {0x3d40010c,0xc0c000}, | ||
| 1754 | {0x3d400110,0xf04080f}, | ||
| 1755 | {0x3d400114,0x2040c0c}, | ||
| 1756 | {0x3d400118,0x1010007}, | ||
| 1757 | {0x3d40011c,0x401}, | ||
| 1758 | {0x3d400130,0x20600}, | ||
| 1759 | {0x3d400134,0xc100002}, | ||
| 1760 | {0x3d400138,0xe6}, | ||
| 1761 | {0x3d400144,0xa00050}, | ||
| 1762 | {0x3d400180,0xc3200018}, | ||
| 1763 | {0x3d400184,0x28061a8}, | ||
| 1764 | {0x3d400188,0x0}, | ||
| 1765 | {0x3d400190,0x497820a}, | ||
| 1766 | {0x3d400194,0x80303}, | ||
| 1767 | {0x3d4001a0,0xe0400018}, | ||
| 1768 | {0x3d4001a4,0xdf00e4}, | ||
| 1769 | {0x3d4001a8,0x80000000}, | ||
| 1770 | {0x3d4001b0,0x11}, | ||
| 1771 | {0x3d4001b4,0x170a}, | ||
| 1772 | {0x3d4001c0,0x1}, | ||
| 1773 | {0x3d4001c4,0x1}, | ||
| 1774 | {0x3d4000f4,0x639}, | ||
| 1775 | {0x3d400108,0x70e1617}, | ||
| 1776 | {0x3d400200,0x17}, | ||
| 1777 | {0x3d40020c,0x0}, | ||
| 1778 | {0x3d400210,0x1f1f}, | ||
| 1779 | {0x3d400204,0x80808}, | ||
| 1780 | {0x3d400214,0x7070707}, | ||
| 1781 | {0x3d400218,0x7070707}, | ||
| 1782 | {0x3d402020,0x1}, | ||
| 1783 | {0x3d402024,0xd0c0}, | ||
| 1784 | {0x3d402050,0x20d040}, | ||
| 1785 | {0x3d402064,0x14002f}, | ||
| 1786 | {0x3d4020dc,0x940009}, | ||
| 1787 | {0x3d4020e0,0x310000}, | ||
| 1788 | {0x3d4020e8,0x66004a}, | ||
| 1789 | {0x3d4020ec,0x16004a}, | ||
| 1790 | {0x3d402100,0xb070508}, | ||
| 1791 | {0x3d402104,0x3040b}, | ||
| 1792 | {0x3d402108,0x305090c}, | ||
| 1793 | {0x3d40210c,0x505000}, | ||
| 1794 | {0x3d402110,0x4040204}, | ||
| 1795 | {0x3d402114,0x2030303}, | ||
| 1796 | {0x3d402118,0x1010004}, | ||
| 1797 | {0x3d40211c,0x301}, | ||
| 1798 | {0x3d402130,0x20300}, | ||
| 1799 | {0x3d402134,0xa100002}, | ||
| 1800 | {0x3d402138,0x31}, | ||
| 1801 | {0x3d402144,0x220011}, | ||
| 1802 | {0x3d402180,0xc0a70006}, | ||
| 1803 | {0x3d402190,0x3858202}, | ||
| 1804 | {0x3d402194,0x80303}, | ||
| 1805 | {0x3d4021b4,0x502}, | ||
| 1806 | {0x3d400244,0x0}, | ||
| 1807 | {0x3d400250,0x29001505}, | ||
| 1808 | {0x3d400254,0x2c}, | ||
| 1809 | {0x3d40025c,0x5900575b}, | ||
| 1810 | {0x3d400264,0x90000096}, | ||
| 1811 | {0x3d40026c,0x1000012c}, | ||
| 1812 | {0x3d400300,0x16}, | ||
| 1813 | {0x3d400304,0x0}, | ||
| 1814 | {0x3d40030c,0x0}, | ||
| 1815 | {0x3d400320,0x1}, | ||
| 1816 | {0x3d40036c,0x11}, | ||
| 1817 | {0x3d400400,0x111}, | ||
| 1818 | {0x3d400404,0x10f3}, | ||
| 1819 | {0x3d400408,0x72ff}, | ||
| 1820 | {0x3d400490,0x1}, | ||
| 1821 | {0x3d400494,0xe00}, | ||
| 1822 | {0x3d400498,0x62ffff}, | ||
| 1823 | {0x3d40049c,0xe00}, | ||
| 1824 | {0x3d4004a0,0xffff}, | ||
| 1825 | }; | ||
| 1826 | |||
| 1827 | /* PHY Initialize Configuration */ | ||
| 1828 | struct dram_cfg_param ddr_ddrphy_cfg[] = { | ||
| 1829 | {0x100a0,0x0}, | ||
| 1830 | {0x100a1,0x1}, | ||
| 1831 | {0x100a2,0x2}, | ||
| 1832 | {0x100a3,0x3}, | ||
| 1833 | {0x100a4,0x4}, | ||
| 1834 | {0x100a5,0x5}, | ||
| 1835 | {0x100a6,0x6}, | ||
| 1836 | {0x100a7,0x7}, | ||
| 1837 | {0x110a0,0x0}, | ||
| 1838 | {0x110a1,0x1}, | ||
| 1839 | {0x110a2,0x2}, | ||
| 1840 | {0x110a3,0x3}, | ||
| 1841 | {0x110a4,0x4}, | ||
| 1842 | {0x110a5,0x7}, | ||
| 1843 | {0x110a6,0x6}, | ||
| 1844 | {0x110a7,0x5}, | ||
| 1845 | {0x120a0,0x0}, | ||
| 1846 | {0x120a1,0x1}, | ||
| 1847 | {0x120a2,0x2}, | ||
| 1848 | {0x120a3,0x3}, | ||
| 1849 | {0x120a4,0x4}, | ||
| 1850 | {0x120a5,0x5}, | ||
| 1851 | {0x120a6,0x6}, | ||
| 1852 | {0x120a7,0x7}, | ||
| 1853 | {0x130a0,0x0}, | ||
| 1854 | {0x130a1,0x1}, | ||
| 1855 | {0x130a2,0x2}, | ||
| 1856 | {0x130a3,0x3}, | ||
| 1857 | {0x130a4,0x4}, | ||
| 1858 | {0x130a5,0x5}, | ||
| 1859 | {0x130a6,0x6}, | ||
| 1860 | {0x130a7,0x7}, | ||
| 1861 | {0x20110,0x2}, | ||
| 1862 | {0x20111,0x3}, | ||
| 1863 | {0x20112,0x4}, | ||
| 1864 | {0x20113,0x5}, | ||
| 1865 | {0x20114,0x0}, | ||
| 1866 | {0x20115,0x1}, | ||
| 1867 | {0x1005f,0x1ff}, | ||
| 1868 | {0x1015f,0x1ff}, | ||
| 1869 | {0x1105f,0x1ff}, | ||
| 1870 | {0x1115f,0x1ff}, | ||
| 1871 | {0x1205f,0x1ff}, | ||
| 1872 | {0x1215f,0x1ff}, | ||
| 1873 | {0x1305f,0x1ff}, | ||
| 1874 | {0x1315f,0x1ff}, | ||
| 1875 | {0x11005f,0x1ff}, | ||
| 1876 | {0x11015f,0x1ff}, | ||
| 1877 | {0x11105f,0x1ff}, | ||
| 1878 | {0x11115f,0x1ff}, | ||
| 1879 | {0x11205f,0x1ff}, | ||
| 1880 | {0x11215f,0x1ff}, | ||
| 1881 | {0x11305f,0x1ff}, | ||
| 1882 | {0x11315f,0x1ff}, | ||
| 1883 | {0x55,0x1ff}, | ||
| 1884 | {0x1055,0x1ff}, | ||
| 1885 | {0x2055,0x1ff}, | ||
| 1886 | {0x3055,0x1ff}, | ||
| 1887 | {0x4055,0x1ff}, | ||
| 1888 | {0x5055,0x1ff}, | ||
| 1889 | {0x6055,0x1ff}, | ||
| 1890 | {0x7055,0x1ff}, | ||
| 1891 | {0x8055,0x1ff}, | ||
| 1892 | {0x9055,0x1ff}, | ||
| 1893 | {0x200c5,0x19}, | ||
| 1894 | {0x1200c5,0x7}, | ||
| 1895 | {0x2002e,0x2}, | ||
| 1896 | {0x12002e,0x1}, | ||
| 1897 | {0x90204,0x0}, | ||
| 1898 | {0x190204,0x0}, | ||
| 1899 | {0x20024,0x1ab}, | ||
| 1900 | {0x2003a,0x0}, | ||
| 1901 | {0x120024,0x1ab}, | ||
| 1902 | {0x2003a,0x0}, | ||
| 1903 | {0x20056,0x3}, | ||
| 1904 | {0x120056,0xa}, | ||
| 1905 | {0x1004d,0xe00}, | ||
| 1906 | {0x1014d,0xe00}, | ||
| 1907 | {0x1104d,0xe00}, | ||
| 1908 | {0x1114d,0xe00}, | ||
| 1909 | {0x1204d,0xe00}, | ||
| 1910 | {0x1214d,0xe00}, | ||
| 1911 | {0x1304d,0xe00}, | ||
| 1912 | {0x1314d,0xe00}, | ||
| 1913 | {0x11004d,0xe00}, | ||
| 1914 | {0x11014d,0xe00}, | ||
| 1915 | {0x11104d,0xe00}, | ||
| 1916 | {0x11114d,0xe00}, | ||
| 1917 | {0x11204d,0xe00}, | ||
| 1918 | {0x11214d,0xe00}, | ||
| 1919 | {0x11304d,0xe00}, | ||
| 1920 | {0x11314d,0xe00}, | ||
| 1921 | {0x10049,0xeba}, | ||
| 1922 | {0x10149,0xeba}, | ||
| 1923 | {0x11049,0xeba}, | ||
| 1924 | {0x11149,0xeba}, | ||
| 1925 | {0x12049,0xeba}, | ||
| 1926 | {0x12149,0xeba}, | ||
| 1927 | {0x13049,0xeba}, | ||
| 1928 | {0x13149,0xeba}, | ||
| 1929 | {0x110049,0xeba}, | ||
| 1930 | {0x110149,0xeba}, | ||
| 1931 | {0x111049,0xeba}, | ||
| 1932 | {0x111149,0xeba}, | ||
| 1933 | {0x112049,0xeba}, | ||
| 1934 | {0x112149,0xeba}, | ||
| 1935 | {0x113049,0xeba}, | ||
| 1936 | {0x113149,0xeba}, | ||
| 1937 | {0x43,0x63}, | ||
| 1938 | {0x1043,0x63}, | ||
| 1939 | {0x2043,0x63}, | ||
| 1940 | {0x3043,0x63}, | ||
| 1941 | {0x4043,0x63}, | ||
| 1942 | {0x5043,0x63}, | ||
| 1943 | {0x6043,0x63}, | ||
| 1944 | {0x7043,0x63}, | ||
| 1945 | {0x8043,0x63}, | ||
| 1946 | {0x9043,0x63}, | ||
| 1947 | {0x20018,0x3}, | ||
| 1948 | {0x20075,0x4}, | ||
| 1949 | {0x20050,0x0}, | ||
| 1950 | {0x20008,0x320}, | ||
| 1951 | {0x120008,0xa7}, | ||
| 1952 | {0x20088,0x9}, | ||
| 1953 | {0x200b2,0xdc}, | ||
| 1954 | {0x10043,0x5a1}, | ||
| 1955 | {0x10143,0x5a1}, | ||
| 1956 | {0x11043,0x5a1}, | ||
| 1957 | {0x11143,0x5a1}, | ||
| 1958 | {0x12043,0x5a1}, | ||
| 1959 | {0x12143,0x5a1}, | ||
| 1960 | {0x13043,0x5a1}, | ||
| 1961 | {0x13143,0x5a1}, | ||
| 1962 | {0x1200b2,0xdc}, | ||
| 1963 | {0x110043,0x5a1}, | ||
| 1964 | {0x110143,0x5a1}, | ||
| 1965 | {0x111043,0x5a1}, | ||
| 1966 | {0x111143,0x5a1}, | ||
| 1967 | {0x112043,0x5a1}, | ||
| 1968 | {0x112143,0x5a1}, | ||
| 1969 | {0x113043,0x5a1}, | ||
| 1970 | {0x113143,0x5a1}, | ||
| 1971 | {0x200fa,0x1}, | ||
| 1972 | {0x1200fa,0x1}, | ||
| 1973 | {0x20019,0x1}, | ||
| 1974 | {0x120019,0x1}, | ||
| 1975 | {0x200f0,0x0}, | ||
| 1976 | {0x200f1,0x0}, | ||
| 1977 | {0x200f2,0x4444}, | ||
| 1978 | {0x200f3,0x8888}, | ||
| 1979 | {0x200f4,0x5555}, | ||
| 1980 | {0x200f5,0x0}, | ||
| 1981 | {0x200f6,0x0}, | ||
| 1982 | {0x200f7,0xf000}, | ||
| 1983 | {0x20025,0x0}, | ||
| 1984 | {0x2002d,0x0}, | ||
| 1985 | {0x12002d,0x0}, | ||
| 1986 | {0x200c7,0x80}, | ||
| 1987 | {0x1200c7,0x80}, | ||
| 1988 | {0x200ca,0x106}, | ||
| 1989 | {0x1200ca,0x106}, | ||
| 1990 | }; | ||
| 1991 | |||
| 1992 | /* ddr phy trained csr */ | ||
| 1993 | struct dram_cfg_param ddr_ddrphy_trained_csr[] = { | ||
| 1994 | { 0x200b2, 0x0 }, | ||
| 1995 | { 0x1200b2, 0x0 }, | ||
| 1996 | { 0x2200b2, 0x0 }, | ||
| 1997 | { 0x200cb, 0x0 }, | ||
| 1998 | { 0x10043, 0x0 }, | ||
| 1999 | { 0x110043, 0x0 }, | ||
| 2000 | { 0x210043, 0x0 }, | ||
| 2001 | { 0x10143, 0x0 }, | ||
| 2002 | { 0x110143, 0x0 }, | ||
| 2003 | { 0x210143, 0x0 }, | ||
| 2004 | { 0x11043, 0x0 }, | ||
| 2005 | { 0x111043, 0x0 }, | ||
| 2006 | { 0x211043, 0x0 }, | ||
| 2007 | { 0x11143, 0x0 }, | ||
| 2008 | { 0x111143, 0x0 }, | ||
| 2009 | { 0x211143, 0x0 }, | ||
| 2010 | { 0x12043, 0x0 }, | ||
| 2011 | { 0x112043, 0x0 }, | ||
| 2012 | { 0x212043, 0x0 }, | ||
| 2013 | { 0x12143, 0x0 }, | ||
| 2014 | { 0x112143, 0x0 }, | ||
| 2015 | { 0x212143, 0x0 }, | ||
| 2016 | { 0x13043, 0x0 }, | ||
| 2017 | { 0x113043, 0x0 }, | ||
| 2018 | { 0x213043, 0x0 }, | ||
| 2019 | { 0x13143, 0x0 }, | ||
| 2020 | { 0x113143, 0x0 }, | ||
| 2021 | { 0x213143, 0x0 }, | ||
| 2022 | { 0x80, 0x0 }, | ||
| 2023 | { 0x100080, 0x0 }, | ||
| 2024 | { 0x200080, 0x0 }, | ||
| 2025 | { 0x1080, 0x0 }, | ||
| 2026 | { 0x101080, 0x0 }, | ||
| 2027 | { 0x201080, 0x0 }, | ||
| 2028 | { 0x2080, 0x0 }, | ||
| 2029 | { 0x102080, 0x0 }, | ||
| 2030 | { 0x202080, 0x0 }, | ||
| 2031 | { 0x3080, 0x0 }, | ||
| 2032 | { 0x103080, 0x0 }, | ||
| 2033 | { 0x203080, 0x0 }, | ||
| 2034 | { 0x4080, 0x0 }, | ||
| 2035 | { 0x104080, 0x0 }, | ||
| 2036 | { 0x204080, 0x0 }, | ||
| 2037 | { 0x5080, 0x0 }, | ||
| 2038 | { 0x105080, 0x0 }, | ||
| 2039 | { 0x205080, 0x0 }, | ||
| 2040 | { 0x6080, 0x0 }, | ||
| 2041 | { 0x106080, 0x0 }, | ||
| 2042 | { 0x206080, 0x0 }, | ||
| 2043 | { 0x7080, 0x0 }, | ||
| 2044 | { 0x107080, 0x0 }, | ||
| 2045 | { 0x207080, 0x0 }, | ||
| 2046 | { 0x8080, 0x0 }, | ||
| 2047 | { 0x108080, 0x0 }, | ||
| 2048 | { 0x208080, 0x0 }, | ||
| 2049 | { 0x9080, 0x0 }, | ||
| 2050 | { 0x109080, 0x0 }, | ||
| 2051 | { 0x209080, 0x0 }, | ||
| 2052 | { 0x10080, 0x0 }, | ||
| 2053 | { 0x110080, 0x0 }, | ||
| 2054 | { 0x210080, 0x0 }, | ||
| 2055 | { 0x10180, 0x0 }, | ||
| 2056 | { 0x110180, 0x0 }, | ||
| 2057 | { 0x210180, 0x0 }, | ||
| 2058 | { 0x11080, 0x0 }, | ||
| 2059 | { 0x111080, 0x0 }, | ||
| 2060 | { 0x211080, 0x0 }, | ||
| 2061 | { 0x11180, 0x0 }, | ||
| 2062 | { 0x111180, 0x0 }, | ||
| 2063 | { 0x211180, 0x0 }, | ||
| 2064 | { 0x12080, 0x0 }, | ||
| 2065 | { 0x112080, 0x0 }, | ||
| 2066 | { 0x212080, 0x0 }, | ||
| 2067 | { 0x12180, 0x0 }, | ||
| 2068 | { 0x112180, 0x0 }, | ||
| 2069 | { 0x212180, 0x0 }, | ||
| 2070 | { 0x13080, 0x0 }, | ||
| 2071 | { 0x113080, 0x0 }, | ||
| 2072 | { 0x213080, 0x0 }, | ||
| 2073 | { 0x13180, 0x0 }, | ||
| 2074 | { 0x113180, 0x0 }, | ||
| 2075 | { 0x213180, 0x0 }, | ||
| 2076 | { 0x10081, 0x0 }, | ||
| 2077 | { 0x110081, 0x0 }, | ||
| 2078 | { 0x210081, 0x0 }, | ||
| 2079 | { 0x10181, 0x0 }, | ||
| 2080 | { 0x110181, 0x0 }, | ||
| 2081 | { 0x210181, 0x0 }, | ||
| 2082 | { 0x11081, 0x0 }, | ||
| 2083 | { 0x111081, 0x0 }, | ||
| 2084 | { 0x211081, 0x0 }, | ||
| 2085 | { 0x11181, 0x0 }, | ||
| 2086 | { 0x111181, 0x0 }, | ||
| 2087 | { 0x211181, 0x0 }, | ||
| 2088 | { 0x12081, 0x0 }, | ||
| 2089 | { 0x112081, 0x0 }, | ||
| 2090 | { 0x212081, 0x0 }, | ||
| 2091 | { 0x12181, 0x0 }, | ||
| 2092 | { 0x112181, 0x0 }, | ||
| 2093 | { 0x212181, 0x0 }, | ||
| 2094 | { 0x13081, 0x0 }, | ||
| 2095 | { 0x113081, 0x0 }, | ||
| 2096 | { 0x213081, 0x0 }, | ||
| 2097 | { 0x13181, 0x0 }, | ||
| 2098 | { 0x113181, 0x0 }, | ||
| 2099 | { 0x213181, 0x0 }, | ||
| 2100 | { 0x100d0, 0x0 }, | ||
| 2101 | { 0x1100d0, 0x0 }, | ||
| 2102 | { 0x2100d0, 0x0 }, | ||
| 2103 | { 0x101d0, 0x0 }, | ||
| 2104 | { 0x1101d0, 0x0 }, | ||
| 2105 | { 0x2101d0, 0x0 }, | ||
| 2106 | { 0x110d0, 0x0 }, | ||
| 2107 | { 0x1110d0, 0x0 }, | ||
| 2108 | { 0x2110d0, 0x0 }, | ||
| 2109 | { 0x111d0, 0x0 }, | ||
| 2110 | { 0x1111d0, 0x0 }, | ||
| 2111 | { 0x2111d0, 0x0 }, | ||
| 2112 | { 0x120d0, 0x0 }, | ||
| 2113 | { 0x1120d0, 0x0 }, | ||
| 2114 | { 0x2120d0, 0x0 }, | ||
| 2115 | { 0x121d0, 0x0 }, | ||
| 2116 | { 0x1121d0, 0x0 }, | ||
| 2117 | { 0x2121d0, 0x0 }, | ||
| 2118 | { 0x130d0, 0x0 }, | ||
| 2119 | { 0x1130d0, 0x0 }, | ||
| 2120 | { 0x2130d0, 0x0 }, | ||
| 2121 | { 0x131d0, 0x0 }, | ||
| 2122 | { 0x1131d0, 0x0 }, | ||
| 2123 | { 0x2131d0, 0x0 }, | ||
| 2124 | { 0x100d1, 0x0 }, | ||
| 2125 | { 0x1100d1, 0x0 }, | ||
| 2126 | { 0x2100d1, 0x0 }, | ||
| 2127 | { 0x101d1, 0x0 }, | ||
| 2128 | { 0x1101d1, 0x0 }, | ||
| 2129 | { 0x2101d1, 0x0 }, | ||
| 2130 | { 0x110d1, 0x0 }, | ||
| 2131 | { 0x1110d1, 0x0 }, | ||
| 2132 | { 0x2110d1, 0x0 }, | ||
| 2133 | { 0x111d1, 0x0 }, | ||
| 2134 | { 0x1111d1, 0x0 }, | ||
| 2135 | { 0x2111d1, 0x0 }, | ||
| 2136 | { 0x120d1, 0x0 }, | ||
| 2137 | { 0x1120d1, 0x0 }, | ||
| 2138 | { 0x2120d1, 0x0 }, | ||
| 2139 | { 0x121d1, 0x0 }, | ||
| 2140 | { 0x1121d1, 0x0 }, | ||
| 2141 | { 0x2121d1, 0x0 }, | ||
| 2142 | { 0x130d1, 0x0 }, | ||
| 2143 | { 0x1130d1, 0x0 }, | ||
| 2144 | { 0x2130d1, 0x0 }, | ||
| 2145 | { 0x131d1, 0x0 }, | ||
| 2146 | { 0x1131d1, 0x0 }, | ||
| 2147 | { 0x2131d1, 0x0 }, | ||
| 2148 | { 0x10068, 0x0 }, | ||
| 2149 | { 0x10168, 0x0 }, | ||
| 2150 | { 0x10268, 0x0 }, | ||
| 2151 | { 0x10368, 0x0 }, | ||
| 2152 | { 0x10468, 0x0 }, | ||
| 2153 | { 0x10568, 0x0 }, | ||
| 2154 | { 0x10668, 0x0 }, | ||
| 2155 | { 0x10768, 0x0 }, | ||
| 2156 | { 0x10868, 0x0 }, | ||
| 2157 | { 0x11068, 0x0 }, | ||
| 2158 | { 0x11168, 0x0 }, | ||
| 2159 | { 0x11268, 0x0 }, | ||
| 2160 | { 0x11368, 0x0 }, | ||
| 2161 | { 0x11468, 0x0 }, | ||
| 2162 | { 0x11568, 0x0 }, | ||
| 2163 | { 0x11668, 0x0 }, | ||
| 2164 | { 0x11768, 0x0 }, | ||
| 2165 | { 0x11868, 0x0 }, | ||
| 2166 | { 0x12068, 0x0 }, | ||
| 2167 | { 0x12168, 0x0 }, | ||
| 2168 | { 0x12268, 0x0 }, | ||
| 2169 | { 0x12368, 0x0 }, | ||
| 2170 | { 0x12468, 0x0 }, | ||
| 2171 | { 0x12568, 0x0 }, | ||
| 2172 | { 0x12668, 0x0 }, | ||
| 2173 | { 0x12768, 0x0 }, | ||
| 2174 | { 0x12868, 0x0 }, | ||
| 2175 | { 0x13068, 0x0 }, | ||
| 2176 | { 0x13168, 0x0 }, | ||
| 2177 | { 0x13268, 0x0 }, | ||
| 2178 | { 0x13368, 0x0 }, | ||
| 2179 | { 0x13468, 0x0 }, | ||
| 2180 | { 0x13568, 0x0 }, | ||
| 2181 | { 0x13668, 0x0 }, | ||
| 2182 | { 0x13768, 0x0 }, | ||
| 2183 | { 0x13868, 0x0 }, | ||
| 2184 | { 0x10069, 0x0 }, | ||
| 2185 | { 0x10169, 0x0 }, | ||
| 2186 | { 0x10269, 0x0 }, | ||
| 2187 | { 0x10369, 0x0 }, | ||
| 2188 | { 0x10469, 0x0 }, | ||
| 2189 | { 0x10569, 0x0 }, | ||
| 2190 | { 0x10669, 0x0 }, | ||
| 2191 | { 0x10769, 0x0 }, | ||
| 2192 | { 0x10869, 0x0 }, | ||
| 2193 | { 0x11069, 0x0 }, | ||
| 2194 | { 0x11169, 0x0 }, | ||
| 2195 | { 0x11269, 0x0 }, | ||
| 2196 | { 0x11369, 0x0 }, | ||
| 2197 | { 0x11469, 0x0 }, | ||
| 2198 | { 0x11569, 0x0 }, | ||
| 2199 | { 0x11669, 0x0 }, | ||
| 2200 | { 0x11769, 0x0 }, | ||
| 2201 | { 0x11869, 0x0 }, | ||
| 2202 | { 0x12069, 0x0 }, | ||
| 2203 | { 0x12169, 0x0 }, | ||
| 2204 | { 0x12269, 0x0 }, | ||
| 2205 | { 0x12369, 0x0 }, | ||
| 2206 | { 0x12469, 0x0 }, | ||
| 2207 | { 0x12569, 0x0 }, | ||
| 2208 | { 0x12669, 0x0 }, | ||
| 2209 | { 0x12769, 0x0 }, | ||
| 2210 | { 0x12869, 0x0 }, | ||
| 2211 | { 0x13069, 0x0 }, | ||
| 2212 | { 0x13169, 0x0 }, | ||
| 2213 | { 0x13269, 0x0 }, | ||
| 2214 | { 0x13369, 0x0 }, | ||
| 2215 | { 0x13469, 0x0 }, | ||
| 2216 | { 0x13569, 0x0 }, | ||
| 2217 | { 0x13669, 0x0 }, | ||
| 2218 | { 0x13769, 0x0 }, | ||
| 2219 | { 0x13869, 0x0 }, | ||
| 2220 | { 0x1008c, 0x0 }, | ||
| 2221 | { 0x11008c, 0x0 }, | ||
| 2222 | { 0x21008c, 0x0 }, | ||
| 2223 | { 0x1018c, 0x0 }, | ||
| 2224 | { 0x11018c, 0x0 }, | ||
| 2225 | { 0x21018c, 0x0 }, | ||
| 2226 | { 0x1108c, 0x0 }, | ||
| 2227 | { 0x11108c, 0x0 }, | ||
| 2228 | { 0x21108c, 0x0 }, | ||
| 2229 | { 0x1118c, 0x0 }, | ||
| 2230 | { 0x11118c, 0x0 }, | ||
| 2231 | { 0x21118c, 0x0 }, | ||
| 2232 | { 0x1208c, 0x0 }, | ||
| 2233 | { 0x11208c, 0x0 }, | ||
| 2234 | { 0x21208c, 0x0 }, | ||
| 2235 | { 0x1218c, 0x0 }, | ||
| 2236 | { 0x11218c, 0x0 }, | ||
| 2237 | { 0x21218c, 0x0 }, | ||
| 2238 | { 0x1308c, 0x0 }, | ||
| 2239 | { 0x11308c, 0x0 }, | ||
| 2240 | { 0x21308c, 0x0 }, | ||
| 2241 | { 0x1318c, 0x0 }, | ||
| 2242 | { 0x11318c, 0x0 }, | ||
| 2243 | { 0x21318c, 0x0 }, | ||
| 2244 | { 0x1008d, 0x0 }, | ||
| 2245 | { 0x11008d, 0x0 }, | ||
| 2246 | { 0x21008d, 0x0 }, | ||
| 2247 | { 0x1018d, 0x0 }, | ||
| 2248 | { 0x11018d, 0x0 }, | ||
| 2249 | { 0x21018d, 0x0 }, | ||
| 2250 | { 0x1108d, 0x0 }, | ||
| 2251 | { 0x11108d, 0x0 }, | ||
| 2252 | { 0x21108d, 0x0 }, | ||
| 2253 | { 0x1118d, 0x0 }, | ||
| 2254 | { 0x11118d, 0x0 }, | ||
| 2255 | { 0x21118d, 0x0 }, | ||
| 2256 | { 0x1208d, 0x0 }, | ||
| 2257 | { 0x11208d, 0x0 }, | ||
| 2258 | { 0x21208d, 0x0 }, | ||
| 2259 | { 0x1218d, 0x0 }, | ||
| 2260 | { 0x11218d, 0x0 }, | ||
| 2261 | { 0x21218d, 0x0 }, | ||
| 2262 | { 0x1308d, 0x0 }, | ||
| 2263 | { 0x11308d, 0x0 }, | ||
| 2264 | { 0x21308d, 0x0 }, | ||
| 2265 | { 0x1318d, 0x0 }, | ||
| 2266 | { 0x11318d, 0x0 }, | ||
| 2267 | { 0x21318d, 0x0 }, | ||
| 2268 | { 0x100c0, 0x0 }, | ||
| 2269 | { 0x1100c0, 0x0 }, | ||
| 2270 | { 0x2100c0, 0x0 }, | ||
| 2271 | { 0x101c0, 0x0 }, | ||
| 2272 | { 0x1101c0, 0x0 }, | ||
| 2273 | { 0x2101c0, 0x0 }, | ||
| 2274 | { 0x102c0, 0x0 }, | ||
| 2275 | { 0x1102c0, 0x0 }, | ||
| 2276 | { 0x2102c0, 0x0 }, | ||
| 2277 | { 0x103c0, 0x0 }, | ||
| 2278 | { 0x1103c0, 0x0 }, | ||
| 2279 | { 0x2103c0, 0x0 }, | ||
| 2280 | { 0x104c0, 0x0 }, | ||
| 2281 | { 0x1104c0, 0x0 }, | ||
| 2282 | { 0x2104c0, 0x0 }, | ||
| 2283 | { 0x105c0, 0x0 }, | ||
| 2284 | { 0x1105c0, 0x0 }, | ||
| 2285 | { 0x2105c0, 0x0 }, | ||
| 2286 | { 0x106c0, 0x0 }, | ||
| 2287 | { 0x1106c0, 0x0 }, | ||
| 2288 | { 0x2106c0, 0x0 }, | ||
| 2289 | { 0x107c0, 0x0 }, | ||
| 2290 | { 0x1107c0, 0x0 }, | ||
| 2291 | { 0x2107c0, 0x0 }, | ||
| 2292 | { 0x108c0, 0x0 }, | ||
| 2293 | { 0x1108c0, 0x0 }, | ||
| 2294 | { 0x2108c0, 0x0 }, | ||
| 2295 | { 0x110c0, 0x0 }, | ||
| 2296 | { 0x1110c0, 0x0 }, | ||
| 2297 | { 0x2110c0, 0x0 }, | ||
| 2298 | { 0x111c0, 0x0 }, | ||
| 2299 | { 0x1111c0, 0x0 }, | ||
| 2300 | { 0x2111c0, 0x0 }, | ||
| 2301 | { 0x112c0, 0x0 }, | ||
| 2302 | { 0x1112c0, 0x0 }, | ||
| 2303 | { 0x2112c0, 0x0 }, | ||
| 2304 | { 0x113c0, 0x0 }, | ||
| 2305 | { 0x1113c0, 0x0 }, | ||
| 2306 | { 0x2113c0, 0x0 }, | ||
| 2307 | { 0x114c0, 0x0 }, | ||
| 2308 | { 0x1114c0, 0x0 }, | ||
| 2309 | { 0x2114c0, 0x0 }, | ||
| 2310 | { 0x115c0, 0x0 }, | ||
| 2311 | { 0x1115c0, 0x0 }, | ||
| 2312 | { 0x2115c0, 0x0 }, | ||
| 2313 | { 0x116c0, 0x0 }, | ||
| 2314 | { 0x1116c0, 0x0 }, | ||
| 2315 | { 0x2116c0, 0x0 }, | ||
| 2316 | { 0x117c0, 0x0 }, | ||
| 2317 | { 0x1117c0, 0x0 }, | ||
| 2318 | { 0x2117c0, 0x0 }, | ||
| 2319 | { 0x118c0, 0x0 }, | ||
| 2320 | { 0x1118c0, 0x0 }, | ||
| 2321 | { 0x2118c0, 0x0 }, | ||
| 2322 | { 0x120c0, 0x0 }, | ||
| 2323 | { 0x1120c0, 0x0 }, | ||
| 2324 | { 0x2120c0, 0x0 }, | ||
| 2325 | { 0x121c0, 0x0 }, | ||
| 2326 | { 0x1121c0, 0x0 }, | ||
| 2327 | { 0x2121c0, 0x0 }, | ||
| 2328 | { 0x122c0, 0x0 }, | ||
| 2329 | { 0x1122c0, 0x0 }, | ||
| 2330 | { 0x2122c0, 0x0 }, | ||
| 2331 | { 0x123c0, 0x0 }, | ||
| 2332 | { 0x1123c0, 0x0 }, | ||
| 2333 | { 0x2123c0, 0x0 }, | ||
| 2334 | { 0x124c0, 0x0 }, | ||
| 2335 | { 0x1124c0, 0x0 }, | ||
| 2336 | { 0x2124c0, 0x0 }, | ||
| 2337 | { 0x125c0, 0x0 }, | ||
| 2338 | { 0x1125c0, 0x0 }, | ||
| 2339 | { 0x2125c0, 0x0 }, | ||
| 2340 | { 0x126c0, 0x0 }, | ||
| 2341 | { 0x1126c0, 0x0 }, | ||
| 2342 | { 0x2126c0, 0x0 }, | ||
| 2343 | { 0x127c0, 0x0 }, | ||
| 2344 | { 0x1127c0, 0x0 }, | ||
| 2345 | { 0x2127c0, 0x0 }, | ||
| 2346 | { 0x128c0, 0x0 }, | ||
| 2347 | { 0x1128c0, 0x0 }, | ||
| 2348 | { 0x2128c0, 0x0 }, | ||
| 2349 | { 0x130c0, 0x0 }, | ||
| 2350 | { 0x1130c0, 0x0 }, | ||
| 2351 | { 0x2130c0, 0x0 }, | ||
| 2352 | { 0x131c0, 0x0 }, | ||
| 2353 | { 0x1131c0, 0x0 }, | ||
| 2354 | { 0x2131c0, 0x0 }, | ||
| 2355 | { 0x132c0, 0x0 }, | ||
| 2356 | { 0x1132c0, 0x0 }, | ||
| 2357 | { 0x2132c0, 0x0 }, | ||
| 2358 | { 0x133c0, 0x0 }, | ||
| 2359 | { 0x1133c0, 0x0 }, | ||
| 2360 | { 0x2133c0, 0x0 }, | ||
| 2361 | { 0x134c0, 0x0 }, | ||
| 2362 | { 0x1134c0, 0x0 }, | ||
| 2363 | { 0x2134c0, 0x0 }, | ||
| 2364 | { 0x135c0, 0x0 }, | ||
| 2365 | { 0x1135c0, 0x0 }, | ||
| 2366 | { 0x2135c0, 0x0 }, | ||
| 2367 | { 0x136c0, 0x0 }, | ||
| 2368 | { 0x1136c0, 0x0 }, | ||
| 2369 | { 0x2136c0, 0x0 }, | ||
| 2370 | { 0x137c0, 0x0 }, | ||
| 2371 | { 0x1137c0, 0x0 }, | ||
| 2372 | { 0x2137c0, 0x0 }, | ||
| 2373 | { 0x138c0, 0x0 }, | ||
| 2374 | { 0x1138c0, 0x0 }, | ||
| 2375 | { 0x2138c0, 0x0 }, | ||
| 2376 | { 0x100c1, 0x0 }, | ||
| 2377 | { 0x1100c1, 0x0 }, | ||
| 2378 | { 0x2100c1, 0x0 }, | ||
| 2379 | { 0x101c1, 0x0 }, | ||
| 2380 | { 0x1101c1, 0x0 }, | ||
| 2381 | { 0x2101c1, 0x0 }, | ||
| 2382 | { 0x102c1, 0x0 }, | ||
| 2383 | { 0x1102c1, 0x0 }, | ||
| 2384 | { 0x2102c1, 0x0 }, | ||
| 2385 | { 0x103c1, 0x0 }, | ||
| 2386 | { 0x1103c1, 0x0 }, | ||
| 2387 | { 0x2103c1, 0x0 }, | ||
| 2388 | { 0x104c1, 0x0 }, | ||
| 2389 | { 0x1104c1, 0x0 }, | ||
| 2390 | { 0x2104c1, 0x0 }, | ||
| 2391 | { 0x105c1, 0x0 }, | ||
| 2392 | { 0x1105c1, 0x0 }, | ||
| 2393 | { 0x2105c1, 0x0 }, | ||
| 2394 | { 0x106c1, 0x0 }, | ||
| 2395 | { 0x1106c1, 0x0 }, | ||
| 2396 | { 0x2106c1, 0x0 }, | ||
| 2397 | { 0x107c1, 0x0 }, | ||
| 2398 | { 0x1107c1, 0x0 }, | ||
| 2399 | { 0x2107c1, 0x0 }, | ||
| 2400 | { 0x108c1, 0x0 }, | ||
| 2401 | { 0x1108c1, 0x0 }, | ||
| 2402 | { 0x2108c1, 0x0 }, | ||
| 2403 | { 0x110c1, 0x0 }, | ||
| 2404 | { 0x1110c1, 0x0 }, | ||
| 2405 | { 0x2110c1, 0x0 }, | ||
| 2406 | { 0x111c1, 0x0 }, | ||
| 2407 | { 0x1111c1, 0x0 }, | ||
| 2408 | { 0x2111c1, 0x0 }, | ||
| 2409 | { 0x112c1, 0x0 }, | ||
| 2410 | { 0x1112c1, 0x0 }, | ||
| 2411 | { 0x2112c1, 0x0 }, | ||
| 2412 | { 0x113c1, 0x0 }, | ||
| 2413 | { 0x1113c1, 0x0 }, | ||
| 2414 | { 0x2113c1, 0x0 }, | ||
| 2415 | { 0x114c1, 0x0 }, | ||
| 2416 | { 0x1114c1, 0x0 }, | ||
| 2417 | { 0x2114c1, 0x0 }, | ||
| 2418 | { 0x115c1, 0x0 }, | ||
| 2419 | { 0x1115c1, 0x0 }, | ||
| 2420 | { 0x2115c1, 0x0 }, | ||
| 2421 | { 0x116c1, 0x0 }, | ||
| 2422 | { 0x1116c1, 0x0 }, | ||
| 2423 | { 0x2116c1, 0x0 }, | ||
| 2424 | { 0x117c1, 0x0 }, | ||
| 2425 | { 0x1117c1, 0x0 }, | ||
| 2426 | { 0x2117c1, 0x0 }, | ||
| 2427 | { 0x118c1, 0x0 }, | ||
| 2428 | { 0x1118c1, 0x0 }, | ||
| 2429 | { 0x2118c1, 0x0 }, | ||
| 2430 | { 0x120c1, 0x0 }, | ||
| 2431 | { 0x1120c1, 0x0 }, | ||
| 2432 | { 0x2120c1, 0x0 }, | ||
| 2433 | { 0x121c1, 0x0 }, | ||
| 2434 | { 0x1121c1, 0x0 }, | ||
| 2435 | { 0x2121c1, 0x0 }, | ||
| 2436 | { 0x122c1, 0x0 }, | ||
| 2437 | { 0x1122c1, 0x0 }, | ||
| 2438 | { 0x2122c1, 0x0 }, | ||
| 2439 | { 0x123c1, 0x0 }, | ||
| 2440 | { 0x1123c1, 0x0 }, | ||
| 2441 | { 0x2123c1, 0x0 }, | ||
| 2442 | { 0x124c1, 0x0 }, | ||
| 2443 | { 0x1124c1, 0x0 }, | ||
| 2444 | { 0x2124c1, 0x0 }, | ||
| 2445 | { 0x125c1, 0x0 }, | ||
| 2446 | { 0x1125c1, 0x0 }, | ||
| 2447 | { 0x2125c1, 0x0 }, | ||
| 2448 | { 0x126c1, 0x0 }, | ||
| 2449 | { 0x1126c1, 0x0 }, | ||
| 2450 | { 0x2126c1, 0x0 }, | ||
| 2451 | { 0x127c1, 0x0 }, | ||
| 2452 | { 0x1127c1, 0x0 }, | ||
| 2453 | { 0x2127c1, 0x0 }, | ||
| 2454 | { 0x128c1, 0x0 }, | ||
| 2455 | { 0x1128c1, 0x0 }, | ||
| 2456 | { 0x2128c1, 0x0 }, | ||
| 2457 | { 0x130c1, 0x0 }, | ||
| 2458 | { 0x1130c1, 0x0 }, | ||
| 2459 | { 0x2130c1, 0x0 }, | ||
| 2460 | { 0x131c1, 0x0 }, | ||
| 2461 | { 0x1131c1, 0x0 }, | ||
| 2462 | { 0x2131c1, 0x0 }, | ||
| 2463 | { 0x132c1, 0x0 }, | ||
| 2464 | { 0x1132c1, 0x0 }, | ||
| 2465 | { 0x2132c1, 0x0 }, | ||
| 2466 | { 0x133c1, 0x0 }, | ||
| 2467 | { 0x1133c1, 0x0 }, | ||
| 2468 | { 0x2133c1, 0x0 }, | ||
| 2469 | { 0x134c1, 0x0 }, | ||
| 2470 | { 0x1134c1, 0x0 }, | ||
| 2471 | { 0x2134c1, 0x0 }, | ||
| 2472 | { 0x135c1, 0x0 }, | ||
| 2473 | { 0x1135c1, 0x0 }, | ||
| 2474 | { 0x2135c1, 0x0 }, | ||
| 2475 | { 0x136c1, 0x0 }, | ||
| 2476 | { 0x1136c1, 0x0 }, | ||
| 2477 | { 0x2136c1, 0x0 }, | ||
| 2478 | { 0x137c1, 0x0 }, | ||
| 2479 | { 0x1137c1, 0x0 }, | ||
| 2480 | { 0x2137c1, 0x0 }, | ||
| 2481 | { 0x138c1, 0x0 }, | ||
| 2482 | { 0x1138c1, 0x0 }, | ||
| 2483 | { 0x2138c1, 0x0 }, | ||
| 2484 | { 0x10020, 0x0 }, | ||
| 2485 | { 0x110020, 0x0 }, | ||
| 2486 | { 0x210020, 0x0 }, | ||
| 2487 | { 0x11020, 0x0 }, | ||
| 2488 | { 0x111020, 0x0 }, | ||
| 2489 | { 0x211020, 0x0 }, | ||
| 2490 | { 0x12020, 0x0 }, | ||
| 2491 | { 0x112020, 0x0 }, | ||
| 2492 | { 0x212020, 0x0 }, | ||
| 2493 | { 0x13020, 0x0 }, | ||
| 2494 | { 0x113020, 0x0 }, | ||
| 2495 | { 0x213020, 0x0 }, | ||
| 2496 | { 0x20072, 0x0 }, | ||
| 2497 | { 0x20073, 0x0 }, | ||
| 2498 | { 0x20074, 0x0 }, | ||
| 2499 | { 0x100aa, 0x0 }, | ||
| 2500 | { 0x110aa, 0x0 }, | ||
| 2501 | { 0x120aa, 0x0 }, | ||
| 2502 | { 0x130aa, 0x0 }, | ||
| 2503 | { 0x20010, 0x0 }, | ||
| 2504 | { 0x120010, 0x0 }, | ||
| 2505 | { 0x220010, 0x0 }, | ||
| 2506 | { 0x20011, 0x0 }, | ||
| 2507 | { 0x120011, 0x0 }, | ||
| 2508 | { 0x220011, 0x0 }, | ||
| 2509 | { 0x100ae, 0x0 }, | ||
| 2510 | { 0x1100ae, 0x0 }, | ||
| 2511 | { 0x2100ae, 0x0 }, | ||
| 2512 | { 0x100af, 0x0 }, | ||
| 2513 | { 0x1100af, 0x0 }, | ||
| 2514 | { 0x2100af, 0x0 }, | ||
| 2515 | { 0x110ae, 0x0 }, | ||
| 2516 | { 0x1110ae, 0x0 }, | ||
| 2517 | { 0x2110ae, 0x0 }, | ||
| 2518 | { 0x110af, 0x0 }, | ||
| 2519 | { 0x1110af, 0x0 }, | ||
| 2520 | { 0x2110af, 0x0 }, | ||
| 2521 | { 0x120ae, 0x0 }, | ||
| 2522 | { 0x1120ae, 0x0 }, | ||
| 2523 | { 0x2120ae, 0x0 }, | ||
| 2524 | { 0x120af, 0x0 }, | ||
| 2525 | { 0x1120af, 0x0 }, | ||
| 2526 | { 0x2120af, 0x0 }, | ||
| 2527 | { 0x130ae, 0x0 }, | ||
| 2528 | { 0x1130ae, 0x0 }, | ||
| 2529 | { 0x2130ae, 0x0 }, | ||
| 2530 | { 0x130af, 0x0 }, | ||
| 2531 | { 0x1130af, 0x0 }, | ||
| 2532 | { 0x2130af, 0x0 }, | ||
| 2533 | { 0x20020, 0x0 }, | ||
| 2534 | { 0x120020, 0x0 }, | ||
| 2535 | { 0x220020, 0x0 }, | ||
| 2536 | { 0x100a0, 0x0 }, | ||
| 2537 | { 0x100a1, 0x0 }, | ||
| 2538 | { 0x100a2, 0x0 }, | ||
| 2539 | { 0x100a3, 0x0 }, | ||
| 2540 | { 0x100a4, 0x0 }, | ||
| 2541 | { 0x100a5, 0x0 }, | ||
| 2542 | { 0x100a6, 0x0 }, | ||
| 2543 | { 0x100a7, 0x0 }, | ||
| 2544 | { 0x110a0, 0x0 }, | ||
| 2545 | { 0x110a1, 0x0 }, | ||
| 2546 | { 0x110a2, 0x0 }, | ||
| 2547 | { 0x110a3, 0x0 }, | ||
| 2548 | { 0x110a4, 0x0 }, | ||
| 2549 | { 0x110a5, 0x0 }, | ||
| 2550 | { 0x110a6, 0x0 }, | ||
| 2551 | { 0x110a7, 0x0 }, | ||
| 2552 | { 0x120a0, 0x0 }, | ||
| 2553 | { 0x120a1, 0x0 }, | ||
| 2554 | { 0x120a2, 0x0 }, | ||
| 2555 | { 0x120a3, 0x0 }, | ||
| 2556 | { 0x120a4, 0x0 }, | ||
| 2557 | { 0x120a5, 0x0 }, | ||
| 2558 | { 0x120a6, 0x0 }, | ||
| 2559 | { 0x120a7, 0x0 }, | ||
| 2560 | { 0x130a0, 0x0 }, | ||
| 2561 | { 0x130a1, 0x0 }, | ||
| 2562 | { 0x130a2, 0x0 }, | ||
| 2563 | { 0x130a3, 0x0 }, | ||
| 2564 | { 0x130a4, 0x0 }, | ||
| 2565 | { 0x130a5, 0x0 }, | ||
| 2566 | { 0x130a6, 0x0 }, | ||
| 2567 | { 0x130a7, 0x0 }, | ||
| 2568 | { 0x2007c, 0x0 }, | ||
| 2569 | { 0x12007c, 0x0 }, | ||
| 2570 | { 0x22007c, 0x0 }, | ||
| 2571 | { 0x2007d, 0x0 }, | ||
| 2572 | { 0x12007d, 0x0 }, | ||
| 2573 | { 0x22007d, 0x0 }, | ||
| 2574 | { 0x400fd, 0x0 }, | ||
| 2575 | { 0x400c0, 0x0 }, | ||
| 2576 | { 0x90201, 0x0 }, | ||
| 2577 | { 0x190201, 0x0 }, | ||
| 2578 | { 0x290201, 0x0 }, | ||
| 2579 | { 0x90202, 0x0 }, | ||
| 2580 | { 0x190202, 0x0 }, | ||
| 2581 | { 0x290202, 0x0 }, | ||
| 2582 | { 0x90203, 0x0 }, | ||
| 2583 | { 0x190203, 0x0 }, | ||
| 2584 | { 0x290203, 0x0 }, | ||
| 2585 | { 0x90204, 0x0 }, | ||
| 2586 | { 0x190204, 0x0 }, | ||
| 2587 | { 0x290204, 0x0 }, | ||
| 2588 | { 0x90205, 0x0 }, | ||
| 2589 | { 0x190205, 0x0 }, | ||
| 2590 | { 0x290205, 0x0 }, | ||
| 2591 | { 0x90206, 0x0 }, | ||
| 2592 | { 0x190206, 0x0 }, | ||
| 2593 | { 0x290206, 0x0 }, | ||
| 2594 | { 0x90207, 0x0 }, | ||
| 2595 | { 0x190207, 0x0 }, | ||
| 2596 | { 0x290207, 0x0 }, | ||
| 2597 | { 0x90208, 0x0 }, | ||
| 2598 | { 0x190208, 0x0 }, | ||
| 2599 | { 0x290208, 0x0 }, | ||
| 2600 | { 0x10062, 0x0 }, | ||
| 2601 | { 0x10162, 0x0 }, | ||
| 2602 | { 0x10262, 0x0 }, | ||
| 2603 | { 0x10362, 0x0 }, | ||
| 2604 | { 0x10462, 0x0 }, | ||
| 2605 | { 0x10562, 0x0 }, | ||
| 2606 | { 0x10662, 0x0 }, | ||
| 2607 | { 0x10762, 0x0 }, | ||
| 2608 | { 0x10862, 0x0 }, | ||
| 2609 | { 0x11062, 0x0 }, | ||
| 2610 | { 0x11162, 0x0 }, | ||
| 2611 | { 0x11262, 0x0 }, | ||
| 2612 | { 0x11362, 0x0 }, | ||
| 2613 | { 0x11462, 0x0 }, | ||
| 2614 | { 0x11562, 0x0 }, | ||
| 2615 | { 0x11662, 0x0 }, | ||
| 2616 | { 0x11762, 0x0 }, | ||
| 2617 | { 0x11862, 0x0 }, | ||
| 2618 | { 0x12062, 0x0 }, | ||
| 2619 | { 0x12162, 0x0 }, | ||
| 2620 | { 0x12262, 0x0 }, | ||
| 2621 | { 0x12362, 0x0 }, | ||
| 2622 | { 0x12462, 0x0 }, | ||
| 2623 | { 0x12562, 0x0 }, | ||
| 2624 | { 0x12662, 0x0 }, | ||
| 2625 | { 0x12762, 0x0 }, | ||
| 2626 | { 0x12862, 0x0 }, | ||
| 2627 | { 0x13062, 0x0 }, | ||
| 2628 | { 0x13162, 0x0 }, | ||
| 2629 | { 0x13262, 0x0 }, | ||
| 2630 | { 0x13362, 0x0 }, | ||
| 2631 | { 0x13462, 0x0 }, | ||
| 2632 | { 0x13562, 0x0 }, | ||
| 2633 | { 0x13662, 0x0 }, | ||
| 2634 | { 0x13762, 0x0 }, | ||
| 2635 | { 0x13862, 0x0 }, | ||
| 2636 | { 0x20077, 0x0 }, | ||
| 2637 | { 0x10001, 0x0 }, | ||
| 2638 | { 0x11001, 0x0 }, | ||
| 2639 | { 0x12001, 0x0 }, | ||
| 2640 | { 0x13001, 0x0 }, | ||
| 2641 | { 0x10040, 0x0 }, | ||
| 2642 | { 0x10140, 0x0 }, | ||
| 2643 | { 0x10240, 0x0 }, | ||
| 2644 | { 0x10340, 0x0 }, | ||
| 2645 | { 0x10440, 0x0 }, | ||
| 2646 | { 0x10540, 0x0 }, | ||
| 2647 | { 0x10640, 0x0 }, | ||
| 2648 | { 0x10740, 0x0 }, | ||
| 2649 | { 0x10840, 0x0 }, | ||
| 2650 | { 0x10030, 0x0 }, | ||
| 2651 | { 0x10130, 0x0 }, | ||
| 2652 | { 0x10230, 0x0 }, | ||
| 2653 | { 0x10330, 0x0 }, | ||
| 2654 | { 0x10430, 0x0 }, | ||
| 2655 | { 0x10530, 0x0 }, | ||
| 2656 | { 0x10630, 0x0 }, | ||
| 2657 | { 0x10730, 0x0 }, | ||
| 2658 | { 0x10830, 0x0 }, | ||
| 2659 | { 0x11040, 0x0 }, | ||
| 2660 | { 0x11140, 0x0 }, | ||
| 2661 | { 0x11240, 0x0 }, | ||
| 2662 | { 0x11340, 0x0 }, | ||
| 2663 | { 0x11440, 0x0 }, | ||
| 2664 | { 0x11540, 0x0 }, | ||
| 2665 | { 0x11640, 0x0 }, | ||
| 2666 | { 0x11740, 0x0 }, | ||
| 2667 | { 0x11840, 0x0 }, | ||
| 2668 | { 0x11030, 0x0 }, | ||
| 2669 | { 0x11130, 0x0 }, | ||
| 2670 | { 0x11230, 0x0 }, | ||
| 2671 | { 0x11330, 0x0 }, | ||
| 2672 | { 0x11430, 0x0 }, | ||
| 2673 | { 0x11530, 0x0 }, | ||
| 2674 | { 0x11630, 0x0 }, | ||
| 2675 | { 0x11730, 0x0 }, | ||
| 2676 | { 0x11830, 0x0 }, | ||
| 2677 | { 0x12040, 0x0 }, | ||
| 2678 | { 0x12140, 0x0 }, | ||
| 2679 | { 0x12240, 0x0 }, | ||
| 2680 | { 0x12340, 0x0 }, | ||
| 2681 | { 0x12440, 0x0 }, | ||
| 2682 | { 0x12540, 0x0 }, | ||
| 2683 | { 0x12640, 0x0 }, | ||
| 2684 | { 0x12740, 0x0 }, | ||
| 2685 | { 0x12840, 0x0 }, | ||
| 2686 | { 0x12030, 0x0 }, | ||
| 2687 | { 0x12130, 0x0 }, | ||
| 2688 | { 0x12230, 0x0 }, | ||
| 2689 | { 0x12330, 0x0 }, | ||
| 2690 | { 0x12430, 0x0 }, | ||
| 2691 | { 0x12530, 0x0 }, | ||
| 2692 | { 0x12630, 0x0 }, | ||
| 2693 | { 0x12730, 0x0 }, | ||
| 2694 | { 0x12830, 0x0 }, | ||
| 2695 | { 0x13040, 0x0 }, | ||
| 2696 | { 0x13140, 0x0 }, | ||
| 2697 | { 0x13240, 0x0 }, | ||
| 2698 | { 0x13340, 0x0 }, | ||
| 2699 | { 0x13440, 0x0 }, | ||
| 2700 | { 0x13540, 0x0 }, | ||
| 2701 | { 0x13640, 0x0 }, | ||
| 2702 | { 0x13740, 0x0 }, | ||
| 2703 | { 0x13840, 0x0 }, | ||
| 2704 | { 0x13030, 0x0 }, | ||
| 2705 | { 0x13130, 0x0 }, | ||
| 2706 | { 0x13230, 0x0 }, | ||
| 2707 | { 0x13330, 0x0 }, | ||
| 2708 | { 0x13430, 0x0 }, | ||
| 2709 | { 0x13530, 0x0 }, | ||
| 2710 | { 0x13630, 0x0 }, | ||
| 2711 | { 0x13730, 0x0 }, | ||
| 2712 | { 0x13830, 0x0 }, | ||
| 2713 | }; | ||
| 2714 | /* P0 message block paremeter for training firmware */ | ||
| 2715 | struct dram_cfg_param ddr_fsp0_cfg[] = { | ||
| 2716 | {0xd0000, 0x0}, | ||
| 2717 | {0x54003,0xc80}, | ||
| 2718 | {0x54004,0x2}, | ||
| 2719 | {0x54005,0x2228}, | ||
| 2720 | {0x54006,0x11}, | ||
| 2721 | {0x54008,0x131f}, | ||
| 2722 | {0x54009,0xc8}, | ||
| 2723 | {0x5400b,0x2}, | ||
| 2724 | {0x5400d,0x100}, | ||
| 2725 | {0x54012,0x310}, | ||
| 2726 | {0x54019,0x2dd4}, | ||
| 2727 | {0x5401a,0x31}, | ||
| 2728 | {0x5401b,0x4a66}, | ||
| 2729 | {0x5401c,0x4a08}, | ||
| 2730 | {0x5401e,0x16}, | ||
| 2731 | {0x5401f,0x2dd4}, | ||
| 2732 | {0x54020,0x31}, | ||
| 2733 | {0x54021,0x4a66}, | ||
| 2734 | {0x54022,0x4a08}, | ||
| 2735 | {0x54024,0x16}, | ||
| 2736 | {0x5402b,0x1000}, | ||
| 2737 | {0x5402c,0x3}, | ||
| 2738 | {0x54032,0xd400}, | ||
| 2739 | {0x54033,0x312d}, | ||
| 2740 | {0x54034,0x6600}, | ||
| 2741 | {0x54035,0x84a}, | ||
| 2742 | {0x54036,0x4a}, | ||
| 2743 | {0x54037,0x1600}, | ||
| 2744 | {0x54038,0xd400}, | ||
| 2745 | {0x54039,0x312d}, | ||
| 2746 | {0x5403a,0x6600}, | ||
| 2747 | {0x5403b,0x84a}, | ||
| 2748 | {0x5403c,0x4a}, | ||
| 2749 | {0x5403d,0x1600}, | ||
| 2750 | {0xd0000, 0x1}, | ||
| 2751 | }; | ||
| 2752 | |||
| 2753 | |||
| 2754 | /* P1 message block paremeter for training firmware */ | ||
| 2755 | struct dram_cfg_param ddr_fsp1_cfg[] = { | ||
| 2756 | {0xd0000, 0x0}, | ||
| 2757 | {0x54002,0x1}, | ||
| 2758 | {0x54003,0x29c}, | ||
| 2759 | {0x54004,0x2}, | ||
| 2760 | {0x54005,0x2228}, | ||
| 2761 | {0x54006,0x11}, | ||
| 2762 | {0x54008,0x121f}, | ||
| 2763 | {0x54009,0xc8}, | ||
| 2764 | {0x5400b,0x2}, | ||
| 2765 | {0x5400d,0x100}, | ||
| 2766 | {0x54012,0x310}, | ||
| 2767 | {0x54019,0x994}, | ||
| 2768 | {0x5401a,0x31}, | ||
| 2769 | {0x5401b,0x4a66}, | ||
| 2770 | {0x5401c,0x4a08}, | ||
| 2771 | {0x5401e,0x16}, | ||
| 2772 | {0x5401f,0x994}, | ||
| 2773 | {0x54020,0x31}, | ||
| 2774 | {0x54021,0x4a66}, | ||
| 2775 | {0x54022,0x4a08}, | ||
| 2776 | {0x54024,0x16}, | ||
| 2777 | {0x5402b,0x1000}, | ||
| 2778 | {0x5402c,0x3}, | ||
| 2779 | {0x54032,0x9400}, | ||
| 2780 | {0x54033,0x3109}, | ||
| 2781 | {0x54034,0x6600}, | ||
| 2782 | {0x54035,0x84a}, | ||
| 2783 | {0x54036,0x4a}, | ||
| 2784 | {0x54037,0x1600}, | ||
| 2785 | {0x54038,0x9400}, | ||
| 2786 | {0x54039,0x3109}, | ||
| 2787 | {0x5403a,0x6600}, | ||
| 2788 | {0x5403b,0x84a}, | ||
| 2789 | {0x5403c,0x4a}, | ||
| 2790 | {0x5403d,0x1600}, | ||
| 2791 | {0xd0000, 0x1}, | ||
| 2792 | }; | ||
| 2793 | |||
| 2794 | |||
| 2795 | /* P0 2D message block paremeter for training firmware */ | ||
| 2796 | struct dram_cfg_param ddr_fsp0_2d_cfg[] = { | ||
| 2797 | {0xd0000, 0x0}, | ||
| 2798 | {0x54003,0xc80}, | ||
| 2799 | {0x54004,0x2}, | ||
| 2800 | {0x54005,0x2228}, | ||
| 2801 | {0x54006,0x11}, | ||
| 2802 | {0x54008,0x61}, | ||
| 2803 | {0x54009,0xc8}, | ||
| 2804 | {0x5400b,0x2}, | ||
| 2805 | {0x5400f,0x100}, | ||
| 2806 | {0x54010,0x1f7f}, | ||
| 2807 | {0x54012,0x310}, | ||
| 2808 | {0x54019,0x2dd4}, | ||
| 2809 | {0x5401a,0x31}, | ||
| 2810 | {0x5401b,0x4a66}, | ||
| 2811 | {0x5401c,0x4a08}, | ||
| 2812 | {0x5401e,0x16}, | ||
| 2813 | {0x5401f,0x2dd4}, | ||
| 2814 | {0x54020,0x31}, | ||
| 2815 | {0x54021,0x4a66}, | ||
| 2816 | {0x54022,0x4a08}, | ||
| 2817 | {0x54024,0x16}, | ||
| 2818 | {0x5402b,0x1000}, | ||
| 2819 | {0x5402c,0x3}, | ||
| 2820 | {0x54032,0xd400}, | ||
| 2821 | {0x54033,0x312d}, | ||
| 2822 | {0x54034,0x6600}, | ||
| 2823 | {0x54035,0x84a}, | ||
| 2824 | {0x54036,0x4a}, | ||
| 2825 | {0x54037,0x1600}, | ||
| 2826 | {0x54038,0xd400}, | ||
| 2827 | {0x54039,0x312d}, | ||
| 2828 | {0x5403a,0x6600}, | ||
| 2829 | {0x5403b,0x84a}, | ||
| 2830 | {0x5403c,0x4a}, | ||
| 2831 | {0x5403d,0x1600}, | ||
| 2832 | { 0xd0000, 0x1 }, | ||
| 2833 | }; | ||
| 2834 | |||
| 2835 | /* DRAM PHY init engine image */ | ||
| 2836 | struct dram_cfg_param ddr_phy_pie[] = { | ||
| 2837 | {0xd0000, 0x0}, | ||
| 2838 | {0x90000,0x10}, | ||
| 2839 | {0x90001,0x400}, | ||
| 2840 | {0x90002,0x10e}, | ||
| 2841 | {0x90003,0x0}, | ||
| 2842 | {0x90004,0x0}, | ||
| 2843 | {0x90005,0x8}, | ||
| 2844 | {0x90029,0xb}, | ||
| 2845 | {0x9002a,0x480}, | ||
| 2846 | {0x9002b,0x109}, | ||
| 2847 | {0x9002c,0x8}, | ||
| 2848 | {0x9002d,0x448}, | ||
| 2849 | {0x9002e,0x139}, | ||
| 2850 | {0x9002f,0x8}, | ||
| 2851 | {0x90030,0x478}, | ||
| 2852 | {0x90031,0x109}, | ||
| 2853 | {0x90032,0x0}, | ||
| 2854 | {0x90033,0xe8}, | ||
| 2855 | {0x90034,0x109}, | ||
| 2856 | {0x90035,0x2}, | ||
| 2857 | {0x90036,0x10}, | ||
| 2858 | {0x90037,0x139}, | ||
| 2859 | {0x90038,0xf}, | ||
| 2860 | {0x90039,0x7c0}, | ||
| 2861 | {0x9003a,0x139}, | ||
| 2862 | {0x9003b,0x44}, | ||
| 2863 | {0x9003c,0x630}, | ||
| 2864 | {0x9003d,0x159}, | ||
| 2865 | {0x9003e,0x14f}, | ||
| 2866 | {0x9003f,0x630}, | ||
| 2867 | {0x90040,0x159}, | ||
| 2868 | {0x90041,0x47}, | ||
| 2869 | {0x90042,0x630}, | ||
| 2870 | {0x90043,0x149}, | ||
| 2871 | {0x90044,0x4f}, | ||
| 2872 | {0x90045,0x630}, | ||
| 2873 | {0x90046,0x179}, | ||
| 2874 | {0x90047,0x8}, | ||
| 2875 | {0x90048,0xe0}, | ||
| 2876 | {0x90049,0x109}, | ||
| 2877 | {0x9004a,0x0}, | ||
| 2878 | {0x9004b,0x7c8}, | ||
| 2879 | {0x9004c,0x109}, | ||
| 2880 | {0x9004d,0x0}, | ||
| 2881 | {0x9004e,0x1}, | ||
| 2882 | {0x9004f,0x8}, | ||
| 2883 | {0x90050,0x0}, | ||
| 2884 | {0x90051,0x45a}, | ||
| 2885 | {0x90052,0x9}, | ||
| 2886 | {0x90053,0x0}, | ||
| 2887 | {0x90054,0x448}, | ||
| 2888 | {0x90055,0x109}, | ||
| 2889 | {0x90056,0x40}, | ||
| 2890 | {0x90057,0x630}, | ||
| 2891 | {0x90058,0x179}, | ||
| 2892 | {0x90059,0x1}, | ||
| 2893 | {0x9005a,0x618}, | ||
| 2894 | {0x9005b,0x109}, | ||
| 2895 | {0x9005c,0x40c0}, | ||
| 2896 | {0x9005d,0x630}, | ||
| 2897 | {0x9005e,0x149}, | ||
| 2898 | {0x9005f,0x8}, | ||
| 2899 | {0x90060,0x4}, | ||
| 2900 | {0x90061,0x48}, | ||
| 2901 | {0x90062,0x4040}, | ||
| 2902 | {0x90063,0x630}, | ||
| 2903 | {0x90064,0x149}, | ||
| 2904 | {0x90065,0x0}, | ||
| 2905 | {0x90066,0x4}, | ||
| 2906 | {0x90067,0x48}, | ||
| 2907 | {0x90068,0x40}, | ||
| 2908 | {0x90069,0x630}, | ||
| 2909 | {0x9006a,0x149}, | ||
| 2910 | {0x9006b,0x10}, | ||
| 2911 | {0x9006c,0x4}, | ||
| 2912 | {0x9006d,0x18}, | ||
| 2913 | {0x9006e,0x0}, | ||
| 2914 | {0x9006f,0x4}, | ||
| 2915 | {0x90070,0x78}, | ||
| 2916 | {0x90071,0x549}, | ||
| 2917 | {0x90072,0x630}, | ||
| 2918 | {0x90073,0x159}, | ||
| 2919 | {0x90074,0xd49}, | ||
| 2920 | {0x90075,0x630}, | ||
| 2921 | {0x90076,0x159}, | ||
| 2922 | {0x90077,0x94a}, | ||
| 2923 | {0x90078,0x630}, | ||
| 2924 | {0x90079,0x159}, | ||
| 2925 | {0x9007a,0x441}, | ||
| 2926 | {0x9007b,0x630}, | ||
| 2927 | {0x9007c,0x149}, | ||
| 2928 | {0x9007d,0x42}, | ||
| 2929 | {0x9007e,0x630}, | ||
| 2930 | {0x9007f,0x149}, | ||
| 2931 | {0x90080,0x1}, | ||
| 2932 | {0x90081,0x630}, | ||
| 2933 | {0x90082,0x149}, | ||
| 2934 | {0x90083,0x0}, | ||
| 2935 | {0x90084,0xe0}, | ||
| 2936 | {0x90085,0x109}, | ||
| 2937 | {0x90086,0xa}, | ||
| 2938 | {0x90087,0x10}, | ||
| 2939 | {0x90088,0x109}, | ||
| 2940 | {0x90089,0x9}, | ||
| 2941 | {0x9008a,0x3c0}, | ||
| 2942 | {0x9008b,0x149}, | ||
| 2943 | {0x9008c,0x9}, | ||
| 2944 | {0x9008d,0x3c0}, | ||
| 2945 | {0x9008e,0x159}, | ||
| 2946 | {0x9008f,0x18}, | ||
| 2947 | {0x90090,0x10}, | ||
| 2948 | {0x90091,0x109}, | ||
| 2949 | {0x90092,0x0}, | ||
| 2950 | {0x90093,0x3c0}, | ||
| 2951 | {0x90094,0x109}, | ||
| 2952 | {0x90095,0x18}, | ||
| 2953 | {0x90096,0x4}, | ||
| 2954 | {0x90097,0x48}, | ||
| 2955 | {0x90098,0x18}, | ||
| 2956 | {0x90099,0x4}, | ||
| 2957 | {0x9009a,0x58}, | ||
| 2958 | {0x9009b,0xa}, | ||
| 2959 | {0x9009c,0x10}, | ||
| 2960 | {0x9009d,0x109}, | ||
| 2961 | {0x9009e,0x2}, | ||
| 2962 | {0x9009f,0x10}, | ||
| 2963 | {0x900a0,0x109}, | ||
| 2964 | {0x900a1,0x5}, | ||
| 2965 | {0x900a2,0x7c0}, | ||
| 2966 | {0x900a3,0x109}, | ||
| 2967 | {0x900a4,0x10}, | ||
| 2968 | {0x900a5,0x10}, | ||
| 2969 | {0x900a6,0x109}, | ||
| 2970 | {0x40000,0x811}, | ||
| 2971 | {0x40020,0x880}, | ||
| 2972 | {0x40040,0x0}, | ||
| 2973 | {0x40060,0x0}, | ||
| 2974 | {0x40001,0x4008}, | ||
| 2975 | {0x40021,0x83}, | ||
| 2976 | {0x40041,0x4f}, | ||
| 2977 | {0x40061,0x0}, | ||
| 2978 | {0x40002,0x4040}, | ||
| 2979 | {0x40022,0x83}, | ||
| 2980 | {0x40042,0x51}, | ||
| 2981 | {0x40062,0x0}, | ||
| 2982 | {0x40003,0x811}, | ||
| 2983 | {0x40023,0x880}, | ||
| 2984 | {0x40043,0x0}, | ||
| 2985 | {0x40063,0x0}, | ||
| 2986 | {0x40004,0x720}, | ||
| 2987 | {0x40024,0xf}, | ||
| 2988 | {0x40044,0x1740}, | ||
| 2989 | {0x40064,0x0}, | ||
| 2990 | {0x40005,0x16}, | ||
| 2991 | {0x40025,0x83}, | ||
| 2992 | {0x40045,0x4b}, | ||
| 2993 | {0x40065,0x0}, | ||
| 2994 | {0x40006,0x716}, | ||
| 2995 | {0x40026,0xf}, | ||
| 2996 | {0x40046,0x2001}, | ||
| 2997 | {0x40066,0x0}, | ||
| 2998 | {0x40007,0x716}, | ||
| 2999 | {0x40027,0xf}, | ||
| 3000 | {0x40047,0x2800}, | ||
| 3001 | {0x40067,0x0}, | ||
| 3002 | {0x40008,0x716}, | ||
| 3003 | {0x40028,0xf}, | ||
| 3004 | {0x40048,0xf00}, | ||
| 3005 | {0x40068,0x0}, | ||
| 3006 | {0x40009,0x720}, | ||
| 3007 | {0x40029,0xf}, | ||
| 3008 | {0x40049,0x1400}, | ||
| 3009 | {0x40069,0x0}, | ||
| 3010 | {0x4000a,0xe08}, | ||
| 3011 | {0x4002a,0xc15}, | ||
| 3012 | {0x4004a,0x0}, | ||
| 3013 | {0x4006a,0x0}, | ||
| 3014 | {0x4000b,0x623}, | ||
| 3015 | {0x4002b,0x15}, | ||
| 3016 | {0x4004b,0x0}, | ||
| 3017 | {0x4006b,0x0}, | ||
| 3018 | {0x4000c,0x4028}, | ||
| 3019 | {0x4002c,0x80}, | ||
| 3020 | {0x4004c,0x0}, | ||
| 3021 | {0x4006c,0x0}, | ||
| 3022 | {0x4000d,0xe08}, | ||
| 3023 | {0x4002d,0xc1a}, | ||
| 3024 | {0x4004d,0x0}, | ||
| 3025 | {0x4006d,0x0}, | ||
| 3026 | {0x4000e,0x623}, | ||
| 3027 | {0x4002e,0x1a}, | ||
| 3028 | {0x4004e,0x0}, | ||
| 3029 | {0x4006e,0x0}, | ||
| 3030 | {0x4000f,0x4040}, | ||
| 3031 | {0x4002f,0x80}, | ||
| 3032 | {0x4004f,0x0}, | ||
| 3033 | {0x4006f,0x0}, | ||
| 3034 | {0x40010,0x2604}, | ||
| 3035 | {0x40030,0x15}, | ||
| 3036 | {0x40050,0x0}, | ||
| 3037 | {0x40070,0x0}, | ||
| 3038 | {0x40011,0x708}, | ||
| 3039 | {0x40031,0x5}, | ||
| 3040 | {0x40051,0x0}, | ||
| 3041 | {0x40071,0x2002}, | ||
| 3042 | {0x40012,0x8}, | ||
| 3043 | {0x40032,0x80}, | ||
| 3044 | {0x40052,0x0}, | ||
| 3045 | {0x40072,0x0}, | ||
| 3046 | {0x40013,0x2604}, | ||
| 3047 | {0x40033,0x1a}, | ||
| 3048 | {0x40053,0x0}, | ||
| 3049 | {0x40073,0x0}, | ||
| 3050 | {0x40014,0x708}, | ||
| 3051 | {0x40034,0xa}, | ||
| 3052 | {0x40054,0x0}, | ||
| 3053 | {0x40074,0x2002}, | ||
| 3054 | {0x40015,0x4040}, | ||
| 3055 | {0x40035,0x80}, | ||
| 3056 | {0x40055,0x0}, | ||
| 3057 | {0x40075,0x0}, | ||
| 3058 | {0x40016,0x60a}, | ||
| 3059 | {0x40036,0x15}, | ||
| 3060 | {0x40056,0x1200}, | ||
| 3061 | {0x40076,0x0}, | ||
| 3062 | {0x40017,0x61a}, | ||
| 3063 | {0x40037,0x15}, | ||
| 3064 | {0x40057,0x1300}, | ||
| 3065 | {0x40077,0x0}, | ||
| 3066 | {0x40018,0x60a}, | ||
| 3067 | {0x40038,0x1a}, | ||
| 3068 | {0x40058,0x1200}, | ||
| 3069 | {0x40078,0x0}, | ||
| 3070 | {0x40019,0x642}, | ||
| 3071 | {0x40039,0x1a}, | ||
| 3072 | {0x40059,0x1300}, | ||
| 3073 | {0x40079,0x0}, | ||
| 3074 | {0x4001a,0x4808}, | ||
| 3075 | {0x4003a,0x880}, | ||
| 3076 | {0x4005a,0x0}, | ||
| 3077 | {0x4007a,0x0}, | ||
| 3078 | {0x900a7,0x0}, | ||
| 3079 | {0x900a8,0x790}, | ||
| 3080 | {0x900a9,0x11a}, | ||
| 3081 | {0x900aa,0x8}, | ||
| 3082 | {0x900ab,0x7aa}, | ||
| 3083 | {0x900ac,0x2a}, | ||
| 3084 | {0x900ad,0x10}, | ||
| 3085 | {0x900ae,0x7b2}, | ||
| 3086 | {0x900af,0x2a}, | ||
| 3087 | {0x900b0,0x0}, | ||
| 3088 | {0x900b1,0x7c8}, | ||
| 3089 | {0x900b2,0x109}, | ||
| 3090 | {0x900b3,0x10}, | ||
| 3091 | {0x900b4,0x2a8}, | ||
| 3092 | {0x900b5,0x129}, | ||
| 3093 | {0x900b6,0x8}, | ||
| 3094 | {0x900b7,0x370}, | ||
| 3095 | {0x900b8,0x129}, | ||
| 3096 | {0x900b9,0xa}, | ||
| 3097 | {0x900ba,0x3c8}, | ||
| 3098 | {0x900bb,0x1a9}, | ||
| 3099 | {0x900bc,0xc}, | ||
| 3100 | {0x900bd,0x408}, | ||
| 3101 | {0x900be,0x199}, | ||
| 3102 | {0x900bf,0x14}, | ||
| 3103 | {0x900c0,0x790}, | ||
| 3104 | {0x900c1,0x11a}, | ||
| 3105 | {0x900c2,0x8}, | ||
| 3106 | {0x900c3,0x4}, | ||
| 3107 | {0x900c4,0x18}, | ||
| 3108 | {0x900c5,0xe}, | ||
| 3109 | {0x900c6,0x408}, | ||
| 3110 | {0x900c7,0x199}, | ||
| 3111 | {0x900c8,0x8}, | ||
| 3112 | {0x900c9,0x8568}, | ||
| 3113 | {0x900ca,0x108}, | ||
| 3114 | {0x900cb,0x18}, | ||
| 3115 | {0x900cc,0x790}, | ||
| 3116 | {0x900cd,0x16a}, | ||
| 3117 | {0x900ce,0x8}, | ||
| 3118 | {0x900cf,0x1d8}, | ||
| 3119 | {0x900d0,0x169}, | ||
| 3120 | {0x900d1,0x10}, | ||
| 3121 | {0x900d2,0x8558}, | ||
| 3122 | {0x900d3,0x168}, | ||
| 3123 | {0x900d4,0x70}, | ||
| 3124 | {0x900d5,0x788}, | ||
| 3125 | {0x900d6,0x16a}, | ||
| 3126 | {0x900d7,0x1ff8}, | ||
| 3127 | {0x900d8,0x85a8}, | ||
| 3128 | {0x900d9,0x1e8}, | ||
| 3129 | {0x900da,0x50}, | ||
| 3130 | {0x900db,0x798}, | ||
| 3131 | {0x900dc,0x16a}, | ||
| 3132 | {0x900dd,0x60}, | ||
| 3133 | {0x900de,0x7a0}, | ||
| 3134 | {0x900df,0x16a}, | ||
| 3135 | {0x900e0,0x8}, | ||
| 3136 | {0x900e1,0x8310}, | ||
| 3137 | {0x900e2,0x168}, | ||
| 3138 | {0x900e3,0x8}, | ||
| 3139 | {0x900e4,0xa310}, | ||
| 3140 | {0x900e5,0x168}, | ||
| 3141 | {0x900e6,0xa}, | ||
| 3142 | {0x900e7,0x408}, | ||
| 3143 | {0x900e8,0x169}, | ||
| 3144 | {0x900e9,0x6e}, | ||
| 3145 | {0x900ea,0x0}, | ||
| 3146 | {0x900eb,0x68}, | ||
| 3147 | {0x900ec,0x0}, | ||
| 3148 | {0x900ed,0x408}, | ||
| 3149 | {0x900ee,0x169}, | ||
| 3150 | {0x900ef,0x0}, | ||
| 3151 | {0x900f0,0x8310}, | ||
| 3152 | {0x900f1,0x168}, | ||
| 3153 | {0x900f2,0x0}, | ||
| 3154 | {0x900f3,0xa310}, | ||
| 3155 | {0x900f4,0x168}, | ||
| 3156 | {0x900f5,0x1ff8}, | ||
| 3157 | {0x900f6,0x85a8}, | ||
| 3158 | {0x900f7,0x1e8}, | ||
| 3159 | {0x900f8,0x68}, | ||
| 3160 | {0x900f9,0x798}, | ||
| 3161 | {0x900fa,0x16a}, | ||
| 3162 | {0x900fb,0x78}, | ||
| 3163 | {0x900fc,0x7a0}, | ||
| 3164 | {0x900fd,0x16a}, | ||
| 3165 | {0x900fe,0x68}, | ||
| 3166 | {0x900ff,0x790}, | ||
| 3167 | {0x90100,0x16a}, | ||
| 3168 | {0x90101,0x8}, | ||
| 3169 | {0x90102,0x8b10}, | ||
| 3170 | {0x90103,0x168}, | ||
| 3171 | {0x90104,0x8}, | ||
| 3172 | {0x90105,0xab10}, | ||
| 3173 | {0x90106,0x168}, | ||
| 3174 | {0x90107,0xa}, | ||
| 3175 | {0x90108,0x408}, | ||
| 3176 | {0x90109,0x169}, | ||
| 3177 | {0x9010a,0x58}, | ||
| 3178 | {0x9010b,0x0}, | ||
| 3179 | {0x9010c,0x68}, | ||
| 3180 | {0x9010d,0x0}, | ||
| 3181 | {0x9010e,0x408}, | ||
| 3182 | {0x9010f,0x169}, | ||
| 3183 | {0x90110,0x0}, | ||
| 3184 | {0x90111,0x8b10}, | ||
| 3185 | {0x90112,0x168}, | ||
| 3186 | {0x90113,0x0}, | ||
| 3187 | {0x90114,0xab10}, | ||
| 3188 | {0x90115,0x168}, | ||
| 3189 | {0x90116,0x0}, | ||
| 3190 | {0x90117,0x1d8}, | ||
| 3191 | {0x90118,0x169}, | ||
| 3192 | {0x90119,0x80}, | ||
| 3193 | {0x9011a,0x790}, | ||
| 3194 | {0x9011b,0x16a}, | ||
| 3195 | {0x9011c,0x18}, | ||
| 3196 | {0x9011d,0x7aa}, | ||
| 3197 | {0x9011e,0x6a}, | ||
| 3198 | {0x9011f,0xa}, | ||
| 3199 | {0x90120,0x0}, | ||
| 3200 | {0x90121,0x1e9}, | ||
| 3201 | {0x90122,0x8}, | ||
| 3202 | {0x90123,0x8080}, | ||
| 3203 | {0x90124,0x108}, | ||
| 3204 | {0x90125,0xf}, | ||
| 3205 | {0x90126,0x408}, | ||
| 3206 | {0x90127,0x169}, | ||
| 3207 | {0x90128,0xc}, | ||
| 3208 | {0x90129,0x0}, | ||
| 3209 | {0x9012a,0x68}, | ||
| 3210 | {0x9012b,0x9}, | ||
| 3211 | {0x9012c,0x0}, | ||
| 3212 | {0x9012d,0x1a9}, | ||
| 3213 | {0x9012e,0x0}, | ||
| 3214 | {0x9012f,0x408}, | ||
| 3215 | {0x90130,0x169}, | ||
| 3216 | {0x90131,0x0}, | ||
| 3217 | {0x90132,0x8080}, | ||
| 3218 | {0x90133,0x108}, | ||
| 3219 | {0x90134,0x8}, | ||
| 3220 | {0x90135,0x7aa}, | ||
| 3221 | {0x90136,0x6a}, | ||
| 3222 | {0x90137,0x0}, | ||
| 3223 | {0x90138,0x8568}, | ||
| 3224 | {0x90139,0x108}, | ||
| 3225 | {0x9013a,0xb7}, | ||
| 3226 | {0x9013b,0x790}, | ||
| 3227 | {0x9013c,0x16a}, | ||
| 3228 | {0x9013d,0x1f}, | ||
| 3229 | {0x9013e,0x0}, | ||
| 3230 | {0x9013f,0x68}, | ||
| 3231 | {0x90140,0x8}, | ||
| 3232 | {0x90141,0x8558}, | ||
| 3233 | {0x90142,0x168}, | ||
| 3234 | {0x90143,0xf}, | ||
| 3235 | {0x90144,0x408}, | ||
| 3236 | {0x90145,0x169}, | ||
| 3237 | {0x90146,0xc}, | ||
| 3238 | {0x90147,0x0}, | ||
| 3239 | {0x90148,0x68}, | ||
| 3240 | {0x90149,0x0}, | ||
| 3241 | {0x9014a,0x408}, | ||
| 3242 | {0x9014b,0x169}, | ||
| 3243 | {0x9014c,0x0}, | ||
| 3244 | {0x9014d,0x8558}, | ||
| 3245 | {0x9014e,0x168}, | ||
| 3246 | {0x9014f,0x8}, | ||
| 3247 | {0x90150,0x3c8}, | ||
| 3248 | {0x90151,0x1a9}, | ||
| 3249 | {0x90152,0x3}, | ||
| 3250 | {0x90153,0x370}, | ||
| 3251 | {0x90154,0x129}, | ||
| 3252 | {0x90155,0x20}, | ||
| 3253 | {0x90156,0x2aa}, | ||
| 3254 | {0x90157,0x9}, | ||
| 3255 | {0x90158,0x0}, | ||
| 3256 | {0x90159,0x400}, | ||
| 3257 | {0x9015a,0x10e}, | ||
| 3258 | {0x9015b,0x8}, | ||
| 3259 | {0x9015c,0xe8}, | ||
| 3260 | {0x9015d,0x109}, | ||
| 3261 | {0x9015e,0x0}, | ||
| 3262 | {0x9015f,0x8140}, | ||
| 3263 | {0x90160,0x10c}, | ||
| 3264 | {0x90161,0x10}, | ||
| 3265 | {0x90162,0x8138}, | ||
| 3266 | {0x90163,0x10c}, | ||
| 3267 | {0x90164,0x8}, | ||
| 3268 | {0x90165,0x7c8}, | ||
| 3269 | {0x90166,0x101}, | ||
| 3270 | {0x90167,0x8}, | ||
| 3271 | {0x90168,0x0}, | ||
| 3272 | {0x90169,0x8}, | ||
| 3273 | {0x9016a,0x8}, | ||
| 3274 | {0x9016b,0x448}, | ||
| 3275 | {0x9016c,0x109}, | ||
| 3276 | {0x9016d,0xf}, | ||
| 3277 | {0x9016e,0x7c0}, | ||
| 3278 | {0x9016f,0x109}, | ||
| 3279 | {0x90170,0x0}, | ||
| 3280 | {0x90171,0xe8}, | ||
| 3281 | {0x90172,0x109}, | ||
| 3282 | {0x90173,0x47}, | ||
| 3283 | {0x90174,0x630}, | ||
| 3284 | {0x90175,0x109}, | ||
| 3285 | {0x90176,0x8}, | ||
| 3286 | {0x90177,0x618}, | ||
| 3287 | {0x90178,0x109}, | ||
| 3288 | {0x90179,0x8}, | ||
| 3289 | {0x9017a,0xe0}, | ||
| 3290 | {0x9017b,0x109}, | ||
| 3291 | {0x9017c,0x0}, | ||
| 3292 | {0x9017d,0x7c8}, | ||
| 3293 | {0x9017e,0x109}, | ||
| 3294 | {0x9017f,0x8}, | ||
| 3295 | {0x90180,0x8140}, | ||
| 3296 | {0x90181,0x10c}, | ||
| 3297 | {0x90182,0x0}, | ||
| 3298 | {0x90183,0x1}, | ||
| 3299 | {0x90184,0x8}, | ||
| 3300 | {0x90185,0x8}, | ||
| 3301 | {0x90186,0x4}, | ||
| 3302 | {0x90187,0x8}, | ||
| 3303 | {0x90188,0x8}, | ||
| 3304 | {0x90189,0x7c8}, | ||
| 3305 | {0x9018a,0x101}, | ||
| 3306 | {0x90006,0x0}, | ||
| 3307 | {0x90007,0x0}, | ||
| 3308 | {0x90008,0x8}, | ||
| 3309 | {0x90009,0x0}, | ||
| 3310 | {0x9000a,0x0}, | ||
| 3311 | {0x9000b,0x0}, | ||
| 3312 | {0xd00e7,0x400}, | ||
| 3313 | {0x90017,0x0}, | ||
| 3314 | {0x9001f,0x2a}, | ||
| 3315 | {0x90026,0x6a}, | ||
| 3316 | {0x400d0,0x0}, | ||
| 3317 | {0x400d1,0x101}, | ||
| 3318 | {0x400d2,0x105}, | ||
| 3319 | {0x400d3,0x107}, | ||
| 3320 | {0x400d4,0x10f}, | ||
| 3321 | {0x400d5,0x202}, | ||
| 3322 | {0x400d6,0x20a}, | ||
| 3323 | {0x400d7,0x20b}, | ||
| 3324 | {0x2003a,0x2}, | ||
| 3325 | {0x2000b,0x64}, | ||
| 3326 | {0x2000c,0xc8}, | ||
| 3327 | {0x2000d,0x7d0}, | ||
| 3328 | {0x2000e,0x2c}, | ||
| 3329 | {0x12000b,0x14}, | ||
| 3330 | {0x12000c,0x29}, | ||
| 3331 | {0x12000d,0x1a1}, | ||
| 3332 | {0x12000e,0x10}, | ||
| 3333 | {0x9000c,0x0}, | ||
| 3334 | {0x9000d,0x173}, | ||
| 3335 | {0x9000e,0x60}, | ||
| 3336 | {0x9000f,0x6110}, | ||
| 3337 | {0x90010,0x2152}, | ||
| 3338 | {0x90011,0xdfbd}, | ||
| 3339 | {0x90012,0x60}, | ||
| 3340 | {0x90013,0x6152}, | ||
| 3341 | {0x20010,0x5a}, | ||
| 3342 | {0x20011,0x3}, | ||
| 3343 | {0x120010,0x5a}, | ||
| 3344 | {0x120011,0x3}, | ||
| 3345 | {0x40080,0xe0}, | ||
| 3346 | {0x40081,0x12}, | ||
| 3347 | {0x40082,0xe0}, | ||
| 3348 | {0x40083,0x12}, | ||
| 3349 | {0x40084,0xe0}, | ||
| 3350 | {0x40085,0x12}, | ||
| 3351 | {0x140080,0xe0}, | ||
| 3352 | {0x140081,0x12}, | ||
| 3353 | {0x140082,0xe0}, | ||
| 3354 | {0x140083,0x12}, | ||
| 3355 | {0x140084,0xe0}, | ||
| 3356 | {0x140085,0x12}, | ||
| 3357 | {0x400fd,0xf}, | ||
| 3358 | {0x10011,0x1}, | ||
| 3359 | {0x10012,0x1}, | ||
| 3360 | {0x10013,0x180}, | ||
| 3361 | {0x10018,0x1}, | ||
| 3362 | {0x10002,0x6209}, | ||
| 3363 | {0x100b2,0x1}, | ||
| 3364 | {0x101b4,0x1}, | ||
| 3365 | {0x102b4,0x1}, | ||
| 3366 | {0x103b4,0x1}, | ||
| 3367 | {0x104b4,0x1}, | ||
| 3368 | {0x105b4,0x1}, | ||
| 3369 | {0x106b4,0x1}, | ||
| 3370 | {0x107b4,0x1}, | ||
| 3371 | {0x108b4,0x1}, | ||
| 3372 | {0x11011,0x1}, | ||
| 3373 | {0x11012,0x1}, | ||
| 3374 | {0x11013,0x180}, | ||
| 3375 | {0x11018,0x1}, | ||
| 3376 | {0x11002,0x6209}, | ||
| 3377 | {0x110b2,0x1}, | ||
| 3378 | {0x111b4,0x1}, | ||
| 3379 | {0x112b4,0x1}, | ||
| 3380 | {0x113b4,0x1}, | ||
| 3381 | {0x114b4,0x1}, | ||
| 3382 | {0x115b4,0x1}, | ||
| 3383 | {0x116b4,0x1}, | ||
| 3384 | {0x117b4,0x1}, | ||
| 3385 | {0x118b4,0x1}, | ||
| 3386 | {0x12011,0x1}, | ||
| 3387 | {0x12012,0x1}, | ||
| 3388 | {0x12013,0x180}, | ||
| 3389 | {0x12018,0x1}, | ||
| 3390 | {0x12002,0x6209}, | ||
| 3391 | {0x120b2,0x1}, | ||
| 3392 | {0x121b4,0x1}, | ||
| 3393 | {0x122b4,0x1}, | ||
| 3394 | {0x123b4,0x1}, | ||
| 3395 | {0x124b4,0x1}, | ||
| 3396 | {0x125b4,0x1}, | ||
| 3397 | {0x126b4,0x1}, | ||
| 3398 | {0x127b4,0x1}, | ||
| 3399 | {0x128b4,0x1}, | ||
| 3400 | {0x13011,0x1}, | ||
| 3401 | {0x13012,0x1}, | ||
| 3402 | {0x13013,0x180}, | ||
| 3403 | {0x13018,0x1}, | ||
| 3404 | {0x13002,0x6209}, | ||
| 3405 | {0x130b2,0x1}, | ||
| 3406 | {0x131b4,0x1}, | ||
| 3407 | {0x132b4,0x1}, | ||
| 3408 | {0x133b4,0x1}, | ||
| 3409 | {0x134b4,0x1}, | ||
| 3410 | {0x135b4,0x1}, | ||
| 3411 | {0x136b4,0x1}, | ||
| 3412 | {0x137b4,0x1}, | ||
| 3413 | {0x138b4,0x1}, | ||
| 3414 | {0x2003a,0x2}, | ||
| 3415 | {0xc0080,0x2}, | ||
| 3416 | {0xd0000, 0x1} | ||
| 3417 | }; | ||
| 3418 | |||
| 3419 | struct dram_fsp_msg ddr_dram_fsp_msg[] = { | ||
| 3420 | { | ||
| 3421 | /* P0 3200mts 1D */ | ||
| 3422 | .drate = 3200, | ||
| 3423 | .fw_type = FW_1D_IMAGE, | ||
| 3424 | .fsp_cfg = ddr_fsp0_cfg, | ||
| 3425 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_cfg), | ||
| 3426 | }, | ||
| 3427 | { | ||
| 3428 | /* P1 667mts 1D */ | ||
| 3429 | .drate = 667, | ||
| 3430 | .fw_type = FW_1D_IMAGE, | ||
| 3431 | .fsp_cfg = ddr_fsp1_cfg, | ||
| 3432 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp1_cfg), | ||
| 3433 | }, | ||
| 3434 | { | ||
| 3435 | /* P0 3200mts 2D */ | ||
| 3436 | .drate = 3200, | ||
| 3437 | .fw_type = FW_2D_IMAGE, | ||
| 3438 | .fsp_cfg = ddr_fsp0_2d_cfg, | ||
| 3439 | .fsp_cfg_num = ARRAY_SIZE(ddr_fsp0_2d_cfg), | ||
| 3440 | }, | ||
| 3441 | }; | ||
| 3442 | |||
| 3443 | /* ddr timing config params */ | ||
| 3444 | struct dram_timing_info dram_timing = { | ||
| 3445 | .ddrc_cfg = ddr_ddrc_cfg, | ||
| 3446 | .ddrc_cfg_num = ARRAY_SIZE(ddr_ddrc_cfg), | ||
| 3447 | .ddrphy_cfg = ddr_ddrphy_cfg, | ||
| 3448 | .ddrphy_cfg_num = ARRAY_SIZE(ddr_ddrphy_cfg), | ||
| 3449 | .fsp_msg = ddr_dram_fsp_msg, | ||
| 3450 | .fsp_msg_num = ARRAY_SIZE(ddr_dram_fsp_msg), | ||
| 3451 | .ddrphy_trained_csr = ddr_ddrphy_trained_csr, | ||
| 3452 | .ddrphy_trained_csr_num = ARRAY_SIZE(ddr_ddrphy_trained_csr), | ||
| 3453 | .ddrphy_pie = ddr_phy_pie, | ||
| 3454 | .ddrphy_pie_num = ARRAY_SIZE(ddr_phy_pie), | ||
| 3455 | .fsp_table = { 3200, 667, }, | ||
| 3456 | }; | ||
| 3457 | #else | ||
| 3458 | #error "no configuration for this board" | ||
| 3459 | #endif | ||
| 3460 | 1 | /* |
board/embedian/embedian/smarcimx8mq/smarcimx8mq.c
| 1 | /* | File was deleted | |
| 2 | * Copyright 2016 Freescale Semiconductor, Inc. | ||
| 3 | * Copyright 2017-2018 NXP | ||
| 4 | * | ||
| 5 | * SPDX-License-Identifier: GPL-2.0+ | ||
| 6 | */ | ||
| 7 | |||
| 8 | #include <common.h> | ||
| 9 | #include <malloc.h> | ||
| 10 | #include <errno.h> | ||
| 11 | #include <asm/io.h> | ||
| 12 | #include <miiphy.h> | ||
| 13 | #include <netdev.h> | ||
| 14 | #include <asm/mach-imx/iomux-v3.h> | ||
| 15 | #include <asm-generic/gpio.h> | ||
| 16 | #include <fsl_esdhc.h> | ||
| 17 | #include <mmc.h> | ||
| 18 | #include <asm/arch/imx8mq_pins.h> | ||
| 19 | #include <asm/arch/sys_proto.h> | ||
| 20 | #include <asm/mach-imx/gpio.h> | ||
| 21 | #include <asm/mach-imx/mxc_i2c.h> | ||
| 22 | #include <asm/arch/clock.h> | ||
| 23 | #include <asm/mach-imx/video.h> | ||
| 24 | #include <asm/arch/video_common.h> | ||
| 25 | #include <spl.h> | ||
| 26 | #include <power/pmic.h> | ||
| 27 | #include <power/pfuze100_pmic.h> | ||
| 28 | #include <dm.h> | ||
| 29 | #include "../../freescale/common/tcpc.h" | ||
| 30 | #include "../../freescale/common/pfuze.h" | ||
| 31 | #include "../../freescale/common/mmc.c" | ||
| 32 | #include <usb.h> | ||
| 33 | #include <dwc3-uboot.h> | ||
| 34 | |||
| 35 | DECLARE_GLOBAL_DATA_PTR; | ||
| 36 | |||
| 37 | #define QSPI_PAD_CTRL (PAD_CTL_DSE2 | PAD_CTL_HYS) | ||
| 38 | |||
| 39 | #define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) | ||
| 40 | |||
| 41 | #define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) | ||
| 42 | |||
| 43 | #define WEAK_PULLUP (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) | ||
| 44 | |||
| 45 | #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) | ||
| 46 | |||
| 47 | static iomux_v3_cfg_t const wdog_pads[] = { | ||
| 48 | IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), | ||
| 49 | }; | ||
| 50 | |||
| 51 | #ifdef CONFIG_FSL_QSPI | ||
| 52 | static iomux_v3_cfg_t const qspi_pads[] = { | ||
| 53 | IMX8MQ_PAD_NAND_ALE__QSPI_A_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), | ||
| 54 | IMX8MQ_PAD_NAND_CE0_B__QSPI_A_SS0_B | MUX_PAD_CTRL(QSPI_PAD_CTRL), | ||
| 55 | |||
| 56 | IMX8MQ_PAD_NAND_DATA00__QSPI_A_DATA0 | MUX_PAD_CTRL(QSPI_PAD_CTRL), | ||
| 57 | IMX8MQ_PAD_NAND_DATA01__QSPI_A_DATA1 | MUX_PAD_CTRL(QSPI_PAD_CTRL), | ||
| 58 | IMX8MQ_PAD_NAND_DATA02__QSPI_A_DATA2 | MUX_PAD_CTRL(QSPI_PAD_CTRL), | ||
| 59 | IMX8MQ_PAD_NAND_DATA03__QSPI_A_DATA3 | MUX_PAD_CTRL(QSPI_PAD_CTRL), | ||
| 60 | }; | ||
| 61 | |||
| 62 | int board_qspi_init(void) | ||
| 63 | { | ||
| 64 | imx_iomux_v3_setup_multiple_pads(qspi_pads, ARRAY_SIZE(qspi_pads)); | ||
| 65 | |||
| 66 | set_clk_qspi(); | ||
| 67 | |||
| 68 | return 0; | ||
| 69 | } | ||
| 70 | #endif | ||
| 71 | |||
| 72 | #ifdef CONFIG_CONSOLE_SER3 | ||
| 73 | static iomux_v3_cfg_t const uart1_pads[] = { | ||
| 74 | IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 75 | IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 76 | }; | ||
| 77 | #endif | ||
| 78 | |||
| 79 | #ifdef CONFIG_CONSOLE_SER2 | ||
| 80 | static iomux_v3_cfg_t const uart2_pads[] = { | ||
| 81 | IMX8MQ_PAD_UART2_RXD__UART2_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 82 | IMX8MQ_PAD_UART2_TXD__UART2_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 83 | }; | ||
| 84 | #endif | ||
| 85 | |||
| 86 | #ifdef CONFIG_CONSOLE_SER1 | ||
| 87 | static iomux_v3_cfg_t const uart3_pads[] = { | ||
| 88 | IMX8MQ_PAD_UART3_RXD__UART3_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 89 | IMX8MQ_PAD_UART3_TXD__UART3_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 90 | }; | ||
| 91 | #endif | ||
| 92 | |||
| 93 | #ifdef CONFIG_CONSOLE_SER0 | ||
| 94 | static iomux_v3_cfg_t const uart4_pads[] = { | ||
| 95 | IMX8MQ_PAD_UART4_RXD__UART4_RX | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 96 | IMX8MQ_PAD_ECSPI2_SS0__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 97 | IMX8MQ_PAD_ECSPI2_MISO__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 98 | IMX8MQ_PAD_UART4_TXD__UART4_TX | MUX_PAD_CTRL(UART_PAD_CTRL), | ||
| 99 | }; | ||
| 100 | #endif | ||
| 101 | |||
| 102 | /* SPI0*/ | ||
| 103 | static iomux_v3_cfg_t const ecspi1_pads[] = { | ||
| 104 | IMX8MQ_PAD_ECSPI1_MISO__ECSPI1_MISO | MUX_PAD_CTRL(QSPI_PAD_CTRL), | ||
| 105 | IMX8MQ_PAD_ECSPI1_MOSI__ECSPI1_MOSI | MUX_PAD_CTRL(QSPI_PAD_CTRL), | ||
| 106 | IMX8MQ_PAD_ECSPI1_SCLK__ECSPI1_SCLK | MUX_PAD_CTRL(QSPI_PAD_CTRL), | ||
| 107 | |||
| 108 | IMX8MQ_PAD_ECSPI1_SS0__GPIO5_IO9 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/ | ||
| 109 | IMX8MQ_PAD_GPIO1_IO00__GPIO1_IO0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/ | ||
| 110 | IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/ | ||
| 111 | IMX8MQ_PAD_NAND_WE_B__GPIO3_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/ | ||
| 112 | }; | ||
| 113 | |||
| 114 | /* MISC PINs */ | ||
| 115 | static iomux_v3_cfg_t const misc_pads[] = { | ||
| 116 | IMX8MQ_PAD_NAND_CLE__GPIO3_IO5 | MUX_PAD_CTRL(WEAK_PULLUP), /*S146, PCIE_WAKE*/ | ||
| 117 | IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(WEAK_PULLUP), /*S148, LID#*/ | ||
| 118 | IMX8MQ_PAD_GPIO1_IO12__GPIO1_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), /*S149, SLEEP#*/ | ||
| 119 | IMX8MQ_PAD_GPIO1_IO01__GPIO1_IO1 | MUX_PAD_CTRL(WEAK_PULLUP), /*S151, CHARGING#*/ | ||
| 120 | IMX8MQ_PAD_SAI2_RXC__GPIO4_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), /*S152, CHARGER_PRSNT#*/ | ||
| 121 | IMX8MQ_PAD_SAI3_MCLK__GPIO5_IO2 | MUX_PAD_CTRL(WEAK_PULLUP), /*S153, CARRIER_STBY#*/ | ||
| 122 | IMX8MQ_PAD_SAI2_RXFS__GPIO4_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*S156, BATLOW#*/ | ||
| 123 | IMX8MQ_PAD_NAND_WP_B__GPIO3_IO18 | MUX_PAD_CTRL(WEAK_PULLUP), /*CAN0_INT#*/ | ||
| 124 | IMX8MQ_PAD_NAND_READY_B__GPIO3_IO16 | MUX_PAD_CTRL(WEAK_PULLUP), /*CAN1_INT#*/ | ||
| 125 | }; | ||
| 126 | |||
| 127 | static void setup_iomux_misc(void) | ||
| 128 | { | ||
| 129 | imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); | ||
| 130 | |||
| 131 | /* Set CARRIER_LID# as Input*/ | ||
| 132 | gpio_request(IMX_GPIO_NR(1, 9), "LID#"); | ||
| 133 | gpio_direction_input(IMX_GPIO_NR(1, 9)); | ||
| 134 | /* Set CARRIER_SLEEP# as Input*/ | ||
| 135 | gpio_request(IMX_GPIO_NR(1, 12), "SLEEP#"); | ||
| 136 | gpio_direction_input(IMX_GPIO_NR(1, 12)); | ||
| 137 | /* Set CARRIER_CHARGING# as Input*/ | ||
| 138 | gpio_request(IMX_GPIO_NR(1, 01), "CHARGING#"); | ||
| 139 | gpio_direction_input(IMX_GPIO_NR(1, 01)); | ||
| 140 | /* Set CARRIER_CHARGER_PRSNT# as Input*/ | ||
| 141 | gpio_request(IMX_GPIO_NR(4, 22), "CHARGER_PRSNT#"); | ||
| 142 | gpio_direction_input(IMX_GPIO_NR(4, 22)); | ||
| 143 | /* Set CARRIER_STBY# as Output High*/ | ||
| 144 | gpio_request(IMX_GPIO_NR(5, 02), "CARRIER_STBY#"); | ||
| 145 | gpio_direction_output(IMX_GPIO_NR(5, 02) , 1); | ||
| 146 | /* Set CARRIER_BATLOW# as Input*/ | ||
| 147 | gpio_request(IMX_GPIO_NR(4, 21), "BATLOW#"); | ||
| 148 | gpio_direction_input(IMX_GPIO_NR(4, 21)); | ||
| 149 | /* Set PCIE_WAKE# as Input*/ | ||
| 150 | gpio_request(IMX_GPIO_NR(3, 5), "PCIE_WAKE#"); | ||
| 151 | gpio_direction_input(IMX_GPIO_NR(3, 5)); | ||
| 152 | /* Set CAN0_INT# as Input*/ | ||
| 153 | gpio_request(IMX_GPIO_NR(3, 18), "CAN0_INT#"); | ||
| 154 | gpio_direction_input(IMX_GPIO_NR(3, 18)); | ||
| 155 | /* Set CAN1_INT# as Input*/ | ||
| 156 | gpio_request(IMX_GPIO_NR(3, 16), "CAN1_INT#"); | ||
| 157 | gpio_direction_input(IMX_GPIO_NR(3, 16)); | ||
| 158 | } | ||
| 159 | |||
| 160 | /* GPIO PINs, By SMARC specification, GPIO0~GPIO5 are recommended set as Output Low by default and GPIO6~GPIO11 are recommended set as Input*/ | ||
| 161 | static iomux_v3_cfg_t const gpio_pads[] = { | ||
| 162 | IMX8MQ_PAD_SAI5_MCLK__GPIO3_IO25 | MUX_PAD_CTRL(WEAK_PULLUP), /*P108, GPIO0*/ | ||
| 163 | IMX8MQ_PAD_SAI5_RXFS__GPIO3_IO19 | MUX_PAD_CTRL(WEAK_PULLUP), /*P109, GPIO1*/ | ||
| 164 | IMX8MQ_PAD_SAI5_RXC__GPIO3_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), /*P110, GPIO2*/ | ||
| 165 | IMX8MQ_PAD_SAI5_RXD0__GPIO3_IO21 | MUX_PAD_CTRL(WEAK_PULLUP), /*P111, GPIO3*/ | ||
| 166 | IMX8MQ_PAD_SAI5_RXD1__GPIO3_IO22 | MUX_PAD_CTRL(WEAK_PULLUP), /*P112, GPIO4*/ | ||
| 167 | IMX8MQ_PAD_SPDIF_TX__GPIO5_IO3 | MUX_PAD_CTRL(WEAK_PULLUP), /*P113, GPIO5*/ | ||
| 168 | IMX8MQ_PAD_SPDIF_RX__GPIO5_IO4 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO6*/ | ||
| 169 | IMX8MQ_PAD_SAI5_RXD2__GPIO3_IO23 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO7*/ | ||
| 170 | IMX8MQ_PAD_SAI5_RXD3__GPIO3_IO24 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO8*/ | ||
| 171 | IMX8MQ_PAD_SAI1_TXC__GPIO4_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /*P114, GPIO9*/ | ||
| 172 | IMX8MQ_PAD_SAI1_TXFS__GPIO4_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), /*P115, GPIO10*/ | ||
| 173 | IMX8MQ_PAD_SAI1_MCLK__GPIO4_IO20 | MUX_PAD_CTRL(WEAK_PULLUP), /*P116, GPIO11*/ | ||
| 174 | }; | ||
| 175 | |||
| 176 | static void setup_iomux_gpio(void) | ||
| 177 | { | ||
| 178 | imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); | ||
| 179 | |||
| 180 | /* Set GPIO0 as Output Low*/ | ||
| 181 | gpio_request(IMX_GPIO_NR(3, 25), "GPIO0"); | ||
| 182 | gpio_direction_output(IMX_GPIO_NR(3, 25), 0); | ||
| 183 | /* Set GPIO1 as Output Low*/ | ||
| 184 | gpio_request(IMX_GPIO_NR(3, 19), "GPIO1"); | ||
| 185 | gpio_direction_output(IMX_GPIO_NR(3, 19), 0); | ||
| 186 | /* Set GPIO2 as Output Low*/ | ||
| 187 | gpio_request(IMX_GPIO_NR(3, 20), "GPIO2"); | ||
| 188 | gpio_direction_output(IMX_GPIO_NR(3, 20), 0); | ||
| 189 | /* Set GPIO3 as Output Low*/ | ||
| 190 | gpio_request(IMX_GPIO_NR(3, 21), "GPIO3"); | ||
| 191 | gpio_direction_output(IMX_GPIO_NR(3, 21), 0); | ||
| 192 | /* Set GPIO4 as Output Low*/ | ||
| 193 | gpio_request(IMX_GPIO_NR(3, 22), "GPIO4"); | ||
| 194 | gpio_direction_output(IMX_GPIO_NR(3, 22), 0); | ||
| 195 | /* Set GPIO5 as Output Low*/ | ||
| 196 | gpio_request(IMX_GPIO_NR(5, 3), "GPIO5"); | ||
| 197 | gpio_direction_output(IMX_GPIO_NR(5, 3), 0); | ||
| 198 | /* Set GPIO6 as Input*/ | ||
| 199 | gpio_request(IMX_GPIO_NR(5, 4), "GPIO6"); | ||
| 200 | gpio_direction_input(IMX_GPIO_NR(5, 4)); | ||
| 201 | /* Set GPIO7 as Input*/ | ||
| 202 | gpio_request(IMX_GPIO_NR(3, 23), "GPIO7"); | ||
| 203 | gpio_direction_input(IMX_GPIO_NR(3, 23)); | ||
| 204 | /* Set GPIO8 as Input*/ | ||
| 205 | gpio_request(IMX_GPIO_NR(3, 24), "GPIO8"); | ||
| 206 | gpio_direction_input(IMX_GPIO_NR(3, 24)); | ||
| 207 | /* Set GPIO9 as Input*/ | ||
| 208 | gpio_request(IMX_GPIO_NR(4, 11), "GPIO9"); | ||
| 209 | gpio_direction_input(IMX_GPIO_NR(4, 11)); | ||
| 210 | /* Set GPIO10 as Input*/ | ||
| 211 | gpio_request(IMX_GPIO_NR(4, 10), "GPIO10"); | ||
| 212 | gpio_direction_input(IMX_GPIO_NR(4, 10)); | ||
| 213 | /* Set GPIO11 as Input*/ | ||
| 214 | gpio_request(IMX_GPIO_NR(4, 20), "GPIO11"); | ||
| 215 | gpio_direction_input(IMX_GPIO_NR(4, 20)); | ||
| 216 | } | ||
| 217 | |||
| 218 | |||
| 219 | int board_early_init_f(void) | ||
| 220 | { | ||
| 221 | struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; | ||
| 222 | |||
| 223 | imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); | ||
| 224 | |||
| 225 | set_wdog_reset(wdog); | ||
| 226 | |||
| 227 | #ifdef CONFIG_CONSOLE_SER0 | ||
| 228 | imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads)); | ||
| 229 | #endif | ||
| 230 | #ifdef CONFIG_CONSOLE_SER1 | ||
| 231 | imx_iomux_v3_setup_multiple_pads(uart3_pads, ARRAY_SIZE(uart3_pads)); | ||
| 232 | #endif | ||
| 233 | #ifdef CONFIG_CONSOLE_SER2 | ||
| 234 | imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); | ||
| 235 | #endif | ||
| 236 | #ifdef CONFIG_CONSOLE_SER3 | ||
| 237 | imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); | ||
| 238 | #endif | ||
| 239 | |||
| 240 | return 0; | ||
| 241 | } | ||
| 242 | |||
| 243 | #ifdef CONFIG_BOARD_POSTCLK_INIT | ||
| 244 | int board_postclk_init(void) | ||
| 245 | { | ||
| 246 | /* TODO */ | ||
| 247 | return 0; | ||
| 248 | } | ||
| 249 | #endif | ||
| 250 | |||
| 251 | int dram_init(void) | ||
| 252 | { | ||
| 253 | /* rom_pointer[1] contains the size of TEE occupies */ | ||
| 254 | if (rom_pointer[1]) | ||
| 255 | gd->ram_size = PHYS_SDRAM_SIZE - rom_pointer[1]; | ||
| 256 | else | ||
| 257 | gd->ram_size = PHYS_SDRAM_SIZE; | ||
| 258 | |||
| 259 | return 0; | ||
| 260 | } | ||
| 261 | |||
| 262 | #ifdef CONFIG_SYS_I2C | ||
| 263 | /*I2C2, I2C_CAM0 and I2C_LCD*/ | ||
| 264 | struct i2c_pads_info i2c_pad_info2 = { | ||
| 265 | .scl = { | ||
| 266 | .i2c_mode = IMX8MQ_PAD_I2C2_SCL__I2C2_SCL | I2C_PAD_CTRL, | ||
| 267 | .gpio_mode = IMX8MQ_PAD_I2C2_SCL__GPIO5_IO16 | I2C_PAD_CTRL, | ||
| 268 | .gp = IMX_GPIO_NR(5, 16), | ||
| 269 | }, | ||
| 270 | .sda = { | ||
| 271 | .i2c_mode = IMX8MQ_PAD_I2C2_SDA__I2C2_SDA | I2C_PAD_CTRL, | ||
| 272 | .gpio_mode = IMX8MQ_PAD_I2C2_SDA__GPIO5_IO17 | I2C_PAD_CTRL, | ||
| 273 | .gp = IMX_GPIO_NR(5, 17), | ||
| 274 | }, | ||
| 275 | }; | ||
| 276 | |||
| 277 | /*I2C3, I2C_GP*/ | ||
| 278 | struct i2c_pads_info i2c_pad_info3 = { | ||
| 279 | .scl = { | ||
| 280 | .i2c_mode = IMX8MQ_PAD_I2C3_SCL__I2C3_SCL | I2C_PAD_CTRL, | ||
| 281 | .gpio_mode = IMX8MQ_PAD_I2C3_SCL__GPIO5_IO18 | I2C_PAD_CTRL, | ||
| 282 | .gp = IMX_GPIO_NR(5, 18), | ||
| 283 | }, | ||
| 284 | .sda = { | ||
| 285 | .i2c_mode = IMX8MQ_PAD_I2C3_SDA__I2C3_SDA | I2C_PAD_CTRL, | ||
| 286 | .gpio_mode = IMX8MQ_PAD_I2C3_SDA__GPIO5_IO19 | I2C_PAD_CTRL, | ||
| 287 | .gp = IMX_GPIO_NR(5, 19), | ||
| 288 | }, | ||
| 289 | }; | ||
| 290 | |||
| 291 | /*I2C4, I2C_CAM1*/ | ||
| 292 | struct i2c_pads_info i2c_pad_info4 = { | ||
| 293 | .scl = { | ||
| 294 | .i2c_mode = IMX8MQ_PAD_I2C4_SCL__I2C4_SCL | I2C_PAD_CTRL, | ||
| 295 | .gpio_mode = IMX8MQ_PAD_I2C4_SCL__GPIO5_IO20 | I2C_PAD_CTRL, | ||
| 296 | .gp = IMX_GPIO_NR(5, 20), | ||
| 297 | }, | ||
| 298 | .sda = { | ||
| 299 | .i2c_mode = IMX8MQ_PAD_I2C4_SDA__I2C4_SDA | I2C_PAD_CTRL, | ||
| 300 | .gpio_mode = IMX8MQ_PAD_I2C4_SDA__GPIO5_IO21 | I2C_PAD_CTRL, | ||
| 301 | .gp = IMX_GPIO_NR(5, 21), | ||
| 302 | }, | ||
| 303 | }; | ||
| 304 | #endif | ||
| 305 | |||
| 306 | #ifdef CONFIG_OF_BOARD_SETUP | ||
| 307 | int ft_board_setup(void *blob, bd_t *bd) | ||
| 308 | { | ||
| 309 | return 0; | ||
| 310 | } | ||
| 311 | #endif | ||
| 312 | |||
| 313 | /* Get the top of usable RAM */ | ||
| 314 | ulong board_get_usable_ram_top(ulong total_size) | ||
| 315 | { | ||
| 316 | |||
| 317 | //printf("board_get_usable_ram_top total_size is 0x%lx \n", total_size); | ||
| 318 | |||
| 319 | if(gd->ram_top > 0x100000000) | ||
| 320 | gd->ram_top = 0x100000000; | ||
| 321 | |||
| 322 | return gd->ram_top; | ||
| 323 | } | ||
| 324 | |||
| 325 | #ifdef CONFIG_FEC_MXC | ||
| 326 | #define FEC_RST_PAD IMX_GPIO_NR(1, 11) | ||
| 327 | static iomux_v3_cfg_t const fec1_irq_pads[] = { | ||
| 328 | IMX8MQ_PAD_GPIO1_IO11__GPIO1_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), | ||
| 329 | }; | ||
| 330 | |||
| 331 | static void setup_iomux_fec(void) | ||
| 332 | { | ||
| 333 | imx_iomux_v3_setup_multiple_pads(fec1_irq_pads, | ||
| 334 | ARRAY_SIZE(fec1_irq_pads)); | ||
| 335 | |||
| 336 | gpio_request(IMX_GPIO_NR(1, 11), "fec1_irq"); | ||
| 337 | gpio_direction_input(IMX_GPIO_NR(1, 11)); | ||
| 338 | } | ||
| 339 | |||
| 340 | static int setup_fec(void) | ||
| 341 | { | ||
| 342 | struct iomuxc_gpr_base_regs *const iomuxc_gpr_regs | ||
| 343 | = (struct iomuxc_gpr_base_regs *) IOMUXC_GPR_BASE_ADDR; | ||
| 344 | |||
| 345 | setup_iomux_fec(); | ||
| 346 | |||
| 347 | /* Use 125M anatop REF_CLK1 for ENET1, not from external */ | ||
| 348 | clrsetbits_le32(&iomuxc_gpr_regs->gpr[1], | ||
| 349 | IOMUXC_GPR_GPR1_GPR_ENET1_TX_CLK_SEL_SHIFT, 0); | ||
| 350 | return set_clk_enet(ENET_125MHZ); | ||
| 351 | } | ||
| 352 | |||
| 353 | |||
| 354 | int board_phy_config(struct phy_device *phydev) | ||
| 355 | { | ||
| 356 | /* enable rgmii rxc skew and phy mode select to RGMII copper */ | ||
| 357 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x1f); | ||
| 358 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x8); | ||
| 359 | |||
| 360 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); | ||
| 361 | phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x100); | ||
| 362 | |||
| 363 | if (phydev->drv->config) | ||
| 364 | phydev->drv->config(phydev); | ||
| 365 | return 0; | ||
| 366 | } | ||
| 367 | #endif | ||
| 368 | |||
| 369 | static void setup_iomux_ecspi1(void) | ||
| 370 | { | ||
| 371 | imx_iomux_v3_setup_multiple_pads(ecspi1_pads, | ||
| 372 | ARRAY_SIZE(ecspi1_pads)); | ||
| 373 | } | ||
| 374 | |||
| 375 | int board_spi_cs_gpio(unsigned bus, unsigned cs) | ||
| 376 | { | ||
| 377 | gpio_request(IMX_GPIO_NR(5, 9), "espi1_cs0"); | ||
| 378 | return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(5, 9)) : -1; | ||
| 379 | gpio_request(IMX_GPIO_NR(1, 0), "espi1_cs1"); | ||
| 380 | return (bus == 0 && cs == 1) ? (IMX_GPIO_NR(1, 0)) : -1; | ||
| 381 | gpio_request(IMX_GPIO_NR(3, 15), "espi1_cs2"); | ||
| 382 | return (bus == 0 && cs == 2) ? (IMX_GPIO_NR(3, 15)) : -1; | ||
| 383 | gpio_request(IMX_GPIO_NR(3, 17), "espi1_cs3"); | ||
| 384 | return (bus == 0 && cs == 3) ? (IMX_GPIO_NR(3, 17)) : -1; | ||
| 385 | } | ||
| 386 | |||
| 387 | #ifdef CONFIG_USB_DWC3 | ||
| 388 | |||
| 389 | #define USB_PHY_CTRL0 0xF0040 | ||
| 390 | #define USB_PHY_CTRL0_REF_SSP_EN BIT(2) | ||
| 391 | |||
| 392 | #define USB_PHY_CTRL1 0xF0044 | ||
| 393 | #define USB_PHY_CTRL1_RESET BIT(0) | ||
| 394 | #define USB_PHY_CTRL1_COMMONONN BIT(1) | ||
| 395 | #define USB_PHY_CTRL1_ATERESET BIT(3) | ||
| 396 | #define USB_PHY_CTRL1_VDATSRCENB0 BIT(19) | ||
| 397 | #define USB_PHY_CTRL1_VDATDETENB0 BIT(20) | ||
| 398 | |||
| 399 | #define USB_PHY_CTRL2 0xF0048 | ||
| 400 | #define USB_PHY_CTRL2_TXENABLEN0 BIT(8) | ||
| 401 | |||
| 402 | static struct dwc3_device dwc3_device_data = { | ||
| 403 | #ifdef CONFIG_SPL_BUILD | ||
| 404 | .maximum_speed = USB_SPEED_HIGH, | ||
| 405 | #else | ||
| 406 | .maximum_speed = USB_SPEED_SUPER, | ||
| 407 | #endif | ||
| 408 | .base = USB1_BASE_ADDR, | ||
| 409 | .dr_mode = USB_DR_MODE_PERIPHERAL, | ||
| 410 | .index = 0, | ||
| 411 | .power_down_scale = 2, | ||
| 412 | }; | ||
| 413 | |||
| 414 | int usb_gadget_handle_interrupts(void) | ||
| 415 | { | ||
| 416 | dwc3_uboot_handle_interrupt(0); | ||
| 417 | return 0; | ||
| 418 | } | ||
| 419 | |||
| 420 | static void dwc3_nxp_usb_phy_init(struct dwc3_device *dwc3) | ||
| 421 | { | ||
| 422 | u32 RegData; | ||
| 423 | |||
| 424 | RegData = readl(dwc3->base + USB_PHY_CTRL1); | ||
| 425 | RegData &= ~(USB_PHY_CTRL1_VDATSRCENB0 | USB_PHY_CTRL1_VDATDETENB0 | | ||
| 426 | USB_PHY_CTRL1_COMMONONN); | ||
| 427 | RegData |= USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET; | ||
| 428 | writel(RegData, dwc3->base + USB_PHY_CTRL1); | ||
| 429 | |||
| 430 | RegData = readl(dwc3->base + USB_PHY_CTRL0); | ||
| 431 | RegData |= USB_PHY_CTRL0_REF_SSP_EN; | ||
| 432 | writel(RegData, dwc3->base + USB_PHY_CTRL0); | ||
| 433 | |||
| 434 | RegData = readl(dwc3->base + USB_PHY_CTRL2); | ||
| 435 | RegData |= USB_PHY_CTRL2_TXENABLEN0; | ||
| 436 | writel(RegData, dwc3->base + USB_PHY_CTRL2); | ||
| 437 | |||
| 438 | RegData = readl(dwc3->base + USB_PHY_CTRL1); | ||
| 439 | RegData &= ~(USB_PHY_CTRL1_RESET | USB_PHY_CTRL1_ATERESET); | ||
| 440 | writel(RegData, dwc3->base + USB_PHY_CTRL1); | ||
| 441 | } | ||
| 442 | #endif | ||
| 443 | |||
| 444 | /*USB Enable Over-Current Pin Setting*/ | ||
| 445 | static iomux_v3_cfg_t const usb_en_oc_pads[] = { | ||
| 446 | IMX8MQ_PAD_NAND_DATA04__GPIO3_IO10 | MUX_PAD_CTRL(WEAK_PULLUP), | ||
| 447 | IMX8MQ_PAD_NAND_DATA06__GPIO3_IO12 | MUX_PAD_CTRL(WEAK_PULLUP), | ||
| 448 | IMX8MQ_PAD_NAND_DATA07__GPIO3_IO13 | MUX_PAD_CTRL(WEAK_PULLUP), | ||
| 449 | }; | ||
| 450 | |||
| 451 | static void setup_iomux_usb_en_oc(void) | ||
| 452 | { | ||
| 453 | imx_iomux_v3_setup_multiple_pads(usb_en_oc_pads, | ||
| 454 | ARRAY_SIZE(usb_en_oc_pads)); | ||
| 455 | |||
| 456 | gpio_request(IMX_GPIO_NR(3, 10), "usb0_en_oc#"); | ||
| 457 | gpio_direction_input(IMX_GPIO_NR(3, 10)); | ||
| 458 | gpio_request(IMX_GPIO_NR(3, 12), "usb2_en_oc#"); | ||
| 459 | gpio_direction_input(IMX_GPIO_NR(3, 12)); | ||
| 460 | gpio_request(IMX_GPIO_NR(3, 13), "usb3_en_oc#"); | ||
| 461 | gpio_direction_input(IMX_GPIO_NR(3, 13)); | ||
| 462 | } | ||
| 463 | |||
| 464 | #ifdef CONFIG_USB_TCPC | ||
| 465 | struct tcpc_port port; | ||
| 466 | struct tcpc_port_config port_config = { | ||
| 467 | .i2c_bus = 0, | ||
| 468 | .addr = 0x50, | ||
| 469 | .port_type = TYPEC_PORT_UFP, | ||
| 470 | .max_snk_mv = 20000, | ||
| 471 | .max_snk_ma = 3000, | ||
| 472 | .max_snk_mw = 15000, | ||
| 473 | .op_snk_mv = 9000, | ||
| 474 | }; | ||
| 475 | |||
| 476 | #define USB_TYPEC_SEL IMX_GPIO_NR(3, 15) | ||
| 477 | |||
| 478 | static iomux_v3_cfg_t ss_mux_gpio[] = { | ||
| 479 | IMX8MQ_PAD_NAND_RE_B__GPIO3_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), | ||
| 480 | }; | ||
| 481 | |||
| 482 | void ss_mux_select(enum typec_cc_polarity pol) | ||
| 483 | { | ||
| 484 | if (pol == TYPEC_POLARITY_CC1) | ||
| 485 | gpio_direction_output(USB_TYPEC_SEL, 1); | ||
| 486 | else | ||
| 487 | gpio_direction_output(USB_TYPEC_SEL, 0); | ||
| 488 | } | ||
| 489 | |||
| 490 | static int setup_typec(void) | ||
| 491 | { | ||
| 492 | int ret; | ||
| 493 | |||
| 494 | imx_iomux_v3_setup_multiple_pads(ss_mux_gpio, ARRAY_SIZE(ss_mux_gpio)); | ||
| 495 | gpio_request(USB_TYPEC_SEL, "typec_sel"); | ||
| 496 | |||
| 497 | ret = tcpc_init(&port, port_config, &ss_mux_select); | ||
| 498 | if (ret) { | ||
| 499 | printf("%s: tcpc init failed, err=%d\n", | ||
| 500 | __func__, ret); | ||
| 501 | } | ||
| 502 | |||
| 503 | return ret; | ||
| 504 | } | ||
| 505 | #endif | ||
| 506 | |||
| 507 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) | ||
| 508 | int board_usb_init(int index, enum usb_init_type init) | ||
| 509 | { | ||
| 510 | int ret = 0; | ||
| 511 | imx8m_usb_power(index, true); | ||
| 512 | |||
| 513 | if (index == 0 && init == USB_INIT_DEVICE) { | ||
| 514 | #ifdef CONFIG_USB_TCPC | ||
| 515 | ret = tcpc_setup_ufp_mode(&port); | ||
| 516 | #endif | ||
| 517 | dwc3_nxp_usb_phy_init(&dwc3_device_data); | ||
| 518 | return dwc3_uboot_init(&dwc3_device_data); | ||
| 519 | } else if (index == 0 && init == USB_INIT_HOST) { | ||
| 520 | #ifdef CONFIG_USB_TCPC | ||
| 521 | ret = tcpc_setup_dfp_mode(&port); | ||
| 522 | #endif | ||
| 523 | return ret; | ||
| 524 | } | ||
| 525 | |||
| 526 | return 0; | ||
| 527 | } | ||
| 528 | |||
| 529 | int board_usb_cleanup(int index, enum usb_init_type init) | ||
| 530 | { | ||
| 531 | int ret = 0; | ||
| 532 | if (index == 0 && init == USB_INIT_DEVICE) { | ||
| 533 | dwc3_uboot_exit(index); | ||
| 534 | } else if (index == 0 && init == USB_INIT_HOST) { | ||
| 535 | #ifdef CONFIG_USB_TCPC | ||
| 536 | ret = tcpc_disable_src_vbus(&port); | ||
| 537 | #endif | ||
| 538 | } | ||
| 539 | |||
| 540 | imx8m_usb_power(index, false); | ||
| 541 | |||
| 542 | return ret; | ||
| 543 | } | ||
| 544 | #endif | ||
| 545 | |||
| 546 | int board_init(void) | ||
| 547 | { | ||
| 548 | board_qspi_init(); | ||
| 549 | setup_iomux_usb_en_oc(); | ||
| 550 | setup_iomux_misc(); | ||
| 551 | setup_iomux_gpio(); | ||
| 552 | |||
| 553 | #ifdef CONFIG_FEC_MXC | ||
| 554 | setup_fec(); | ||
| 555 | #endif | ||
| 556 | |||
| 557 | #if defined(CONFIG_USB_DWC3) || defined(CONFIG_USB_XHCI_IMX8M) | ||
| 558 | init_usb_clk(); | ||
| 559 | #endif | ||
| 560 | |||
| 561 | #ifdef CONFIG_USB_TCPC | ||
| 562 | setup_typec(); | ||
| 563 | #endif | ||
| 564 | return 0; | ||
| 565 | } | ||
| 566 | |||
| 567 | int board_mmc_get_env_dev(int devno) | ||
| 568 | { | ||
| 569 | return devno; | ||
| 570 | } | ||
| 571 | |||
| 572 | int board_late_init(void) | ||
| 573 | { | ||
| 574 | setup_iomux_ecspi1(); | ||
| 575 | |||
| 576 | /* Read Module Information from on module EEPROM and pass | ||
| 577 | * mac address to kernel | ||
| 578 | */ | ||
| 579 | struct udevice *dev; | ||
| 580 | int ret; | ||
| 581 | u8 name[8]; | ||
| 582 | u8 serial[12]; | ||
| 583 | u8 revision[4]; | ||
| 584 | u8 mac[6]; | ||
| 585 | |||
| 586 | ret = i2c_get_chip_for_busnum(2, 0x50, 2, &dev); | ||
| 587 | if (ret) { | ||
| 588 | debug("failed to get eeprom\n"); | ||
| 589 | return 0; | ||
| 590 | } | ||
| 591 | |||
| 592 | /* Board ID */ | ||
| 593 | ret = dm_i2c_read(dev, 0x4, name, 8); | ||
| 594 | if (ret) { | ||
| 595 | debug("failed to read board ID from EEPROM\n"); | ||
| 596 | return 0; | ||
| 597 | } | ||
| 598 | puts("---------Embedian SMARC-iMX8M------------\n"); | ||
| 599 | printf(" Board ID: %c%c%c%c%c%c%c%c\n", | ||
| 600 | name[0], name[1], name[2], name[3], name[4], name[5], name[6], name[7]); | ||
| 601 | |||
| 602 | /* Board Hardware Revision */ | ||
| 603 | ret = dm_i2c_read(dev, 0xc, revision, 4); | ||
| 604 | if (ret) { | ||
| 605 | debug("failed to read hardware revison from EEPROM\n"); | ||
| 606 | return 0; | ||
| 607 | } | ||
| 608 | printf(" Hardware Revision: %c%c%c%c\n", | ||
| 609 | revision[0], revision[1], revision[2], revision[3]); | ||
| 610 | |||
| 611 | /* Serial number */ | ||
| 612 | ret = dm_i2c_read(dev, 0x10, serial, 12); | ||
| 613 | if (ret) { | ||
| 614 | debug("failed to read srial number from EEPROM\n"); | ||
| 615 | return 0; | ||
| 616 | } | ||
| 617 | printf(" Serial Number#: %c%c%c%c%c%c%c%c%c%c%c%c\n", | ||
| 618 | serial[0], serial[1], serial[2], serial[3], serial[4], serial[5], serial[6], serial[7], serial[8], serial[9], serial[10], serial[11]); | ||
| 619 | |||
| 620 | /*MAC address */ | ||
| 621 | ret = dm_i2c_read(dev, 0x3c, mac, 6); | ||
| 622 | if (ret) { | ||
| 623 | debug("failed to read eth0 mac address from EEPROM\n"); | ||
| 624 | return 0; | ||
| 625 | } | ||
| 626 | |||
| 627 | if (is_valid_ethaddr(mac)) | ||
| 628 | printf(" MAC Address: %02x:%02x:%02x:%02x:%02x:%02x\n", | ||
| 629 | mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); | ||
| 630 | eth_env_set_enetaddr("ethaddr", mac); | ||
| 631 | puts("-----------------------------------------\n"); | ||
| 632 | |||
| 633 | #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | ||
| 634 | env_set("board_name", "SMARC-iMX8M"); | ||
| 635 | env_set("board_rev", "iMX8MQ"); | ||
| 636 | #endif | ||
| 637 | |||
| 638 | #ifdef CONFIG_ENV_IS_IN_MMC | ||
| 639 | board_late_mmc_env_init(); | ||
| 640 | #endif | ||
| 641 | |||
| 642 | /* SMARC BOOT_SEL*/ | ||
| 643 | gpio_request(IMX_GPIO_NR(1, 8), "BOOT_SEL_1"); | ||
| 644 | gpio_request(IMX_GPIO_NR(1, 5), "BOOT_SEL_2"); | ||
| 645 | gpio_request(IMX_GPIO_NR(1, 6), "BOOT_SEL_3"); | ||
| 646 | if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | ||
| 647 | puts("BOOT_SEL Detected: OFF OFF OFF, Boot from Carrier SATA is not supported...\n"); | ||
| 648 | hang(); | ||
| 649 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | ||
| 650 | puts("BOOT_SEL Detected: OFF OFF ON, Load Image from USB0...\n"); | ||
| 651 | env_set_ulong("usb dev", 1); | ||
| 652 | env_set("bootcmd", "usb start; run loadusbbootenv; run importusbbootenv; run uenvcmd; loadusbimage; run usbboot;"); | ||
| 653 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | ||
| 654 | puts("BOOT_SEL Detected: OFF ON OFF, Boot from Carrier eSPI is not supported...\n"); | ||
| 655 | hang(); | ||
| 656 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | ||
| 657 | puts("BOOT_SEL Detected: ON OFF OFF, Load Image from Carrier SD Card...\n"); | ||
| 658 | env_set_ulong("mmcdev", 1); | ||
| 659 | env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;"); | ||
| 660 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | ||
| 661 | puts("BOOT_SEL Detected: OFF ON ON, Load Image from Module eMMC Flash...\n"); | ||
| 662 | env_set_ulong("mmcdev", 0); | ||
| 663 | env_set("bootcmd", "mmc rescan; run loadbootenv; run importbootenv; run uenvcmd; run loadimage; run mmcboot;"); | ||
| 664 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 0)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | ||
| 665 | puts("BOOT_SEL Detected: ON OFF ON, Load zImage from GBE...\n"); | ||
| 666 | env_set("bootcmd", "run netboot;"); | ||
| 667 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 0)) { | ||
| 668 | puts("Carrier SPI Boot is not supported...\n"); | ||
| 669 | hang(); | ||
| 670 | } else if ((gpio_get_value(IMX_GPIO_NR(1, 8)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 5)) == 1)&&(gpio_get_value(IMX_GPIO_NR(1, 6)) == 1)) { | ||
| 671 | puts("BOOT_SEL Detected: ON ON ON, Boot from Module SPI is not supported...\n"); | ||
| 672 | hang(); | ||
| 673 | } else { | ||
| 674 | puts("unsupported boot devices\n"); | ||
| 675 | hang(); | ||
| 676 | } | ||
| 677 | |||
| 678 | return 0; | ||
| 679 | } | ||
| 680 | |||
| 681 | #ifdef CONFIG_FSL_FASTBOOT | ||
| 682 | #ifdef CONFIG_ANDROID_RECOVERY | ||
| 683 | #define LID_KEY IMX_GPIO_NR(1, 9) | ||
| 684 | #define LID_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) | ||
| 685 | |||
| 686 | static iomux_v3_cfg_t const lid_pads[] = { | ||
| 687 | IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(LID_PAD_CTRL), | ||
| 688 | }; | ||
| 689 | |||
| 690 | int is_recovery_key_pressing(void) | ||
| 691 | { | ||
| 692 | imx_iomux_v3_setup_multiple_pads(lid_pads, ARRAY_SIZE(lid_pads)); | ||
| 693 | gpio_request(LID_KEY, "LID"); | ||
| 694 | gpio_direction_input(LID_KEY); | ||
| 695 | if (gpio_get_value(LID_KEY) == 0) { /* LID key is low assert */ | ||
| 696 | printf("Recovery key pressed\n"); | ||
| 697 | return 1; | ||
| 698 | } | ||
| 699 | return 0; | ||
| 700 | } | ||
| 701 | #endif /*CONFIG_ANDROID_RECOVERY*/ | ||
| 702 | #endif /*CONFIG_FSL_FASTBOOT*/ | ||
| 703 | |||
| 704 | #if defined(CONFIG_VIDEO_IMXDCSS) | ||
| 705 | |||
| 706 | struct display_info_t const displays[] = {{ | ||
| 707 | .bus = 0, /* Unused */ | ||
| 708 | .addr = 0, /* Unused */ | ||
| 709 | .pixfmt = GDF_32BIT_X888RGB, | ||
| 710 | .detect = NULL, | ||
| 711 | .enable = NULL, | ||
| 712 | #ifndef CONFIG_VIDEO_IMXDCSS_1080P | ||
| 713 | .mode = { | ||
| 714 | .name = "HDMI", /* 720P60 */ | ||
| 715 | .refresh = 60, | ||
| 716 | .xres = 1280, | ||
| 717 | .yres = 720, | ||
| 718 | .pixclock = 13468, /* 74250 kHz */ | ||
| 719 | .left_margin = 110, | ||
| 720 | .right_margin = 220, | ||
| 721 | .upper_margin = 5, | ||
| 722 | .lower_margin = 20, | ||
| 723 | .hsync_len = 40, | ||
| 724 | .vsync_len = 5, | ||
| 725 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | ||
| 726 | .vmode = FB_VMODE_NONINTERLACED | ||
| 727 | } | ||
| 728 | #else | ||
| 729 | .mode = { | ||
| 730 | .name = "HDMI", /* 1080P60 */ | ||
| 731 | .refresh = 60, | ||
| 732 | .xres = 1920, | ||
| 733 | .yres = 1080, | ||
| 734 | .pixclock = 6734, /* 148500 kHz */ | ||
| 735 | .left_margin = 148, | ||
| 736 | .right_margin = 88, | ||
| 737 | .upper_margin = 36, | ||
| 738 | .lower_margin = 4, | ||
| 739 | .hsync_len = 44, | ||
| 740 | .vsync_len = 5, | ||
| 741 | .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT, | ||
| 742 | .vmode = FB_VMODE_NONINTERLACED | ||
| 743 | } | ||
| 744 | #endif | ||
| 745 | } }; | ||
| 746 | size_t display_count = ARRAY_SIZE(displays); | ||
| 747 | |||
| 748 | #endif /* CONFIG_VIDEO_IMXDCSS */ | ||
| 749 | |||
| 750 | /* return hard code board id for imx8m_ref */ | ||
| 751 | #if defined(CONFIG_ANDROID_THINGS_SUPPORT) && defined(CONFIG_ARCH_IMX8M) | ||
| 752 | int get_imx8m_baseboard_id(void) | ||
| 753 | { | ||
| 754 | return IMX8M_REF_3G; | ||
| 755 | } | ||
| 756 | #endif | ||
| 757 | 1 | /* |
board/embedian/embedian/smarcimx8mq/spl.c
| 1 | /* | File was deleted | |
| 2 | * Copyright 2017 NXP | ||
| 3 | * | ||
| 4 | * SPDX-License-Identifier: GPL-2.0+ | ||
| 5 | */ | ||
| 6 | |||
| 7 | #include <common.h> | ||
| 8 | #include <spl.h> | ||
| 9 | #include <asm/io.h> | ||
| 10 | #include <errno.h> | ||
| 11 | #include <asm/io.h> | ||
| 12 | #include <asm/mach-imx/iomux-v3.h> | ||
| 13 | #include <asm/arch/ddr.h> | ||
| 14 | #include <asm/arch/imx8mq_pins.h> | ||
| 15 | #include <asm/arch/sys_proto.h> | ||
| 16 | #include <power/pmic.h> | ||
| 17 | #include <power/pfuze100_pmic.h> | ||
| 18 | #include "../../freescale/common/pfuze.h" | ||
| 19 | #include <asm/arch/clock.h> | ||
| 20 | #include <asm/mach-imx/gpio.h> | ||
| 21 | #include <asm/mach-imx/mxc_i2c.h> | ||
| 22 | #include <fsl_esdhc.h> | ||
| 23 | #include <mmc.h> | ||
| 24 | #include <asm/arch/imx8m_ddr.h> | ||
| 25 | |||
| 26 | DECLARE_GLOBAL_DATA_PTR; | ||
| 27 | |||
| 28 | /*extern struct dram_timing_info dram_timing_b0;*/ | ||
| 29 | |||
| 30 | void spl_dram_init(void) | ||
| 31 | { | ||
| 32 | /* ddr init */ | ||
| 33 | ddr_init(&dram_timing); | ||
| 34 | } | ||
| 35 | |||
| 36 | #define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) | ||
| 37 | #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) | ||
| 38 | struct i2c_pads_info i2c_pad_info1 = { | ||
| 39 | .scl = { | ||
| 40 | .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, | ||
| 41 | .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, | ||
| 42 | .gp = IMX_GPIO_NR(5, 14), | ||
| 43 | }, | ||
| 44 | .sda = { | ||
| 45 | .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, | ||
| 46 | .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, | ||
| 47 | .gp = IMX_GPIO_NR(5, 15), | ||
| 48 | }, | ||
| 49 | }; | ||
| 50 | |||
| 51 | #define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) | ||
| 52 | #define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) | ||
| 53 | #define USDHC2_PWR_GPIO IMX_GPIO_NR(2, 19) | ||
| 54 | |||
| 55 | int board_mmc_getcd(struct mmc *mmc) | ||
| 56 | { | ||
| 57 | struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; | ||
| 58 | int ret = 0; | ||
| 59 | |||
| 60 | switch (cfg->esdhc_base) { | ||
| 61 | case USDHC1_BASE_ADDR: | ||
| 62 | ret = 1; | ||
| 63 | break; | ||
| 64 | case USDHC2_BASE_ADDR: | ||
| 65 | ret = !gpio_get_value(USDHC2_CD_GPIO); | ||
| 66 | return ret; | ||
| 67 | } | ||
| 68 | |||
| 69 | return 1; | ||
| 70 | } | ||
| 71 | |||
| 72 | #define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ | ||
| 73 | PAD_CTL_FSEL2) | ||
| 74 | #define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) | ||
| 75 | |||
| 76 | static iomux_v3_cfg_t const usdhc1_pads[] = { | ||
| 77 | IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), | ||
| 78 | IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), | ||
| 79 | IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | ||
| 80 | IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | ||
| 81 | IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | ||
| 82 | IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | ||
| 83 | IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | ||
| 84 | IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | ||
| 85 | IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | ||
| 86 | IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), | ||
| 87 | IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), | ||
| 88 | }; | ||
| 89 | |||
| 90 | static iomux_v3_cfg_t const usdhc2_pads[] = { | ||
| 91 | IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ | ||
| 92 | IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ | ||
| 93 | IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ | ||
| 94 | IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ | ||
| 95 | IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ | ||
| 96 | IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ | ||
| 97 | IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), | ||
| 98 | IMX8MQ_PAD_SD2_RESET_B__GPIO2_IO19 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), | ||
| 99 | }; | ||
| 100 | |||
| 101 | /* RESET_OUT */ | ||
| 102 | static iomux_v3_cfg_t const reset_out_pads[] = { | ||
| 103 | IMX8MQ_PAD_GPIO1_IO03__GPIO1_IO3 | MUX_PAD_CTRL(NO_PAD_CTRL), | ||
| 104 | }; | ||
| 105 | |||
| 106 | static void setup_iomux_reset_out(void) | ||
| 107 | { | ||
| 108 | imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads)); | ||
| 109 | |||
| 110 | /* Set CPU RESET_OUT as Output */ | ||
| 111 | gpio_request(IMX_GPIO_NR(1, 03), "CPU_RESET"); | ||
| 112 | gpio_direction_output(IMX_GPIO_NR(1, 03) , 0); | ||
| 113 | } | ||
| 114 | |||
| 115 | static struct fsl_esdhc_cfg usdhc_cfg[2] = { | ||
| 116 | {USDHC1_BASE_ADDR, 0, 8}, | ||
| 117 | {USDHC2_BASE_ADDR, 0, 4}, | ||
| 118 | }; | ||
| 119 | |||
| 120 | int board_mmc_init(bd_t *bis) | ||
| 121 | { | ||
| 122 | int i, ret; | ||
| 123 | /* | ||
| 124 | * According to the board_mmc_init() the following map is done: | ||
| 125 | * (U-Boot device node) (Physical Port) | ||
| 126 | * mmc0 USDHC1 | ||
| 127 | * mmc1 USDHC2 | ||
| 128 | */ | ||
| 129 | for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { | ||
| 130 | switch (i) { | ||
| 131 | case 0: | ||
| 132 | usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); | ||
| 133 | imx_iomux_v3_setup_multiple_pads( | ||
| 134 | usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); | ||
| 135 | gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); | ||
| 136 | gpio_direction_output(USDHC1_PWR_GPIO, 0); | ||
| 137 | udelay(500); | ||
| 138 | gpio_direction_output(USDHC1_PWR_GPIO, 1); | ||
| 139 | break; | ||
| 140 | case 1: | ||
| 141 | usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); | ||
| 142 | imx_iomux_v3_setup_multiple_pads( | ||
| 143 | usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); | ||
| 144 | gpio_request(USDHC2_PWR_GPIO, "usdhc2_reset"); | ||
| 145 | gpio_direction_output(USDHC2_PWR_GPIO, 0); | ||
| 146 | udelay(500); | ||
| 147 | gpio_direction_output(USDHC2_PWR_GPIO, 1); | ||
| 148 | break; | ||
| 149 | default: | ||
| 150 | printf("Warning: you configured more USDHC controllers" | ||
| 151 | "(%d) than supported by the board\n", i + 1); | ||
| 152 | return -EINVAL; | ||
| 153 | } | ||
| 154 | |||
| 155 | ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); | ||
| 156 | if (ret) | ||
| 157 | return ret; | ||
| 158 | } | ||
| 159 | |||
| 160 | return 0; | ||
| 161 | } | ||
| 162 | |||
| 163 | #ifdef CONFIG_POWER | ||
| 164 | #define I2C_PMIC 0 | ||
| 165 | int power_init_board(void) | ||
| 166 | { | ||
| 167 | struct pmic *p; | ||
| 168 | int ret; | ||
| 169 | unsigned int reg; | ||
| 170 | |||
| 171 | ret = power_pfuze100_init(I2C_PMIC); | ||
| 172 | if (ret) | ||
| 173 | return -ENODEV; | ||
| 174 | |||
| 175 | p = pmic_get("PFUZE100"); | ||
| 176 | ret = pmic_probe(p); | ||
| 177 | if (ret) | ||
| 178 | return -ENODEV; | ||
| 179 | |||
| 180 | pmic_reg_read(p, PFUZE100_DEVICEID, ®); | ||
| 181 | printf("PMIC: PFUZE100 ID=0x%02x\n", reg); | ||
| 182 | |||
| 183 | pmic_reg_read(p, PFUZE100_SW3AVOL, ®); | ||
| 184 | if ((reg & 0x3f) != 0x18) { | ||
| 185 | reg &= ~0x3f; | ||
| 186 | reg |= 0x18; | ||
| 187 | pmic_reg_write(p, PFUZE100_SW3AVOL, reg); | ||
| 188 | } | ||
| 189 | |||
| 190 | ret = pfuze_mode_init(p, APS_PFM); | ||
| 191 | if (ret < 0) | ||
| 192 | return ret; | ||
| 193 | |||
| 194 | /* set SW3A standby mode to off */ | ||
| 195 | pmic_reg_read(p, PFUZE100_SW3AMODE, ®); | ||
| 196 | reg &= ~0xf; | ||
| 197 | reg |= APS_OFF; | ||
| 198 | pmic_reg_write(p, PFUZE100_SW3AMODE, reg); | ||
| 199 | |||
| 200 | return 0; | ||
| 201 | } | ||
| 202 | #endif | ||
| 203 | |||
| 204 | void spl_board_init(void) | ||
| 205 | { | ||
| 206 | #ifndef CONFIG_SPL_USB_SDP_SUPPORT | ||
| 207 | /* Serial download mode */ | ||
| 208 | if (is_usb_boot()) { | ||
| 209 | puts("Back to ROM, SDP\n"); | ||
| 210 | restore_boot_params(); | ||
| 211 | } | ||
| 212 | #endif | ||
| 213 | |||
| 214 | init_usb_clk(); | ||
| 215 | |||
| 216 | puts("Normal Boot\n"); | ||
| 217 | setup_iomux_reset_out(); | ||
| 218 | } | ||
| 219 | |||
| 220 | #ifdef CONFIG_SPL_LOAD_FIT | ||
| 221 | int board_fit_config_name_match(const char *name) | ||
| 222 | { | ||
| 223 | /* Just empty function now - can't decide what to choose */ | ||
| 224 | debug("%s: %s\n", __func__, name); | ||
| 225 | |||
| 226 | return 0; | ||
| 227 | } | ||
| 228 | #endif | ||
| 229 | |||
| 230 | void board_init_f(ulong dummy) | ||
| 231 | { | ||
| 232 | int ret; | ||
| 233 | |||
| 234 | /* Clear global data */ | ||
| 235 | memset((void *)gd, 0, sizeof(gd_t)); | ||
| 236 | |||
| 237 | arch_cpu_init(); | ||
| 238 | |||
| 239 | #ifdef CONFIG_CONSOLE_SER3 | ||
| 240 | init_uart_clk(0); /* Init UART0 clock */ | ||
| 241 | #endif | ||
| 242 | |||
| 243 | #ifdef CONFIG_CONSOLE_SER2 | ||
| 244 | init_uart_clk(1); /* Init UART1 clock */ | ||
| 245 | #endif | ||
| 246 | |||
| 247 | #ifdef CONFIG_CONSOLE_SER1 | ||
| 248 | init_uart_clk(2); /* Init UART2 clock */ | ||
| 249 | #endif | ||
| 250 | |||
| 251 | #ifdef CONFIG_CONSOLE_SER0 | ||
| 252 | init_uart_clk(3); /* Init UART3 clock */ | ||
| 253 | #endif | ||
| 254 | |||
| 255 | board_early_init_f(); | ||
| 256 | |||
| 257 | timer_init(); | ||
| 258 | |||
| 259 | preloader_console_init(); | ||
| 260 | |||
| 261 | /* Clear the BSS. */ | ||
| 262 | memset(__bss_start, 0, __bss_end - __bss_start); | ||
| 263 | |||
| 264 | ret = spl_init(); | ||
| 265 | if (ret) { | ||
| 266 | debug("spl_init() failed: %d\n", ret); | ||
| 267 | hang(); | ||
| 268 | } | ||
| 269 | |||
| 270 | enable_tzc380(); | ||
| 271 | |||
| 272 | /* Adjust pmic voltage to 1.0V for 800M */ | ||
| 273 | setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x08, &i2c_pad_info1); | ||
| 274 | |||
| 275 | power_init_board(); | ||
| 276 | |||
| 277 | /* DDR initialization */ | ||
| 278 | spl_dram_init(); | ||
| 279 | |||
| 280 | board_init_r(NULL, 0); | ||
| 281 | } | ||
| 282 | 1 | /* |