27 Feb, 2014

6 commits


26 Feb, 2014

21 commits


25 Feb, 2014

10 commits

  • If -fstack-usage option is given to crosstools
    that do not support it, gcc displays a warning message
    but still exits with status 0.

    This means we can not rely on $(call cc-option,...)
    to detect if -fstack-usage option is supported or not.

    Signed-off-by: Masahiro Yamada

    Masahiro Yamada
     
  • Use first four characters for phy_type comparison. Strcmp() should not
    be used to check the phy_type string which maybe parsed by hwconfig_subarg().
    Hwconfig_subarg() returns part of hwconfig string starting from
    phy_type value till the end of the string. Since phy_type could be
    either "utmi" or "ulpi", strncmp() should be used so that a comparison
    of "utmi;fsl_ddr:bank_intlv=auto" with "utmi" will succeed.

    Signed-off-by: Shaohui Xie
    Signed-off-by: Nikhil Badola
    Reviewed-by: York Sun

    Nikhil Badola
     
  • u-boot binary size for Freescale mpc8536DS platforms is 512KB.
    This has been reached to upper limit of the platforms and causig
    linker error. So increase the u-boot binary size to 768KB.

    Signed-off-by: Haijun Zhang
    Reviewed-by: York Sun

    Haijun.Zhang
     
  • Function "genphy_parse_link()" used "if (mii_reg & BMSR_ANEGCAPABLE)" before
    while "if (phydev->supported & SUPPORTED_Autoneg)" now.
    So assign "phydev->supported" to "phydev->drv->features" for ar8031/8033
    to enable autonegotiation.

    Signed-off-by: Zhao Qiang
    Reviewed-by: York Sun

    Zhao Qiang
     
  • In the previous patches, we introduced the SPL/TPL fraamework.
    For SD/SPI flash booting way, we introduce the SPL to enable a loader stub. The
    SPL was loaded by the code from the internal on-chip ROM. The SPL initializes
    the DDR according to the SPD and loads the final uboot image into DDR, then
    jump to the DDR to begin execution.

    For NAND booting way, the nand SPL has size limitation on some board(e.g.
    P1010RDB), it can not be more than 8KB, we can call it "minimal SPL", So the
    dynamic DDR driver doesn't fit into this minimum SPL. We added the TPL that is
    loaded by the the minimal SPL. The TPL initializes the DDR according to the SPD
    and loads the final uboot image into DDR,then jump to the DDR to begin execution.

    This patch enabled SPL/TPL for P1010RDB to support starting from NAND/SD/SPI
    flash with SPL framework and initializing the DDR according to SPD in the SPL/TPL.
    Because the minimal SPL load the TPL to L2 SRAM and the jump to the L2 SRAM to
    execute, so the section .resetvec is no longer needed.

    Signed-off-by: Ying Zhang
    Reviewed-by: York Sun

    Ying Zhang
     
  • There was no enough memory for malloc in SPL booting from spi flash, so
    relayout the memory in SPL: reduce the memory for global data from 16K
    Bytes to 4K Bytes, save the space for malloc.

    Signed-off-by: Ying Zhang
    Reviewed-by: York Sun

    Ying Zhang
     
  • There was no enough stack in SPL, so the buffer needed in SPL is to malloc
    from memory pool and to repalce the temporary variable.

    Signed-off-by: Ying Zhang
    Reviewed-by: York Sun

    Ying Zhang
     
  • 1. The SPL's length of SDCARD boot has not enough,expand the SPL's
    length to 128K.
    2. deleted unused symbol: CONFIG_SYS_RUN_INDDR

    Signed-off-by: Ying Zhang
    Reviewed-by: York Sun

    Ying Zhang
     
  • T2081 QDS is a high-performance computing evaluation, development and
    test platform supporting the T2081 QorIQ Power Architecture processor.

    T2081QDS board Overview
    -----------------------
    - T2081 SoC integrating four 64-bit dual-threads e6500 cores up to 1.8GHz
    - 2MB shared L2 and 512KB L3 CoreNet platform cache (CPC)
    - CoreNet fabric supporting coherent and noncoherent transactions with
    prioritization and bandwidth allocation
    - 32-/64-bit DDR3/DDR3LP SDRAM memory controller with ECC and interleaving
    - Ethernet interfaces:
    - Two on-board 10M/100M/1G bps RGMII ports
    - Two 10Gbps XFI with on-board SFP+ cage
    - 1Gbps/2.5Gbps SGMII Riser card
    - 10Gbps XAUI Riser card
    - Accelerator:
    - DPAA components consist of FMan, BMan, QMan, PME, DCE and SEC
    - SerDes:
    - 8 lanes up to 10.3125GHz
    - Supports SGMII, HiGig, XFI, XAUI and Aurora debug,
    - IFC:
    - 512MB NOR Flash, 2GB NAND Flash, PromJet debug port and Qixis FPGA
    - eSPI:
    - Three SPI flash (16MB N25Q128A + 16MB EN25S64 + 512KB SST25WF040)
    - USB:
    - Two USB2.0 ports with internal PHY (one Type-A + one micro Type mini-AB)
    - PCIe:
    - Four PCI Express controllers (two PCIe 2.0 and two PCIe 3.0 with SR-IOV)
    - eSDHC:
    - Supports various SD/SDHC/SDXC/eMMC devices with adapter cards and
    voltage translators
    - I2C:
    - Four I2C controllers.
    - UART:
    - Dual 4-pins UART serial ports

    Signed-off-by: Shengzhou Liu
    Reviewed-by: York Sun

    Shengzhou Liu
     
  • - fix serdes definition for t2081.
    - fix clock speed for t2081.
    - update ids, as CONFIG_FSL_SATA_V2 is needed only for t2080,
    T2081 has no SATA.

    Signed-off-by: Shengzhou Liu
    Reviewed-by: York Sun

    Shengzhou Liu
     

24 Feb, 2014

3 commits