Eric Lee / smarc-uboot

Download as
Browse Code »

Commit 00b132bf34c5be86a108ac7fe8231ad9e97f6de4

Authored by Łukasz Majewski
Committed by Minkyu Kang
1 parent da0c5748a3
Exists in v2017.01-smarct4x and in 48 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

config:trats2: Change u-boot's TEXT_BASE from 0x78100000 to 0x43e00000 

The u-boot's image TEXT_BASE needs to be changed to 0x43e00000 from 0x78100000.

This change provides compatibility with other trats2 (RD_PQ) devices
(http://download.tizen.org/releases/system/).

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>

Showing 1 changed file with 1 additions and 1 deletions Inline Diff

include/configs/trats2.h
Diff comments   View file @ 00b132b
1 /* 1 /*
2 * Copyright (C) 2013 Samsung Electronics 2 * Copyright (C) 2013 Samsung Electronics
3 * Sanghee Kim <sh0130.kim@samsung.com> 3 * Sanghee Kim <sh0130.kim@samsung.com>
4 * Piotr Wilczek <p.wilczek@samsung.com> 4 * Piotr Wilczek <p.wilczek@samsung.com>
5 * 5 *
6 * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board. 6 * Configuation settings for the SAMSUNG TRATS2 (EXYNOS4412) board.
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0+ 8 * SPDX-License-Identifier: GPL-2.0+
9 */ 9 */
10 10
11 #ifndef __CONFIG_TRATS2_H 11 #ifndef __CONFIG_TRATS2_H
12 #define __CONFIG_TRATS2_H 12 #define __CONFIG_TRATS2_H
13 13
14 #include <configs/exynos4-dt.h> 14 #include <configs/exynos4-dt.h>
15 15
16 #define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */ 16 #define CONFIG_SYS_PROMPT "Trats2 # " /* Monitor Command Prompt */
17 17
18 #undef CONFIG_DEFAULT_DEVICE_TREE 18 #undef CONFIG_DEFAULT_DEVICE_TREE
19 #define CONFIG_DEFAULT_DEVICE_TREE exynos4412-trats2 19 #define CONFIG_DEFAULT_DEVICE_TREE exynos4412-trats2
20 20
21 #define CONFIG_TIZEN /* TIZEN lib */ 21 #define CONFIG_TIZEN /* TIZEN lib */
22 22
23 #define CONFIG_SYS_L2CACHE_OFF 23 #define CONFIG_SYS_L2CACHE_OFF
24 #ifndef CONFIG_SYS_L2CACHE_OFF 24 #ifndef CONFIG_SYS_L2CACHE_OFF
25 #define CONFIG_SYS_L2_PL310 25 #define CONFIG_SYS_L2_PL310
26 #define CONFIG_SYS_PL310_BASE 0x10502000 26 #define CONFIG_SYS_PL310_BASE 0x10502000
27 #endif 27 #endif
28 28
29 /* TRATS2 has 4 banks of DRAM */ 29 /* TRATS2 has 4 banks of DRAM */
30 #define CONFIG_NR_DRAM_BANKS 4 30 #define CONFIG_NR_DRAM_BANKS 4
31 #define CONFIG_SYS_SDRAM_BASE 0x40000000 31 #define CONFIG_SYS_SDRAM_BASE 0x40000000
32 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE 32 #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
33 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ 33 #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
34 /* memtest works on */ 34 /* memtest works on */
35 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE 35 #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
36 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000) 36 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5E00000)
37 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) 37 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000)
38 38
39 #define CONFIG_SYS_TEXT_BASE 0x78100000 39 #define CONFIG_SYS_TEXT_BASE 0x43e00000
40 40
41 #include <linux/sizes.h> 41 #include <linux/sizes.h>
42 /* Size of malloc() pool */ 42 /* Size of malloc() pool */
43 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M)) 43 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (80 * SZ_1M))
44 44
45 /* select serial console configuration */ 45 /* select serial console configuration */
46 #define CONFIG_SERIAL2 46 #define CONFIG_SERIAL2
47 #define CONFIG_BAUDRATE 115200 47 #define CONFIG_BAUDRATE 115200
48 48
49 /* Console configuration */ 49 /* Console configuration */
50 #define CONFIG_SYS_CONSOLE_INFO_QUIET 50 #define CONFIG_SYS_CONSOLE_INFO_QUIET
51 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 51 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
52 52
53 #define CONFIG_BOOTARGS "Please use defined boot" 53 #define CONFIG_BOOTARGS "Please use defined boot"
54 #define CONFIG_BOOTCOMMAND "run mmcboot" 54 #define CONFIG_BOOTCOMMAND "run mmcboot"
55 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0" 55 #define CONFIG_DEFAULT_CONSOLE "console=ttySAC1,115200n8\0"
56 56
57 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ 57 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
58 - GENERATED_GBL_DATA_SIZE) 58 - GENERATED_GBL_DATA_SIZE)
59 59
60 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ 60 #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
61 61
62 #define CONFIG_SYS_MONITOR_BASE 0x00000000 62 #define CONFIG_SYS_MONITOR_BASE 0x00000000
63 63
64 #define CONFIG_ENV_IS_IN_MMC 64 #define CONFIG_ENV_IS_IN_MMC
65 #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV 65 #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
66 #define CONFIG_ENV_SIZE 4096 66 #define CONFIG_ENV_SIZE 4096
67 #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ 67 #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
68 68
69 #define CONFIG_ENV_OVERWRITE 69 #define CONFIG_ENV_OVERWRITE
70 70
71 #define CONFIG_ENV_VARS_UBOOT_CONFIG 71 #define CONFIG_ENV_VARS_UBOOT_CONFIG
72 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG 72 #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
73 73
74 /* Tizen - partitions definitions */ 74 /* Tizen - partitions definitions */
75 #define PARTS_CSA "csa-mmc" 75 #define PARTS_CSA "csa-mmc"
76 #define PARTS_BOOT "boot" 76 #define PARTS_BOOT "boot"
77 #define PARTS_QBOOT "qboot" 77 #define PARTS_QBOOT "qboot"
78 #define PARTS_CSC "csc" 78 #define PARTS_CSC "csc"
79 #define PARTS_ROOT "platform" 79 #define PARTS_ROOT "platform"
80 #define PARTS_DATA "data" 80 #define PARTS_DATA "data"
81 #define PARTS_UMS "ums" 81 #define PARTS_UMS "ums"
82 82
83 #define PARTS_DEFAULT \ 83 #define PARTS_DEFAULT \
84 "uuid_disk=${uuid_gpt_disk};" \ 84 "uuid_disk=${uuid_gpt_disk};" \
85 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ 85 "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
86 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ 86 "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
87 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ 87 "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
88 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ 88 "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
89 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ 89 "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
90 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ 90 "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
91 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ 91 "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
92 92
93 #define CONFIG_DFU_ALT \ 93 #define CONFIG_DFU_ALT \
94 "u-boot mmc 80 800;" \ 94 "u-boot mmc 80 800;" \
95 "uImage ext4 0 2;" \ 95 "uImage ext4 0 2;" \
96 "modem.bin ext4 0 2;" \ 96 "modem.bin ext4 0 2;" \
97 "exynos4412-trats2.dtb ext4 0 2;" \ 97 "exynos4412-trats2.dtb ext4 0 2;" \
98 ""PARTS_CSA" part 0 1;" \ 98 ""PARTS_CSA" part 0 1;" \
99 ""PARTS_BOOT" part 0 2;" \ 99 ""PARTS_BOOT" part 0 2;" \
100 ""PARTS_QBOOT" part 0 3;" \ 100 ""PARTS_QBOOT" part 0 3;" \
101 ""PARTS_CSC" part 0 4;" \ 101 ""PARTS_CSC" part 0 4;" \
102 ""PARTS_ROOT" part 0 5;" \ 102 ""PARTS_ROOT" part 0 5;" \
103 ""PARTS_DATA" part 0 6;" \ 103 ""PARTS_DATA" part 0 6;" \
104 ""PARTS_UMS" part 0 7;" \ 104 ""PARTS_UMS" part 0 7;" \
105 "params.bin mmc 0x38 0x8\0" 105 "params.bin mmc 0x38 0x8\0"
106 106
107 #define CONFIG_EXTRA_ENV_SETTINGS \ 107 #define CONFIG_EXTRA_ENV_SETTINGS \
108 "bootk=" \ 108 "bootk=" \
109 "run loaduimage;" \ 109 "run loaduimage;" \
110 "if run loaddtb; then " \ 110 "if run loaddtb; then " \
111 "bootm 0x40007FC0 - ${fdtaddr};" \ 111 "bootm 0x40007FC0 - ${fdtaddr};" \
112 "fi;" \ 112 "fi;" \
113 "bootm 0x40007FC0;\0" \ 113 "bootm 0x40007FC0;\0" \
114 "updatemmc=" \ 114 "updatemmc=" \
115 "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \ 115 "mmc boot 0 1 1 1; mmc write 0x42008000 0 0x200;" \
116 "mmc boot 0 1 1 0\0" \ 116 "mmc boot 0 1 1 0\0" \
117 "updatebackup=" \ 117 "updatebackup=" \
118 "mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \ 118 "mmc boot 0 1 1 2; mmc write 0x42100000 0 0x200;" \
119 " mmc boot 0 1 1 0\0" \ 119 " mmc boot 0 1 1 0\0" \
120 "updatebootb=" \ 120 "updatebootb=" \
121 "mmc read 0x51000000 0x80 0x200; run updatebackup\0" \ 121 "mmc read 0x51000000 0x80 0x200; run updatebackup\0" \
122 "updateuboot=" \ 122 "updateuboot=" \
123 "mmc write 0x50000000 0x80 0x400\0" \ 123 "mmc write 0x50000000 0x80 0x400\0" \
124 "mmcboot=" \ 124 "mmcboot=" \
125 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 125 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
126 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ 126 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
127 "run bootk\0" \ 127 "run bootk\0" \
128 "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \ 128 "bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
129 "boottrace=setenv opts initcall_debug; run bootcmd\0" \ 129 "boottrace=setenv opts initcall_debug; run bootcmd\0" \
130 "verify=n\0" \ 130 "verify=n\0" \
131 "rootfstype=ext4\0" \ 131 "rootfstype=ext4\0" \
132 "console=" CONFIG_DEFAULT_CONSOLE \ 132 "console=" CONFIG_DEFAULT_CONSOLE \
133 "kernelname=uImage\0" \ 133 "kernelname=uImage\0" \
134 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \ 134 "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 " \
135 "${kernelname}\0" \ 135 "${kernelname}\0" \
136 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ 136 "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
137 "${fdtfile}\0" \ 137 "${fdtfile}\0" \
138 "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \ 138 "mmcdev=" __stringify(CONFIG_MMC_DEFAULT_DEV) "\0" \
139 "mmcbootpart=2\0" \ 139 "mmcbootpart=2\0" \
140 "mmcrootpart=5\0" \ 140 "mmcrootpart=5\0" \
141 "opts=always_resume=1\0" \ 141 "opts=always_resume=1\0" \
142 "partitions=" PARTS_DEFAULT \ 142 "partitions=" PARTS_DEFAULT \
143 "dfu_alt_info=" CONFIG_DFU_ALT \ 143 "dfu_alt_info=" CONFIG_DFU_ALT \
144 "uartpath=ap\0" \ 144 "uartpath=ap\0" \
145 "usbpath=ap\0" \ 145 "usbpath=ap\0" \
146 "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \ 146 "consoleon=set console console=ttySAC2,115200n8; save; reset\0" \
147 "consoleoff=set console console=ram; save; reset\0" \ 147 "consoleoff=set console console=ram; save; reset\0" \
148 "spladdr=0x40000100\0" \ 148 "spladdr=0x40000100\0" \
149 "splsize=0x200\0" \ 149 "splsize=0x200\0" \
150 "splfile=falcon.bin\0" \ 150 "splfile=falcon.bin\0" \
151 "spl_export=" \ 151 "spl_export=" \
152 "setexpr spl_imgsize ${splsize} + 8 ;" \ 152 "setexpr spl_imgsize ${splsize} + 8 ;" \
153 "setenv spl_imgsize 0x${spl_imgsize};" \ 153 "setenv spl_imgsize 0x${spl_imgsize};" \
154 "setexpr spl_imgaddr ${spladdr} - 8 ;" \ 154 "setexpr spl_imgaddr ${spladdr} - 8 ;" \
155 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ 155 "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
156 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ 156 "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
157 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ 157 "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
158 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ 158 "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
159 "spl export atags 0x40007FC0;" \ 159 "spl export atags 0x40007FC0;" \
160 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ 160 "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
161 "mw.l ${spl_addr_tmp} ${splsize};" \ 161 "mw.l ${spl_addr_tmp} ${splsize};" \
162 "ext4write mmc ${mmcdev}:${mmcbootpart}" \ 162 "ext4write mmc ${mmcdev}:${mmcbootpart}" \
163 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ 163 " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
164 "setenv spl_imgsize;" \ 164 "setenv spl_imgsize;" \
165 "setenv spl_imgaddr;" \ 165 "setenv spl_imgaddr;" \
166 "setenv spl_addr_tmp;\0" \ 166 "setenv spl_addr_tmp;\0" \
167 "fdtaddr=40800000\0" \ 167 "fdtaddr=40800000\0" \
168 168
169 /* I2C */ 169 /* I2C */
170 #include <asm/arch/gpio.h> 170 #include <asm/arch/gpio.h>
171 171
172 #define CONFIG_CMD_I2C 172 #define CONFIG_CMD_I2C
173 173
174 #define CONFIG_SYS_I2C 174 #define CONFIG_SYS_I2C
175 #define CONFIG_SYS_I2C_S3C24X0 175 #define CONFIG_SYS_I2C_S3C24X0
176 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 176 #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
177 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0 177 #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0
178 #define CONFIG_MAX_I2C_NUM 8 178 #define CONFIG_MAX_I2C_NUM 8
179 #define CONFIG_SYS_I2C_SOFT 179 #define CONFIG_SYS_I2C_SOFT
180 #define CONFIG_SYS_I2C_SOFT_SPEED 50000 180 #define CONFIG_SYS_I2C_SOFT_SPEED 50000
181 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00 181 #define CONFIG_SYS_I2C_SOFT_SLAVE 0x00
182 #define I2C_SOFT_DECLARATIONS2 182 #define I2C_SOFT_DECLARATIONS2
183 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000 183 #define CONFIG_SYS_I2C_SOFT_SPEED_2 50000
184 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00 184 #define CONFIG_SYS_I2C_SOFT_SLAVE_2 0x00
185 #define CONFIG_SOFT_I2C_READ_REPEATED_START 185 #define CONFIG_SOFT_I2C_READ_REPEATED_START
186 #define CONFIG_SYS_I2C_INIT_BOARD 186 #define CONFIG_SYS_I2C_INIT_BOARD
187 187
188 #ifndef __ASSEMBLY__ 188 #ifndef __ASSEMBLY__
189 int get_soft_i2c_scl_pin(void); 189 int get_soft_i2c_scl_pin(void);
190 int get_soft_i2c_sda_pin(void); 190 int get_soft_i2c_sda_pin(void);
191 #endif 191 #endif
192 #define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin() 192 #define CONFIG_SOFT_I2C_GPIO_SCL get_soft_i2c_scl_pin()
193 #define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin() 193 #define CONFIG_SOFT_I2C_GPIO_SDA get_soft_i2c_sda_pin()
194 194
195 /* POWER */ 195 /* POWER */
196 #define CONFIG_POWER 196 #define CONFIG_POWER
197 #define CONFIG_POWER_I2C 197 #define CONFIG_POWER_I2C
198 #define CONFIG_POWER_MAX77686 198 #define CONFIG_POWER_MAX77686
199 #define CONFIG_POWER_PMIC_MAX77693 199 #define CONFIG_POWER_PMIC_MAX77693
200 #define CONFIG_POWER_MUIC_MAX77693 200 #define CONFIG_POWER_MUIC_MAX77693
201 #define CONFIG_POWER_FG_MAX77693 201 #define CONFIG_POWER_FG_MAX77693
202 #define CONFIG_POWER_BATTERY_TRATS2 202 #define CONFIG_POWER_BATTERY_TRATS2
203 203
204 /* Common misc for Samsung */ 204 /* Common misc for Samsung */
205 #define CONFIG_MISC_COMMON 205 #define CONFIG_MISC_COMMON
206 206
207 #define CONFIG_MISC_INIT_R 207 #define CONFIG_MISC_INIT_R
208 208
209 /* Download menu - Samsung common */ 209 /* Download menu - Samsung common */
210 #define CONFIG_LCD_MENU 210 #define CONFIG_LCD_MENU
211 #define CONFIG_LCD_MENU_BOARD 211 #define CONFIG_LCD_MENU_BOARD
212 212
213 /* Download menu - definitions for check keys */ 213 /* Download menu - definitions for check keys */
214 #ifndef __ASSEMBLY__ 214 #ifndef __ASSEMBLY__
215 #include <power/max77686_pmic.h> 215 #include <power/max77686_pmic.h>
216 216
217 #define KEY_PWR_PMIC_NAME "MAX77686_PMIC" 217 #define KEY_PWR_PMIC_NAME "MAX77686_PMIC"
218 #define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1 218 #define KEY_PWR_STATUS_REG MAX77686_REG_PMIC_STATUS1
219 #define KEY_PWR_STATUS_MASK (1 << 0) 219 #define KEY_PWR_STATUS_MASK (1 << 0)
220 #define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1 220 #define KEY_PWR_INTERRUPT_REG MAX77686_REG_PMIC_INT1
221 #define KEY_PWR_INTERRUPT_MASK (1 << 1) 221 #define KEY_PWR_INTERRUPT_MASK (1 << 1)
222 222
223 #define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2) 223 #define KEY_VOL_UP_GPIO exynos4x12_gpio_get(2, x2, 2)
224 #define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3) 224 #define KEY_VOL_DOWN_GPIO exynos4x12_gpio_get(2, x3, 3)
225 #endif /* __ASSEMBLY__ */ 225 #endif /* __ASSEMBLY__ */
226 226
227 /* LCD console */ 227 /* LCD console */
228 #define LCD_BPP LCD_COLOR16 228 #define LCD_BPP LCD_COLOR16
229 #define CONFIG_SYS_WHITE_ON_BLACK 229 #define CONFIG_SYS_WHITE_ON_BLACK
230 230
231 /* LCD */ 231 /* LCD */
232 #define CONFIG_EXYNOS_FB 232 #define CONFIG_EXYNOS_FB
233 #define CONFIG_LCD 233 #define CONFIG_LCD
234 #define CONFIG_CMD_BMP 234 #define CONFIG_CMD_BMP
235 #define CONFIG_BMP_16BPP 235 #define CONFIG_BMP_16BPP
236 #define CONFIG_FB_ADDR 0x52504000 236 #define CONFIG_FB_ADDR 0x52504000
237 #define CONFIG_S6E8AX0 237 #define CONFIG_S6E8AX0
238 #define CONFIG_EXYNOS_MIPI_DSIM 238 #define CONFIG_EXYNOS_MIPI_DSIM
239 #define CONFIG_VIDEO_BMP_GZIP 239 #define CONFIG_VIDEO_BMP_GZIP
240 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) 240 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
241 241
242 #define LCD_XRES 720 242 #define LCD_XRES 720
243 #define LCD_YRES 1280 243 #define LCD_YRES 1280
244 244
245 #endif /* __CONFIG_H */ 245 #endif /* __CONFIG_H */
246 246