Eric Lee / smarc-uboot

Download as
Browse Code ยป

Commit 042b83d4c502d17db40f1fa4f6d9b6cb86c653d2

Authored by Thierry Reding
Committed by Tom Rini
1 parent 1eebd14b79
Exists in v2017.01-smarct4x and in 37 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc

pci: Abort early if bus does not exist 

When listing the devices on a PCI bus, the current code will blindly try
to access all devices. Internally this causes pci_bus_to_hose() to be
repeatedly called and output an error message every time. Prevent this
by calling pci_bus_to_hose() once and abort early if no bus was found.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>

Showing 1 changed file with 4 additions and 0 deletions Inline Diff

1 /* 1 /*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> 2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de> 3 * Andreas Heppel <aheppel@sysgo.de>
4 * 4 *
5 * (C) Copyright 2002 5 * (C) Copyright 2002
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de. 7 * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
8 * 8 *
9 * SPDX-License-Identifier: GPL-2.0+ 9 * SPDX-License-Identifier: GPL-2.0+
10 */ 10 */
11 11
12 /* 12 /*
13 * PCI routines 13 * PCI routines
14 */ 14 */
15 15
16 #include <common.h> 16 #include <common.h>
17 #include <bootretry.h> 17 #include <bootretry.h>
18 #include <cli.h> 18 #include <cli.h>
19 #include <command.h> 19 #include <command.h>
20 #include <asm/processor.h> 20 #include <asm/processor.h>
21 #include <asm/io.h> 21 #include <asm/io.h>
22 #include <pci.h> 22 #include <pci.h>
23 23
24 /* 24 /*
25 * Follows routines for the output of infos about devices on PCI bus. 25 * Follows routines for the output of infos about devices on PCI bus.
26 */ 26 */
27 27
28 void pci_header_show(pci_dev_t dev); 28 void pci_header_show(pci_dev_t dev);
29 void pci_header_show_brief(pci_dev_t dev); 29 void pci_header_show_brief(pci_dev_t dev);
30 30
31 /* 31 /*
32 * Subroutine: pciinfo 32 * Subroutine: pciinfo
33 * 33 *
34 * Description: Show information about devices on PCI bus. 34 * Description: Show information about devices on PCI bus.
35 * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING 35 * Depending on the define CONFIG_SYS_SHORT_PCI_LISTING
36 * the output will be more or less exhaustive. 36 * the output will be more or less exhaustive.
37 * 37 *
38 * Inputs: bus_no the number of the bus to be scanned. 38 * Inputs: bus_no the number of the bus to be scanned.
39 * 39 *
40 * Return: None 40 * Return: None
41 * 41 *
42 */ 42 */
43 void pciinfo(int BusNum, int ShortPCIListing) 43 void pciinfo(int BusNum, int ShortPCIListing)
44 { 44 {
45 struct pci_controller *hose = pci_bus_to_hose(BusNum);
45 int Device; 46 int Device;
46 int Function; 47 int Function;
47 unsigned char HeaderType; 48 unsigned char HeaderType;
48 unsigned short VendorID; 49 unsigned short VendorID;
49 pci_dev_t dev; 50 pci_dev_t dev;
51
52 if (!hose)
53 return;
50 54
51 printf("Scanning PCI devices on bus %d\n", BusNum); 55 printf("Scanning PCI devices on bus %d\n", BusNum);
52 56
53 if (ShortPCIListing) { 57 if (ShortPCIListing) {
54 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n"); 58 printf("BusDevFun VendorId DeviceId Device Class Sub-Class\n");
55 printf("_____________________________________________________________\n"); 59 printf("_____________________________________________________________\n");
56 } 60 }
57 61
58 for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) { 62 for (Device = 0; Device < PCI_MAX_PCI_DEVICES; Device++) {
59 HeaderType = 0; 63 HeaderType = 0;
60 VendorID = 0; 64 VendorID = 0;
61 for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) { 65 for (Function = 0; Function < PCI_MAX_PCI_FUNCTIONS; Function++) {
62 /* 66 /*
63 * If this is not a multi-function device, we skip the rest. 67 * If this is not a multi-function device, we skip the rest.
64 */ 68 */
65 if (Function && !(HeaderType & 0x80)) 69 if (Function && !(HeaderType & 0x80))
66 break; 70 break;
67 71
68 dev = PCI_BDF(BusNum, Device, Function); 72 dev = PCI_BDF(BusNum, Device, Function);
69 73
70 pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID); 74 pci_read_config_word(dev, PCI_VENDOR_ID, &VendorID);
71 if ((VendorID == 0xFFFF) || (VendorID == 0x0000)) 75 if ((VendorID == 0xFFFF) || (VendorID == 0x0000))
72 continue; 76 continue;
73 77
74 if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType); 78 if (!Function) pci_read_config_byte(dev, PCI_HEADER_TYPE, &HeaderType);
75 79
76 if (ShortPCIListing) 80 if (ShortPCIListing)
77 { 81 {
78 printf("%02x.%02x.%02x ", BusNum, Device, Function); 82 printf("%02x.%02x.%02x ", BusNum, Device, Function);
79 pci_header_show_brief(dev); 83 pci_header_show_brief(dev);
80 } 84 }
81 else 85 else
82 { 86 {
83 printf("\nFound PCI device %02x.%02x.%02x:\n", 87 printf("\nFound PCI device %02x.%02x.%02x:\n",
84 BusNum, Device, Function); 88 BusNum, Device, Function);
85 pci_header_show(dev); 89 pci_header_show(dev);
86 } 90 }
87 } 91 }
88 } 92 }
89 } 93 }
90 94
91 95
92 /* 96 /*
93 * Subroutine: pci_header_show_brief 97 * Subroutine: pci_header_show_brief
94 * 98 *
95 * Description: Reads and prints the header of the 99 * Description: Reads and prints the header of the
96 * specified PCI device in short form. 100 * specified PCI device in short form.
97 * 101 *
98 * Inputs: dev Bus+Device+Function number 102 * Inputs: dev Bus+Device+Function number
99 * 103 *
100 * Return: None 104 * Return: None
101 * 105 *
102 */ 106 */
103 void pci_header_show_brief(pci_dev_t dev) 107 void pci_header_show_brief(pci_dev_t dev)
104 { 108 {
105 u16 vendor, device; 109 u16 vendor, device;
106 u8 class, subclass; 110 u8 class, subclass;
107 111
108 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor); 112 pci_read_config_word(dev, PCI_VENDOR_ID, &vendor);
109 pci_read_config_word(dev, PCI_DEVICE_ID, &device); 113 pci_read_config_word(dev, PCI_DEVICE_ID, &device);
110 pci_read_config_byte(dev, PCI_CLASS_CODE, &class); 114 pci_read_config_byte(dev, PCI_CLASS_CODE, &class);
111 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass); 115 pci_read_config_byte(dev, PCI_CLASS_SUB_CODE, &subclass);
112 116
113 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n", 117 printf("0x%.4x 0x%.4x %-23s 0x%.2x\n",
114 vendor, device, 118 vendor, device,
115 pci_class_str(class), subclass); 119 pci_class_str(class), subclass);
116 } 120 }
117 121
118 /* 122 /*
119 * Subroutine: PCI_Header_Show 123 * Subroutine: PCI_Header_Show
120 * 124 *
121 * Description: Reads the header of the specified PCI device. 125 * Description: Reads the header of the specified PCI device.
122 * 126 *
123 * Inputs: BusDevFunc Bus+Device+Function number 127 * Inputs: BusDevFunc Bus+Device+Function number
124 * 128 *
125 * Return: None 129 * Return: None
126 * 130 *
127 */ 131 */
128 void pci_header_show(pci_dev_t dev) 132 void pci_header_show(pci_dev_t dev)
129 { 133 {
130 u8 _byte, header_type; 134 u8 _byte, header_type;
131 u16 _word; 135 u16 _word;
132 u32 _dword; 136 u32 _dword;
133 137
134 #define PRINT(msg, type, reg) \ 138 #define PRINT(msg, type, reg) \
135 pci_read_config_##type(dev, reg, &_##type); \ 139 pci_read_config_##type(dev, reg, &_##type); \
136 printf(msg, _##type) 140 printf(msg, _##type)
137 141
138 #define PRINT2(msg, type, reg, func) \ 142 #define PRINT2(msg, type, reg, func) \
139 pci_read_config_##type(dev, reg, &_##type); \ 143 pci_read_config_##type(dev, reg, &_##type); \
140 printf(msg, _##type, func(_##type)) 144 printf(msg, _##type, func(_##type))
141 145
142 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type); 146 pci_read_config_byte(dev, PCI_HEADER_TYPE, &header_type);
143 147
144 PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID); 148 PRINT (" vendor ID = 0x%.4x\n", word, PCI_VENDOR_ID);
145 PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID); 149 PRINT (" device ID = 0x%.4x\n", word, PCI_DEVICE_ID);
146 PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND); 150 PRINT (" command register = 0x%.4x\n", word, PCI_COMMAND);
147 PRINT (" status register = 0x%.4x\n", word, PCI_STATUS); 151 PRINT (" status register = 0x%.4x\n", word, PCI_STATUS);
148 PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID); 152 PRINT (" revision ID = 0x%.2x\n", byte, PCI_REVISION_ID);
149 PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE, 153 PRINT2(" class code = 0x%.2x (%s)\n", byte, PCI_CLASS_CODE,
150 pci_class_str); 154 pci_class_str);
151 PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE); 155 PRINT (" sub class code = 0x%.2x\n", byte, PCI_CLASS_SUB_CODE);
152 PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG); 156 PRINT (" programming interface = 0x%.2x\n", byte, PCI_CLASS_PROG);
153 PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE); 157 PRINT (" cache line = 0x%.2x\n", byte, PCI_CACHE_LINE_SIZE);
154 PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER); 158 PRINT (" latency time = 0x%.2x\n", byte, PCI_LATENCY_TIMER);
155 PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE); 159 PRINT (" header type = 0x%.2x\n", byte, PCI_HEADER_TYPE);
156 PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST); 160 PRINT (" BIST = 0x%.2x\n", byte, PCI_BIST);
157 PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0); 161 PRINT (" base address 0 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_0);
158 162
159 switch (header_type & 0x03) { 163 switch (header_type & 0x03) {
160 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */ 164 case PCI_HEADER_TYPE_NORMAL: /* "normal" PCI device */
161 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); 165 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
162 PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2); 166 PRINT (" base address 2 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_2);
163 PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3); 167 PRINT (" base address 3 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_3);
164 PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4); 168 PRINT (" base address 4 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_4);
165 PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5); 169 PRINT (" base address 5 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_5);
166 PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS); 170 PRINT (" cardBus CIS pointer = 0x%.8x\n", dword, PCI_CARDBUS_CIS);
167 PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID); 171 PRINT (" sub system vendor ID = 0x%.4x\n", word, PCI_SUBSYSTEM_VENDOR_ID);
168 PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID); 172 PRINT (" sub system ID = 0x%.4x\n", word, PCI_SUBSYSTEM_ID);
169 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS); 173 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS);
170 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); 174 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
171 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); 175 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
172 PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT); 176 PRINT (" min Grant = 0x%.2x\n", byte, PCI_MIN_GNT);
173 PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT); 177 PRINT (" max Latency = 0x%.2x\n", byte, PCI_MAX_LAT);
174 break; 178 break;
175 179
176 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */ 180 case PCI_HEADER_TYPE_BRIDGE: /* PCI-to-PCI bridge */
177 181
178 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1); 182 PRINT (" base address 1 = 0x%.8x\n", dword, PCI_BASE_ADDRESS_1);
179 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS); 183 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_PRIMARY_BUS);
180 PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS); 184 PRINT (" secondary bus number = 0x%.2x\n", byte, PCI_SECONDARY_BUS);
181 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS); 185 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_SUBORDINATE_BUS);
182 PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER); 186 PRINT (" secondary latency timer = 0x%.2x\n", byte, PCI_SEC_LATENCY_TIMER);
183 PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE); 187 PRINT (" IO base = 0x%.2x\n", byte, PCI_IO_BASE);
184 PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT); 188 PRINT (" IO limit = 0x%.2x\n", byte, PCI_IO_LIMIT);
185 PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS); 189 PRINT (" secondary status = 0x%.4x\n", word, PCI_SEC_STATUS);
186 PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE); 190 PRINT (" memory base = 0x%.4x\n", word, PCI_MEMORY_BASE);
187 PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT); 191 PRINT (" memory limit = 0x%.4x\n", word, PCI_MEMORY_LIMIT);
188 PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE); 192 PRINT (" prefetch memory base = 0x%.4x\n", word, PCI_PREF_MEMORY_BASE);
189 PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT); 193 PRINT (" prefetch memory limit = 0x%.4x\n", word, PCI_PREF_MEMORY_LIMIT);
190 PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32); 194 PRINT (" prefetch memory base upper = 0x%.8x\n", dword, PCI_PREF_BASE_UPPER32);
191 PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32); 195 PRINT (" prefetch memory limit upper = 0x%.8x\n", dword, PCI_PREF_LIMIT_UPPER32);
192 PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16); 196 PRINT (" IO base upper 16 bits = 0x%.4x\n", word, PCI_IO_BASE_UPPER16);
193 PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16); 197 PRINT (" IO limit upper 16 bits = 0x%.4x\n", word, PCI_IO_LIMIT_UPPER16);
194 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1); 198 PRINT (" expansion ROM base address = 0x%.8x\n", dword, PCI_ROM_ADDRESS1);
195 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); 199 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
196 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); 200 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
197 PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL); 201 PRINT (" bridge control = 0x%.4x\n", word, PCI_BRIDGE_CONTROL);
198 break; 202 break;
199 203
200 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */ 204 case PCI_HEADER_TYPE_CARDBUS: /* PCI-to-CardBus bridge */
201 205
202 PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST); 206 PRINT (" capabilities = 0x%.2x\n", byte, PCI_CB_CAPABILITY_LIST);
203 PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS); 207 PRINT (" secondary status = 0x%.4x\n", word, PCI_CB_SEC_STATUS);
204 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS); 208 PRINT (" primary bus number = 0x%.2x\n", byte, PCI_CB_PRIMARY_BUS);
205 PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS); 209 PRINT (" CardBus number = 0x%.2x\n", byte, PCI_CB_CARD_BUS);
206 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS); 210 PRINT (" subordinate bus number = 0x%.2x\n", byte, PCI_CB_SUBORDINATE_BUS);
207 PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER); 211 PRINT (" CardBus latency timer = 0x%.2x\n", byte, PCI_CB_LATENCY_TIMER);
208 PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0); 212 PRINT (" CardBus memory base 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_0);
209 PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0); 213 PRINT (" CardBus memory limit 0 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_0);
210 PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1); 214 PRINT (" CardBus memory base 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_BASE_1);
211 PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1); 215 PRINT (" CardBus memory limit 1 = 0x%.8x\n", dword, PCI_CB_MEMORY_LIMIT_1);
212 PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0); 216 PRINT (" CardBus IO base 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0);
213 PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI); 217 PRINT (" CardBus IO base high 0 = 0x%.4x\n", word, PCI_CB_IO_BASE_0_HI);
214 PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0); 218 PRINT (" CardBus IO limit 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0);
215 PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI); 219 PRINT (" CardBus IO limit high 0 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_0_HI);
216 PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1); 220 PRINT (" CardBus IO base 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1);
217 PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI); 221 PRINT (" CardBus IO base high 1 = 0x%.4x\n", word, PCI_CB_IO_BASE_1_HI);
218 PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1); 222 PRINT (" CardBus IO limit 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1);
219 PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI); 223 PRINT (" CardBus IO limit high 1 = 0x%.4x\n", word, PCI_CB_IO_LIMIT_1_HI);
220 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE); 224 PRINT (" interrupt line = 0x%.2x\n", byte, PCI_INTERRUPT_LINE);
221 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN); 225 PRINT (" interrupt pin = 0x%.2x\n", byte, PCI_INTERRUPT_PIN);
222 PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL); 226 PRINT (" bridge control = 0x%.4x\n", word, PCI_CB_BRIDGE_CONTROL);
223 PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID); 227 PRINT (" subvendor ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_VENDOR_ID);
224 PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID); 228 PRINT (" subdevice ID = 0x%.4x\n", word, PCI_CB_SUBSYSTEM_ID);
225 PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE); 229 PRINT (" PC Card 16bit base address = 0x%.8x\n", dword, PCI_CB_LEGACY_MODE_BASE);
226 break; 230 break;
227 231
228 default: 232 default:
229 printf("unknown header\n"); 233 printf("unknown header\n");
230 break; 234 break;
231 } 235 }
232 236
233 #undef PRINT 237 #undef PRINT
234 #undef PRINT2 238 #undef PRINT2
235 } 239 }
236 240
237 /* Convert the "bus.device.function" identifier into a number. 241 /* Convert the "bus.device.function" identifier into a number.
238 */ 242 */
239 static pci_dev_t get_pci_dev(char* name) 243 static pci_dev_t get_pci_dev(char* name)
240 { 244 {
241 char cnum[12]; 245 char cnum[12];
242 int len, i, iold, n; 246 int len, i, iold, n;
243 int bdfs[3] = {0,0,0}; 247 int bdfs[3] = {0,0,0};
244 248
245 len = strlen(name); 249 len = strlen(name);
246 if (len > 8) 250 if (len > 8)
247 return -1; 251 return -1;
248 for (i = 0, iold = 0, n = 0; i < len; i++) { 252 for (i = 0, iold = 0, n = 0; i < len; i++) {
249 if (name[i] == '.') { 253 if (name[i] == '.') {
250 memcpy(cnum, &name[iold], i - iold); 254 memcpy(cnum, &name[iold], i - iold);
251 cnum[i - iold] = '\0'; 255 cnum[i - iold] = '\0';
252 bdfs[n++] = simple_strtoul(cnum, NULL, 16); 256 bdfs[n++] = simple_strtoul(cnum, NULL, 16);
253 iold = i + 1; 257 iold = i + 1;
254 } 258 }
255 } 259 }
256 strcpy(cnum, &name[iold]); 260 strcpy(cnum, &name[iold]);
257 if (n == 0) 261 if (n == 0)
258 n = 1; 262 n = 1;
259 bdfs[n] = simple_strtoul(cnum, NULL, 16); 263 bdfs[n] = simple_strtoul(cnum, NULL, 16);
260 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]); 264 return PCI_BDF(bdfs[0], bdfs[1], bdfs[2]);
261 } 265 }
262 266
263 static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length) 267 static int pci_cfg_display(pci_dev_t bdf, ulong addr, ulong size, ulong length)
264 { 268 {
265 #define DISP_LINE_LEN 16 269 #define DISP_LINE_LEN 16
266 ulong i, nbytes, linebytes; 270 ulong i, nbytes, linebytes;
267 int rc = 0; 271 int rc = 0;
268 272
269 if (length == 0) 273 if (length == 0)
270 length = 0x40 / size; /* Standard PCI configuration space */ 274 length = 0x40 / size; /* Standard PCI configuration space */
271 275
272 /* Print the lines. 276 /* Print the lines.
273 * once, and all accesses are with the specified bus width. 277 * once, and all accesses are with the specified bus width.
274 */ 278 */
275 nbytes = length * size; 279 nbytes = length * size;
276 do { 280 do {
277 uint val4; 281 uint val4;
278 ushort val2; 282 ushort val2;
279 u_char val1; 283 u_char val1;
280 284
281 printf("%08lx:", addr); 285 printf("%08lx:", addr);
282 linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes; 286 linebytes = (nbytes>DISP_LINE_LEN)?DISP_LINE_LEN:nbytes;
283 for (i=0; i<linebytes; i+= size) { 287 for (i=0; i<linebytes; i+= size) {
284 if (size == 4) { 288 if (size == 4) {
285 pci_read_config_dword(bdf, addr, &val4); 289 pci_read_config_dword(bdf, addr, &val4);
286 printf(" %08x", val4); 290 printf(" %08x", val4);
287 } else if (size == 2) { 291 } else if (size == 2) {
288 pci_read_config_word(bdf, addr, &val2); 292 pci_read_config_word(bdf, addr, &val2);
289 printf(" %04x", val2); 293 printf(" %04x", val2);
290 } else { 294 } else {
291 pci_read_config_byte(bdf, addr, &val1); 295 pci_read_config_byte(bdf, addr, &val1);
292 printf(" %02x", val1); 296 printf(" %02x", val1);
293 } 297 }
294 addr += size; 298 addr += size;
295 } 299 }
296 printf("\n"); 300 printf("\n");
297 nbytes -= linebytes; 301 nbytes -= linebytes;
298 if (ctrlc()) { 302 if (ctrlc()) {
299 rc = 1; 303 rc = 1;
300 break; 304 break;
301 } 305 }
302 } while (nbytes > 0); 306 } while (nbytes > 0);
303 307
304 return (rc); 308 return (rc);
305 } 309 }
306 310
307 static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value) 311 static int pci_cfg_write (pci_dev_t bdf, ulong addr, ulong size, ulong value)
308 { 312 {
309 if (size == 4) { 313 if (size == 4) {
310 pci_write_config_dword(bdf, addr, value); 314 pci_write_config_dword(bdf, addr, value);
311 } 315 }
312 else if (size == 2) { 316 else if (size == 2) {
313 ushort val = value & 0xffff; 317 ushort val = value & 0xffff;
314 pci_write_config_word(bdf, addr, val); 318 pci_write_config_word(bdf, addr, val);
315 } 319 }
316 else { 320 else {
317 u_char val = value & 0xff; 321 u_char val = value & 0xff;
318 pci_write_config_byte(bdf, addr, val); 322 pci_write_config_byte(bdf, addr, val);
319 } 323 }
320 return 0; 324 return 0;
321 } 325 }
322 326
323 static int 327 static int
324 pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag) 328 pci_cfg_modify (pci_dev_t bdf, ulong addr, ulong size, ulong value, int incrflag)
325 { 329 {
326 ulong i; 330 ulong i;
327 int nbytes; 331 int nbytes;
328 uint val4; 332 uint val4;
329 ushort val2; 333 ushort val2;
330 u_char val1; 334 u_char val1;
331 335
332 /* Print the address, followed by value. Then accept input for 336 /* Print the address, followed by value. Then accept input for
333 * the next value. A non-converted value exits. 337 * the next value. A non-converted value exits.
334 */ 338 */
335 do { 339 do {
336 printf("%08lx:", addr); 340 printf("%08lx:", addr);
337 if (size == 4) { 341 if (size == 4) {
338 pci_read_config_dword(bdf, addr, &val4); 342 pci_read_config_dword(bdf, addr, &val4);
339 printf(" %08x", val4); 343 printf(" %08x", val4);
340 } 344 }
341 else if (size == 2) { 345 else if (size == 2) {
342 pci_read_config_word(bdf, addr, &val2); 346 pci_read_config_word(bdf, addr, &val2);
343 printf(" %04x", val2); 347 printf(" %04x", val2);
344 } 348 }
345 else { 349 else {
346 pci_read_config_byte(bdf, addr, &val1); 350 pci_read_config_byte(bdf, addr, &val1);
347 printf(" %02x", val1); 351 printf(" %02x", val1);
348 } 352 }
349 353
350 nbytes = cli_readline(" ? "); 354 nbytes = cli_readline(" ? ");
351 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) { 355 if (nbytes == 0 || (nbytes == 1 && console_buffer[0] == '-')) {
352 /* <CR> pressed as only input, don't modify current 356 /* <CR> pressed as only input, don't modify current
353 * location and move to next. "-" pressed will go back. 357 * location and move to next. "-" pressed will go back.
354 */ 358 */
355 if (incrflag) 359 if (incrflag)
356 addr += nbytes ? -size : size; 360 addr += nbytes ? -size : size;
357 nbytes = 1; 361 nbytes = 1;
358 /* good enough to not time out */ 362 /* good enough to not time out */
359 bootretry_reset_cmd_timeout(); 363 bootretry_reset_cmd_timeout();
360 } 364 }
361 #ifdef CONFIG_BOOT_RETRY_TIME 365 #ifdef CONFIG_BOOT_RETRY_TIME
362 else if (nbytes == -2) { 366 else if (nbytes == -2) {
363 break; /* timed out, exit the command */ 367 break; /* timed out, exit the command */
364 } 368 }
365 #endif 369 #endif
366 else { 370 else {
367 char *endp; 371 char *endp;
368 i = simple_strtoul(console_buffer, &endp, 16); 372 i = simple_strtoul(console_buffer, &endp, 16);
369 nbytes = endp - console_buffer; 373 nbytes = endp - console_buffer;
370 if (nbytes) { 374 if (nbytes) {
371 /* good enough to not time out 375 /* good enough to not time out
372 */ 376 */
373 bootretry_reset_cmd_timeout(); 377 bootretry_reset_cmd_timeout();
374 pci_cfg_write (bdf, addr, size, i); 378 pci_cfg_write (bdf, addr, size, i);
375 if (incrflag) 379 if (incrflag)
376 addr += size; 380 addr += size;
377 } 381 }
378 } 382 }
379 } while (nbytes); 383 } while (nbytes);
380 384
381 return 0; 385 return 0;
382 } 386 }
383 387
384 /* PCI Configuration Space access commands 388 /* PCI Configuration Space access commands
385 * 389 *
386 * Syntax: 390 * Syntax:
387 * pci display[.b, .w, .l] bus.device.function} [addr] [len] 391 * pci display[.b, .w, .l] bus.device.function} [addr] [len]
388 * pci next[.b, .w, .l] bus.device.function [addr] 392 * pci next[.b, .w, .l] bus.device.function [addr]
389 * pci modify[.b, .w, .l] bus.device.function [addr] 393 * pci modify[.b, .w, .l] bus.device.function [addr]
390 * pci write[.b, .w, .l] bus.device.function addr value 394 * pci write[.b, .w, .l] bus.device.function addr value
391 */ 395 */
392 static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) 396 static int do_pci(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
393 { 397 {
394 ulong addr = 0, value = 0, size = 0; 398 ulong addr = 0, value = 0, size = 0;
395 pci_dev_t bdf = 0; 399 pci_dev_t bdf = 0;
396 char cmd = 's'; 400 char cmd = 's';
397 401
398 if (argc > 1) 402 if (argc > 1)
399 cmd = argv[1][0]; 403 cmd = argv[1][0];
400 404
401 switch (cmd) { 405 switch (cmd) {
402 case 'd': /* display */ 406 case 'd': /* display */
403 case 'n': /* next */ 407 case 'n': /* next */
404 case 'm': /* modify */ 408 case 'm': /* modify */
405 case 'w': /* write */ 409 case 'w': /* write */
406 /* Check for a size specification. */ 410 /* Check for a size specification. */
407 size = cmd_get_data_size(argv[1], 4); 411 size = cmd_get_data_size(argv[1], 4);
408 if (argc > 3) 412 if (argc > 3)
409 addr = simple_strtoul(argv[3], NULL, 16); 413 addr = simple_strtoul(argv[3], NULL, 16);
410 if (argc > 4) 414 if (argc > 4)
411 value = simple_strtoul(argv[4], NULL, 16); 415 value = simple_strtoul(argv[4], NULL, 16);
412 case 'h': /* header */ 416 case 'h': /* header */
413 if (argc < 3) 417 if (argc < 3)
414 goto usage; 418 goto usage;
415 if ((bdf = get_pci_dev(argv[2])) == -1) 419 if ((bdf = get_pci_dev(argv[2])) == -1)
416 return 1; 420 return 1;
417 break; 421 break;
418 #ifdef CONFIG_CMD_PCI_ENUM 422 #ifdef CONFIG_CMD_PCI_ENUM
419 case 'e': 423 case 'e':
420 break; 424 break;
421 #endif 425 #endif
422 default: /* scan bus */ 426 default: /* scan bus */
423 value = 1; /* short listing */ 427 value = 1; /* short listing */
424 bdf = 0; /* bus number */ 428 bdf = 0; /* bus number */
425 if (argc > 1) { 429 if (argc > 1) {
426 if (argv[argc-1][0] == 'l') { 430 if (argv[argc-1][0] == 'l') {
427 value = 0; 431 value = 0;
428 argc--; 432 argc--;
429 } 433 }
430 if (argc > 1) 434 if (argc > 1)
431 bdf = simple_strtoul(argv[1], NULL, 16); 435 bdf = simple_strtoul(argv[1], NULL, 16);
432 } 436 }
433 pciinfo(bdf, value); 437 pciinfo(bdf, value);
434 return 0; 438 return 0;
435 } 439 }
436 440
437 switch (argv[1][0]) { 441 switch (argv[1][0]) {
438 case 'h': /* header */ 442 case 'h': /* header */
439 pci_header_show(bdf); 443 pci_header_show(bdf);
440 return 0; 444 return 0;
441 case 'd': /* display */ 445 case 'd': /* display */
442 return pci_cfg_display(bdf, addr, size, value); 446 return pci_cfg_display(bdf, addr, size, value);
443 #ifdef CONFIG_CMD_PCI_ENUM 447 #ifdef CONFIG_CMD_PCI_ENUM
444 case 'e': 448 case 'e':
445 pci_init(); 449 pci_init();
446 return 0; 450 return 0;
447 #endif 451 #endif
448 case 'n': /* next */ 452 case 'n': /* next */
449 if (argc < 4) 453 if (argc < 4)
450 goto usage; 454 goto usage;
451 return pci_cfg_modify(bdf, addr, size, value, 0); 455 return pci_cfg_modify(bdf, addr, size, value, 0);
452 case 'm': /* modify */ 456 case 'm': /* modify */
453 if (argc < 4) 457 if (argc < 4)
454 goto usage; 458 goto usage;
455 return pci_cfg_modify(bdf, addr, size, value, 1); 459 return pci_cfg_modify(bdf, addr, size, value, 1);
456 case 'w': /* write */ 460 case 'w': /* write */
457 if (argc < 5) 461 if (argc < 5)
458 goto usage; 462 goto usage;
459 return pci_cfg_write(bdf, addr, size, value); 463 return pci_cfg_write(bdf, addr, size, value);
460 } 464 }
461 465
462 return 1; 466 return 1;
463 usage: 467 usage:
464 return CMD_RET_USAGE; 468 return CMD_RET_USAGE;
465 } 469 }
466 470
467 /***************************************************/ 471 /***************************************************/
468 472
469 #ifdef CONFIG_SYS_LONGHELP 473 #ifdef CONFIG_SYS_LONGHELP
470 static char pci_help_text[] = 474 static char pci_help_text[] =
471 "[bus] [long]\n" 475 "[bus] [long]\n"
472 " - short or long list of PCI devices on bus 'bus'\n" 476 " - short or long list of PCI devices on bus 'bus'\n"
473 #ifdef CONFIG_CMD_PCI_ENUM 477 #ifdef CONFIG_CMD_PCI_ENUM
474 "pci enum\n" 478 "pci enum\n"
475 " - re-enumerate PCI buses\n" 479 " - re-enumerate PCI buses\n"
476 #endif 480 #endif
477 "pci header b.d.f\n" 481 "pci header b.d.f\n"
478 " - show header of PCI device 'bus.device.function'\n" 482 " - show header of PCI device 'bus.device.function'\n"
479 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n" 483 "pci display[.b, .w, .l] b.d.f [address] [# of objects]\n"
480 " - display PCI configuration space (CFG)\n" 484 " - display PCI configuration space (CFG)\n"
481 "pci next[.b, .w, .l] b.d.f address\n" 485 "pci next[.b, .w, .l] b.d.f address\n"
482 " - modify, read and keep CFG address\n" 486 " - modify, read and keep CFG address\n"
483 "pci modify[.b, .w, .l] b.d.f address\n" 487 "pci modify[.b, .w, .l] b.d.f address\n"
484 " - modify, auto increment CFG address\n" 488 " - modify, auto increment CFG address\n"
485 "pci write[.b, .w, .l] b.d.f address value\n" 489 "pci write[.b, .w, .l] b.d.f address value\n"
486 " - write to CFG address"; 490 " - write to CFG address";
487 #endif 491 #endif
488 492
489 U_BOOT_CMD( 493 U_BOOT_CMD(
490 pci, 5, 1, do_pci, 494 pci, 5, 1, do_pci,
491 "list and access PCI Configuration Space", pci_help_text 495 "list and access PCI Configuration Space", pci_help_text
492 ); 496 );
493 497