Eric Lee / smarc-uboot | Embedian Git Server

Commit 056fbc73d54df64adcb93c513cba708acb2683bd

Authored by Jagannadha Sutradharudu Teki 2014-01-07 02:41:35 +0800

Exists in master and in 50 other branches

sf: Add dual memories support - DUAL_PARALLEL

This patch added support for accessing dual memories in
parallel connection with single chipselect line from controller.

For more info - see doc/SPI/README.dual-flash

Signed-off-by: Jagannadha Sutradharudu Teki <jaganna@xilinx.com>

Showing 5 changed files with 45 additions and 9 deletions Inline Diff

doc/SPI/README.dual-flash
drivers/mtd/spi/sf_ops.c
drivers/mtd/spi/sf_probe.c
include/spi.h
include/spi_flash.h

doc/SPI/README.dual-flash

Diff comments View file @ 056fbc7

 SPI/QSPI Dual flash connection modes:
 =====================================
 This describes how SPI/QSPI flash memories are connected to a given
 controller in a single chip select line.
 Current spi_flash framework supports, single flash memory connected
 to a given controller with single chip select line, but there are some
 hw logics(ex: xilinx zynq qspi) that describes two/dual memories are
 connected with a single chip select line from a controller.
 "dual_flash" from include/spi.h describes these types of connection mode
 Possible connections:
 --------------------
 SF_SINGLE_FLASH:
        - single spi flash memory connected with single chip select line.
   +------------+             CS         +---------------+
   |            |----------------------->|               |
   | Controller |         I0[3:0]        | Flash memory  |
   | SPI/QSPI   |<======================>| (SPI/QSPI)    |
   |            |           CLK          |               |
   |            |----------------------->|               |
   +------------+                        +---------------+
 SF_DUAL_STACKED_FLASH:
        - dual spi/qspi flash memories are connected with a single chipselect
          line and these two memories are operating stacked fasion with shared buses.
        - xilinx zynq qspi controller has implemented this feature [1]
   +------------+        CS             +---------------+
   |            |---------------------->|               |
   |            |              I0[3:0]  | Upper Flash   |
   |            |            +=========>| memory        |
   |            |            |     CLK  | (SPI/QSPI)    |
   |            |            |    +---->|               |
   | Controller |        CS  |    |     +---------------+
   | SPI/QSPI   |------------|----|---->|               |
   |            |    I0[3:0] |    |     | Lower Flash   |
   |            |<===========+====|====>| memory        |
   |            |          CLK    |     | (SPI/QSPI)    |
   |            |-----------------+---->|               |
   +------------+                       +---------------+
        - two memory flash devices should has same hw part attributes (like size,
          vendor..etc)
        - Configurations:
                on LQSPI_CFG register, Enable TWO_MEM[BIT:30] on LQSPI_CFG
                Enable U_PAGE[BIT:28] if U_PAGE flag set - upper memory
                Disable U_PAGE[BIT:28] if U_PAGE flag unset - lower memory
        - Operation:
                accessing memories serially like one after another.
                by default, if U_PAGE is unset lower memory should accessible,
                once user wants to access upper memory need to set U_PAGE.
+SPI_FLASH_CONN_DUALPARALLEL:
+	- dual spi/qspi flash memories are connected with a single chipselect
+	  line and these two memories are operating parallel with separate buses.
+	- xilinx zynq qspi controller has implemented this feature [1]
+  +-------------+           CS		+---------------+
+  |		|---------------------->|		|
+  | 		|        I0[3:0]	| Upper Flash	|
+  | 		|<=====================>| memory	|
+  |		|	   CLK		| (SPI/QSPI)	|
+  |		|---------------------->|		|
+  | Controller	|	    CS		+---------------+
+  | SPI/QSPI	|---------------------->|		|
+  | 		|        I0[3:0]	| Lower Flash	|
+  | 		|<=====================>| memory	|
+  |		|	   CLK		| (SPI/QSPI)	|
+  |		|---------------------->|		|
+  +-------------+			+---------------+
+	- two memory flash devices should has same hw part attributes (like size,
+	  vendor..etc)
+	- Configurations:
+		Need to enable SEP_BUS[BIT:29],TWO_MEM[BIT:30] on LQSPI_CFG register.
+	- Operation:
+		Even bits, i.e. bit 0, 2, 4 ., of a data word is located in the lower memory
+		and odd bits, i.e. bit 1, 3, 5, ., of a data word is located in the upper memory.
 Note: Technically there is only one CS line from the controller, but
 zynq qspi controller has an internal hw logic to enable additional CS
 when controller is configured for dual memories.
 [1] http://www.xilinx.com/support/documentation/user_guides/ug585-Zynq-7000-TRM.pdf
 --
 Jagannadha Sutradharudu Teki <jaganna@xilinx.com>
 05-01-2014.

drivers/mtd/spi/sf_ops.c

Diff comments View file @ 056fbc7

 /*
  * SPI flash operations
  *
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <malloc.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <watchdog.h>
 #include "sf_internal.h"
 static void spi_flash_addr(u32 addr, u8 *cmd)
 {
 	/* cmd[0] is actual command */
 	cmd[1] = addr >> 16;
 	cmd[2] = addr >> 8;
 	cmd[3] = addr >> 0;
 }
 int spi_flash_cmd_read_status(struct spi_flash *flash, u8 *rs)
 {
 	int ret;
 	u8 cmd;
 	cmd = CMD_READ_STATUS;
 	ret = spi_flash_read_common(flash, &cmd, 1, rs, 1);
 	if (ret < 0) {
 		debug("SF: fail to read status register\n");
 		return ret;
 	}
 	return 0;
 }
 int spi_flash_cmd_write_status(struct spi_flash *flash, u8 ws)
 {
 	u8 cmd;
 	int ret;
 	cmd = CMD_WRITE_STATUS;
 	ret = spi_flash_write_common(flash, &cmd, 1, &ws, 1);
 	if (ret < 0) {
 		debug("SF: fail to write status register\n");
 		return ret;
 	}
 	return 0;
 }
 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
 int spi_flash_cmd_read_config(struct spi_flash *flash, u8 *rc)
 {
 	int ret;
 	u8 cmd;
 	cmd = CMD_READ_CONFIG;
 	ret = spi_flash_read_common(flash, &cmd, 1, rc, 1);
 	if (ret < 0) {
 		debug("SF: fail to read config register\n");
 		return ret;
 	}
 	return 0;
 }
 int spi_flash_cmd_write_config(struct spi_flash *flash, u8 wc)
 {
 	u8 data[2];
 	u8 cmd;
 	int ret;
 	ret = spi_flash_cmd_read_status(flash, &data[0]);
 	if (ret < 0)
 		return ret;
 	cmd = CMD_WRITE_STATUS;
 	data[1] = wc;
 	ret = spi_flash_write_common(flash, &cmd, 1, &data, 2);
 	if (ret) {
 		debug("SF: fail to write config register\n");
 		return ret;
 	}
 	return 0;
 }
 #endif
 #ifdef CONFIG_SPI_FLASH_BAR
 static int spi_flash_cmd_bankaddr_write(struct spi_flash *flash, u8 bank_sel)
 {
 	u8 cmd;
 	int ret;
 	if (flash->bank_curr == bank_sel) {
 		debug("SF: not require to enable bank%d\n", bank_sel);
 		return 0;
 	}
 	cmd = flash->bank_write_cmd;
 	ret = spi_flash_write_common(flash, &cmd, 1, &bank_sel, 1);
 	if (ret < 0) {
 		debug("SF: fail to write bank register\n");
 		return ret;
 	}
 	flash->bank_curr = bank_sel;
 	return 0;
 }
 static int spi_flash_bank(struct spi_flash *flash, u32 offset)
 {
 	u8 bank_sel;
 	int ret;
-	bank_sel = offset / SPI_FLASH_16MB_BOUN;
+	bank_sel = offset / (SPI_FLASH_16MB_BOUN << flash->shift);
 	ret = spi_flash_cmd_bankaddr_write(flash, bank_sel);
 	if (ret) {
 		debug("SF: fail to set bank%d\n", bank_sel);
 		return ret;
 	}
 	return bank_sel;
 }
 #endif
 static void spi_flash_dual_flash(struct spi_flash *flash, u32 *addr)
 {
 	switch (flash->dual_flash) {
 	case SF_DUAL_STACKED_FLASH:
 		if (*addr >= (flash->size >> 1)) {
 			*addr -= flash->size >> 1;
 			flash->spi->flags |= SPI_XFER_U_PAGE;
 		} else {
 			flash->spi->flags &= ~SPI_XFER_U_PAGE;
 		}
 		break;
+	case SF_DUAL_PARALLEL_FLASH:
+		*addr >>= flash->shift;
+		break;
 	default:
 		debug("SF: Unsupported dual_flash=%d\n", flash->dual_flash);
 		break;
 	}
 }
 int spi_flash_cmd_wait_ready(struct spi_flash *flash, unsigned long timeout)
 {
 	struct spi_slave *spi = flash->spi;
 	unsigned long timebase;
 	unsigned long flags = SPI_XFER_BEGIN;
 	int ret;
 	u8 status;
 	u8 check_status = 0x0;
 	u8 poll_bit = STATUS_WIP;
 	u8 cmd = flash->poll_cmd;
 	if (cmd == CMD_FLAG_STATUS) {
 		poll_bit = STATUS_PEC;
 		check_status = poll_bit;
 	}
 	if (spi->flags & SPI_XFER_U_PAGE)
 		flags |= SPI_XFER_U_PAGE;
 	ret = spi_xfer(spi, 8, &cmd, NULL, flags);
 	if (ret) {
 		debug("SF: fail to read %s status register\n",
 		      cmd == CMD_READ_STATUS ? "read" : "flag");
 		return ret;
 	}
 	timebase = get_timer(0);
 	do {
 		WATCHDOG_RESET();
 		ret = spi_xfer(spi, 8, NULL, &status, 0);
 		if (ret)
 			return -1;
 		if ((status & poll_bit) == check_status)
 			break;
 	} while (get_timer(timebase) < timeout);
 	spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END);
 	if ((status & poll_bit) == check_status)
 		return 0;
 	/* Timed out */
 	debug("SF: time out!\n");
 	return -1;
 }
 int spi_flash_write_common(struct spi_flash *flash, const u8 *cmd,
 		size_t cmd_len, const void *buf, size_t buf_len)
 {
 	struct spi_slave *spi = flash->spi;
 	unsigned long timeout = SPI_FLASH_PROG_TIMEOUT;
 	int ret;
 	if (buf == NULL)
 		timeout = SPI_FLASH_PAGE_ERASE_TIMEOUT;
 	ret = spi_claim_bus(flash->spi);
 	if (ret) {
 		debug("SF: unable to claim SPI bus\n");
 		return ret;
 	}
 	ret = spi_flash_cmd_write_enable(flash);
 	if (ret < 0) {
 		debug("SF: enabling write failed\n");
 		return ret;
 	}
 	ret = spi_flash_cmd_write(spi, cmd, cmd_len, buf, buf_len);
 	if (ret < 0) {
 		debug("SF: write cmd failed\n");
 		return ret;
 	}
 	ret = spi_flash_cmd_wait_ready(flash, timeout);
 	if (ret < 0) {
 		debug("SF: write %s timed out\n",
 		      timeout == SPI_FLASH_PROG_TIMEOUT ?
 			"program" : "page erase");
 		return ret;
 	}
 	spi_release_bus(spi);
 	return ret;
 }
 int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
 {
 	u32 erase_size, erase_addr;
 	u8 cmd[SPI_FLASH_CMD_LEN];
 	int ret = -1;
 	erase_size = flash->erase_size;
 	if (offset % erase_size || len % erase_size) {
 		debug("SF: Erase offset/length not multiple of erase size\n");
 		return -1;
 	}
 	cmd[0] = flash->erase_cmd;
 	while (len) {
 		erase_addr = offset;
 		if (flash->dual_flash > SF_SINGLE_FLASH)
 			spi_flash_dual_flash(flash, &erase_addr);
 #ifdef CONFIG_SPI_FLASH_BAR
 		ret = spi_flash_bank(flash, erase_addr);
 		if (ret < 0)
 			return ret;
 #endif
 		spi_flash_addr(erase_addr, cmd);
 		debug("SF: erase %2x %2x %2x %2x (%x)\n", cmd[0], cmd[1],
 		      cmd[2], cmd[3], erase_addr);
 		ret = spi_flash_write_common(flash, cmd, sizeof(cmd), NULL, 0);
 		if (ret < 0) {
 			debug("SF: erase failed\n");
 			break;
 		}
 		offset += erase_size;
 		len -= erase_size;
 	}
 	return ret;
 }
 int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
 		size_t len, const void *buf)
 {
 	unsigned long byte_addr, page_size;
 	u32 write_addr;
 	size_t chunk_len, actual;
 	u8 cmd[SPI_FLASH_CMD_LEN];
 	int ret = -1;
 	page_size = flash->page_size;
 	cmd[0] = flash->write_cmd;
 	for (actual = 0; actual < len; actual += chunk_len) {
 		write_addr = offset;
 		if (flash->dual_flash > SF_SINGLE_FLASH)
 			spi_flash_dual_flash(flash, &write_addr);
 #ifdef CONFIG_SPI_FLASH_BAR
 		ret = spi_flash_bank(flash, write_addr);
 		if (ret < 0)
 			return ret;
 #endif
 		byte_addr = offset % page_size;
 		chunk_len = min(len - actual, page_size - byte_addr);
 		if (flash->spi->max_write_size)
 			chunk_len = min(chunk_len, flash->spi->max_write_size);
 		spi_flash_addr(write_addr, cmd);
 		debug("SF: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %zu\n",
 		      buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len);
 		ret = spi_flash_write_common(flash, cmd, sizeof(cmd),
 					buf + actual, chunk_len);
 		if (ret < 0) {
 			debug("SF: write failed\n");
 			break;
 		}
 		offset += chunk_len;
 	}
 	return ret;
 }
 int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
 		size_t cmd_len, void *data, size_t data_len)
 {
 	struct spi_slave *spi = flash->spi;
 	int ret;
 	ret = spi_claim_bus(flash->spi);
 	if (ret) {
 		debug("SF: unable to claim SPI bus\n");
 		return ret;
 	}
 	ret = spi_flash_cmd_read(spi, cmd, cmd_len, data, data_len);
 	if (ret < 0) {
 		debug("SF: read cmd failed\n");
 		return ret;
 	}
 	spi_release_bus(spi);
 	return ret;
 }
 int spi_flash_cmd_read_ops(struct spi_flash *flash, u32 offset,
 		size_t len, void *data)
 {
 	u8 *cmd, cmdsz;
 	u32 remain_len, read_len, read_addr;
 	int bank_sel = 0;
 	int ret = -1;
 	/* Handle memory-mapped SPI */
 	if (flash->memory_map) {
 		ret = spi_claim_bus(flash->spi);
 		if (ret) {
 			debug("SF: unable to claim SPI bus\n");
 			return ret;
 		}
 		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP);
 		memcpy(data, flash->memory_map + offset, len);
 		spi_xfer(flash->spi, 0, NULL, NULL, SPI_XFER_MMAP_END);
 		spi_release_bus(flash->spi);
 		return 0;
 	}
 	cmdsz = SPI_FLASH_CMD_LEN + flash->dummy_byte;
 	cmd = malloc(cmdsz);
 	memset(cmd, 0, cmdsz);
 	cmd[0] = flash->read_cmd;
 	while (len) {
 		read_addr = offset;
 		if (flash->dual_flash > SF_SINGLE_FLASH)
 			spi_flash_dual_flash(flash, &read_addr);
 #ifdef CONFIG_SPI_FLASH_BAR
 		bank_sel = spi_flash_bank(flash, read_addr);
 		if (bank_sel < 0)
 			return ret;
 #endif
-		remain_len = (SPI_FLASH_16MB_BOUN * (bank_sel + 1)) - offset;
+		remain_len = ((SPI_FLASH_16MB_BOUN << flash->shift) *
+				(bank_sel + 1)) - offset;
 		if (len < remain_len)
 			read_len = len;
 		else
 			read_len = remain_len;
 		spi_flash_addr(read_addr, cmd);
 		ret = spi_flash_read_common(flash, cmd, cmdsz, data, read_len);
 		if (ret < 0) {
 			debug("SF: read failed\n");
 			break;
 		}
 		offset += read_len;
 		len -= read_len;
 		data += read_len;
 	}
 	return ret;
 }
 #ifdef CONFIG_SPI_FLASH_SST
 static int sst_byte_write(struct spi_flash *flash, u32 offset, const void *buf)
 {
 	int ret;
 	u8 cmd[4] = {
 		CMD_SST_BP,
 		offset >> 16,
 		offset >> 8,
 		offset,
 	};
 	debug("BP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
 	      spi_w8r8(flash->spi, CMD_READ_STATUS), buf, cmd[0], offset);
 	ret = spi_flash_cmd_write_enable(flash);
 	if (ret)
 		return ret;
 	ret = spi_flash_cmd_write(flash->spi, cmd, sizeof(cmd), buf, 1);
 	if (ret)
 		return ret;
 	return spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
 }
 int sst_write_wp(struct spi_flash *flash, u32 offset, size_t len,
 		const void *buf)
 {
 	size_t actual, cmd_len;
 	int ret;
 	u8 cmd[4];
 	ret = spi_claim_bus(flash->spi);
 	if (ret) {
 		debug("SF: Unable to claim SPI bus\n");
 		return ret;
 	}
 	/* If the data is not word aligned, write out leading single byte */
 	actual = offset % 2;
 	if (actual) {
 		ret = sst_byte_write(flash, offset, buf);
 		if (ret)
 			goto done;
 	}
 	offset += actual;
 	ret = spi_flash_cmd_write_enable(flash);
 	if (ret)
 		goto done;
 	cmd_len = 4;
 	cmd[0] = CMD_SST_AAI_WP;
 	cmd[1] = offset >> 16;
 	cmd[2] = offset >> 8;
 	cmd[3] = offset;
 	for (; actual < len - 1; actual += 2) {
 		debug("WP[%02x]: 0x%p => cmd = { 0x%02x 0x%06x }\n",
 		      spi_w8r8(flash->spi, CMD_READ_STATUS), buf + actual,
 		      cmd[0], offset);
 		ret = spi_flash_cmd_write(flash->spi, cmd, cmd_len,
 					buf + actual, 2);
 		if (ret) {
 			debug("SF: sst word program failed\n");
 			break;
 		}
 		ret = spi_flash_cmd_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT);
 		if (ret)
 			break;
 		cmd_len = 1;
 		offset += 2;
 	}
 	if (!ret)
 		ret = spi_flash_cmd_write_disable(flash);
 	/* If there is a single trailing byte, write it out */
 	if (!ret && actual != len)
 		ret = sst_byte_write(flash, offset, buf + actual);
  done:
 	debug("SF: sst: program %s %zu bytes @ 0x%zx\n",
 	      ret ? "failure" : "success", len, offset - actual);
 	spi_release_bus(flash->spi);
 	return ret;
 }
 #endif

drivers/mtd/spi/sf_probe.c

Diff comments View file @ 056fbc7

 /*
  * SPI flash probing
  *
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2010 Reinhard Meyer, EMK Elektronik
  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <fdtdec.h>
 #include <malloc.h>
 #include <spi.h>
 #include <spi_flash.h>
 #include <asm/io.h>
 #include "sf_internal.h"
 DECLARE_GLOBAL_DATA_PTR;
 /* Read commands array */
 static u8 spi_read_cmds_array[] = {
 	CMD_READ_ARRAY_SLOW,
 	CMD_READ_DUAL_OUTPUT_FAST,
 	CMD_READ_DUAL_IO_FAST,
 	CMD_READ_QUAD_OUTPUT_FAST,
 	CMD_READ_QUAD_IO_FAST,
 };
 #ifdef CONFIG_SPI_FLASH_MACRONIX
 static int spi_flash_set_qeb_mxic(struct spi_flash *flash)
 {
 	u8 qeb_status;
 	int ret;
 	ret = spi_flash_cmd_read_status(flash, &qeb_status);
 	if (ret < 0)
 		return ret;
 	if (qeb_status & STATUS_QEB_MXIC) {
 		debug("SF: mxic: QEB is already set\n");
 	} else {
 		ret = spi_flash_cmd_write_status(flash, STATUS_QEB_MXIC);
 		if (ret < 0)
 			return ret;
 	}
 	return ret;
 }
 #endif
 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
 static int spi_flash_set_qeb_winspan(struct spi_flash *flash)
 {
 	u8 qeb_status;
 	int ret;
 	ret = spi_flash_cmd_read_config(flash, &qeb_status);
 	if (ret < 0)
 		return ret;
 	if (qeb_status & STATUS_QEB_WINSPAN) {
 		debug("SF: winspan: QEB is already set\n");
 	} else {
 		ret = spi_flash_cmd_write_config(flash, STATUS_QEB_WINSPAN);
 		if (ret < 0)
 			return ret;
 	}
 	return ret;
 }
 #endif
 static int spi_flash_set_qeb(struct spi_flash *flash, u8 idcode0)
 {
 	switch (idcode0) {
 #ifdef CONFIG_SPI_FLASH_MACRONIX
 	case SPI_FLASH_CFI_MFR_MACRONIX:
 		return spi_flash_set_qeb_mxic(flash);
 #endif
 #if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
 	case SPI_FLASH_CFI_MFR_SPANSION:
 	case SPI_FLASH_CFI_MFR_WINBOND:
 		return spi_flash_set_qeb_winspan(flash);
 #endif
 #ifdef CONFIG_SPI_FLASH_STMICRO
 	case SPI_FLASH_CFI_MFR_STMICRO:
 		debug("SF: QEB is volatile for %02x flash\n", idcode0);
 		return 0;
 #endif
 	default:
 		printf("SF: Need set QEB func for %02x flash\n", idcode0);
 		return -1;
 	}
 }
 static struct spi_flash *spi_flash_validate_params(struct spi_slave *spi,
 		u8 *idcode)
 {
 	const struct spi_flash_params *params;
 	struct spi_flash *flash;
 	u8 cmd;
 	u16 jedec = idcode[1] << 8 | idcode[2];
 	u16 ext_jedec = idcode[3] << 8 | idcode[4];
 	params = spi_flash_params_table;
 	for (; params->name != NULL; params++) {
 		if ((params->jedec >> 16) == idcode[0]) {
 			if ((params->jedec & 0xFFFF) == jedec) {
 				if (params->ext_jedec == 0)
 					break;
 				else if (params->ext_jedec == ext_jedec)
 					break;
 			}
 		}
 	}
 	if (!params->name) {
 		printf("SF: Unsupported flash IDs: ");
 		printf("manuf %02x, jedec %04x, ext_jedec %04x\n",
 		       idcode[0], jedec, ext_jedec);
 		return NULL;
 	}
 	flash = malloc(sizeof(*flash));
 	if (!flash) {
 		debug("SF: Failed to allocate spi_flash\n");
 		return NULL;
 	}
 	memset(flash, '\0', sizeof(*flash));
 	/* Assign spi data */
 	flash->spi = spi;
 	flash->name = params->name;
 	flash->memory_map = spi->memory_map;
 	flash->dual_flash = flash->spi->option;
 	/* Assign spi_flash ops */
 	flash->write = spi_flash_cmd_write_ops;
 #ifdef CONFIG_SPI_FLASH_SST
 	if (params->flags & SST_WP)
 		flash->write = sst_write_wp;
 #endif
 	flash->erase = spi_flash_cmd_erase_ops;
 	flash->read = spi_flash_cmd_read_ops;
 	/* Compute the flash size */
-	flash->page_size = (ext_jedec == 0x4d00) ? 512 : 256;
+	flash->shift = (flash->dual_flash & SF_DUAL_PARALLEL_FLASH) ? 1 : 0;
-	flash->sector_size = params->sector_size;
+	flash->page_size = ((ext_jedec == 0x4d00) ? 512 : 256) << flash->shift;
-	flash->size = flash->sector_size * params->nr_sectors;
+	flash->sector_size = params->sector_size << flash->shift;
+	flash->size = flash->sector_size * params->nr_sectors << flash->shift;
 	if (flash->dual_flash & SF_DUAL_STACKED_FLASH)
 		flash->size <<= 1;
 	/* Compute erase sector and command */
 	if (params->flags & SECT_4K) {
 		flash->erase_cmd = CMD_ERASE_4K;
-		flash->erase_size = 4096;
+		flash->erase_size = 4096 << flash->shift;
 	} else if (params->flags & SECT_32K) {
 		flash->erase_cmd = CMD_ERASE_32K;
-		flash->erase_size = 32768;
+		flash->erase_size = 32768 << flash->shift;
 	} else {
 		flash->erase_cmd = CMD_ERASE_64K;
 		flash->erase_size = flash->sector_size;
 	}
 	/* Look for the fastest read cmd */
 	cmd = fls(params->e_rd_cmd & flash->spi->op_mode_rx);
 	if (cmd) {
 		cmd = spi_read_cmds_array[cmd - 1];
 		flash->read_cmd = cmd;
 	} else {
 		/* Go for default supported read cmd */
 		flash->read_cmd = CMD_READ_ARRAY_FAST;
 	}
 	/* Not require to look for fastest only two write cmds yet */
 	if (params->flags & WR_QPP && flash->spi->op_mode_tx & SPI_OPM_TX_QPP)
 		flash->write_cmd = CMD_QUAD_PAGE_PROGRAM;
 	else
 		/* Go for default supported write cmd */
 		flash->write_cmd = CMD_PAGE_PROGRAM;
 	/* Set the quad enable bit - only for quad commands */
 	if ((flash->read_cmd == CMD_READ_QUAD_OUTPUT_FAST) ||
 	    (flash->read_cmd == CMD_READ_QUAD_IO_FAST) ||
 	    (flash->write_cmd == CMD_QUAD_PAGE_PROGRAM)) {
 		if (spi_flash_set_qeb(flash, idcode[0])) {
 			debug("SF: Fail to set QEB for %02x\n", idcode[0]);
 			return NULL;
 		}
 	}
 	/* Read dummy_byte: dummy byte is determined based on the
 	 * dummy cycles of a particular command.
 	 * Fast commands - dummy_byte = dummy_cycles/8
 	 * I/O commands- dummy_byte = (dummy_cycles * no.of lines)/8
 	 * For I/O commands except cmd[0] everything goes on no.of lines
 	 * based on particular command but incase of fast commands except
 	 * data all go on single line irrespective of command.
 	 */
 	switch (flash->read_cmd) {
 	case CMD_READ_QUAD_IO_FAST:
 		flash->dummy_byte = 2;
 		break;
 	case CMD_READ_ARRAY_SLOW:
 		flash->dummy_byte = 0;
 		break;
 	default:
 		flash->dummy_byte = 1;
 	}
 	/* Poll cmd selection */
 	flash->poll_cmd = CMD_READ_STATUS;
 #ifdef CONFIG_SPI_FLASH_STMICRO
 	if (params->flags & E_FSR)
 		flash->poll_cmd = CMD_FLAG_STATUS;
 #endif
 	/* Configure the BAR - discover bank cmds and read current bank */
 #ifdef CONFIG_SPI_FLASH_BAR
 	u8 curr_bank = 0;
 	if (flash->size > SPI_FLASH_16MB_BOUN) {
 		flash->bank_read_cmd = (idcode[0] == 0x01) ?
 					CMD_BANKADDR_BRRD : CMD_EXTNADDR_RDEAR;
 		flash->bank_write_cmd = (idcode[0] == 0x01) ?
 					CMD_BANKADDR_BRWR : CMD_EXTNADDR_WREAR;
 		if (spi_flash_read_common(flash, &flash->bank_read_cmd, 1,
 					  &curr_bank, 1)) {
 			debug("SF: fail to read bank addr register\n");
 			return NULL;
 		}
 		flash->bank_curr = curr_bank;
 	} else {
 		flash->bank_curr = curr_bank;
 	}
 #endif
 	/* Flash powers up read-only, so clear BP# bits */
 #if defined(CONFIG_SPI_FLASH_ATMEL) || \
 	defined(CONFIG_SPI_FLASH_MACRONIX) || \
 	defined(CONFIG_SPI_FLASH_SST)
 		spi_flash_cmd_write_status(flash, 0);
 #endif
 	return flash;
 }
 #ifdef CONFIG_OF_CONTROL
 int spi_flash_decode_fdt(const void *blob, struct spi_flash *flash)
 {
 	fdt_addr_t addr;
 	fdt_size_t size;
 	int node;
 	/* If there is no node, do nothing */
 	node = fdtdec_next_compatible(blob, 0, COMPAT_GENERIC_SPI_FLASH);
 	if (node < 0)
 		return 0;
 	addr = fdtdec_get_addr_size(blob, node, "memory-map", &size);
 	if (addr == FDT_ADDR_T_NONE) {
 		debug("%s: Cannot decode address\n", __func__);
 		return 0;
 	}
 	if (flash->size != size) {
 		debug("%s: Memory map must cover entire device\n", __func__);
 		return -1;
 	}
 	flash->memory_map = map_sysmem(addr, size);
 	return 0;
 }
 #endif /* CONFIG_OF_CONTROL */
 static struct spi_flash *spi_flash_probe_slave(struct spi_slave *spi)
 {
 	struct spi_flash *flash = NULL;
 	u8 idcode[5];
 	int ret;
 	/* Setup spi_slave */
 	if (!spi) {
 		printf("SF: Failed to set up slave\n");
 		return NULL;
 	}
 	/* Claim spi bus */
 	ret = spi_claim_bus(spi);
 	if (ret) {
 		debug("SF: Failed to claim SPI bus: %d\n", ret);
 		goto err_claim_bus;
 	}
 	/* Read the ID codes */
 	ret = spi_flash_cmd(spi, CMD_READ_ID, idcode, sizeof(idcode));
 	if (ret) {
 		printf("SF: Failed to get idcodes\n");
 		goto err_read_id;
 	}
 #ifdef DEBUG
 	printf("SF: Got idcodes\n");
 	print_buffer(0, idcode, 1, sizeof(idcode), 0);
 #endif
 	/* Validate params from spi_flash_params table */
 	flash = spi_flash_validate_params(spi, idcode);
 	if (!flash)
 		goto err_read_id;
 #ifdef CONFIG_OF_CONTROL
 	if (spi_flash_decode_fdt(gd->fdt_blob, flash)) {
 		debug("SF: FDT decode error\n");
 		goto err_read_id;
 	}
 #endif
 #ifndef CONFIG_SPL_BUILD
 	printf("SF: Detected %s with page size ", flash->name);
 	print_size(flash->page_size, ", erase size ");
 	print_size(flash->erase_size, ", total ");
 	print_size(flash->size, "");
 	if (flash->memory_map)
 		printf(", mapped at %p", flash->memory_map);
 	puts("\n");
 #endif
 #ifndef CONFIG_SPI_FLASH_BAR
 	if (((flash->dual_flash == SF_SINGLE_FLASH) &&
 	     (flash->size > SPI_FLASH_16MB_BOUN)) ||
 	     ((flash->dual_flash > SF_SINGLE_FLASH) &&
 	     (flash->size > SPI_FLASH_16MB_BOUN << 1))) {
 		puts("SF: Warning - Only lower 16MiB accessible,");
 		puts(" Full access #define CONFIG_SPI_FLASH_BAR\n");
 	}
 #endif
 	/* Release spi bus */
 	spi_release_bus(spi);
 	return flash;
 err_read_id:
 	spi_release_bus(spi);
 err_claim_bus:
 	spi_free_slave(spi);
 	return NULL;
 }
 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int spi_mode)
 {
 	struct spi_slave *spi;
 	spi = spi_setup_slave(bus, cs, max_hz, spi_mode);
 	return spi_flash_probe_slave(spi);
 }
 #ifdef CONFIG_OF_SPI_FLASH
 struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
 				      int spi_node)
 {
 	struct spi_slave *spi;
 	spi = spi_setup_slave_fdt(blob, slave_node, spi_node);
 	return spi_flash_probe_slave(spi);
 }
 #endif
 void spi_flash_free(struct spi_flash *flash)
 {
 	spi_free_slave(flash->spi);
 	free(flash);
 }

include/spi.h

Diff comments View file @ 056fbc7

 /*
  * Common SPI Interface: Controller-specific definitions
  *
  * (C) Copyright 2001
  * Gerald Van Baren, Custom IDEAS, vanbaren@cideas.com.
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #ifndef _SPI_H_
 #define _SPI_H_
 /* SPI mode flags */
 #define	SPI_CPHA	0x01			/* clock phase */
 #define	SPI_CPOL	0x02			/* clock polarity */
 #define	SPI_MODE_0	(0|0)			/* (original MicroWire) */
 #define	SPI_MODE_1	(0|SPI_CPHA)
 #define	SPI_MODE_2	(SPI_CPOL|0)
 #define	SPI_MODE_3	(SPI_CPOL|SPI_CPHA)
 #define	SPI_CS_HIGH	0x04			/* CS active high */
 #define	SPI_LSB_FIRST	0x08			/* per-word bits-on-wire */
 #define	SPI_3WIRE	0x10			/* SI/SO signals shared */
 #define	SPI_LOOP	0x20			/* loopback mode */
 #define	SPI_SLAVE	0x40			/* slave mode */
 #define	SPI_PREAMBLE	0x80			/* Skip preamble bytes */
 /* SPI transfer flags */
 #define SPI_XFER_BEGIN		0x01	/* Assert CS before transfer */
 #define SPI_XFER_END		0x02	/* Deassert CS after transfer */
 #define SPI_XFER_MMAP		0x08	/* Memory Mapped start */
 #define SPI_XFER_MMAP_END	0x10	/* Memory Mapped End */
 #define SPI_XFER_ONCE		(SPI_XFER_BEGIN | SPI_XFER_END)
 #define SPI_XFER_U_PAGE		(1 << 5)
 /* SPI TX operation modes */
 #define SPI_OPM_TX_QPP		1 << 0
 /* SPI RX operation modes */
 #define SPI_OPM_RX_AS		1 << 0
 #define SPI_OPM_RX_DOUT		1 << 1
 #define SPI_OPM_RX_DIO		1 << 2
 #define SPI_OPM_RX_QOF		1 << 3
 #define SPI_OPM_RX_QIOF		1 << 4
 #define SPI_OPM_RX_EXTN		SPI_OPM_RX_AS | SPI_OPM_RX_DOUT | \
 				SPI_OPM_RX_DIO | SPI_OPM_RX_QOF | \
 				SPI_OPM_RX_QIOF
 /* SPI bus connection options */
 #define SPI_CONN_DUAL_SHARED	1 << 0
+#define SPI_CONN_DUAL_SEPARATED	1 << 1
 /* Header byte that marks the start of the message */
 #define SPI_PREAMBLE_END_BYTE	0xec
 #define SPI_DEFAULT_WORDLEN 8
 /**
  * struct spi_slave - Representation of a SPI slave
  *
  * Drivers are expected to extend this with controller-specific data.
  *
  * @bus:		ID of the bus that the slave is attached to.
  * @cs:			ID of the chip select connected to the slave.
  * @op_mode_rx:		SPI RX operation mode.
  * @op_mode_tx:		SPI TX operation mode.
  * @wordlen:		Size of SPI word in number of bits
  * @max_write_size:	If non-zero, the maximum number of bytes which can
  *			be written at once, excluding command bytes.
  * @memory_map:		Address of read-only SPI flash access.
- * @option:		Varies SPI bus options - separate bus.
+ * @option:		Varies SPI bus options - separate, shared bus.
  * @flags:		Indication of SPI flags.
  */
 struct spi_slave {
 	unsigned int bus;
 	unsigned int cs;
 	u8 op_mode_rx;
 	u8 op_mode_tx;
 	unsigned int wordlen;
 	unsigned int max_write_size;
 	void *memory_map;
 	u8 option;
 	u8 flags;
 };
 /**
  * Initialization, must be called once on start up.
  *
  * TODO: I don't think we really need this.
  */
 void spi_init(void);
 /**
  * spi_do_alloc_slave - Allocate a new SPI slave (internal)
  *
  * Allocate and zero all fields in the spi slave, and set the bus/chip
  * select. Use the helper macro spi_alloc_slave() to call this.
  *
  * @offset:	Offset of struct spi_slave within slave structure.
  * @size:	Size of slave structure.
  * @bus:	Bus ID of the slave chip.
  * @cs:		Chip select ID of the slave chip on the specified bus.
  */
 void *spi_do_alloc_slave(int offset, int size, unsigned int bus,
 			 unsigned int cs);
 /**
  * spi_alloc_slave - Allocate a new SPI slave
  *
  * Allocate and zero all fields in the spi slave, and set the bus/chip
  * select.
  *
  * @_struct:	Name of structure to allocate (e.g. struct tegra_spi).
  *		This structure must contain a member 'struct spi_slave *slave'.
  * @bus:	Bus ID of the slave chip.
  * @cs:		Chip select ID of the slave chip on the specified bus.
  */
 #define spi_alloc_slave(_struct, bus, cs) \
 	spi_do_alloc_slave(offsetof(_struct, slave), \
 			    sizeof(_struct), bus, cs)
 /**
  * spi_alloc_slave_base - Allocate a new SPI slave with no private data
  *
  * Allocate and zero all fields in the spi slave, and set the bus/chip
  * select.
  *
  * @bus:	Bus ID of the slave chip.
  * @cs:		Chip select ID of the slave chip on the specified bus.
  */
 #define spi_alloc_slave_base(bus, cs) \
 	spi_do_alloc_slave(0, sizeof(struct spi_slave), bus, cs)
 /**
  * Set up communications parameters for a SPI slave.
  *
  * This must be called once for each slave. Note that this function
  * usually doesn't touch any actual hardware, it only initializes the
  * contents of spi_slave so that the hardware can be easily
  * initialized later.
  *
  * @bus:	Bus ID of the slave chip.
  * @cs:		Chip select ID of the slave chip on the specified bus.
  * @max_hz:	Maximum SCK rate in Hz.
  * @mode:	Clock polarity, clock phase and other parameters.
  *
  * Returns: A spi_slave reference that can be used in subsequent SPI
  * calls, or NULL if one or more of the parameters are not supported.
  */
 struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int mode);
 /**
  * Free any memory associated with a SPI slave.
  *
  * @slave:	The SPI slave
  */
 void spi_free_slave(struct spi_slave *slave);
 /**
  * Claim the bus and prepare it for communication with a given slave.
  *
  * This must be called before doing any transfers with a SPI slave. It
  * will enable and initialize any SPI hardware as necessary, and make
  * sure that the SCK line is in the correct idle state. It is not
  * allowed to claim the same bus for several slaves without releasing
  * the bus in between.
  *
  * @slave:	The SPI slave
  *
  * Returns: 0 if the bus was claimed successfully, or a negative value
  * if it wasn't.
  */
 int spi_claim_bus(struct spi_slave *slave);
 /**
  * Release the SPI bus
  *
  * This must be called once for every call to spi_claim_bus() after
  * all transfers have finished. It may disable any SPI hardware as
  * appropriate.
  *
  * @slave:	The SPI slave
  */
 void spi_release_bus(struct spi_slave *slave);
 /**
  * Set the word length for SPI transactions
  *
  * Set the word length (number of bits per word) for SPI transactions.
  *
  * @slave:	The SPI slave
  * @wordlen:	The number of bits in a word
  *
  * Returns: 0 on success, -1 on failure.
  */
 int spi_set_wordlen(struct spi_slave *slave, unsigned int wordlen);
 /**
  * SPI transfer
  *
  * This writes "bitlen" bits out the SPI MOSI port and simultaneously clocks
  * "bitlen" bits in the SPI MISO port.  That's just the way SPI works.
  *
  * The source of the outgoing bits is the "dout" parameter and the
  * destination of the input bits is the "din" parameter.  Note that "dout"
  * and "din" can point to the same memory location, in which case the
  * input data overwrites the output data (since both are buffered by
  * temporary variables, this is OK).
  *
  * spi_xfer() interface:
  * @slave:	The SPI slave which will be sending/receiving the data.
  * @bitlen:	How many bits to write and read.
  * @dout:	Pointer to a string of bits to send out.  The bits are
  *		held in a byte array and are sent MSB first.
  * @din:	Pointer to a string of bits that will be filled in.
  * @flags:	A bitwise combination of SPI_XFER_* flags.
  *
  * Returns: 0 on success, not 0 on failure
  */
 int  spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout,
 		void *din, unsigned long flags);
 /**
  * Determine if a SPI chipselect is valid.
  * This function is provided by the board if the low-level SPI driver
  * needs it to determine if a given chipselect is actually valid.
  *
  * Returns: 1 if bus:cs identifies a valid chip on this board, 0
  * otherwise.
  */
 int  spi_cs_is_valid(unsigned int bus, unsigned int cs);
 /**
  * Activate a SPI chipselect.
  * This function is provided by the board code when using a driver
  * that can't control its chipselects automatically (e.g.
  * common/soft_spi.c). When called, it should activate the chip select
  * to the device identified by "slave".
  */
 void spi_cs_activate(struct spi_slave *slave);
 /**
  * Deactivate a SPI chipselect.
  * This function is provided by the board code when using a driver
  * that can't control its chipselects automatically (e.g.
  * common/soft_spi.c). When called, it should deactivate the chip
  * select to the device identified by "slave".
  */
 void spi_cs_deactivate(struct spi_slave *slave);
 /**
  * Set transfer speed.
  * This sets a new speed to be applied for next spi_xfer().
  * @slave:	The SPI slave
  * @hz:		The transfer speed
  */
 void spi_set_speed(struct spi_slave *slave, uint hz);
 /**
  * Write 8 bits, then read 8 bits.
  * @slave:	The SPI slave we're communicating with
  * @byte:	Byte to be written
  *
  * Returns: The value that was read, or a negative value on error.
  *
  * TODO: This function probably shouldn't be inlined.
  */
 static inline int spi_w8r8(struct spi_slave *slave, unsigned char byte)
 {
 	unsigned char dout[2];
 	unsigned char din[2];
 	int ret;
 	dout[0] = byte;
 	dout[1] = 0;
 	ret = spi_xfer(slave, 16, dout, din, SPI_XFER_BEGIN | SPI_XFER_END);
 	return ret < 0 ? ret : din[1];
 }
 /**
  * Set up a SPI slave for a particular device tree node
  *
  * This calls spi_setup_slave() with the correct bus number. Call
  * spi_free_slave() to free it later.
  *
  * @param blob:		Device tree blob
  * @param slave_node:	Slave node to use
  * @param spi_node:	SPI peripheral node to use
  * @return pointer to new spi_slave structure
  */
 struct spi_slave *spi_setup_slave_fdt(const void *blob, int slave_node,
 				      int spi_node);
 /**
  * spi_base_setup_slave_fdt() - helper function to set up a SPI slace
  *
  * This decodes SPI properties from the slave node to determine the
  * chip select and SPI parameters.
  *
  * @blob:	Device tree blob
  * @busnum:	Bus number to use
  * @node:	Device tree node for the SPI bus
  */
 struct spi_slave *spi_base_setup_slave_fdt(const void *blob, int busnum,
 					   int node);
 #endif	/* _SPI_H_ */

include/spi_flash.h

Diff comments View file @ 056fbc7

 /*
  * Common SPI flash Interface
  *
  * Copyright (C) 2008 Atmel Corporation
  * Copyright (C) 2013 Jagannadha Sutradharudu Teki, Xilinx Inc.
  *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License
  * version 2 as published by the Free Software Foundation.
  */
 #ifndef _SPI_FLASH_H_
 #define _SPI_FLASH_H_
 #include <spi.h>
 #include <linux/types.h>
 #include <linux/compiler.h>
 /* sf param flags */
 #define SECT_4K		1 << 1
 #define SECT_32K	1 << 2
 #define E_FSR		1 << 3
 #define WR_QPP		1 << 4
 /* Enum list - Full read commands */
 enum spi_read_cmds {
 	ARRAY_SLOW = 1 << 0,
 	DUAL_OUTPUT_FAST = 1 << 1,
 	DUAL_IO_FAST = 1 << 2,
 	QUAD_OUTPUT_FAST = 1 << 3,
 	QUAD_IO_FAST = 1 << 4,
 };
 #define RD_EXTN		ARRAY_SLOW | DUAL_OUTPUT_FAST | DUAL_IO_FAST
 #define RD_FULL		RD_EXTN | QUAD_OUTPUT_FAST | QUAD_IO_FAST
 /* Dual SPI flash memories */
 enum spi_dual_flash {
 	SF_SINGLE_FLASH = 0,
 	SF_DUAL_STACKED_FLASH = 1 << 0,
+	SF_DUAL_PARALLEL_FLASH = 1 << 1,
 };
 /**
  * struct spi_flash_params - SPI/QSPI flash device params structure
  *
  * @name:		Device name ([MANUFLETTER][DEVTYPE][DENSITY][EXTRAINFO])
  * @jedec:		Device jedec ID (0x[1byte_manuf_id][2byte_dev_id])
  * @ext_jedec:		Device ext_jedec ID
  * @sector_size:	Sector size of this device
  * @nr_sectors:		No.of sectors on this device
  * @e_rd_cmd:		Enum list for read commands
  * @flags:		Importent param, for flash specific behaviour
  */
 struct spi_flash_params {
 	const char *name;
 	u32 jedec;
 	u16 ext_jedec;
 	u32 sector_size;
 	u32 nr_sectors;
 	u8 e_rd_cmd;
 	u16 flags;
 };
 extern const struct spi_flash_params spi_flash_params_table[];
 /**
  * struct spi_flash - SPI flash structure
  *
  * @spi:		SPI slave
  * @name:		Name of SPI flash
- * @dual_flash:		Indicates dual flash memories - dual stacked
+ * @dual_flash:		Indicates dual flash memories - dual stacked, parallel
+ * @shift:		Flash shift useful in dual parallel
  * @size:		Total flash size
  * @page_size:		Write (page) size
  * @sector_size:	Sector size
  * @erase_size:		Erase size
  * @bank_read_cmd:	Bank read cmd
  * @bank_write_cmd:	Bank write cmd
  * @bank_curr:		Current flash bank
  * @poll_cmd:		Poll cmd - for flash erase/program
  * @erase_cmd:		Erase cmd 4K, 32K, 64K
  * @read_cmd:		Read cmd - Array Fast, Extn read and quad read.
  * @write_cmd:		Write cmd - page and quad program.
  * @dummy_byte:		Dummy cycles for read operation.
  * @memory_map:		Address of read-only SPI flash access
  * @read:		Flash read ops: Read len bytes at offset into buf
  *			Supported cmds: Fast Array Read
  * @write:		Flash write ops: Write len bytes from buf into offeset
  *			Supported cmds: Page Program
  * @erase:		Flash erase ops: Erase len bytes from offset
  *			Supported cmds: Sector erase 4K, 32K, 64K
  * return 0 - Sucess, 1 - Failure
  */
 struct spi_flash {
 	struct spi_slave *spi;
 	const char *name;
 	u8 dual_flash;
+	u8 shift;
 	u32 size;
 	u32 page_size;
 	u32 sector_size;
 	u32 erase_size;
 #ifdef CONFIG_SPI_FLASH_BAR
 	u8 bank_read_cmd;
 	u8 bank_write_cmd;
 	u8 bank_curr;
 #endif
 	u8 poll_cmd;
 	u8 erase_cmd;
 	u8 read_cmd;
 	u8 write_cmd;
 	u8 dummy_byte;
 	void *memory_map;
 	int (*read)(struct spi_flash *flash, u32 offset, size_t len, void *buf);
 	int (*write)(struct spi_flash *flash, u32 offset, size_t len,
 			const void *buf);
 	int (*erase)(struct spi_flash *flash, u32 offset, size_t len);
 };
 struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs,
 		unsigned int max_hz, unsigned int spi_mode);
 /**
  * Set up a new SPI flash from an fdt node
  *
  * @param blob		Device tree blob
  * @param slave_node	Pointer to this SPI slave node in the device tree
  * @param spi_node	Cached pointer to the SPI interface this node belongs
  *			to
  * @return 0 if ok, -1 on error
  */
 struct spi_flash *spi_flash_probe_fdt(const void *blob, int slave_node,
 				      int spi_node);
 void spi_flash_free(struct spi_flash *flash);
 static inline int spi_flash_read(struct spi_flash *flash, u32 offset,
 		size_t len, void *buf)
 {
 	return flash->read(flash, offset, len, buf);
 }
 static inline int spi_flash_write(struct spi_flash *flash, u32 offset,
 		size_t len, const void *buf)
 {
 	return flash->write(flash, offset, len, buf);
 }
 static inline int spi_flash_erase(struct spi_flash *flash, u32 offset,
 		size_t len)
 {
 	return flash->erase(flash, offset, len);
 }
 void spi_boot(void) __noreturn;
 #endif /* _SPI_FLASH_H_ */