Eric Lee / smarc-uboot

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Commit 0636b7aa1de19eb6cb6e4bebeeef955c4ee67e51

Authored by Hou Zhiqiang
Committed by Priyanka Jain
1 parent b3a7ea0a13
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

fsl-layerscape: Kconfig: Select RESV_RAM config if GIC_V3_ITS is enabled 

The GIC redistributor tables initialization depends on RESV_RAM config,
so select RESV_RAM if GIC_V3_ITS is enabled.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>

Showing 1 changed file with 4 additions and 0 deletions Inline Diff

arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Diff comments   View file @ 0636b7a
1 config ARCH_LS1012A 1 config ARCH_LS1012A
2 bool 2 bool
3 select ARMV8_SET_SMPEN 3 select ARMV8_SET_SMPEN
4 select ARM_ERRATA_855873 if !TFABOOT 4 select ARM_ERRATA_855873 if !TFABOOT
5 select FSL_LAYERSCAPE 5 select FSL_LAYERSCAPE
6 select FSL_LSCH2 6 select FSL_LSCH2
7 select SYS_FSL_SRDS_1 7 select SYS_FSL_SRDS_1
8 select SYS_HAS_SERDES 8 select SYS_HAS_SERDES
9 select SYS_FSL_DDR_BE 9 select SYS_FSL_DDR_BE
10 select SYS_FSL_MMDC 10 select SYS_FSL_MMDC
11 select SYS_FSL_ERRATUM_A010315 11 select SYS_FSL_ERRATUM_A010315
12 select SYS_FSL_ERRATUM_A009798 12 select SYS_FSL_ERRATUM_A009798
13 select SYS_FSL_ERRATUM_A008997 13 select SYS_FSL_ERRATUM_A008997
14 select SYS_FSL_ERRATUM_A009007 14 select SYS_FSL_ERRATUM_A009007
15 select SYS_FSL_ERRATUM_A009008 15 select SYS_FSL_ERRATUM_A009008
16 select ARCH_EARLY_INIT_R 16 select ARCH_EARLY_INIT_R
17 select BOARD_EARLY_INIT_F 17 select BOARD_EARLY_INIT_F
18 select SYS_I2C_MXC 18 select SYS_I2C_MXC
19 select SYS_I2C_MXC_I2C1 if !DM_I2C 19 select SYS_I2C_MXC_I2C1 if !DM_I2C
20 select SYS_I2C_MXC_I2C2 if !DM_I2C 20 select SYS_I2C_MXC_I2C2 if !DM_I2C
21 imply PANIC_HANG 21 imply PANIC_HANG
22 22
23 config ARCH_LS1028A 23 config ARCH_LS1028A
24 bool 24 bool
25 select ARMV8_SET_SMPEN 25 select ARMV8_SET_SMPEN
26 select FSL_LSCH3 26 select FSL_LSCH3
27 select NXP_LSCH3_2 27 select NXP_LSCH3_2
28 select SYS_FSL_HAS_CCI400 28 select SYS_FSL_HAS_CCI400
29 select SYS_FSL_SRDS_1 29 select SYS_FSL_SRDS_1
30 select SYS_HAS_SERDES 30 select SYS_HAS_SERDES
31 select SYS_FSL_DDR 31 select SYS_FSL_DDR
32 select SYS_FSL_DDR_LE 32 select SYS_FSL_DDR_LE
33 select SYS_FSL_DDR_VER_50 33 select SYS_FSL_DDR_VER_50
34 select SYS_FSL_HAS_DDR3 34 select SYS_FSL_HAS_DDR3
35 select SYS_FSL_HAS_DDR4 35 select SYS_FSL_HAS_DDR4
36 select SYS_FSL_HAS_SEC 36 select SYS_FSL_HAS_SEC
37 select SYS_FSL_SEC_COMPAT_5 37 select SYS_FSL_SEC_COMPAT_5
38 select SYS_FSL_SEC_LE 38 select SYS_FSL_SEC_LE
39 select FSL_TZASC_1 39 select FSL_TZASC_1
40 select ARCH_EARLY_INIT_R 40 select ARCH_EARLY_INIT_R
41 select BOARD_EARLY_INIT_F 41 select BOARD_EARLY_INIT_F
42 select SYS_I2C_MXC 42 select SYS_I2C_MXC
43 select SYS_FSL_ERRATUM_A008997 43 select SYS_FSL_ERRATUM_A008997
44 select SYS_FSL_ERRATUM_A009007 44 select SYS_FSL_ERRATUM_A009007
45 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 45 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
46 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 46 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
47 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 47 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
48 select SYS_FSL_ERRATUM_A050382 48 select SYS_FSL_ERRATUM_A050382
49 select RESV_RAM if GIC_V3_ITS
49 imply PANIC_HANG 50 imply PANIC_HANG
50 51
51 config ARCH_LS1043A 52 config ARCH_LS1043A
52 bool 53 bool
53 select ARMV8_SET_SMPEN 54 select ARMV8_SET_SMPEN
54 select ARM_ERRATA_855873 if !TFABOOT 55 select ARM_ERRATA_855873 if !TFABOOT
55 select FSL_LAYERSCAPE 56 select FSL_LAYERSCAPE
56 select FSL_LSCH2 57 select FSL_LSCH2
57 select SYS_FSL_SRDS_1 58 select SYS_FSL_SRDS_1
58 select SYS_HAS_SERDES 59 select SYS_HAS_SERDES
59 select SYS_FSL_DDR 60 select SYS_FSL_DDR
60 select SYS_FSL_DDR_BE 61 select SYS_FSL_DDR_BE
61 select SYS_FSL_DDR_VER_50 62 select SYS_FSL_DDR_VER_50
62 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 63 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
63 select SYS_FSL_ERRATUM_A008997 64 select SYS_FSL_ERRATUM_A008997
64 select SYS_FSL_ERRATUM_A009007 65 select SYS_FSL_ERRATUM_A009007
65 select SYS_FSL_ERRATUM_A009008 66 select SYS_FSL_ERRATUM_A009008
66 select SYS_FSL_ERRATUM_A009660 if !TFABOOT 67 select SYS_FSL_ERRATUM_A009660 if !TFABOOT
67 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 68 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
68 select SYS_FSL_ERRATUM_A009798 69 select SYS_FSL_ERRATUM_A009798
69 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 70 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
70 select SYS_FSL_ERRATUM_A010315 71 select SYS_FSL_ERRATUM_A010315
71 select SYS_FSL_ERRATUM_A010539 72 select SYS_FSL_ERRATUM_A010539
72 select SYS_FSL_HAS_DDR3 73 select SYS_FSL_HAS_DDR3
73 select SYS_FSL_HAS_DDR4 74 select SYS_FSL_HAS_DDR4
74 select ARCH_EARLY_INIT_R 75 select ARCH_EARLY_INIT_R
75 select BOARD_EARLY_INIT_F 76 select BOARD_EARLY_INIT_F
76 select SYS_I2C_MXC 77 select SYS_I2C_MXC
77 select SYS_I2C_MXC_I2C1 if !DM_I2C 78 select SYS_I2C_MXC_I2C1 if !DM_I2C
78 select SYS_I2C_MXC_I2C2 if !DM_I2C 79 select SYS_I2C_MXC_I2C2 if !DM_I2C
79 select SYS_I2C_MXC_I2C3 if !DM_I2C 80 select SYS_I2C_MXC_I2C3 if !DM_I2C
80 select SYS_I2C_MXC_I2C4 if !DM_I2C 81 select SYS_I2C_MXC_I2C4 if !DM_I2C
81 imply CMD_PCI 82 imply CMD_PCI
82 83
83 config ARCH_LS1046A 84 config ARCH_LS1046A
84 bool 85 bool
85 select ARMV8_SET_SMPEN 86 select ARMV8_SET_SMPEN
86 select FSL_LAYERSCAPE 87 select FSL_LAYERSCAPE
87 select FSL_LSCH2 88 select FSL_LSCH2
88 select SYS_FSL_SRDS_1 89 select SYS_FSL_SRDS_1
89 select SYS_HAS_SERDES 90 select SYS_HAS_SERDES
90 select SYS_FSL_DDR 91 select SYS_FSL_DDR
91 select SYS_FSL_DDR_BE 92 select SYS_FSL_DDR_BE
92 select SYS_FSL_DDR_VER_50 93 select SYS_FSL_DDR_VER_50
93 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 94 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
94 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 95 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
95 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 96 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
96 select SYS_FSL_ERRATUM_A008997 97 select SYS_FSL_ERRATUM_A008997
97 select SYS_FSL_ERRATUM_A009007 98 select SYS_FSL_ERRATUM_A009007
98 select SYS_FSL_ERRATUM_A009008 99 select SYS_FSL_ERRATUM_A009008
99 select SYS_FSL_ERRATUM_A009798 100 select SYS_FSL_ERRATUM_A009798
100 select SYS_FSL_ERRATUM_A009801 101 select SYS_FSL_ERRATUM_A009801
101 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 102 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
102 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 103 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
103 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 104 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
104 select SYS_FSL_ERRATUM_A010539 105 select SYS_FSL_ERRATUM_A010539
105 select SYS_FSL_HAS_DDR4 106 select SYS_FSL_HAS_DDR4
106 select SYS_FSL_SRDS_2 107 select SYS_FSL_SRDS_2
107 select ARCH_EARLY_INIT_R 108 select ARCH_EARLY_INIT_R
108 select BOARD_EARLY_INIT_F 109 select BOARD_EARLY_INIT_F
109 select SYS_I2C_MXC 110 select SYS_I2C_MXC
110 select SYS_I2C_MXC_I2C1 if !DM_I2C 111 select SYS_I2C_MXC_I2C1 if !DM_I2C
111 select SYS_I2C_MXC_I2C2 if !DM_I2C 112 select SYS_I2C_MXC_I2C2 if !DM_I2C
112 select SYS_I2C_MXC_I2C3 if !DM_I2C 113 select SYS_I2C_MXC_I2C3 if !DM_I2C
113 select SYS_I2C_MXC_I2C4 if !DM_I2C 114 select SYS_I2C_MXC_I2C4 if !DM_I2C
114 imply SCSI 115 imply SCSI
115 imply SCSI_AHCI 116 imply SCSI_AHCI
116 117
117 config ARCH_LS1088A 118 config ARCH_LS1088A
118 bool 119 bool
119 select ARMV8_SET_SMPEN 120 select ARMV8_SET_SMPEN
120 select ARM_ERRATA_855873 if !TFABOOT 121 select ARM_ERRATA_855873 if !TFABOOT
121 select FSL_LAYERSCAPE 122 select FSL_LAYERSCAPE
122 select FSL_LSCH3 123 select FSL_LSCH3
123 select SYS_FSL_SRDS_1 124 select SYS_FSL_SRDS_1
124 select SYS_HAS_SERDES 125 select SYS_HAS_SERDES
125 select SYS_FSL_DDR 126 select SYS_FSL_DDR
126 select SYS_FSL_DDR_LE 127 select SYS_FSL_DDR_LE
127 select SYS_FSL_DDR_VER_50 128 select SYS_FSL_DDR_VER_50
128 select SYS_FSL_EC1 129 select SYS_FSL_EC1
129 select SYS_FSL_EC2 130 select SYS_FSL_EC2
130 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 131 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
131 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 132 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
132 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 133 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
133 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 134 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
134 select SYS_FSL_ERRATUM_A008850 if !TFABOOT 135 select SYS_FSL_ERRATUM_A008850 if !TFABOOT
135 select SYS_FSL_ERRATUM_A009007 136 select SYS_FSL_ERRATUM_A009007
136 select SYS_FSL_HAS_CCI400 137 select SYS_FSL_HAS_CCI400
137 select SYS_FSL_HAS_DDR4 138 select SYS_FSL_HAS_DDR4
138 select SYS_FSL_HAS_RGMII 139 select SYS_FSL_HAS_RGMII
139 select SYS_FSL_HAS_SEC 140 select SYS_FSL_HAS_SEC
140 select SYS_FSL_SEC_COMPAT_5 141 select SYS_FSL_SEC_COMPAT_5
141 select SYS_FSL_SEC_LE 142 select SYS_FSL_SEC_LE
142 select SYS_FSL_SRDS_1 143 select SYS_FSL_SRDS_1
143 select SYS_FSL_SRDS_2 144 select SYS_FSL_SRDS_2
144 select FSL_TZASC_1 145 select FSL_TZASC_1
145 select FSL_TZASC_400 146 select FSL_TZASC_400
146 select FSL_TZPC_BP147 147 select FSL_TZPC_BP147
147 select ARCH_EARLY_INIT_R 148 select ARCH_EARLY_INIT_R
148 select BOARD_EARLY_INIT_F 149 select BOARD_EARLY_INIT_F
149 select SYS_I2C_MXC 150 select SYS_I2C_MXC
150 select SYS_I2C_MXC_I2C1 if !TFABOOT 151 select SYS_I2C_MXC_I2C1 if !TFABOOT
151 select SYS_I2C_MXC_I2C2 if !TFABOOT 152 select SYS_I2C_MXC_I2C2 if !TFABOOT
152 select SYS_I2C_MXC_I2C3 if !TFABOOT 153 select SYS_I2C_MXC_I2C3 if !TFABOOT
153 select SYS_I2C_MXC_I2C4 if !TFABOOT 154 select SYS_I2C_MXC_I2C4 if !TFABOOT
155 select RESV_RAM if GIC_V3_ITS
154 imply SCSI 156 imply SCSI
155 imply PANIC_HANG 157 imply PANIC_HANG
156 158
157 config ARCH_LS2080A 159 config ARCH_LS2080A
158 bool 160 bool
159 select ARMV8_SET_SMPEN 161 select ARMV8_SET_SMPEN
160 select ARM_ERRATA_826974 162 select ARM_ERRATA_826974
161 select ARM_ERRATA_828024 163 select ARM_ERRATA_828024
162 select ARM_ERRATA_829520 164 select ARM_ERRATA_829520
163 select ARM_ERRATA_833471 165 select ARM_ERRATA_833471
164 select FSL_LAYERSCAPE 166 select FSL_LAYERSCAPE
165 select FSL_LSCH3 167 select FSL_LSCH3
166 select SYS_FSL_SRDS_1 168 select SYS_FSL_SRDS_1
167 select SYS_HAS_SERDES 169 select SYS_HAS_SERDES
168 select SYS_FSL_DDR 170 select SYS_FSL_DDR
169 select SYS_FSL_DDR_LE 171 select SYS_FSL_DDR_LE
170 select SYS_FSL_DDR_VER_50 172 select SYS_FSL_DDR_VER_50
171 select SYS_FSL_HAS_CCN504 173 select SYS_FSL_HAS_CCN504
172 select SYS_FSL_HAS_DP_DDR 174 select SYS_FSL_HAS_DP_DDR
173 select SYS_FSL_HAS_SEC 175 select SYS_FSL_HAS_SEC
174 select SYS_FSL_HAS_DDR4 176 select SYS_FSL_HAS_DDR4
175 select SYS_FSL_SEC_COMPAT_5 177 select SYS_FSL_SEC_COMPAT_5
176 select SYS_FSL_SEC_LE 178 select SYS_FSL_SEC_LE
177 select SYS_FSL_SRDS_2 179 select SYS_FSL_SRDS_2
178 select FSL_TZASC_1 180 select FSL_TZASC_1
179 select FSL_TZASC_2 181 select FSL_TZASC_2
180 select FSL_TZASC_400 182 select FSL_TZASC_400
181 select FSL_TZPC_BP147 183 select FSL_TZPC_BP147
182 select SYS_FSL_ERRATUM_A008336 if !TFABOOT 184 select SYS_FSL_ERRATUM_A008336 if !TFABOOT
183 select SYS_FSL_ERRATUM_A008511 if !TFABOOT 185 select SYS_FSL_ERRATUM_A008511 if !TFABOOT
184 select SYS_FSL_ERRATUM_A008514 if !TFABOOT 186 select SYS_FSL_ERRATUM_A008514 if !TFABOOT
185 select SYS_FSL_ERRATUM_A008585 187 select SYS_FSL_ERRATUM_A008585
186 select SYS_FSL_ERRATUM_A008997 188 select SYS_FSL_ERRATUM_A008997
187 select SYS_FSL_ERRATUM_A009007 189 select SYS_FSL_ERRATUM_A009007
188 select SYS_FSL_ERRATUM_A009008 190 select SYS_FSL_ERRATUM_A009008
189 select SYS_FSL_ERRATUM_A009635 191 select SYS_FSL_ERRATUM_A009635
190 select SYS_FSL_ERRATUM_A009663 if !TFABOOT 192 select SYS_FSL_ERRATUM_A009663 if !TFABOOT
191 select SYS_FSL_ERRATUM_A009798 193 select SYS_FSL_ERRATUM_A009798
192 select SYS_FSL_ERRATUM_A009801 194 select SYS_FSL_ERRATUM_A009801
193 select SYS_FSL_ERRATUM_A009803 if !TFABOOT 195 select SYS_FSL_ERRATUM_A009803 if !TFABOOT
194 select SYS_FSL_ERRATUM_A009942 if !TFABOOT 196 select SYS_FSL_ERRATUM_A009942 if !TFABOOT
195 select SYS_FSL_ERRATUM_A010165 if !TFABOOT 197 select SYS_FSL_ERRATUM_A010165 if !TFABOOT
196 select SYS_FSL_ERRATUM_A009203 198 select SYS_FSL_ERRATUM_A009203
197 select ARCH_EARLY_INIT_R 199 select ARCH_EARLY_INIT_R
198 select BOARD_EARLY_INIT_F 200 select BOARD_EARLY_INIT_F
199 select SYS_I2C_MXC 201 select SYS_I2C_MXC
200 select SYS_I2C_MXC_I2C1 if !TFABOOT 202 select SYS_I2C_MXC_I2C1 if !TFABOOT
201 select SYS_I2C_MXC_I2C2 if !TFABOOT 203 select SYS_I2C_MXC_I2C2 if !TFABOOT
202 select SYS_I2C_MXC_I2C3 if !TFABOOT 204 select SYS_I2C_MXC_I2C3 if !TFABOOT
203 select SYS_I2C_MXC_I2C4 if !TFABOOT 205 select SYS_I2C_MXC_I2C4 if !TFABOOT
206 select RESV_RAM if GIC_V3_ITS
204 imply DISTRO_DEFAULTS 207 imply DISTRO_DEFAULTS
205 imply PANIC_HANG 208 imply PANIC_HANG
206 209
207 config ARCH_LX2162A 210 config ARCH_LX2162A
208 bool 211 bool
209 select ARMV8_SET_SMPEN 212 select ARMV8_SET_SMPEN
210 select FSL_LSCH3 213 select FSL_LSCH3
211 select NXP_LSCH3_2 214 select NXP_LSCH3_2
212 select SYS_HAS_SERDES 215 select SYS_HAS_SERDES
213 select SYS_FSL_SRDS_1 216 select SYS_FSL_SRDS_1
214 select SYS_FSL_SRDS_2 217 select SYS_FSL_SRDS_2
215 select SYS_FSL_DDR 218 select SYS_FSL_DDR
216 select SYS_FSL_DDR_LE 219 select SYS_FSL_DDR_LE
217 select SYS_FSL_DDR_VER_50 220 select SYS_FSL_DDR_VER_50
218 select SYS_FSL_EC1 221 select SYS_FSL_EC1
219 select SYS_FSL_EC2 222 select SYS_FSL_EC2
220 select SYS_FSL_ERRATUM_A050106 223 select SYS_FSL_ERRATUM_A050106
221 select SYS_FSL_HAS_RGMII 224 select SYS_FSL_HAS_RGMII
222 select SYS_FSL_HAS_SEC 225 select SYS_FSL_HAS_SEC
223 select SYS_FSL_HAS_CCN508 226 select SYS_FSL_HAS_CCN508
224 select SYS_FSL_HAS_DDR4 227 select SYS_FSL_HAS_DDR4
225 select SYS_FSL_SEC_COMPAT_5 228 select SYS_FSL_SEC_COMPAT_5
226 select SYS_FSL_SEC_LE 229 select SYS_FSL_SEC_LE
227 select ARCH_EARLY_INIT_R 230 select ARCH_EARLY_INIT_R
228 select BOARD_EARLY_INIT_F 231 select BOARD_EARLY_INIT_F
229 select SYS_I2C_MXC 232 select SYS_I2C_MXC
233 select RESV_RAM if GIC_V3_ITS
230 imply DISTRO_DEFAULTS 234 imply DISTRO_DEFAULTS
231 imply PANIC_HANG 235 imply PANIC_HANG
232 imply SCSI 236 imply SCSI
233 imply SCSI_AHCI 237 imply SCSI_AHCI
234 238
235 config ARCH_LX2160A 239 config ARCH_LX2160A
236 bool 240 bool
237 select ARMV8_SET_SMPEN 241 select ARMV8_SET_SMPEN
238 select FSL_LSCH3 242 select FSL_LSCH3
239 select NXP_LSCH3_2 243 select NXP_LSCH3_2
240 select SYS_HAS_SERDES 244 select SYS_HAS_SERDES
241 select SYS_FSL_SRDS_1 245 select SYS_FSL_SRDS_1
242 select SYS_FSL_SRDS_2 246 select SYS_FSL_SRDS_2
243 select SYS_NXP_SRDS_3 247 select SYS_NXP_SRDS_3
244 select SYS_FSL_DDR 248 select SYS_FSL_DDR
245 select SYS_FSL_DDR_LE 249 select SYS_FSL_DDR_LE
246 select SYS_FSL_DDR_VER_50 250 select SYS_FSL_DDR_VER_50
247 select SYS_FSL_EC1 251 select SYS_FSL_EC1
248 select SYS_FSL_EC2 252 select SYS_FSL_EC2
249 select SYS_FSL_ERRATUM_A050106 253 select SYS_FSL_ERRATUM_A050106
250 select SYS_FSL_HAS_RGMII 254 select SYS_FSL_HAS_RGMII
251 select SYS_FSL_HAS_SEC 255 select SYS_FSL_HAS_SEC
252 select SYS_FSL_HAS_CCN508 256 select SYS_FSL_HAS_CCN508
253 select SYS_FSL_HAS_DDR4 257 select SYS_FSL_HAS_DDR4
254 select SYS_FSL_SEC_COMPAT_5 258 select SYS_FSL_SEC_COMPAT_5
255 select SYS_FSL_SEC_LE 259 select SYS_FSL_SEC_LE
256 select ARCH_EARLY_INIT_R 260 select ARCH_EARLY_INIT_R
257 select BOARD_EARLY_INIT_F 261 select BOARD_EARLY_INIT_F
258 select SYS_I2C_MXC 262 select SYS_I2C_MXC
259 imply DISTRO_DEFAULTS 263 imply DISTRO_DEFAULTS
260 imply PANIC_HANG 264 imply PANIC_HANG
261 imply SCSI 265 imply SCSI
262 imply SCSI_AHCI 266 imply SCSI_AHCI
263 267
264 config FSL_LSCH2 268 config FSL_LSCH2
265 bool 269 bool
266 select SYS_FSL_HAS_CCI400 270 select SYS_FSL_HAS_CCI400
267 select SYS_FSL_HAS_SEC 271 select SYS_FSL_HAS_SEC
268 select SYS_FSL_SEC_COMPAT_5 272 select SYS_FSL_SEC_COMPAT_5
269 select SYS_FSL_SEC_BE 273 select SYS_FSL_SEC_BE
270 274
271 config FSL_LSCH3 275 config FSL_LSCH3
272 select ARCH_MISC_INIT 276 select ARCH_MISC_INIT
273 bool 277 bool
274 278
275 config NXP_LSCH3_2 279 config NXP_LSCH3_2
276 bool 280 bool
277 281
278 menu "Layerscape architecture" 282 menu "Layerscape architecture"
279 depends on FSL_LSCH2 || FSL_LSCH3 283 depends on FSL_LSCH2 || FSL_LSCH3
280 284
281 config FSL_LAYERSCAPE 285 config FSL_LAYERSCAPE
282 bool 286 bool
283 287
284 config HAS_FEATURE_GIC64K_ALIGN 288 config HAS_FEATURE_GIC64K_ALIGN
285 bool 289 bool
286 default y if ARCH_LS1043A 290 default y if ARCH_LS1043A
287 291
288 config HAS_FEATURE_ENHANCED_MSI 292 config HAS_FEATURE_ENHANCED_MSI
289 bool 293 bool
290 default y if ARCH_LS1043A 294 default y if ARCH_LS1043A
291 295
292 menu "Layerscape PPA" 296 menu "Layerscape PPA"
293 config FSL_LS_PPA 297 config FSL_LS_PPA
294 bool "FSL Layerscape PPA firmware support" 298 bool "FSL Layerscape PPA firmware support"
295 depends on !ARMV8_PSCI 299 depends on !ARMV8_PSCI
296 select ARMV8_SEC_FIRMWARE_SUPPORT 300 select ARMV8_SEC_FIRMWARE_SUPPORT
297 select SEC_FIRMWARE_ARMV8_PSCI 301 select SEC_FIRMWARE_ARMV8_PSCI
298 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 302 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
299 help 303 help
300 The FSL Primary Protected Application (PPA) is a software component 304 The FSL Primary Protected Application (PPA) is a software component
301 which is loaded during boot stage, and then remains resident in RAM 305 which is loaded during boot stage, and then remains resident in RAM
302 and runs in the TrustZone after boot. 306 and runs in the TrustZone after boot.
303 Say y to enable it. 307 Say y to enable it.
304 308
305 config SPL_FSL_LS_PPA 309 config SPL_FSL_LS_PPA
306 bool "FSL Layerscape PPA firmware support for SPL build" 310 bool "FSL Layerscape PPA firmware support for SPL build"
307 depends on !ARMV8_PSCI 311 depends on !ARMV8_PSCI
308 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT 312 select SPL_ARMV8_SEC_FIRMWARE_SUPPORT
309 select SEC_FIRMWARE_ARMV8_PSCI 313 select SEC_FIRMWARE_ARMV8_PSCI
310 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2 314 select ARMV8_SEC_FIRMWARE_ERET_ADDR_REVERT if FSL_LSCH2
311 help 315 help
312 The FSL Primary Protected Application (PPA) is a software component 316 The FSL Primary Protected Application (PPA) is a software component
313 which is loaded during boot stage, and then remains resident in RAM 317 which is loaded during boot stage, and then remains resident in RAM
314 and runs in the TrustZone after boot. This is to load PPA during SPL 318 and runs in the TrustZone after boot. This is to load PPA during SPL
315 stage instead of the RAM version of U-Boot. Once PPA is initialized, 319 stage instead of the RAM version of U-Boot. Once PPA is initialized,
316 the rest of U-Boot (including RAM version) runs at EL2. 320 the rest of U-Boot (including RAM version) runs at EL2.
317 choice 321 choice
318 prompt "FSL Layerscape PPA firmware loading-media select" 322 prompt "FSL Layerscape PPA firmware loading-media select"
319 depends on FSL_LS_PPA 323 depends on FSL_LS_PPA
320 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT 324 default SYS_LS_PPA_FW_IN_MMC if SD_BOOT
321 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT 325 default SYS_LS_PPA_FW_IN_NAND if NAND_BOOT
322 default SYS_LS_PPA_FW_IN_XIP 326 default SYS_LS_PPA_FW_IN_XIP
323 327
324 config SYS_LS_PPA_FW_IN_XIP 328 config SYS_LS_PPA_FW_IN_XIP
325 bool "XIP" 329 bool "XIP"
326 help 330 help
327 Say Y here if the PPA firmware locate at XIP flash, such 331 Say Y here if the PPA firmware locate at XIP flash, such
328 as NOR or QSPI flash. 332 as NOR or QSPI flash.
329 333
330 config SYS_LS_PPA_FW_IN_MMC 334 config SYS_LS_PPA_FW_IN_MMC
331 bool "eMMC or SD Card" 335 bool "eMMC or SD Card"
332 help 336 help
333 Say Y here if the PPA firmware locate at eMMC/SD card. 337 Say Y here if the PPA firmware locate at eMMC/SD card.
334 338
335 config SYS_LS_PPA_FW_IN_NAND 339 config SYS_LS_PPA_FW_IN_NAND
336 bool "NAND" 340 bool "NAND"
337 help 341 help
338 Say Y here if the PPA firmware locate at NAND flash. 342 Say Y here if the PPA firmware locate at NAND flash.
339 343
340 endchoice 344 endchoice
341 345
342 config LS_PPA_ESBC_HDR_SIZE 346 config LS_PPA_ESBC_HDR_SIZE
343 hex "Length of PPA ESBC header" 347 hex "Length of PPA ESBC header"
344 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP 348 depends on FSL_LS_PPA && CHAIN_OF_TRUST && !SYS_LS_PPA_FW_IN_XIP
345 default 0x2000 349 default 0x2000
346 help 350 help
347 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or 351 Length (in bytes) of PPA ESBC header to be copied from MMC/SD or
348 NAND to memory to validate PPA image. 352 NAND to memory to validate PPA image.
349 353
350 endmenu 354 endmenu
351 355
352 config SYS_FSL_ERRATUM_A008997 356 config SYS_FSL_ERRATUM_A008997
353 bool "Workaround for USB PHY erratum A008997" 357 bool "Workaround for USB PHY erratum A008997"
354 358
355 config SYS_FSL_ERRATUM_A009007 359 config SYS_FSL_ERRATUM_A009007
356 bool 360 bool
357 help 361 help
358 Workaround for USB PHY erratum A009007 362 Workaround for USB PHY erratum A009007
359 363
360 config SYS_FSL_ERRATUM_A009008 364 config SYS_FSL_ERRATUM_A009008
361 bool "Workaround for USB PHY erratum A009008" 365 bool "Workaround for USB PHY erratum A009008"
362 366
363 config SYS_FSL_ERRATUM_A009798 367 config SYS_FSL_ERRATUM_A009798
364 bool "Workaround for USB PHY erratum A009798" 368 bool "Workaround for USB PHY erratum A009798"
365 369
366 config SYS_FSL_ERRATUM_A050106 370 config SYS_FSL_ERRATUM_A050106
367 bool "Workaround for USB PHY erratum A050106" 371 bool "Workaround for USB PHY erratum A050106"
368 help 372 help
369 USB3.0 Receiver needs to enable fixed equalization 373 USB3.0 Receiver needs to enable fixed equalization
370 for each of PHY instances in an SOC. This is similar 374 for each of PHY instances in an SOC. This is similar
371 to erratum A-009007, but this one is for LX2160A and LX2162A, 375 to erratum A-009007, but this one is for LX2160A and LX2162A,
372 and the register value is different. 376 and the register value is different.
373 377
374 config SYS_FSL_ERRATUM_A010315 378 config SYS_FSL_ERRATUM_A010315
375 bool "Workaround for PCIe erratum A010315" 379 bool "Workaround for PCIe erratum A010315"
376 380
377 config SYS_FSL_ERRATUM_A010539 381 config SYS_FSL_ERRATUM_A010539
378 bool "Workaround for PIN MUX erratum A010539" 382 bool "Workaround for PIN MUX erratum A010539"
379 383
380 config MAX_CPUS 384 config MAX_CPUS
381 int "Maximum number of CPUs permitted for Layerscape" 385 int "Maximum number of CPUs permitted for Layerscape"
382 default 2 if ARCH_LS1028A 386 default 2 if ARCH_LS1028A
383 default 4 if ARCH_LS1043A 387 default 4 if ARCH_LS1043A
384 default 4 if ARCH_LS1046A 388 default 4 if ARCH_LS1046A
385 default 16 if ARCH_LS2080A 389 default 16 if ARCH_LS2080A
386 default 8 if ARCH_LS1088A 390 default 8 if ARCH_LS1088A
387 default 16 if ARCH_LX2160A 391 default 16 if ARCH_LX2160A
388 default 16 if ARCH_LX2162A 392 default 16 if ARCH_LX2162A
389 default 1 393 default 1
390 help 394 help
391 Set this number to the maximum number of possible CPUs in the SoC. 395 Set this number to the maximum number of possible CPUs in the SoC.
392 SoCs may have multiple clusters with each cluster may have multiple 396 SoCs may have multiple clusters with each cluster may have multiple
393 ports. If some ports are reserved but higher ports are used for 397 ports. If some ports are reserved but higher ports are used for
394 cores, count the reserved ports. This will allocate enough memory 398 cores, count the reserved ports. This will allocate enough memory
395 in spin table to properly handle all cores. 399 in spin table to properly handle all cores.
396 400
397 config EMC2305 401 config EMC2305
398 bool "Fan controller" 402 bool "Fan controller"
399 help 403 help
400 Enable the EMC2305 fan controller for configuration of fan 404 Enable the EMC2305 fan controller for configuration of fan
401 speed. 405 speed.
402 406
403 config NXP_ESBC 407 config NXP_ESBC
404 bool "NXP_ESBC" 408 bool "NXP_ESBC"
405 help 409 help
406 Enable Freescale Secure Boot feature 410 Enable Freescale Secure Boot feature
407 411
408 config QSPI_AHB_INIT 412 config QSPI_AHB_INIT
409 bool "Init the QSPI AHB bus" 413 bool "Init the QSPI AHB bus"
410 help 414 help
411 The default setting for QSPI AHB bus just support 3bytes addressing. 415 The default setting for QSPI AHB bus just support 3bytes addressing.
412 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB 416 But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
413 bus for those flashes to support the full QSPI flash size. 417 bus for those flashes to support the full QSPI flash size.
414 418
415 config FSPI_AHB_EN_4BYTE 419 config FSPI_AHB_EN_4BYTE
416 bool "Enable 4-byte Fast Read command for AHB mode" 420 bool "Enable 4-byte Fast Read command for AHB mode"
417 default n 421 default n
418 help 422 help
419 The default setting for FlexSPI AHB bus just supports 3-byte addressing. 423 The default setting for FlexSPI AHB bus just supports 3-byte addressing.
420 But some FlexSPI flash sizes are up to 64MBytes. 424 But some FlexSPI flash sizes are up to 64MBytes.
421 This flag enables fast read command for AHB mode and modifies required 425 This flag enables fast read command for AHB mode and modifies required
422 LUT to support full FlexSPI flash. 426 LUT to support full FlexSPI flash.
423 427
424 config SYS_CCI400_OFFSET 428 config SYS_CCI400_OFFSET
425 hex "Offset for CCI400 base" 429 hex "Offset for CCI400 base"
426 depends on SYS_FSL_HAS_CCI400 430 depends on SYS_FSL_HAS_CCI400
427 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A 431 default 0x3090000 if ARCH_LS1088A || ARCH_LS1028A
428 default 0x180000 if FSL_LSCH2 432 default 0x180000 if FSL_LSCH2
429 help 433 help
430 Offset for CCI400 base 434 Offset for CCI400 base
431 CCI400 base addr = CCSRBAR + CCI400_OFFSET 435 CCI400 base addr = CCSRBAR + CCI400_OFFSET
432 436
433 config SYS_FSL_IFC_BANK_COUNT 437 config SYS_FSL_IFC_BANK_COUNT
434 int "Maximum banks of Integrated flash controller" 438 int "Maximum banks of Integrated flash controller"
435 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A 439 depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A || ARCH_LS1088A
436 default 4 if ARCH_LS1043A 440 default 4 if ARCH_LS1043A
437 default 4 if ARCH_LS1046A 441 default 4 if ARCH_LS1046A
438 default 8 if ARCH_LS2080A || ARCH_LS1088A 442 default 8 if ARCH_LS2080A || ARCH_LS1088A
439 443
440 config SYS_FSL_HAS_CCI400 444 config SYS_FSL_HAS_CCI400
441 bool 445 bool
442 446
443 config SYS_FSL_HAS_CCN504 447 config SYS_FSL_HAS_CCN504
444 bool 448 bool
445 449
446 config SYS_FSL_HAS_CCN508 450 config SYS_FSL_HAS_CCN508
447 bool 451 bool
448 452
449 config SYS_FSL_HAS_DP_DDR 453 config SYS_FSL_HAS_DP_DDR
450 bool 454 bool
451 455
452 config SYS_FSL_SRDS_1 456 config SYS_FSL_SRDS_1
453 bool 457 bool
454 458
455 config SYS_FSL_SRDS_2 459 config SYS_FSL_SRDS_2
456 bool 460 bool
457 461
458 config SYS_NXP_SRDS_3 462 config SYS_NXP_SRDS_3
459 bool 463 bool
460 464
461 config SYS_HAS_SERDES 465 config SYS_HAS_SERDES
462 bool 466 bool
463 467
464 config FSL_TZASC_1 468 config FSL_TZASC_1
465 bool 469 bool
466 470
467 config FSL_TZASC_2 471 config FSL_TZASC_2
468 bool 472 bool
469 473
470 config FSL_TZASC_400 474 config FSL_TZASC_400
471 bool 475 bool
472 476
473 config FSL_TZPC_BP147 477 config FSL_TZPC_BP147
474 bool 478 bool
475 endmenu 479 endmenu
476 480
477 menu "Layerscape clock tree configuration" 481 menu "Layerscape clock tree configuration"
478 depends on FSL_LSCH2 || FSL_LSCH3 482 depends on FSL_LSCH2 || FSL_LSCH3
479 483
480 config SYS_FSL_CLK 484 config SYS_FSL_CLK
481 bool "Enable clock tree initialization" 485 bool "Enable clock tree initialization"
482 default y 486 default y
483 487
484 config CLUSTER_CLK_FREQ 488 config CLUSTER_CLK_FREQ
485 int "Reference clock of core cluster" 489 int "Reference clock of core cluster"
486 depends on ARCH_LS1012A 490 depends on ARCH_LS1012A
487 default 100000000 491 default 100000000
488 help 492 help
489 This number is the reference clock frequency of core PLL. 493 This number is the reference clock frequency of core PLL.
490 For most platforms, the core PLL and Platform PLL have the same 494 For most platforms, the core PLL and Platform PLL have the same
491 reference clock, but for some platforms, LS1012A for instance, 495 reference clock, but for some platforms, LS1012A for instance,
492 they are provided sepatately. 496 they are provided sepatately.
493 497
494 config SYS_FSL_PCLK_DIV 498 config SYS_FSL_PCLK_DIV
495 int "Platform clock divider" 499 int "Platform clock divider"
496 default 1 if ARCH_LS1028A 500 default 1 if ARCH_LS1028A
497 default 1 if ARCH_LS1043A 501 default 1 if ARCH_LS1043A
498 default 1 if ARCH_LS1046A 502 default 1 if ARCH_LS1046A
499 default 1 if ARCH_LS1088A 503 default 1 if ARCH_LS1088A
500 default 2 504 default 2
501 help 505 help
502 This is the divider that is used to derive Platform clock from 506 This is the divider that is used to derive Platform clock from
503 Platform PLL, in another word: 507 Platform PLL, in another word:
504 Platform_clk = Platform_PLL_freq / this_divider 508 Platform_clk = Platform_PLL_freq / this_divider
505 509
506 config SYS_FSL_DSPI_CLK_DIV 510 config SYS_FSL_DSPI_CLK_DIV
507 int "DSPI clock divider" 511 int "DSPI clock divider"
508 default 1 if ARCH_LS1043A 512 default 1 if ARCH_LS1043A
509 default 2 513 default 2
510 help 514 help
511 This is the divider that is used to derive DSPI clock from Platform 515 This is the divider that is used to derive DSPI clock from Platform
512 clock, in another word DSPI_clk = Platform_clk / this_divider. 516 clock, in another word DSPI_clk = Platform_clk / this_divider.
513 517
514 config SYS_FSL_DUART_CLK_DIV 518 config SYS_FSL_DUART_CLK_DIV
515 int "DUART clock divider" 519 int "DUART clock divider"
516 default 1 if ARCH_LS1043A 520 default 1 if ARCH_LS1043A
517 default 4 if ARCH_LX2160A 521 default 4 if ARCH_LX2160A
518 default 4 if ARCH_LX2162A 522 default 4 if ARCH_LX2162A
519 default 2 523 default 2
520 help 524 help
521 This is the divider that is used to derive DUART clock from Platform 525 This is the divider that is used to derive DUART clock from Platform
522 clock, in another word DUART_clk = Platform_clk / this_divider. 526 clock, in another word DUART_clk = Platform_clk / this_divider.
523 527
524 config SYS_FSL_I2C_CLK_DIV 528 config SYS_FSL_I2C_CLK_DIV
525 int "I2C clock divider" 529 int "I2C clock divider"
526 default 1 if ARCH_LS1043A 530 default 1 if ARCH_LS1043A
527 default 4 if ARCH_LS1012A 531 default 4 if ARCH_LS1012A
528 default 4 if ARCH_LS1028A 532 default 4 if ARCH_LS1028A
529 default 8 if ARCH_LX2160A 533 default 8 if ARCH_LX2160A
530 default 8 if ARCH_LX2162A 534 default 8 if ARCH_LX2162A
531 default 8 if ARCH_LS1088A 535 default 8 if ARCH_LS1088A
532 default 2 536 default 2
533 help 537 help
534 This is the divider that is used to derive I2C clock from Platform 538 This is the divider that is used to derive I2C clock from Platform
535 clock, in another word I2C_clk = Platform_clk / this_divider. 539 clock, in another word I2C_clk = Platform_clk / this_divider.
536 540
537 config SYS_FSL_IFC_CLK_DIV 541 config SYS_FSL_IFC_CLK_DIV
538 int "IFC clock divider" 542 int "IFC clock divider"
539 default 1 if ARCH_LS1043A 543 default 1 if ARCH_LS1043A
540 default 4 if ARCH_LS1012A 544 default 4 if ARCH_LS1012A
541 default 4 if ARCH_LS1028A 545 default 4 if ARCH_LS1028A
542 default 8 if ARCH_LX2160A 546 default 8 if ARCH_LX2160A
543 default 8 if ARCH_LX2162A 547 default 8 if ARCH_LX2162A
544 default 8 if ARCH_LS1088A 548 default 8 if ARCH_LS1088A
545 default 2 549 default 2
546 help 550 help
547 This is the divider that is used to derive IFC clock from Platform 551 This is the divider that is used to derive IFC clock from Platform
548 clock, in another word IFC_clk = Platform_clk / this_divider. 552 clock, in another word IFC_clk = Platform_clk / this_divider.
549 553
550 config SYS_FSL_LPUART_CLK_DIV 554 config SYS_FSL_LPUART_CLK_DIV
551 int "LPUART clock divider" 555 int "LPUART clock divider"
552 default 1 if ARCH_LS1043A 556 default 1 if ARCH_LS1043A
553 default 2 557 default 2
554 help 558 help
555 This is the divider that is used to derive LPUART clock from Platform 559 This is the divider that is used to derive LPUART clock from Platform
556 clock, in another word LPUART_clk = Platform_clk / this_divider. 560 clock, in another word LPUART_clk = Platform_clk / this_divider.
557 561
558 config SYS_FSL_SDHC_CLK_DIV 562 config SYS_FSL_SDHC_CLK_DIV
559 int "SDHC clock divider" 563 int "SDHC clock divider"
560 default 1 if ARCH_LS1043A 564 default 1 if ARCH_LS1043A
561 default 1 if ARCH_LS1012A 565 default 1 if ARCH_LS1012A
562 default 2 566 default 2
563 help 567 help
564 This is the divider that is used to derive SDHC clock from Platform 568 This is the divider that is used to derive SDHC clock from Platform
565 clock, in another word SDHC_clk = Platform_clk / this_divider. 569 clock, in another word SDHC_clk = Platform_clk / this_divider.
566 570
567 config SYS_FSL_QMAN_CLK_DIV 571 config SYS_FSL_QMAN_CLK_DIV
568 int "QMAN clock divider" 572 int "QMAN clock divider"
569 default 1 if ARCH_LS1043A 573 default 1 if ARCH_LS1043A
570 default 2 574 default 2
571 help 575 help
572 This is the divider that is used to derive QMAN clock from Platform 576 This is the divider that is used to derive QMAN clock from Platform
573 clock, in another word QMAN_clk = Platform_clk / this_divider. 577 clock, in another word QMAN_clk = Platform_clk / this_divider.
574 endmenu 578 endmenu
575 579
576 config RESV_RAM 580 config RESV_RAM
577 bool 581 bool
578 help 582 help
579 Reserve memory from the top, tracked by gd->arch.resv_ram. This 583 Reserve memory from the top, tracked by gd->arch.resv_ram. This
580 reserved RAM can be used by special driver that resides in memory 584 reserved RAM can be used by special driver that resides in memory
581 after U-Boot exits. It's up to implementation to allocate and allow 585 after U-Boot exits. It's up to implementation to allocate and allow
582 access to this reserved memory. For example, the reserved RAM can 586 access to this reserved memory. For example, the reserved RAM can
583 be at the high end of physical memory. The reserve RAM may be 587 be at the high end of physical memory. The reserve RAM may be
584 excluded from memory bank(s) passed to OS, or marked as reserved. 588 excluded from memory bank(s) passed to OS, or marked as reserved.
585 589
586 config SYS_FSL_EC1 590 config SYS_FSL_EC1
587 bool 591 bool
588 help 592 help
589 Ethernet controller 1, this is connected to 593 Ethernet controller 1, this is connected to
590 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs 594 MAC17 for LX2160A and LX2162A or to MAC3 for other SoCs
591 Provides DPAA2 capabilities 595 Provides DPAA2 capabilities
592 596
593 config SYS_FSL_EC2 597 config SYS_FSL_EC2
594 bool 598 bool
595 help 599 help
596 Ethernet controller 2, this is connected to 600 Ethernet controller 2, this is connected to
597 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs 601 MAC18 for LX2160A and LX2162A or to MAC4 for other SoCs
598 Provides DPAA2 capabilities 602 Provides DPAA2 capabilities
599 603
600 config SYS_FSL_ERRATUM_A008336 604 config SYS_FSL_ERRATUM_A008336
601 bool 605 bool
602 606
603 config SYS_FSL_ERRATUM_A008514 607 config SYS_FSL_ERRATUM_A008514
604 bool 608 bool
605 609
606 config SYS_FSL_ERRATUM_A008585 610 config SYS_FSL_ERRATUM_A008585
607 bool 611 bool
608 612
609 config SYS_FSL_ERRATUM_A008850 613 config SYS_FSL_ERRATUM_A008850
610 bool 614 bool
611 615
612 config SYS_FSL_ERRATUM_A009203 616 config SYS_FSL_ERRATUM_A009203
613 bool 617 bool
614 618
615 config SYS_FSL_ERRATUM_A009635 619 config SYS_FSL_ERRATUM_A009635
616 bool 620 bool
617 621
618 config SYS_FSL_ERRATUM_A009660 622 config SYS_FSL_ERRATUM_A009660
619 bool 623 bool
620 624
621 config SYS_FSL_ERRATUM_A050382 625 config SYS_FSL_ERRATUM_A050382
622 bool 626 bool
623 627
624 config SYS_FSL_HAS_RGMII 628 config SYS_FSL_HAS_RGMII
625 bool 629 bool
626 depends on SYS_FSL_EC1 || SYS_FSL_EC2 630 depends on SYS_FSL_EC1 || SYS_FSL_EC2
627 631
628 config SPL_LDSCRIPT 632 config SPL_LDSCRIPT
629 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A 633 default "arch/arm/cpu/armv8/u-boot-spl.lds" if ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A
630 634
631 config HAS_FSL_XHCI_USB 635 config HAS_FSL_XHCI_USB
632 bool 636 bool
633 default y if ARCH_LS1043A || ARCH_LS1046A 637 default y if ARCH_LS1043A || ARCH_LS1046A
634 help 638 help
635 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use 639 For some SoC(such as LS1043A and LS1046A), USB and QE-HDLC multiplex use
636 pins, select it when the pins are assigned to USB. 640 pins, select it when the pins are assigned to USB.
637 641