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Commit 120503f32e1dcad3069633d6319d5d6c37e65c08

Authored by Dan Murphy
Committed by Marek Vasut
1 parent d3d037ae18
Exists in master and in 53 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ARM: OMAP: USB: Fix linker error when ULPI is not defined 

Fix the linker error for missing ulpi_reset when ulpi is not defined
in the board config.

Signed-off-by: Dan Murphy <dmurphy@ti.com>
Acked-by: Marek Vasut <marex@denx.de>

Showing 1 changed file with 7 additions and 0 deletions Inline Diff

drivers/usb/host/ehci-omap.c
Diff comments   View file @ 120503f
1 /* 1 /*
2 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems 2 * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
3 * (C) Copyright 2004-2008 3 * (C) Copyright 2004-2008
4 * Texas Instruments, <www.ti.com> 4 * Texas Instruments, <www.ti.com>
5 * 5 *
6 * Derived from Beagle Board code by 6 * Derived from Beagle Board code by
7 * Sunil Kumar <sunilsaini05@gmail.com> 7 * Sunil Kumar <sunilsaini05@gmail.com>
8 * Shashi Ranjan <shashiranjanmca05@gmail.com> 8 * Shashi Ranjan <shashiranjanmca05@gmail.com>
9 * 9 *
10 * 10 *
11 * SPDX-License-Identifier: GPL-2.0+ 11 * SPDX-License-Identifier: GPL-2.0+
12 */ 12 */
13 13
14 #include <common.h> 14 #include <common.h>
15 #include <usb.h> 15 #include <usb.h>
16 #include <usb/ulpi.h> 16 #include <usb/ulpi.h>
17 #include <errno.h> 17 #include <errno.h>
18 #include <asm/io.h> 18 #include <asm/io.h>
19 #include <asm/gpio.h> 19 #include <asm/gpio.h>
20 #include <asm/arch/ehci.h> 20 #include <asm/arch/ehci.h>
21 #include <asm/ehci-omap.h> 21 #include <asm/ehci-omap.h>
22 22
23 #include "ehci.h" 23 #include "ehci.h"
24 24
25 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE; 25 static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
26 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE; 26 static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
27 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE; 27 static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
28 28
29 static int omap_uhh_reset(void) 29 static int omap_uhh_reset(void)
30 { 30 {
31 /* 31 /*
32 * Soft resetting the UHH module causes instability issues on 32 * Soft resetting the UHH module causes instability issues on
33 * all OMAPs so we just avoid it. 33 * all OMAPs so we just avoid it.
34 * 34 *
35 * See OMAP36xx Errata 35 * See OMAP36xx Errata
36 * i571: USB host EHCI may stall when entering smart-standby mode 36 * i571: USB host EHCI may stall when entering smart-standby mode
37 * i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock 37 * i660: USBHOST Configured In Smart-Idle Can Lead To a Deadlock
38 * 38 *
39 * On OMAP4/5, soft-resetting the UHH module will put it into 39 * On OMAP4/5, soft-resetting the UHH module will put it into
40 * Smart-Idle mode and lead to a deadlock. 40 * Smart-Idle mode and lead to a deadlock.
41 * 41 *
42 * On OMAP3, this doesn't seem to be the case but still instabilities 42 * On OMAP3, this doesn't seem to be the case but still instabilities
43 * are observed on beagle (3530 ES1.0) if soft-reset is used. 43 * are observed on beagle (3530 ES1.0) if soft-reset is used.
44 * e.g. NFS root failures with Linux kernel. 44 * e.g. NFS root failures with Linux kernel.
45 */ 45 */
46 return 0; 46 return 0;
47 } 47 }
48 48
49 static int omap_ehci_tll_reset(void) 49 static int omap_ehci_tll_reset(void)
50 { 50 {
51 unsigned long init = get_timer(0); 51 unsigned long init = get_timer(0);
52 52
53 /* perform TLL soft reset, and wait until reset is complete */ 53 /* perform TLL soft reset, and wait until reset is complete */
54 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc); 54 writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
55 55
56 /* Wait for TLL reset to complete */ 56 /* Wait for TLL reset to complete */
57 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE)) 57 while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
58 if (get_timer(init) > CONFIG_SYS_HZ) { 58 if (get_timer(init) > CONFIG_SYS_HZ) {
59 debug("OMAP EHCI error: timeout resetting TLL\n"); 59 debug("OMAP EHCI error: timeout resetting TLL\n");
60 return -EL3RST; 60 return -EL3RST;
61 } 61 }
62 62
63 return 0; 63 return 0;
64 } 64 }
65 65
66 static void omap_usbhs_hsic_init(int port) 66 static void omap_usbhs_hsic_init(int port)
67 { 67 {
68 unsigned int reg; 68 unsigned int reg;
69 69
70 /* Enable channels now */ 70 /* Enable channels now */
71 reg = readl(&usbtll->channel_conf + port); 71 reg = readl(&usbtll->channel_conf + port);
72 72
73 setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI 73 setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
74 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF 74 | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
75 | OMAP_TLL_CHANNEL_CONF_DRVVBUS 75 | OMAP_TLL_CHANNEL_CONF_DRVVBUS
76 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS 76 | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
77 | OMAP_TLL_CHANNEL_CONF_CHANEN)); 77 | OMAP_TLL_CHANNEL_CONF_CHANEN));
78 78
79 writel(reg, &usbtll->channel_conf + port); 79 writel(reg, &usbtll->channel_conf + port);
80 } 80 }
81 81
82 #ifdef CONFIG_USB_ULPI
82 static void omap_ehci_soft_phy_reset(int port) 83 static void omap_ehci_soft_phy_reset(int port)
83 { 84 {
84 struct ulpi_viewport ulpi_vp; 85 struct ulpi_viewport ulpi_vp;
85 86
86 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi; 87 ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
87 ulpi_vp.port_num = port; 88 ulpi_vp.port_num = port;
88 89
89 ulpi_reset(&ulpi_vp); 90 ulpi_reset(&ulpi_vp);
90 } 91 }
92 #else
93 static void omap_ehci_soft_phy_reset(int port)
94 {
95 return;
96 }
97 #endif
91 98
92 inline int __board_usb_init(void) 99 inline int __board_usb_init(void)
93 { 100 {
94 return 0; 101 return 0;
95 } 102 }
96 int board_usb_init(void) __attribute__((weak, alias("__board_usb_init"))); 103 int board_usb_init(void) __attribute__((weak, alias("__board_usb_init")));
97 104
98 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \ 105 #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
99 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \ 106 defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
100 defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO) 107 defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
101 /* controls PHY(s) reset signal(s) */ 108 /* controls PHY(s) reset signal(s) */
102 static inline void omap_ehci_phy_reset(int on, int delay) 109 static inline void omap_ehci_phy_reset(int on, int delay)
103 { 110 {
104 /* 111 /*
105 * Refer ISSUE1: 112 * Refer ISSUE1:
106 * Hold the PHY in RESET for enough time till 113 * Hold the PHY in RESET for enough time till
107 * PHY is settled and ready 114 * PHY is settled and ready
108 */ 115 */
109 if (delay && !on) 116 if (delay && !on)
110 udelay(delay); 117 udelay(delay);
111 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 118 #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
112 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset"); 119 gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
113 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on); 120 gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
114 #endif 121 #endif
115 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO 122 #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
116 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset"); 123 gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
117 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on); 124 gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
118 #endif 125 #endif
119 #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO 126 #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
120 gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset"); 127 gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
121 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on); 128 gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
122 #endif 129 #endif
123 130
124 /* Hold the PHY in RESET for enough time till DIR is high */ 131 /* Hold the PHY in RESET for enough time till DIR is high */
125 /* Refer: ISSUE1 */ 132 /* Refer: ISSUE1 */
126 if (delay && on) 133 if (delay && on)
127 udelay(delay); 134 udelay(delay);
128 } 135 }
129 #else 136 #else
130 #define omap_ehci_phy_reset(on, delay) do {} while (0) 137 #define omap_ehci_phy_reset(on, delay) do {} while (0)
131 #endif 138 #endif
132 139
133 /* Reset is needed otherwise the kernel-driver will throw an error. */ 140 /* Reset is needed otherwise the kernel-driver will throw an error. */
134 int omap_ehci_hcd_stop(void) 141 int omap_ehci_hcd_stop(void)
135 { 142 {
136 debug("Resetting OMAP EHCI\n"); 143 debug("Resetting OMAP EHCI\n");
137 omap_ehci_phy_reset(1, 0); 144 omap_ehci_phy_reset(1, 0);
138 145
139 if (omap_uhh_reset() < 0) 146 if (omap_uhh_reset() < 0)
140 return -1; 147 return -1;
141 148
142 if (omap_ehci_tll_reset() < 0) 149 if (omap_ehci_tll_reset() < 0)
143 return -1; 150 return -1;
144 151
145 return 0; 152 return 0;
146 } 153 }
147 154
148 /* 155 /*
149 * Initialize the OMAP EHCI controller and PHY. 156 * Initialize the OMAP EHCI controller and PHY.
150 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1 157 * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
151 * See there for additional Copyrights. 158 * See there for additional Copyrights.
152 */ 159 */
153 int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata, 160 int omap_ehci_hcd_init(struct omap_usbhs_board_data *usbhs_pdata,
154 struct ehci_hccr **hccr, struct ehci_hcor **hcor) 161 struct ehci_hccr **hccr, struct ehci_hcor **hcor)
155 { 162 {
156 int ret; 163 int ret;
157 unsigned int i, reg = 0, rev = 0; 164 unsigned int i, reg = 0, rev = 0;
158 165
159 debug("Initializing OMAP EHCI\n"); 166 debug("Initializing OMAP EHCI\n");
160 167
161 ret = board_usb_init(); 168 ret = board_usb_init();
162 if (ret < 0) 169 if (ret < 0)
163 return ret; 170 return ret;
164 171
165 /* Put the PHY in RESET */ 172 /* Put the PHY in RESET */
166 omap_ehci_phy_reset(1, 10); 173 omap_ehci_phy_reset(1, 10);
167 174
168 ret = omap_uhh_reset(); 175 ret = omap_uhh_reset();
169 if (ret < 0) 176 if (ret < 0)
170 return ret; 177 return ret;
171 178
172 ret = omap_ehci_tll_reset(); 179 ret = omap_ehci_tll_reset();
173 if (ret) 180 if (ret)
174 return ret; 181 return ret;
175 182
176 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP | 183 writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
177 OMAP_USBTLL_SYSCONFIG_SIDLEMODE | 184 OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
178 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc); 185 OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
179 186
180 /* Put UHH in NoIdle/NoStandby mode */ 187 /* Put UHH in NoIdle/NoStandby mode */
181 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc); 188 writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
182 189
183 /* setup ULPI bypass and burst configurations */ 190 /* setup ULPI bypass and burst configurations */
184 clrsetbits_le32(&reg, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN, 191 clrsetbits_le32(&reg, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
185 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN | 192 (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
186 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN | 193 OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
187 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN)); 194 OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
188 195
189 rev = readl(&uhh->rev); 196 rev = readl(&uhh->rev);
190 if (rev == OMAP_USBHS_REV1) { 197 if (rev == OMAP_USBHS_REV1) {
191 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0])) 198 if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
192 clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); 199 clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
193 else 200 else
194 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS); 201 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
195 202
196 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1])) 203 if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
197 clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); 204 clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
198 else 205 else
199 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS); 206 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
200 207
201 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2])) 208 if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
202 clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); 209 clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
203 else 210 else
204 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS); 211 setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
205 } else if (rev == OMAP_USBHS_REV2) { 212 } else if (rev == OMAP_USBHS_REV2) {
206 213
207 clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR), 214 clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
208 OMAP4_UHH_HOSTCONFIG_APP_START_CLK); 215 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
209 216
210 /* Clear port mode fields for PHY mode */ 217 /* Clear port mode fields for PHY mode */
211 218
212 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) 219 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
213 setbits_le32(&reg, OMAP_P1_MODE_HSIC); 220 setbits_le32(&reg, OMAP_P1_MODE_HSIC);
214 221
215 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1])) 222 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
216 setbits_le32(&reg, OMAP_P2_MODE_HSIC); 223 setbits_le32(&reg, OMAP_P2_MODE_HSIC);
217 224
218 } else if (rev == OMAP_USBHS_REV2_1) { 225 } else if (rev == OMAP_USBHS_REV2_1) {
219 226
220 clrsetbits_le32(&reg, 227 clrsetbits_le32(&reg,
221 (OMAP_P1_MODE_CLEAR | 228 (OMAP_P1_MODE_CLEAR |
222 OMAP_P2_MODE_CLEAR | 229 OMAP_P2_MODE_CLEAR |
223 OMAP_P3_MODE_CLEAR), 230 OMAP_P3_MODE_CLEAR),
224 OMAP4_UHH_HOSTCONFIG_APP_START_CLK); 231 OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
225 232
226 /* Clear port mode fields for PHY mode */ 233 /* Clear port mode fields for PHY mode */
227 234
228 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0])) 235 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
229 setbits_le32(&reg, OMAP_P1_MODE_HSIC); 236 setbits_le32(&reg, OMAP_P1_MODE_HSIC);
230 237
231 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1])) 238 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
232 setbits_le32(&reg, OMAP_P2_MODE_HSIC); 239 setbits_le32(&reg, OMAP_P2_MODE_HSIC);
233 240
234 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2])) 241 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
235 setbits_le32(&reg, OMAP_P3_MODE_HSIC); 242 setbits_le32(&reg, OMAP_P3_MODE_HSIC);
236 } 243 }
237 244
238 debug("OMAP UHH_REVISION 0x%x\n", rev); 245 debug("OMAP UHH_REVISION 0x%x\n", rev);
239 writel(reg, &uhh->hostconfig); 246 writel(reg, &uhh->hostconfig);
240 247
241 for (i = 0; i < OMAP_HS_USB_PORTS; i++) 248 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
242 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i])) 249 if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
243 omap_usbhs_hsic_init(i); 250 omap_usbhs_hsic_init(i);
244 251
245 omap_ehci_phy_reset(0, 10); 252 omap_ehci_phy_reset(0, 10);
246 253
247 /* 254 /*
248 * An undocumented "feature" in the OMAP3 EHCI controller, 255 * An undocumented "feature" in the OMAP3 EHCI controller,
249 * causes suspended ports to be taken out of suspend when 256 * causes suspended ports to be taken out of suspend when
250 * the USBCMD.Run/Stop bit is cleared (for example when 257 * the USBCMD.Run/Stop bit is cleared (for example when
251 * we do ehci_bus_suspend). 258 * we do ehci_bus_suspend).
252 * This breaks suspend-resume if the root-hub is allowed 259 * This breaks suspend-resume if the root-hub is allowed
253 * to suspend. Writing 1 to this undocumented register bit 260 * to suspend. Writing 1 to this undocumented register bit
254 * disables this feature and restores normal behavior. 261 * disables this feature and restores normal behavior.
255 */ 262 */
256 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04); 263 writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
257 264
258 for (i = 0; i < OMAP_HS_USB_PORTS; i++) 265 for (i = 0; i < OMAP_HS_USB_PORTS; i++)
259 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i])) 266 if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
260 omap_ehci_soft_phy_reset(i); 267 omap_ehci_soft_phy_reset(i);
261 268
262 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE); 269 *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
263 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10); 270 *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
264 271
265 debug("OMAP EHCI init done\n"); 272 debug("OMAP EHCI init done\n");
266 return 0; 273 return 0;
267 } 274 }
268 275