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Commit 1208523935613a2574f52028ec0d0e2466dcd067

Authored by Philipp Tomsich
Committed by Simon Glass
1 parent a6b08c9677
Exists in smarc_8mq_lf_v2020.04 and in 20 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

rockchip: video: rk_hdmi: fix implicit definition warnings 

When enabling CONFIG_DISPLAY_ROCKCHIP_HDMI, compile-time warning for
the following implicitly defined functions are raised due to a missing
include directive:

  drivers/video/rockchip/rk_hdmi.c: In function 'rk_hdmi_probe':
  drivers/video/rockchip/rk_hdmi.c:150:2: warning: implicit declaration of function 'rk_setreg' [-Wimplicit-function-declaration]
    rk_setreg(&priv->grf->soc_con6, 1 << 15);
    ^~~~~~~~~
  drivers/video/rockchip/rk_hdmi.c:153:2: warning: implicit declaration of function 'rk_clrsetreg' [-Wimplicit-function-declaration]
    rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
    ^~~~~~~~~~~~

This change fixes this by including <asm/hardware.h> in rk_hdmi.c.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: Simon Glass <sjg@chromium.org>

Showing 1 changed file with 1 additions and 0 deletions Inline Diff

drivers/video/rockchip/rk_hdmi.c
Diff comments   View file @ 1208523
1 /* 1 /*
2 * Copyright (c) 2015 Google, Inc 2 * Copyright (c) 2015 Google, Inc
3 * Copyright 2014 Rockchip Inc. 3 * Copyright 2014 Rockchip Inc.
4 * 4 *
5 * SPDX-License-Identifier: GPL-2.0+ 5 * SPDX-License-Identifier: GPL-2.0+
6 */ 6 */
7 7
8 #include <common.h> 8 #include <common.h>
9 #include <clk.h> 9 #include <clk.h>
10 #include <display.h> 10 #include <display.h>
11 #include <dm.h> 11 #include <dm.h>
12 #include <dw_hdmi.h> 12 #include <dw_hdmi.h>
13 #include <edid.h> 13 #include <edid.h>
14 #include <regmap.h> 14 #include <regmap.h>
15 #include <syscon.h> 15 #include <syscon.h>
16 #include <asm/gpio.h> 16 #include <asm/gpio.h>
17 #include <asm/hardware.h>
17 #include <asm/io.h> 18 #include <asm/io.h>
18 #include <asm/arch/clock.h> 19 #include <asm/arch/clock.h>
19 #include <asm/arch/grf_rk3288.h> 20 #include <asm/arch/grf_rk3288.h>
20 #include <power/regulator.h> 21 #include <power/regulator.h>
21 22
22 struct rk_hdmi_priv { 23 struct rk_hdmi_priv {
23 struct dw_hdmi hdmi; 24 struct dw_hdmi hdmi;
24 struct rk3288_grf *grf; 25 struct rk3288_grf *grf;
25 }; 26 };
26 27
27 static const struct hdmi_phy_config rockchip_phy_config[] = { 28 static const struct hdmi_phy_config rockchip_phy_config[] = {
28 { 29 {
29 .mpixelclock = 74250000, 30 .mpixelclock = 74250000,
30 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272, 31 .sym_ctr = 0x8009, .term = 0x0004, .vlev_ctr = 0x0272,
31 }, { 32 }, {
32 .mpixelclock = 148500000, 33 .mpixelclock = 148500000,
33 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d, 34 .sym_ctr = 0x802b, .term = 0x0004, .vlev_ctr = 0x028d,
34 }, { 35 }, {
35 .mpixelclock = 297000000, 36 .mpixelclock = 297000000,
36 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d, 37 .sym_ctr = 0x8039, .term = 0x0005, .vlev_ctr = 0x028d,
37 }, { 38 }, {
38 .mpixelclock = ~0ul, 39 .mpixelclock = ~0ul,
39 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000, 40 .sym_ctr = 0x0000, .term = 0x0000, .vlev_ctr = 0x0000,
40 } 41 }
41 }; 42 };
42 43
43 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = { 44 static const struct hdmi_mpll_config rockchip_mpll_cfg[] = {
44 { 45 {
45 .mpixelclock = 40000000, 46 .mpixelclock = 40000000,
46 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018, 47 .cpce = 0x00b3, .gmp = 0x0000, .curr = 0x0018,
47 }, { 48 }, {
48 .mpixelclock = 65000000, 49 .mpixelclock = 65000000,
49 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, 50 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
50 }, { 51 }, {
51 .mpixelclock = 66000000, 52 .mpixelclock = 66000000,
52 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038, 53 .cpce = 0x013e, .gmp = 0x0003, .curr = 0x0038,
53 }, { 54 }, {
54 .mpixelclock = 83500000, 55 .mpixelclock = 83500000,
55 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028, 56 .cpce = 0x0072, .gmp = 0x0001, .curr = 0x0028,
56 }, { 57 }, {
57 .mpixelclock = 146250000, 58 .mpixelclock = 146250000,
58 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038, 59 .cpce = 0x0051, .gmp = 0x0002, .curr = 0x0038,
59 }, { 60 }, {
60 .mpixelclock = 148500000, 61 .mpixelclock = 148500000,
61 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, 62 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
62 }, { 63 }, {
63 .mpixelclock = ~0ul, 64 .mpixelclock = ~0ul,
64 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000, 65 .cpce = 0x0051, .gmp = 0x0003, .curr = 0x0000,
65 } 66 }
66 }; 67 };
67 68
68 static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size) 69 static int rk_hdmi_read_edid(struct udevice *dev, u8 *buf, int buf_size)
69 { 70 {
70 struct rk_hdmi_priv *priv = dev_get_priv(dev); 71 struct rk_hdmi_priv *priv = dev_get_priv(dev);
71 72
72 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size); 73 return dw_hdmi_read_edid(&priv->hdmi, buf, buf_size);
73 } 74 }
74 75
75 static int rk_hdmi_enable(struct udevice *dev, int panel_bpp, 76 static int rk_hdmi_enable(struct udevice *dev, int panel_bpp,
76 const struct display_timing *edid) 77 const struct display_timing *edid)
77 { 78 {
78 struct rk_hdmi_priv *priv = dev_get_priv(dev); 79 struct rk_hdmi_priv *priv = dev_get_priv(dev);
79 80
80 return dw_hdmi_enable(&priv->hdmi, edid); 81 return dw_hdmi_enable(&priv->hdmi, edid);
81 } 82 }
82 83
83 static int rk_hdmi_ofdata_to_platdata(struct udevice *dev) 84 static int rk_hdmi_ofdata_to_platdata(struct udevice *dev)
84 { 85 {
85 struct rk_hdmi_priv *priv = dev_get_priv(dev); 86 struct rk_hdmi_priv *priv = dev_get_priv(dev);
86 struct dw_hdmi *hdmi = &priv->hdmi; 87 struct dw_hdmi *hdmi = &priv->hdmi;
87 88
88 hdmi->ioaddr = (ulong)devfdt_get_addr(dev); 89 hdmi->ioaddr = (ulong)devfdt_get_addr(dev);
89 hdmi->mpll_cfg = rockchip_mpll_cfg; 90 hdmi->mpll_cfg = rockchip_mpll_cfg;
90 hdmi->phy_cfg = rockchip_phy_config; 91 hdmi->phy_cfg = rockchip_phy_config;
91 hdmi->i2c_clk_high = 0x7a; 92 hdmi->i2c_clk_high = 0x7a;
92 hdmi->i2c_clk_low = 0x8d; 93 hdmi->i2c_clk_low = 0x8d;
93 94
94 /* 95 /*
95 * TODO(sjg@chromium.org): The above values don't work - these ones 96 * TODO(sjg@chromium.org): The above values don't work - these ones
96 * work better, but generate lots of errors in the data. 97 * work better, but generate lots of errors in the data.
97 */ 98 */
98 hdmi->i2c_clk_high = 0x0d; 99 hdmi->i2c_clk_high = 0x0d;
99 hdmi->i2c_clk_low = 0x0d; 100 hdmi->i2c_clk_low = 0x0d;
100 hdmi->reg_io_width = 4; 101 hdmi->reg_io_width = 4;
101 hdmi->phy_set = dw_hdmi_phy_cfg; 102 hdmi->phy_set = dw_hdmi_phy_cfg;
102 103
103 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); 104 priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
104 105
105 return 0; 106 return 0;
106 } 107 }
107 108
108 static int rk_hdmi_probe(struct udevice *dev) 109 static int rk_hdmi_probe(struct udevice *dev)
109 { 110 {
110 struct display_plat *uc_plat = dev_get_uclass_platdata(dev); 111 struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
111 struct rk_hdmi_priv *priv = dev_get_priv(dev); 112 struct rk_hdmi_priv *priv = dev_get_priv(dev);
112 struct dw_hdmi *hdmi = &priv->hdmi; 113 struct dw_hdmi *hdmi = &priv->hdmi;
113 struct udevice *reg; 114 struct udevice *reg;
114 struct clk clk; 115 struct clk clk;
115 int ret; 116 int ret;
116 int vop_id = uc_plat->source_id; 117 int vop_id = uc_plat->source_id;
117 118
118 ret = clk_get_by_index(dev, 0, &clk); 119 ret = clk_get_by_index(dev, 0, &clk);
119 if (ret >= 0) { 120 if (ret >= 0) {
120 ret = clk_set_rate(&clk, 0); 121 ret = clk_set_rate(&clk, 0);
121 clk_free(&clk); 122 clk_free(&clk);
122 } 123 }
123 if (ret) { 124 if (ret) {
124 debug("%s: Failed to set hdmi clock: ret=%d\n", __func__, ret); 125 debug("%s: Failed to set hdmi clock: ret=%d\n", __func__, ret);
125 return ret; 126 return ret;
126 } 127 }
127 128
128 /* 129 /*
129 * Configure the maximum clock to permit whatever resolution the 130 * Configure the maximum clock to permit whatever resolution the
130 * monitor wants 131 * monitor wants
131 */ 132 */
132 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); 133 ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
133 if (ret >= 0) { 134 if (ret >= 0) {
134 ret = clk_set_rate(&clk, 384000000); 135 ret = clk_set_rate(&clk, 384000000);
135 clk_free(&clk); 136 clk_free(&clk);
136 } 137 }
137 if (ret < 0) { 138 if (ret < 0) {
138 debug("%s: Failed to set clock in source device '%s': ret=%d\n", 139 debug("%s: Failed to set clock in source device '%s': ret=%d\n",
139 __func__, uc_plat->src_dev->name, ret); 140 __func__, uc_plat->src_dev->name, ret);
140 return ret; 141 return ret;
141 } 142 }
142 143
143 ret = regulator_get_by_platname("vcc50_hdmi", &reg); 144 ret = regulator_get_by_platname("vcc50_hdmi", &reg);
144 if (!ret) 145 if (!ret)
145 ret = regulator_set_enable(reg, true); 146 ret = regulator_set_enable(reg, true);
146 if (ret) 147 if (ret)
147 debug("%s: Cannot set regulator vcc50_hdmi\n", __func__); 148 debug("%s: Cannot set regulator vcc50_hdmi\n", __func__);
148 149
149 /* hdmi source select hdmi controller */ 150 /* hdmi source select hdmi controller */
150 rk_setreg(&priv->grf->soc_con6, 1 << 15); 151 rk_setreg(&priv->grf->soc_con6, 1 << 15);
151 152
152 /* hdmi data from vop id */ 153 /* hdmi data from vop id */
153 rk_clrsetreg(&priv->grf->soc_con6, 1 << 4, 154 rk_clrsetreg(&priv->grf->soc_con6, 1 << 4,
154 (vop_id == 1) ? (1 << 4) : 0); 155 (vop_id == 1) ? (1 << 4) : 0);
155 156
156 ret = dw_hdmi_phy_wait_for_hpd(hdmi); 157 ret = dw_hdmi_phy_wait_for_hpd(hdmi);
157 if (ret < 0) { 158 if (ret < 0) {
158 debug("hdmi can not get hpd signal\n"); 159 debug("hdmi can not get hpd signal\n");
159 return -1; 160 return -1;
160 } 161 }
161 162
162 dw_hdmi_init(hdmi); 163 dw_hdmi_init(hdmi);
163 dw_hdmi_phy_init(hdmi); 164 dw_hdmi_phy_init(hdmi);
164 165
165 return 0; 166 return 0;
166 } 167 }
167 168
168 static const struct dm_display_ops rk_hdmi_ops = { 169 static const struct dm_display_ops rk_hdmi_ops = {
169 .read_edid = rk_hdmi_read_edid, 170 .read_edid = rk_hdmi_read_edid,
170 .enable = rk_hdmi_enable, 171 .enable = rk_hdmi_enable,
171 }; 172 };
172 173
173 static const struct udevice_id rk_hdmi_ids[] = { 174 static const struct udevice_id rk_hdmi_ids[] = {
174 { .compatible = "rockchip,rk3288-dw-hdmi" }, 175 { .compatible = "rockchip,rk3288-dw-hdmi" },
175 { } 176 { }
176 }; 177 };
177 178
178 U_BOOT_DRIVER(hdmi_rockchip) = { 179 U_BOOT_DRIVER(hdmi_rockchip) = {
179 .name = "hdmi_rockchip", 180 .name = "hdmi_rockchip",
180 .id = UCLASS_DISPLAY, 181 .id = UCLASS_DISPLAY,
181 .of_match = rk_hdmi_ids, 182 .of_match = rk_hdmi_ids,
182 .ops = &rk_hdmi_ops, 183 .ops = &rk_hdmi_ops,
183 .ofdata_to_platdata = rk_hdmi_ofdata_to_platdata, 184 .ofdata_to_platdata = rk_hdmi_ofdata_to_platdata,
184 .probe = rk_hdmi_probe, 185 .probe = rk_hdmi_probe,
185 .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv), 186 .priv_auto_alloc_size = sizeof(struct rk_hdmi_priv),
186 }; 187 };
187 188