Eric Lee / smarc-uboot

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Commit 158d93adb482ef6dc1e50fcf9a7c3b21128d4cd9

Authored by Heiko Schocher
Committed by Stefano Babic
1 parent 9f976bac2b
Exists in smarc_8mq_lf_v2020.04 and in 9 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf_v2022.04, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0

imx6, aristainetos2c: add da9063 pmic setup 

On the aristainetos2c boards the PMIC needs to be initialized,
because the Ethernet PHY uses a different regulator that is not
setup per hardware default. This does not influence the other
versions as this regulator isn't used there at all.

Signed-off-by: Heiko Schocher <hs@denx.de>

Showing 2 changed files with 59 additions and 0 deletions Inline Diff

board/aristainetos/aristainetos.c
Diff comments   View file @ 158d93a
1 // SPDX-License-Identifier: GPL-2.0+ 1 // SPDX-License-Identifier: GPL-2.0+
2 /* 2 /*
3 * (C) Copyright 2014 3 * (C) Copyright 2014
4 * Heiko Schocher, DENX Software Engineering, hs@denx.de. 4 * Heiko Schocher, DENX Software Engineering, hs@denx.de.
5 * 5 *
6 * Based on: 6 * Based on:
7 * Copyright (C) 2012 Freescale Semiconductor, Inc. 7 * Copyright (C) 2012 Freescale Semiconductor, Inc.
8 * 8 *
9 * Author: Fabio Estevam <fabio.estevam@freescale.com> 9 * Author: Fabio Estevam <fabio.estevam@freescale.com>
10 */ 10 */
11 11
12 #include <asm/arch/clock.h> 12 #include <asm/arch/clock.h>
13 #include <asm/arch/imx-regs.h> 13 #include <asm/arch/imx-regs.h>
14 #include <asm/arch/iomux.h> 14 #include <asm/arch/iomux.h>
15 #include <asm/arch/mx6-pins.h> 15 #include <asm/arch/mx6-pins.h>
16 #include <linux/errno.h> 16 #include <linux/errno.h>
17 #include <asm/gpio.h> 17 #include <asm/gpio.h>
18 #include <asm/mach-imx/iomux-v3.h> 18 #include <asm/mach-imx/iomux-v3.h>
19 #include <asm/mach-imx/boot_mode.h> 19 #include <asm/mach-imx/boot_mode.h>
20 #include <asm/mach-imx/video.h> 20 #include <asm/mach-imx/video.h>
21 #include <asm/arch/crm_regs.h> 21 #include <asm/arch/crm_regs.h>
22 #include <asm/io.h> 22 #include <asm/io.h>
23 #include <asm/arch/sys_proto.h> 23 #include <asm/arch/sys_proto.h>
24 #include <bmp_logo.h> 24 #include <bmp_logo.h>
25 #include <dm/root.h> 25 #include <dm/root.h>
26 #include <env.h> 26 #include <env.h>
27 #include <i2c_eeprom.h> 27 #include <i2c_eeprom.h>
28 #include <i2c.h> 28 #include <i2c.h>
29 #include <micrel.h> 29 #include <micrel.h>
30 #include <miiphy.h> 30 #include <miiphy.h>
31 #include <lcd.h> 31 #include <lcd.h>
32 #include <led.h> 32 #include <led.h>
33 #include <power/pmic.h>
34 #include <power/regulator.h>
35 #include <power/da9063_pmic.h>
33 #include <splash.h> 36 #include <splash.h>
34 #include <video_fb.h> 37 #include <video_fb.h>
35 38
36 DECLARE_GLOBAL_DATA_PTR; 39 DECLARE_GLOBAL_DATA_PTR;
37 40
38 enum { 41 enum {
39 BOARD_TYPE_4 = 4, 42 BOARD_TYPE_4 = 4,
40 BOARD_TYPE_7 = 7, 43 BOARD_TYPE_7 = 7,
41 }; 44 };
42 45
43 #define ARI_BT_4 "aristainetos2_4@2" 46 #define ARI_BT_4 "aristainetos2_4@2"
44 #define ARI_BT_7 "aristainetos2_7@1" 47 #define ARI_BT_7 "aristainetos2_7@1"
45 48
46 int board_phy_config(struct phy_device *phydev) 49 int board_phy_config(struct phy_device *phydev)
47 { 50 {
48 /* control data pad skew - devaddr = 0x02, register = 0x04 */ 51 /* control data pad skew - devaddr = 0x02, register = 0x04 */
49 ksz9031_phy_extended_write(phydev, 0x02, 52 ksz9031_phy_extended_write(phydev, 0x02,
50 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, 53 MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW,
51 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 54 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
52 /* rx data pad skew - devaddr = 0x02, register = 0x05 */ 55 /* rx data pad skew - devaddr = 0x02, register = 0x05 */
53 ksz9031_phy_extended_write(phydev, 0x02, 56 ksz9031_phy_extended_write(phydev, 0x02,
54 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, 57 MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW,
55 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 58 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
56 /* tx data pad skew - devaddr = 0x02, register = 0x06 */ 59 /* tx data pad skew - devaddr = 0x02, register = 0x06 */
57 ksz9031_phy_extended_write(phydev, 0x02, 60 ksz9031_phy_extended_write(phydev, 0x02,
58 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, 61 MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW,
59 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); 62 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000);
60 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ 63 /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */
61 ksz9031_phy_extended_write(phydev, 0x02, 64 ksz9031_phy_extended_write(phydev, 0x02,
62 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, 65 MII_KSZ9031_EXT_RGMII_CLOCK_SKEW,
63 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); 66 MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF);
64 67
65 if (phydev->drv->config) 68 if (phydev->drv->config)
66 phydev->drv->config(phydev); 69 phydev->drv->config(phydev);
67 70
68 return 0; 71 return 0;
69 } 72 }
70 73
71 static int rotate_logo_one(unsigned char *out, unsigned char *in) 74 static int rotate_logo_one(unsigned char *out, unsigned char *in)
72 { 75 {
73 int i, j; 76 int i, j;
74 77
75 for (i = 0; i < BMP_LOGO_WIDTH; i++) 78 for (i = 0; i < BMP_LOGO_WIDTH; i++)
76 for (j = 0; j < BMP_LOGO_HEIGHT; j++) 79 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
77 out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] = 80 out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] =
78 in[i * BMP_LOGO_WIDTH + j]; 81 in[i * BMP_LOGO_WIDTH + j];
79 return 0; 82 return 0;
80 } 83 }
81 84
82 /* 85 /*
83 * Rotate the BMP_LOGO (only) 86 * Rotate the BMP_LOGO (only)
84 * Will only work, if the logo is square, as 87 * Will only work, if the logo is square, as
85 * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables 88 * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables
86 */ 89 */
87 void rotate_logo(int rotations) 90 void rotate_logo(int rotations)
88 { 91 {
89 unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT]; 92 unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT];
90 struct bmp_header *header; 93 struct bmp_header *header;
91 unsigned char *in_logo; 94 unsigned char *in_logo;
92 int i, j; 95 int i, j;
93 96
94 if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT) 97 if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT)
95 return; 98 return;
96 99
97 header = (struct bmp_header *)bmp_logo_bitmap; 100 header = (struct bmp_header *)bmp_logo_bitmap;
98 in_logo = bmp_logo_bitmap + header->data_offset; 101 in_logo = bmp_logo_bitmap + header->data_offset;
99 102
100 /* one 90 degree rotation */ 103 /* one 90 degree rotation */
101 if (rotations == 1 || rotations == 2 || rotations == 3) 104 if (rotations == 1 || rotations == 2 || rotations == 3)
102 rotate_logo_one(out_logo, in_logo); 105 rotate_logo_one(out_logo, in_logo);
103 106
104 /* second 90 degree rotation */ 107 /* second 90 degree rotation */
105 if (rotations == 2 || rotations == 3) 108 if (rotations == 2 || rotations == 3)
106 rotate_logo_one(in_logo, out_logo); 109 rotate_logo_one(in_logo, out_logo);
107 110
108 /* third 90 degree rotation */ 111 /* third 90 degree rotation */
109 if (rotations == 3) 112 if (rotations == 3)
110 rotate_logo_one(out_logo, in_logo); 113 rotate_logo_one(out_logo, in_logo);
111 114
112 /* copy result back to original array */ 115 /* copy result back to original array */
113 if (rotations == 1 || rotations == 3) 116 if (rotations == 1 || rotations == 3)
114 for (i = 0; i < BMP_LOGO_WIDTH; i++) 117 for (i = 0; i < BMP_LOGO_WIDTH; i++)
115 for (j = 0; j < BMP_LOGO_HEIGHT; j++) 118 for (j = 0; j < BMP_LOGO_HEIGHT; j++)
116 in_logo[i * BMP_LOGO_WIDTH + j] = 119 in_logo[i * BMP_LOGO_WIDTH + j] =
117 out_logo[i * BMP_LOGO_WIDTH + j]; 120 out_logo[i * BMP_LOGO_WIDTH + j];
118 } 121 }
119 122
120 static void enable_lvds(struct display_info_t const *dev) 123 static void enable_lvds(struct display_info_t const *dev)
121 { 124 {
122 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 125 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
123 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 126 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
124 int reg; 127 int reg;
125 s32 timeout = 100000; 128 s32 timeout = 100000;
126 129
127 /* set PLL5 clock */ 130 /* set PLL5 clock */
128 reg = readl(&ccm->analog_pll_video); 131 reg = readl(&ccm->analog_pll_video);
129 reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; 132 reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN;
130 writel(reg, &ccm->analog_pll_video); 133 writel(reg, &ccm->analog_pll_video);
131 134
132 /* set PLL5 to 232720000Hz */ 135 /* set PLL5 to 232720000Hz */
133 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; 136 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
134 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26); 137 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26);
135 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; 138 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
136 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); 139 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
137 writel(reg, &ccm->analog_pll_video); 140 writel(reg, &ccm->analog_pll_video);
138 141
139 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238), 142 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238),
140 &ccm->analog_pll_video_num); 143 &ccm->analog_pll_video_num);
141 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240), 144 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240),
142 &ccm->analog_pll_video_denom); 145 &ccm->analog_pll_video_denom);
143 146
144 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; 147 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
145 writel(reg, &ccm->analog_pll_video); 148 writel(reg, &ccm->analog_pll_video);
146 149
147 while (timeout--) 150 while (timeout--)
148 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) 151 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
149 break; 152 break;
150 if (timeout < 0) 153 if (timeout < 0)
151 printf("Warning: video pll lock timeout!\n"); 154 printf("Warning: video pll lock timeout!\n");
152 155
153 reg = readl(&ccm->analog_pll_video); 156 reg = readl(&ccm->analog_pll_video);
154 reg |= BM_ANADIG_PLL_VIDEO_ENABLE; 157 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
155 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; 158 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
156 writel(reg, &ccm->analog_pll_video); 159 writel(reg, &ccm->analog_pll_video);
157 160
158 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ 161 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
159 reg = readl(&ccm->cs2cdr); 162 reg = readl(&ccm->cs2cdr);
160 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 163 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
161 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 164 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
162 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 165 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
163 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 166 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
164 writel(reg, &ccm->cs2cdr); 167 writel(reg, &ccm->cs2cdr);
165 168
166 reg = readl(&ccm->cscmr2); 169 reg = readl(&ccm->cscmr2);
167 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 170 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
168 writel(reg, &ccm->cscmr2); 171 writel(reg, &ccm->cscmr2);
169 172
170 reg = readl(&ccm->chsccdr); 173 reg = readl(&ccm->chsccdr);
171 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 174 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
172 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 175 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
173 writel(reg, &ccm->chsccdr); 176 writel(reg, &ccm->chsccdr);
174 177
175 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 178 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
176 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 179 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
177 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH 180 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
178 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 181 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
179 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT 182 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
180 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 183 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
181 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 184 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
182 writel(reg, &iomux->gpr[2]); 185 writel(reg, &iomux->gpr[2]);
183 186
184 reg = readl(&iomux->gpr[3]); 187 reg = readl(&iomux->gpr[3]);
185 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) 188 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
186 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 189 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
187 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 190 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
188 writel(reg, &iomux->gpr[3]); 191 writel(reg, &iomux->gpr[3]);
189 } 192 }
190 193
191 static void enable_spi_display(struct display_info_t const *dev) 194 static void enable_spi_display(struct display_info_t const *dev)
192 { 195 {
193 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 196 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
194 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 197 struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
195 int reg; 198 int reg;
196 s32 timeout = 100000; 199 s32 timeout = 100000;
197 200
198 #if defined(CONFIG_VIDEO_BMP_LOGO) 201 #if defined(CONFIG_VIDEO_BMP_LOGO)
199 rotate_logo(3); /* portrait display in landscape mode */ 202 rotate_logo(3); /* portrait display in landscape mode */
200 #endif 203 #endif
201 204
202 reg = readl(&ccm->cs2cdr); 205 reg = readl(&ccm->cs2cdr);
203 206
204 /* select pll 5 clock */ 207 /* select pll 5 clock */
205 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 208 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
206 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 209 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
207 writel(reg, &ccm->cs2cdr); 210 writel(reg, &ccm->cs2cdr);
208 211
209 /* set PLL5 to 197994996Hz */ 212 /* set PLL5 to 197994996Hz */
210 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; 213 reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT;
211 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21); 214 reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21);
212 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; 215 reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT;
213 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); 216 reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0);
214 writel(reg, &ccm->analog_pll_video); 217 writel(reg, &ccm->analog_pll_video);
215 218
216 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4), 219 writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4),
217 &ccm->analog_pll_video_num); 220 &ccm->analog_pll_video_num);
218 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240), 221 writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240),
219 &ccm->analog_pll_video_denom); 222 &ccm->analog_pll_video_denom);
220 223
221 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; 224 reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN;
222 writel(reg, &ccm->analog_pll_video); 225 writel(reg, &ccm->analog_pll_video);
223 226
224 while (timeout--) 227 while (timeout--)
225 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) 228 if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK)
226 break; 229 break;
227 if (timeout < 0) 230 if (timeout < 0)
228 printf("Warning: video pll lock timeout!\n"); 231 printf("Warning: video pll lock timeout!\n");
229 232
230 reg = readl(&ccm->analog_pll_video); 233 reg = readl(&ccm->analog_pll_video);
231 reg |= BM_ANADIG_PLL_VIDEO_ENABLE; 234 reg |= BM_ANADIG_PLL_VIDEO_ENABLE;
232 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; 235 reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS;
233 writel(reg, &ccm->analog_pll_video); 236 writel(reg, &ccm->analog_pll_video);
234 237
235 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ 238 /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */
236 reg = readl(&ccm->cs2cdr); 239 reg = readl(&ccm->cs2cdr);
237 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK 240 reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
238 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); 241 | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
239 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) 242 reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
240 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); 243 | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
241 writel(reg, &ccm->cs2cdr); 244 writel(reg, &ccm->cs2cdr);
242 245
243 reg = readl(&ccm->cscmr2); 246 reg = readl(&ccm->cscmr2);
244 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; 247 reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV;
245 writel(reg, &ccm->cscmr2); 248 writel(reg, &ccm->cscmr2);
246 249
247 reg = readl(&ccm->chsccdr); 250 reg = readl(&ccm->chsccdr);
248 reg |= (CHSCCDR_CLK_SEL_LDB_DI0 251 reg |= (CHSCCDR_CLK_SEL_LDB_DI0
249 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); 252 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
250 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; 253 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK;
251 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET); 254 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET);
252 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; 255 reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK;
253 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); 256 reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET);
254 writel(reg, &ccm->chsccdr); 257 writel(reg, &ccm->chsccdr);
255 258
256 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES 259 reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
257 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH 260 | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH
258 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH 261 | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH
259 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG 262 | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
260 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT 263 | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT
261 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED 264 | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED
262 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; 265 | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0;
263 writel(reg, &iomux->gpr[2]); 266 writel(reg, &iomux->gpr[2]);
264 267
265 reg = readl(&iomux->gpr[3]); 268 reg = readl(&iomux->gpr[3]);
266 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) 269 reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK)
267 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 270 | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
268 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); 271 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET);
269 writel(reg, &iomux->gpr[3]); 272 writel(reg, &iomux->gpr[3]);
270 } 273 }
271 274
272 static void setup_display(void) 275 static void setup_display(void)
273 { 276 {
274 enable_ipu_clock(); 277 enable_ipu_clock();
275 } 278 }
276 279
277 static void set_gpr_register(void) 280 static void set_gpr_register(void)
278 { 281 {
279 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; 282 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
280 283
281 writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 | 284 writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 |
282 IOMUXC_GPR1_EXC_MON_SLVE | 285 IOMUXC_GPR1_EXC_MON_SLVE |
283 (2 << IOMUXC_GPR1_ADDRS0_OFFSET) | 286 (2 << IOMUXC_GPR1_ADDRS0_OFFSET) |
284 IOMUXC_GPR1_ACT_CS0, 287 IOMUXC_GPR1_ACT_CS0,
285 &iomuxc_regs->gpr[1]); 288 &iomuxc_regs->gpr[1]);
286 writel(0x0, &iomuxc_regs->gpr[8]); 289 writel(0x0, &iomuxc_regs->gpr[8]);
287 writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN | 290 writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN |
288 IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN, 291 IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN,
289 &iomuxc_regs->gpr[12]); 292 &iomuxc_regs->gpr[12]);
290 } 293 }
291 294
292 extern char __bss_start[], __bss_end[]; 295 extern char __bss_start[], __bss_end[];
293 int board_early_init_f(void) 296 int board_early_init_f(void)
294 { 297 {
295 select_ldb_di_clock_source(MXC_PLL5_CLK); 298 select_ldb_di_clock_source(MXC_PLL5_CLK);
296 set_gpr_register(); 299 set_gpr_register();
297 300
298 /* 301 /*
299 * clear bss here, so we can use spi driver 302 * clear bss here, so we can use spi driver
300 * before relocation and read Environment 303 * before relocation and read Environment
301 * from spi flash. 304 * from spi flash.
302 */ 305 */
303 memset(__bss_start, 0x00, __bss_end - __bss_start); 306 memset(__bss_start, 0x00, __bss_end - __bss_start);
304 307
305 return 0; 308 return 0;
306 } 309 }
307 310
308 static void setup_one_led(char *label, int state) 311 static void setup_one_led(char *label, int state)
309 { 312 {
310 struct udevice *dev; 313 struct udevice *dev;
311 int ret; 314 int ret;
312 315
313 ret = led_get_by_label(label, &dev); 316 ret = led_get_by_label(label, &dev);
314 if (ret == 0) 317 if (ret == 0)
315 led_set_state(dev, state); 318 led_set_state(dev, state);
316 } 319 }
317 320
318 static void setup_board_gpio(void) 321 static void setup_board_gpio(void)
319 { 322 {
320 setup_one_led("led_ena", LEDST_ON); 323 setup_one_led("led_ena", LEDST_ON);
321 /* switch off Status LEDs */ 324 /* switch off Status LEDs */
322 setup_one_led("led_yellow", LEDST_OFF); 325 setup_one_led("led_yellow", LEDST_OFF);
323 setup_one_led("led_red", LEDST_OFF); 326 setup_one_led("led_red", LEDST_OFF);
324 setup_one_led("led_green", LEDST_OFF); 327 setup_one_led("led_green", LEDST_OFF);
325 setup_one_led("led_blue", LEDST_OFF); 328 setup_one_led("led_blue", LEDST_OFF);
326 } 329 }
327 330
328 #define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \ 331 #define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \\${bootargs}" \
329 " rescueReason=%d " 332 " rescueReason=%d "
330 333
331 static void aristainetos_run_rescue_command(int reason) 334 static void aristainetos_run_rescue_command(int reason)
332 { 335 {
333 char rescue_reason_command[80]; 336 char rescue_reason_command[80];
334 337
335 sprintf(rescue_reason_command, ARI_RESC_FMT, reason); 338 sprintf(rescue_reason_command, ARI_RESC_FMT, reason);
336 run_command(rescue_reason_command, 0); 339 run_command(rescue_reason_command, 0);
337 } 340 }
338 341
339 static int aristainetos_eeprom(void) 342 static int aristainetos_eeprom(void)
340 { 343 {
341 struct udevice *dev; 344 struct udevice *dev;
342 int off; 345 int off;
343 int ret; 346 int ret;
344 u8 data[0x10]; 347 u8 data[0x10];
345 u8 rescue_reason; 348 u8 rescue_reason;
346 349
347 off = fdt_path_offset(gd->fdt_blob, "eeprom0"); 350 off = fdt_path_offset(gd->fdt_blob, "eeprom0");
348 if (off < 0) { 351 if (off < 0) {
349 printf("%s: No eeprom0 path offset\n", __func__); 352 printf("%s: No eeprom0 path offset\n", __func__);
350 return off; 353 return off;
351 } 354 }
352 355
353 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); 356 ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev);
354 if (ret) { 357 if (ret) {
355 printf("%s: Could not find EEPROM\n", __func__); 358 printf("%s: Could not find EEPROM\n", __func__);
356 return ret; 359 return ret;
357 } 360 }
358 361
359 ret = i2c_set_chip_offset_len(dev, 2); 362 ret = i2c_set_chip_offset_len(dev, 2);
360 if (ret) 363 if (ret)
361 return ret; 364 return ret;
362 365
363 ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6); 366 ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6);
364 if (ret) { 367 if (ret) {
365 printf("%s: Could not read EEPROM\n", __func__); 368 printf("%s: Could not read EEPROM\n", __func__);
366 return ret; 369 return ret;
367 } 370 }
368 371
369 if (strncmp((char *)&data[3], "ReScUe", 6) == 0) { 372 if (strncmp((char *)&data[3], "ReScUe", 6) == 0) {
370 rescue_reason = *(uint8_t *)&data[9]; 373 rescue_reason = *(uint8_t *)&data[9];
371 memset(&data[3], 0xff, 7); 374 memset(&data[3], 0xff, 7);
372 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7); 375 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7);
373 printf("\nBooting into Rescue System (EEPROM)\n"); 376 printf("\nBooting into Rescue System (EEPROM)\n");
374 aristainetos_run_rescue_command(rescue_reason); 377 aristainetos_run_rescue_command(rescue_reason);
375 run_command("run rescue_load_fit rescueboot", 0); 378 run_command("run rescue_load_fit rescueboot", 0);
376 } else if (strncmp((char *)data, "DeF", 3) == 0) { 379 } else if (strncmp((char *)data, "DeF", 3) == 0) {
377 memset(data, 0xff, 3); 380 memset(data, 0xff, 3);
378 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3); 381 i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3);
379 printf("\nClear u-boot environment (set back to defaults)\n"); 382 printf("\nClear u-boot environment (set back to defaults)\n");
380 run_command("run default_env; saveenv; saveenv", 0); 383 run_command("run default_env; saveenv; saveenv", 0);
381 } 384 }
382 385
383 return 0; 386 return 0;
384 }; 387 };
385 388
386 static void aristainetos_bootmode_settings(void) 389 static void aristainetos_bootmode_settings(void)
387 { 390 {
388 struct gpio_desc *desc; 391 struct gpio_desc *desc;
389 struct src *psrc = (struct src *)SRC_BASE_ADDR; 392 struct src *psrc = (struct src *)SRC_BASE_ADDR;
390 unsigned int sbmr1 = readl(&psrc->sbmr1); 393 unsigned int sbmr1 = readl(&psrc->sbmr1);
391 char *my_bootdelay; 394 char *my_bootdelay;
392 char bootmode = 0; 395 char bootmode = 0;
393 int ret; 396 int ret;
394 397
395 /* 398 /*
396 * Check the boot-source. If booting from NOR Flash, 399 * Check the boot-source. If booting from NOR Flash,
397 * disable bootdelay 400 * disable bootdelay
398 */ 401 */
399 ret = gpio_hog_lookup_name("bootsel0", &desc); 402 ret = gpio_hog_lookup_name("bootsel0", &desc);
400 if (!ret) 403 if (!ret)
401 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0; 404 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0;
402 ret = gpio_hog_lookup_name("bootsel1", &desc); 405 ret = gpio_hog_lookup_name("bootsel1", &desc);
403 if (!ret) 406 if (!ret)
404 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1; 407 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1;
405 ret = gpio_hog_lookup_name("bootsel2", &desc); 408 ret = gpio_hog_lookup_name("bootsel2", &desc);
406 if (!ret) 409 if (!ret)
407 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2; 410 bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
408 411
409 if (bootmode == 7) { 412 if (bootmode == 7) {
410 my_bootdelay = env_get("nor_bootdelay"); 413 my_bootdelay = env_get("nor_bootdelay");
411 if (my_bootdelay) 414 if (my_bootdelay)
412 env_set("bootdelay", my_bootdelay); 415 env_set("bootdelay", my_bootdelay);
413 else 416 else
414 env_set("bootdelay", "-2"); 417 env_set("bootdelay", "-2");
415 } 418 }
416 419
417 if (sbmr1 & 0x40) { 420 if (sbmr1 & 0x40) {
418 env_set("bootmode", "1"); 421 env_set("bootmode", "1");
419 printf("SD bootmode jumper set!\n"); 422 printf("SD bootmode jumper set!\n");
420 } else { 423 } else {
421 env_set("bootmode", "0"); 424 env_set("bootmode", "0");
422 } 425 }
423 426
424 /* read out some jumper values*/ 427 /* read out some jumper values*/
425 ret = gpio_hog_lookup_name("env_reset", &desc); 428 ret = gpio_hog_lookup_name("env_reset", &desc);
426 if (!ret) { 429 if (!ret) {
427 if (dm_gpio_get_value(desc)) { 430 if (dm_gpio_get_value(desc)) {
428 printf("\nClear env (set back to defaults)\n"); 431 printf("\nClear env (set back to defaults)\n");
429 run_command("run default_env; saveenv; saveenv", 0); 432 run_command("run default_env; saveenv; saveenv", 0);
430 } 433 }
431 } 434 }
432 ret = gpio_hog_lookup_name("boot_rescue", &desc); 435 ret = gpio_hog_lookup_name("boot_rescue", &desc);
433 if (!ret) { 436 if (!ret) {
434 if (dm_gpio_get_value(desc)) { 437 if (dm_gpio_get_value(desc)) {
435 aristainetos_run_rescue_command(16); 438 aristainetos_run_rescue_command(16);
436 run_command("run rescue_xload_boot", 0); 439 run_command("run rescue_xload_boot", 0);
437 } 440 }
438 } 441 }
439 } 442 }
440 443
444 #if defined(CONFIG_DM_PMIC_DA9063)
445 /*
446 * On the aristainetos2c boards the PMIC needs to be initialized,
447 * because the Ethernet PHY uses a different regulator that is not
448 * setup per hardware default. This does not influence the other versions
449 * as this regulator isn't used there at all.
450 *
451 * Unfortunately we have not yet a interface to setup all
452 * values we need.
453 */
454 static int setup_pmic_voltages(void)
455 {
456 struct udevice *dev;
457 int off;
458 int ret;
459
460 off = fdt_path_offset(gd->fdt_blob, "pmic0");
461 if (off < 0) {
462 printf("%s: No pmic path offset\n", __func__);
463 return off;
464 }
465
466 ret = uclass_get_device_by_of_offset(UCLASS_PMIC, off, &dev);
467 if (ret) {
468 printf("%s: Could not find PMIC\n", __func__);
469 return ret;
470 }
471
472 pmic_reg_write(dev, DA9063_REG_PAGE_CON, 0x01);
473 pmic_reg_write(dev, DA9063_REG_BPRO_CFG, 0xc1);
474 ret = pmic_reg_read(dev, DA9063_REG_BUCK_ILIM_B);
475 if (ret < 0) {
476 printf("%s: error %d get register\n", __func__, ret);
477 return ret;
478 }
479 ret &= 0xf0;
480 ret |= 0x09;
481 pmic_reg_write(dev, DA9063_REG_BUCK_ILIM_B, ret);
482 pmic_reg_write(dev, DA9063_REG_VBPRO_A, 0x43);
483 pmic_reg_write(dev, DA9063_REG_VBPRO_B, 0xc3);
484
485 return 0;
486 }
487 #else
488 static int setup_pmic_voltages(void)
489 {
490 return 0;
491 }
492 #endif
493
441 int board_late_init(void) 494 int board_late_init(void)
442 { 495 {
443 int x, y; 496 int x, y;
444 497
445 led_default_state(); 498 led_default_state();
446 splash_get_pos(&x, &y); 499 splash_get_pos(&x, &y);
447 bmp_display((ulong)&bmp_logo_bitmap[0], x, y); 500 bmp_display((ulong)&bmp_logo_bitmap[0], x, y);
448 501
449 aristainetos_bootmode_settings(); 502 aristainetos_bootmode_settings();
450 503
451 /* eeprom work */ 504 /* eeprom work */
452 aristainetos_eeprom(); 505 aristainetos_eeprom();
453 506
454 /* set board_type */ 507 /* set board_type */
455 if (gd->board_type == BOARD_TYPE_4) 508 if (gd->board_type == BOARD_TYPE_4)
456 env_set("board_type", ARI_BT_4); 509 env_set("board_type", ARI_BT_4);
457 else 510 else
458 env_set("board_type", ARI_BT_7); 511 env_set("board_type", ARI_BT_7);
512
513 if (setup_pmic_voltages())
514 printf("Error setup PMIC\n");
459 515
460 return 0; 516 return 0;
461 } 517 }
462 518
463 int dram_init(void) 519 int dram_init(void)
464 { 520 {
465 gd->ram_size = imx_ddr_size(); 521 gd->ram_size = imx_ddr_size();
466 522
467 return 0; 523 return 0;
468 } 524 }
469 525
470 struct display_info_t const displays[] = { 526 struct display_info_t const displays[] = {
471 { 527 {
472 .bus = -1, 528 .bus = -1,
473 .addr = 0, 529 .addr = 0,
474 .pixfmt = IPU_PIX_FMT_RGB24, 530 .pixfmt = IPU_PIX_FMT_RGB24,
475 .detect = NULL, 531 .detect = NULL,
476 .enable = enable_lvds, 532 .enable = enable_lvds,
477 .mode = { 533 .mode = {
478 .name = "lb07wv8", 534 .name = "lb07wv8",
479 .refresh = 60, 535 .refresh = 60,
480 .xres = 800, 536 .xres = 800,
481 .yres = 480, 537 .yres = 480,
482 .pixclock = 30066, 538 .pixclock = 30066,
483 .left_margin = 88, 539 .left_margin = 88,
484 .right_margin = 88, 540 .right_margin = 88,
485 .upper_margin = 20, 541 .upper_margin = 20,
486 .lower_margin = 20, 542 .lower_margin = 20,
487 .hsync_len = 80, 543 .hsync_len = 80,
488 .vsync_len = 5, 544 .vsync_len = 5,
489 .sync = FB_SYNC_EXT, 545 .sync = FB_SYNC_EXT,
490 .vmode = FB_VMODE_NONINTERLACED 546 .vmode = FB_VMODE_NONINTERLACED
491 } 547 }
492 } 548 }
493 #if ((CONFIG_SYS_BOARD_VERSION == 2) || \ 549 #if ((CONFIG_SYS_BOARD_VERSION == 2) || \
494 (CONFIG_SYS_BOARD_VERSION == 3) || \ 550 (CONFIG_SYS_BOARD_VERSION == 3) || \
495 (CONFIG_SYS_BOARD_VERSION == 4) || \ 551 (CONFIG_SYS_BOARD_VERSION == 4) || \
496 (CONFIG_SYS_BOARD_VERSION == 5)) 552 (CONFIG_SYS_BOARD_VERSION == 5))
497 , { 553 , {
498 .bus = -1, 554 .bus = -1,
499 .addr = 0, 555 .addr = 0,
500 .pixfmt = IPU_PIX_FMT_RGB24, 556 .pixfmt = IPU_PIX_FMT_RGB24,
501 .detect = NULL, 557 .detect = NULL,
502 .enable = enable_spi_display, 558 .enable = enable_spi_display,
503 .mode = { 559 .mode = {
504 .name = "lg4573", 560 .name = "lg4573",
505 .refresh = 57, 561 .refresh = 57,
506 .xres = 480, 562 .xres = 480,
507 .yres = 800, 563 .yres = 800,
508 .pixclock = 37037, 564 .pixclock = 37037,
509 .left_margin = 59, 565 .left_margin = 59,
510 .right_margin = 10, 566 .right_margin = 10,
511 .upper_margin = 15, 567 .upper_margin = 15,
512 .lower_margin = 15, 568 .lower_margin = 15,
513 .hsync_len = 10, 569 .hsync_len = 10,
514 .vsync_len = 15, 570 .vsync_len = 15,
515 .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT | 571 .sync = FB_SYNC_EXT | FB_SYNC_HOR_HIGH_ACT |
516 FB_SYNC_VERT_HIGH_ACT, 572 FB_SYNC_VERT_HIGH_ACT,
517 .vmode = FB_VMODE_NONINTERLACED 573 .vmode = FB_VMODE_NONINTERLACED
518 } 574 }
519 } 575 }
520 #endif 576 #endif
521 }; 577 };
522 size_t display_count = ARRAY_SIZE(displays); 578 size_t display_count = ARRAY_SIZE(displays);
523 579
524 #if defined(CONFIG_MTD_RAW_NAND) 580 #if defined(CONFIG_MTD_RAW_NAND)
525 iomux_v3_cfg_t nfc_pads[] = { 581 iomux_v3_cfg_t nfc_pads[] = {
526 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), 582 MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL),
527 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), 583 MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL),
528 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL), 584 MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NO_PAD_CTRL),
529 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL), 585 MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NO_PAD_CTRL),
530 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL), 586 MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NO_PAD_CTRL),
531 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 587 MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
532 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL), 588 MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NO_PAD_CTRL),
533 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL), 589 MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NO_PAD_CTRL),
534 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL), 590 MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NO_PAD_CTRL),
535 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL), 591 MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NO_PAD_CTRL),
536 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL), 592 MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NO_PAD_CTRL),
537 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL), 593 MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NO_PAD_CTRL),
538 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL), 594 MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NO_PAD_CTRL),
539 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL), 595 MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NO_PAD_CTRL),
540 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL), 596 MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NO_PAD_CTRL),
541 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL), 597 MX6_PAD_SD4_DAT0__NAND_DQS | MUX_PAD_CTRL(NO_PAD_CTRL),
542 }; 598 };
543 599
544 static void setup_gpmi_nand(void) 600 static void setup_gpmi_nand(void)
545 { 601 {
546 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; 602 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
547 603
548 /* config gpmi nand iomux */ 604 /* config gpmi nand iomux */
549 imx_iomux_v3_setup_multiple_pads(nfc_pads, 605 imx_iomux_v3_setup_multiple_pads(nfc_pads,
550 ARRAY_SIZE(nfc_pads)); 606 ARRAY_SIZE(nfc_pads));
551 607
552 /* gate ENFC_CLK_ROOT clock first,before clk source switch */ 608 /* gate ENFC_CLK_ROOT clock first,before clk source switch */
553 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 609 clrbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
554 610
555 /* config gpmi and bch clock to 100 MHz */ 611 /* config gpmi and bch clock to 100 MHz */
556 clrsetbits_le32(&mxc_ccm->cs2cdr, 612 clrsetbits_le32(&mxc_ccm->cs2cdr,
557 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK | 613 MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK |
558 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK | 614 MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK |
559 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK, 615 MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK,
560 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) | 616 MXC_CCM_CS2CDR_ENFC_CLK_PODF(0) |
561 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) | 617 MXC_CCM_CS2CDR_ENFC_CLK_PRED(3) |
562 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3)); 618 MXC_CCM_CS2CDR_ENFC_CLK_SEL(3));
563 619
564 /* enable ENFC_CLK_ROOT clock */ 620 /* enable ENFC_CLK_ROOT clock */
565 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK); 621 setbits_le32(&mxc_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);
566 622
567 /* enable gpmi and bch clock gating */ 623 /* enable gpmi and bch clock gating */
568 setbits_le32(&mxc_ccm->CCGR4, 624 setbits_le32(&mxc_ccm->CCGR4,
569 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK | 625 MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK |
570 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK | 626 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK |
571 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK | 627 MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK |
572 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK | 628 MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK |
573 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET); 629 MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET);
574 630
575 /* enable apbh clock gating */ 631 /* enable apbh clock gating */
576 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); 632 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
577 } 633 }
578 #else 634 #else
579 static void setup_gpmi_nand(void) 635 static void setup_gpmi_nand(void)
580 { 636 {
581 } 637 }
582 #endif 638 #endif
583 639
584 int board_init(void) 640 int board_init(void)
585 { 641 {
586 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; 642 struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
587 643
588 /* address of boot parameters */ 644 /* address of boot parameters */
589 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; 645 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
590 646
591 setup_board_gpio(); 647 setup_board_gpio();
592 setup_gpmi_nand(); 648 setup_gpmi_nand();
593 setup_display(); 649 setup_display();
594 650
595 /* GPIO_1 for USB_OTG_ID */ 651 /* GPIO_1 for USB_OTG_ID */
596 clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0); 652 clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0);
597 return 0; 653 return 0;
598 } 654 }
599 655
600 int board_fit_config_name_match(const char *name) 656 int board_fit_config_name_match(const char *name)
601 { 657 {
602 if (gd->board_type == BOARD_TYPE_4 && 658 if (gd->board_type == BOARD_TYPE_4 &&
603 strchr(name, 0x34)) 659 strchr(name, 0x34))
604 return 0; 660 return 0;
605 661
606 if (gd->board_type == BOARD_TYPE_7 && 662 if (gd->board_type == BOARD_TYPE_7 &&
607 strchr(name, 0x37)) 663 strchr(name, 0x37))
608 return 0; 664 return 0;
609 665
610 return -1; 666 return -1;
611 } 667 }
612 668
613 static void do_board_detect(void) 669 static void do_board_detect(void)
614 { 670 {
615 int ret; 671 int ret;
616 char s[30]; 672 char s[30];
617 673
618 /* default use board type 7 */ 674 /* default use board type 7 */
619 gd->board_type = BOARD_TYPE_7; 675 gd->board_type = BOARD_TYPE_7;
620 if (env_init()) 676 if (env_init())
621 return; 677 return;
622 678
623 ret = env_get_f("panel", s, sizeof(s)); 679 ret = env_get_f("panel", s, sizeof(s));
624 if (ret < 0) 680 if (ret < 0)
625 return; 681 return;
626 682
627 if (!strncmp("lg4573", s, 6)) 683 if (!strncmp("lg4573", s, 6))
628 gd->board_type = BOARD_TYPE_4; 684 gd->board_type = BOARD_TYPE_4;
629 } 685 }
630 686
631 #ifdef CONFIG_DTB_RESELECT 687 #ifdef CONFIG_DTB_RESELECT
632 int embedded_dtb_select(void) 688 int embedded_dtb_select(void)
633 { 689 {
634 int rescan; 690 int rescan;
635 691
636 do_board_detect(); 692 do_board_detect();
637 fdtdec_resetup(&rescan); 693 fdtdec_resetup(&rescan);
638 694
639 return 0; 695 return 0;
640 } 696 }
641 #endif 697 #endif
642 698
configs/aristainetos2c_defconfig
Diff comments   View file @ 158d93a
1 CONFIG_ARM=y 1 CONFIG_ARM=y
2 CONFIG_ARCH_MX6=y 2 CONFIG_ARCH_MX6=y
3 CONFIG_SYS_TEXT_BASE=0x17800000 3 CONFIG_SYS_TEXT_BASE=0x17800000
4 CONFIG_SYS_MALLOC_F_LEN=0xe000 4 CONFIG_SYS_MALLOC_F_LEN=0xe000
5 CONFIG_TARGET_ARISTAINETOS2C=y 5 CONFIG_TARGET_ARISTAINETOS2C=y
6 CONFIG_ENV_OFFSET=0xD0000 6 CONFIG_ENV_OFFSET=0xD0000
7 CONFIG_DM_GPIO=y 7 CONFIG_DM_GPIO=y
8 CONFIG_NR_DRAM_BANKS=1 8 CONFIG_NR_DRAM_BANKS=1
9 CONFIG_ENV_OFFSET_REDUND=0xE0000 9 CONFIG_ENV_OFFSET_REDUND=0xE0000
10 CONFIG_IMX_HAB=y 10 CONFIG_IMX_HAB=y
11 # CONFIG_CMD_DEKBLOB is not set 11 # CONFIG_CMD_DEKBLOB is not set
12 CONFIG_FIT=y 12 CONFIG_FIT=y
13 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" 13 CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg"
14 CONFIG_BOOTDELAY=3 14 CONFIG_BOOTDELAY=3
15 CONFIG_USE_BOOTCOMMAND=y 15 CONFIG_USE_BOOTCOMMAND=y
16 CONFIG_BOOTCOMMAND="run ari_boot" 16 CONFIG_BOOTCOMMAND="run ari_boot"
17 # CONFIG_CONSOLE_MUX is not set 17 # CONFIG_CONSOLE_MUX is not set
18 CONFIG_SYS_CONSOLE_IS_IN_ENV=y 18 CONFIG_SYS_CONSOLE_IS_IN_ENV=y
19 CONFIG_SUPPORT_RAW_INITRD=y 19 CONFIG_SUPPORT_RAW_INITRD=y
20 CONFIG_VERSION_VARIABLE=y 20 CONFIG_VERSION_VARIABLE=y
21 CONFIG_BOUNCE_BUFFER=y 21 CONFIG_BOUNCE_BUFFER=y
22 CONFIG_BOARD_TYPES=y 22 CONFIG_BOARD_TYPES=y
23 CONFIG_BOARD_EARLY_INIT_F=y 23 CONFIG_BOARD_EARLY_INIT_F=y
24 CONFIG_HUSH_PARSER=y 24 CONFIG_HUSH_PARSER=y
25 CONFIG_AUTOBOOT_KEYED=y 25 CONFIG_AUTOBOOT_KEYED=y
26 CONFIG_AUTOBOOT_ENCRYPTION=y 26 CONFIG_AUTOBOOT_ENCRYPTION=y
27 CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" 27 CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb"
28 CONFIG_CMD_BOOTZ=y 28 CONFIG_CMD_BOOTZ=y
29 # CONFIG_BOOTM_NETBSD is not set 29 # CONFIG_BOOTM_NETBSD is not set
30 # CONFIG_BOOTM_PLAN9 is not set 30 # CONFIG_BOOTM_PLAN9 is not set
31 # CONFIG_BOOTM_RTEMS is not set 31 # CONFIG_BOOTM_RTEMS is not set
32 # CONFIG_BOOTM_VXWORKS is not set 32 # CONFIG_BOOTM_VXWORKS is not set
33 # CONFIG_CMD_FLASH is not set 33 # CONFIG_CMD_FLASH is not set
34 CONFIG_CMD_GPIO=y 34 CONFIG_CMD_GPIO=y
35 CONFIG_CMD_I2C=y 35 CONFIG_CMD_I2C=y
36 CONFIG_CMD_MMC=y 36 CONFIG_CMD_MMC=y
37 # CONFIG_CMD_PINMUX is not set 37 # CONFIG_CMD_PINMUX is not set
38 # CONFIG_CMD_SATA is not set 38 # CONFIG_CMD_SATA is not set
39 CONFIG_CMD_USB=y 39 CONFIG_CMD_USB=y
40 CONFIG_CMD_DHCP=y 40 CONFIG_CMD_DHCP=y
41 CONFIG_CMD_MII=y 41 CONFIG_CMD_MII=y
42 CONFIG_CMD_PING=y 42 CONFIG_CMD_PING=y
43 CONFIG_CMD_BMP=y 43 CONFIG_CMD_BMP=y
44 CONFIG_CMD_CACHE=y 44 CONFIG_CMD_CACHE=y
45 # CONFIG_CMD_HASH is not set 45 # CONFIG_CMD_HASH is not set
46 CONFIG_CMD_EXT2=y 46 CONFIG_CMD_EXT2=y
47 CONFIG_CMD_EXT4=y 47 CONFIG_CMD_EXT4=y
48 CONFIG_CMD_EXT4_WRITE=y 48 CONFIG_CMD_EXT4_WRITE=y
49 CONFIG_CMD_FAT=y 49 CONFIG_CMD_FAT=y
50 CONFIG_CMD_FS_GENERIC=y 50 CONFIG_CMD_FS_GENERIC=y
51 CONFIG_CMD_MTDPARTS=y 51 CONFIG_CMD_MTDPARTS=y
52 CONFIG_CMD_UBI=y 52 CONFIG_CMD_UBI=y
53 CONFIG_OF_CONTROL=y 53 CONFIG_OF_CONTROL=y
54 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4" 54 CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4"
55 CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7" 55 CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7"
56 CONFIG_DTB_RESELECT=y 56 CONFIG_DTB_RESELECT=y
57 CONFIG_MULTI_DTB_FIT=y 57 CONFIG_MULTI_DTB_FIT=y
58 CONFIG_ENV_IS_IN_SPI_FLASH=y 58 CONFIG_ENV_IS_IN_SPI_FLASH=y
59 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y 59 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
60 CONFIG_SYS_RELOC_GD_ENV_ADDR=y 60 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
61 CONFIG_APBH_DMA=y 61 CONFIG_APBH_DMA=y
62 CONFIG_APBH_DMA_BURST=y 62 CONFIG_APBH_DMA_BURST=y
63 CONFIG_APBH_DMA_BURST8=y 63 CONFIG_APBH_DMA_BURST8=y
64 CONFIG_GPIO_HOG=y 64 CONFIG_GPIO_HOG=y
65 CONFIG_DM_PCA953X=y 65 CONFIG_DM_PCA953X=y
66 CONFIG_DM_I2C=y 66 CONFIG_DM_I2C=y
67 CONFIG_LED=y 67 CONFIG_LED=y
68 CONFIG_LED_GPIO=y 68 CONFIG_LED_GPIO=y
69 CONFIG_MISC=y 69 CONFIG_MISC=y
70 CONFIG_I2C_EEPROM=y 70 CONFIG_I2C_EEPROM=y
71 CONFIG_DM_MMC=y 71 CONFIG_DM_MMC=y
72 CONFIG_FSL_USDHC=y 72 CONFIG_FSL_USDHC=y
73 CONFIG_MTD=y 73 CONFIG_MTD=y
74 CONFIG_DM_SPI_FLASH=y 74 CONFIG_DM_SPI_FLASH=y
75 CONFIG_SF_DEFAULT_MODE=0 75 CONFIG_SF_DEFAULT_MODE=0
76 CONFIG_SF_DEFAULT_SPEED=20000000 76 CONFIG_SF_DEFAULT_SPEED=20000000
77 CONFIG_SPI_FLASH_STMICRO=y 77 CONFIG_SPI_FLASH_STMICRO=y
78 CONFIG_SPI_FLASH_MTD=y 78 CONFIG_SPI_FLASH_MTD=y
79 CONFIG_MTD_UBI_FASTMAP=y 79 CONFIG_MTD_UBI_FASTMAP=y
80 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 80 CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1
81 CONFIG_PHYLIB=y 81 CONFIG_PHYLIB=y
82 CONFIG_PHY_MICREL=y 82 CONFIG_PHY_MICREL=y
83 CONFIG_PHY_MICREL_KSZ90X1=y 83 CONFIG_PHY_MICREL_KSZ90X1=y
84 CONFIG_DM_ETH=y 84 CONFIG_DM_ETH=y
85 CONFIG_MII=y 85 CONFIG_MII=y
86 CONFIG_PHY=y 86 CONFIG_PHY=y
87 CONFIG_PINCTRL=y 87 CONFIG_PINCTRL=y
88 CONFIG_PINCTRL_IMX6=y 88 CONFIG_PINCTRL_IMX6=y
89 CONFIG_DM_PMIC=y 89 CONFIG_DM_PMIC=y
90 # CONFIG_SPL_PMIC_CHILDREN is not set
91 CONFIG_DM_PMIC_DA9063=y
90 CONFIG_DM_REGULATOR=y 92 CONFIG_DM_REGULATOR=y
93 CONFIG_DM_REGULATOR_DA9063=y
91 CONFIG_DM_REGULATOR_FIXED=y 94 CONFIG_DM_REGULATOR_FIXED=y
92 CONFIG_DM_PWM=y 95 CONFIG_DM_PWM=y
93 CONFIG_PWM_IMX=y 96 CONFIG_PWM_IMX=y
94 CONFIG_DM_RTC=y 97 CONFIG_DM_RTC=y
95 CONFIG_RTC_DS1307=y 98 CONFIG_RTC_DS1307=y
96 CONFIG_DM_SERIAL=y 99 CONFIG_DM_SERIAL=y
97 CONFIG_SPI=y 100 CONFIG_SPI=y
98 CONFIG_DM_SPI=y 101 CONFIG_DM_SPI=y
99 CONFIG_MXC_SPI=y 102 CONFIG_MXC_SPI=y
100 CONFIG_SYSRESET=y 103 CONFIG_SYSRESET=y
101 CONFIG_SYSRESET_WATCHDOG=y 104 CONFIG_SYSRESET_WATCHDOG=y
102 CONFIG_USB=y 105 CONFIG_USB=y
103 CONFIG_DM_USB=y 106 CONFIG_DM_USB=y
104 CONFIG_USB_STORAGE=y 107 CONFIG_USB_STORAGE=y
105 CONFIG_DM_VIDEO=y 108 CONFIG_DM_VIDEO=y
106 CONFIG_SYS_WHITE_ON_BLACK=y 109 CONFIG_SYS_WHITE_ON_BLACK=y
107 CONFIG_DISPLAY=y 110 CONFIG_DISPLAY=y
108 CONFIG_VIDEO_IPUV3=y 111 CONFIG_VIDEO_IPUV3=y
109 CONFIG_IMX_WATCHDOG=y 112 CONFIG_IMX_WATCHDOG=y
110 # CONFIG_EFI_LOADER is not set 113 # CONFIG_EFI_LOADER is not set
111 114