Eric Lee / smarc-uboot

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/*

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/*

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*

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*

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* Author: Fabio Estevam <fabio.estevam@freescale.com>

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* Author: Fabio Estevam <fabio.estevam@freescale.com>

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*

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*

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* SPDX-License-Identifier: GPL-2.0+

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* SPDX-License-Identifier: GPL-2.0+

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*/

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*/

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#include <common.h>

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#include <common.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <asm/arch/clock.h>

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#include <asm/arch/clock.h>

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#include <asm/arch/imx-regs.h>

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#include <asm/arch/imx-regs.h>

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#include <asm/arch/crm_regs.h>

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#include <asm/arch/crm_regs.h>

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#include <asm/arch/iomux.h>

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#include <asm/arch/iomux.h>

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#include <asm/arch/mx6-pins.h>

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#include <asm/arch/mx6-pins.h>

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#include <asm/errno.h>

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#include <asm/errno.h>

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#include <asm/gpio.h>

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#include <asm/gpio.h>

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#include <asm/imx-common/iomux-v3.h>

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#include <asm/imx-common/iomux-v3.h>

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#include <asm/imx-common/boot_mode.h>

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#include <asm/imx-common/boot_mode.h>

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#include <mmc.h>

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#include <mmc.h>

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#include <fsl_esdhc.h>

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#include <fsl_esdhc.h>

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#include <miiphy.h>

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#include <miiphy.h>

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#include <netdev.h>

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#include <netdev.h>

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#include <phy.h>

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#include <phy.h>

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#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

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#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

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#include <lcd.h>

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#include <lcd.h>

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#include <mxc_epdc_fb.h>

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#include <mxc_epdc_fb.h>

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#endif

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#endif

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#include <asm/arch/mxc_hdmi.h>

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#include <asm/arch/mxc_hdmi.h>

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#include <linux/fb.h>

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#include <linux/fb.h>

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#include <ipu_pixfmt.h>

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#include <ipu_pixfmt.h>

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#include <asm/io.h>

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#include <asm/io.h>

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#include <asm/arch/sys_proto.h>

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#include <asm/arch/sys_proto.h>

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#include <pwm.h>

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#include <pwm.h>

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#ifdef CONFIG_SYS_I2C_MXC

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#ifdef CONFIG_SYS_I2C_MXC

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#include <i2c.h>

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#include <i2c.h>

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#include <asm/imx-common/mxc_i2c.h>

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#include <asm/imx-common/mxc_i2c.h>

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#endif

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#endif

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#include "smarcfimx6.h"

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#include "smarcfimx6.h"

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#ifdef CONFIG_CMD_SATA

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#ifdef CONFIG_CMD_SATA

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#include <asm/imx-common/sata.h>

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#include <asm/imx-common/sata.h>

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#endif

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#endif

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#ifdef CONFIG_FASTBOOT

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#ifdef CONFIG_FASTBOOT

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#include <fastboot.h>

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#include <fastboot.h>

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#ifdef CONFIG_ANDROID_RECOVERY

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#ifdef CONFIG_ANDROID_RECOVERY

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#include <recovery.h>

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#include <recovery.h>

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#endif

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#endif

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#endif /*CONFIG_FASTBOOT*/

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#endif /*CONFIG_FASTBOOT*/

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DECLARE_GLOBAL_DATA_PTR;

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DECLARE_GLOBAL_DATA_PTR;

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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \

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PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \

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#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \

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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \

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PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \

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PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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PAD_CTL_SRE_FAST | PAD_CTL_HYS)

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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

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#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \

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#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \

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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_HIGH | \

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#define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_HIGH | \

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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

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PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)

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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \

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#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \

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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \

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PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \

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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \

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PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \

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PAD_CTL_ODE | PAD_CTL_SRE_FAST)

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PAD_CTL_ODE | PAD_CTL_SRE_FAST)

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#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \

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#define EPDC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_SPEED_MED | \

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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

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PAD_CTL_DSE_40ohm | PAD_CTL_HYS)

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#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \

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#define WEAK_PULLUP (PAD_CTL_PUS_100K_UP | \

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \

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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \

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PAD_CTL_SRE_SLOW)

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PAD_CTL_SRE_SLOW)

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#ifdef CONFIG_SYS_I2C_MXC

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#ifdef CONFIG_SYS_I2C_MXC

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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

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#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)

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#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)

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#define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)

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/*

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/*

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* Read header information from EEPROM into global structure.

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* Read header information from EEPROM into global structure.

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*/

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*/

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static int read_eeprom(struct smarcfimx6_id *header)

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static int read_eeprom(struct smarcfimx6_id *header)

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{

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{

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/* Check if baseboard eeprom is available */

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/* Check if baseboard eeprom is available */

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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {

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if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {

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puts("Could not probe the EEPROM; something fundamentally "

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puts("Could not probe the EEPROM; something fundamentally "

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"wrong on the I2C bus.\n");

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"wrong on the I2C bus.\n");

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return -ENODEV;

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return -ENODEV;

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}

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}

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/* read the eeprom using i2c */

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/* read the eeprom using i2c */

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,

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sizeof(struct smarcfimx6_id))) {

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sizeof(struct smarcfimx6_id))) {

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puts("Could not read the EEPROM; something fundamentally"

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puts("Could not read the EEPROM; something fundamentally"

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" wrong on the I2C bus.\n");

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" wrong on the I2C bus.\n");

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return -EIO;

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return -EIO;

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}

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}

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if (header->magic != 0xEE3355AA) {

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if (header->magic != 0xEE3355AA) {

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/*

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/*

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* read the eeprom using i2c again,

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* read the eeprom using i2c again,

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* but use only a 1 byte address

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* but use only a 1 byte address

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*/

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*/

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,

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if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,

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sizeof(struct smarcfimx6_id))) {

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sizeof(struct smarcfimx6_id))) {

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puts("Could not read the EEPROM; something "

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puts("Could not read the EEPROM; something "

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"fundamentally wrong on the I2C bus.\n");

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"fundamentally wrong on the I2C bus.\n");

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return -EIO;

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return -EIO;

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}

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}

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if (header->magic != 0xEE3355AA) {

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if (header->magic != 0xEE3355AA) {

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printf("Incorrect magic number (0x%x) in EEPROM\n",

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printf("Incorrect magic number (0x%x) in EEPROM\n",

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header->magic);

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header->magic);

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return -EINVAL;

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return -EINVAL;

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}

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}

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}

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}

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return 0;

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return 0;

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}

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}

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/*I2C1 I2C_PM*/

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/*I2C1 I2C_PM*/

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struct i2c_pads_info i2c_pad_info1 = {

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struct i2c_pads_info i2c_pad_info1 = {

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.scl = {

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.scl = {

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.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,

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.i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,

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.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,

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.gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,

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.gp = IMX_GPIO_NR(3, 21)

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.gp = IMX_GPIO_NR(3, 21)

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,

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.i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,

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.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,

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.gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,

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.gp = IMX_GPIO_NR(3, 28)

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.gp = IMX_GPIO_NR(3, 28)

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}

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}

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};

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};

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/* I2C2 HDMI */

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/* I2C2 HDMI */

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struct i2c_pads_info i2c_pad_info2 = {

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struct i2c_pads_info i2c_pad_info2 = {

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.scl = {

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.scl = {

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.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,

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.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,

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.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,

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.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,

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.gp = IMX_GPIO_NR(4, 12)

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.gp = IMX_GPIO_NR(4, 12)

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,

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.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,

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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,

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.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,

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.gp = IMX_GPIO_NR(4, 13)

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.gp = IMX_GPIO_NR(4, 13)

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}

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}

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};

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};

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/* I2C3 TCA9546APWR */

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/* I2C3 TCA9546APWR */

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struct i2c_pads_info i2c_pad_info3 = {

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struct i2c_pads_info i2c_pad_info3 = {

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.scl = {

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.scl = {

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.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,

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.i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,

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.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,

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.gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,

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.gp = IMX_GPIO_NR(3, 17)

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.gp = IMX_GPIO_NR(3, 17)

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},

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},

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.sda = {

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.sda = {

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.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,

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.i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,

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.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,

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.gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,

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.gp = IMX_GPIO_NR(3, 18)

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.gp = IMX_GPIO_NR(3, 18)

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}

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}

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};

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};

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#endif

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#endif

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int dram_init(void)

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int dram_init(void)

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{

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{

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gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);

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gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);

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return 0;

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return 0;

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}

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}

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/* SER0/UART1 */

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/* SER0/UART1 */

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iomux_v3_cfg_t const uart1_pads[] = {

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iomux_v3_cfg_t const uart1_pads[] = {

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MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_EIM_D20__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_EIM_D20__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_EIM_D19__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_EIM_D19__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* SER1/UART2 */

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/* SER1/UART2 */

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iomux_v3_cfg_t const uart2_pads[] = {

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iomux_v3_cfg_t const uart2_pads[] = {

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MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* SER2/UART4 */

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/* SER2/UART4 */

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iomux_v3_cfg_t const uart4_pads[] = {

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iomux_v3_cfg_t const uart4_pads[] = {

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MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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/* SER3/UART5 Debug Port */

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/* SER3/UART5 Debug Port */

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iomux_v3_cfg_t const uart5_pads[] = {

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iomux_v3_cfg_t const uart5_pads[] = {

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MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),

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};

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};

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iomux_v3_cfg_t const wdt_pads[] = {

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iomux_v3_cfg_t const wdt_pads[] = {

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MX6_PAD_EIM_D16__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX6_PAD_EIM_D16__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),

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};

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};

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iomux_v3_cfg_t const reset_out_pads[] = {

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iomux_v3_cfg_t const reset_out_pads[] = {

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MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),

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MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),

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};

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};

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iomux_v3_cfg_t const enet_pads[] = {

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iomux_v3_cfg_t const enet_pads[] = {

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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

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MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL),

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};

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};

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static void setup_iomux_enet(void)

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static void setup_iomux_enet(void)

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{

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{

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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

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imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));

237

gpio_direction_input(IMX_GPIO_NR(4, 11));

237

gpio_direction_input(IMX_GPIO_NR(4, 11));

238

}

238

}

239

240

/* SDIO */

240

/* SDIO */

241

iomux_v3_cfg_t const usdhc2_pads[] = {

241

iomux_v3_cfg_t const usdhc2_pads[] = {

242

MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

242

MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

243

MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

243

MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

244

MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

244

MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

245

MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

245

MX6_PAD_SD2_DAT1__SD2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

246

MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

246

MX6_PAD_SD2_DAT2__SD2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

247

MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

247

MX6_PAD_SD2_DAT3__SD2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

248

MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */

248

MX6_PAD_ENET_TX_EN__GPIO1_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */

249

MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */

249

MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */

250

MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), /* SDIO_PWR_EN */

250

MX6_PAD_SD1_CMD__GPIO1_IO18 | MUX_PAD_CTRL(NO_PAD_CTRL), /* SDIO_PWR_EN */

251

};

251

};

252

253

/* SDMMC */

253

/* SDMMC */

254

iomux_v3_cfg_t const usdhc3_pads[] = {

254

iomux_v3_cfg_t const usdhc3_pads[] = {

255

MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

255

MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

256

MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

256

MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

257

MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

257

MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

258

MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

258

MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

259

MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

259

MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

260

MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

260

MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

261

MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),

261

MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),

262

};

262

};

263

264

/* eMMC */

264

/* eMMC */

265

iomux_v3_cfg_t const usdhc4_pads[] = {

265

iomux_v3_cfg_t const usdhc4_pads[] = {

266

MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

266

MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),

267

MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

267

MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),

268

MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

268

MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

269

MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

269

MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

270

MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

270

MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

271

MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

271

MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

272

MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

272

MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

273

MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

273

MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

274

MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

274

MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

275

MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

275

MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),

276

};

276

};

277

278

#ifdef CONFIG_SYS_USE_SPINOR

278

#ifdef CONFIG_SYS_USE_SPINOR

279

/* SPI0 */

279

/* SPI0 */

280

iomux_v3_cfg_t const ecspi2_pads[] = {

280

iomux_v3_cfg_t const ecspi2_pads[] = {

281

MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

281

MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

282

MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

282

MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

283

MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

283

MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

284

MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

284

MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

285

MX6_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/

285

MX6_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS2#*/

286

MX6_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/

286

MX6_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS3#*/

287

};

287

};

288

289

static void setup_spinor(void)

289

static void setup_spinor(void)

290

{

290

{

291

imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));

291

imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));

292

}

292

}

293

#endif

293

#endif

294

295

/* SPI1 */

295

/* SPI1 */

296

iomux_v3_cfg_t const ecspi1_pads[] = {

296

iomux_v3_cfg_t const ecspi1_pads[] = {

297

MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

297

MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),

298

MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

298

MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),

299

MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

299

MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),

300

MX6_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

300

MX6_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS0#*/

301

MX6_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/

301

MX6_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL), /*SS1#*/

302

};

302

};

303

304

iomux_v3_cfg_t const pcie_pads[] = {

304

iomux_v3_cfg_t const pcie_pads[] = {

305

MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Present */

305

MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Present */

306

MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */

306

MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), /* RESET */

307

MX6_PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Clock Request */

307

MX6_PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), /* PCIe Clock Request */

308

};

308

};

309

310

static void setup_pcie(void)

310

static void setup_pcie(void)

311

{

311

{

312

imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));

312

imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));

313

gpio_direction_input(IMX_GPIO_NR(1, 16));

313

gpio_direction_input(IMX_GPIO_NR(1, 16));

314

gpio_direction_input(IMX_GPIO_NR(1, 17));

314

gpio_direction_input(IMX_GPIO_NR(1, 17));

315

gpio_direction_input(IMX_GPIO_NR(1, 19));

315

gpio_direction_input(IMX_GPIO_NR(1, 19));

316

gpio_direction_output(IMX_GPIO_NR(1,20), 0);

316

gpio_direction_output(IMX_GPIO_NR(1,20), 0);

317

}

317

}

318

319

iomux_v3_cfg_t const di0_pads[] = {

319

iomux_v3_cfg_t const di0_pads[] = {

320

MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */

320

MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK, /* DISP0_CLK */

321

MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */

321

MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, /* DISP0_HSYNC */

322

MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */

322

MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, /* DISP0_VSYNC */

323

};

323

};

324

325

/* CAN0/FLEXCAN1 */

325

/* CAN0/FLEXCAN1 */

326

iomux_v3_cfg_t const flexcan1_pads[] = {

326

iomux_v3_cfg_t const flexcan1_pads[] = {

327

328

MX6_PAD_GPIO_7__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),

328

MX6_PAD_GPIO_7__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),

329

MX6_PAD_GPIO_8__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP),

329

MX6_PAD_GPIO_8__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP),

330

};

330

};

331

332

/* CAN1/FLEXCAN2 */

332

/* CAN1/FLEXCAN2 */

333

iomux_v3_cfg_t const flexcan2_pads[] = {

333

iomux_v3_cfg_t const flexcan2_pads[] = {

334

MX6_PAD_KEY_COL4__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP),

334

MX6_PAD_KEY_COL4__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP),

335

MX6_PAD_KEY_ROW4__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP),

335

MX6_PAD_KEY_ROW4__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP),

336

};

336

};

337

338

/* GPIOs */

338

/* GPIOs */

339

iomux_v3_cfg_t const gpios_pads[] = {

339

iomux_v3_cfg_t const gpios_pads[] = {

340

MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */

340

MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */

341

MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */

341

MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */

342

MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */

342

MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */

343

MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */

343

MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */

344

MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */

344

MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */

345

MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */

345

MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */

346

MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */

346

MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */

347

MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */

347

MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */

348

MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */

348

MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */

349

MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */

349

MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */

350

MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */

350

MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */

351

};

351

};

352

353

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

353

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

354

static iomux_v3_cfg_t const epdc_enable_pads[] = {

354

static iomux_v3_cfg_t const epdc_enable_pads[] = {

355

MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

355

MX6_PAD_EIM_A16__EPDC_DATA00 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

356

MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

356

MX6_PAD_EIM_DA10__EPDC_DATA01 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

357

MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

357

MX6_PAD_EIM_DA12__EPDC_DATA02 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

358

MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

358

MX6_PAD_EIM_DA11__EPDC_DATA03 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

359

MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

359

MX6_PAD_EIM_LBA__EPDC_DATA04 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

360

MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

360

MX6_PAD_EIM_EB2__EPDC_DATA05 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

361

MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

361

MX6_PAD_EIM_CS0__EPDC_DATA06 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

362

MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

362

MX6_PAD_EIM_RW__EPDC_DATA07 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

363

MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

363

MX6_PAD_EIM_A21__EPDC_GDCLK | MUX_PAD_CTRL(EPDC_PAD_CTRL),

364

MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),

364

MX6_PAD_EIM_A22__EPDC_GDSP | MUX_PAD_CTRL(EPDC_PAD_CTRL),

365

MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

365

MX6_PAD_EIM_A23__EPDC_GDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

366

MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),

366

MX6_PAD_EIM_A24__EPDC_GDRL | MUX_PAD_CTRL(EPDC_PAD_CTRL),

367

MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL),

367

MX6_PAD_EIM_D31__EPDC_SDCLK_P | MUX_PAD_CTRL(EPDC_PAD_CTRL),

368

MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

368

MX6_PAD_EIM_D27__EPDC_SDOE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

369

MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

369

MX6_PAD_EIM_DA1__EPDC_SDLE | MUX_PAD_CTRL(EPDC_PAD_CTRL),

370

MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),

370

MX6_PAD_EIM_EB1__EPDC_SDSHR | MUX_PAD_CTRL(EPDC_PAD_CTRL),

371

MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

371

MX6_PAD_EIM_DA2__EPDC_BDR0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

372

MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

372

MX6_PAD_EIM_DA4__EPDC_SDCE0 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

373

MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

373

MX6_PAD_EIM_DA5__EPDC_SDCE1 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

374

MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

374

MX6_PAD_EIM_DA6__EPDC_SDCE2 | MUX_PAD_CTRL(EPDC_PAD_CTRL),

375

};

375

};

376

377

static iomux_v3_cfg_t const epdc_disable_pads[] = {

377

static iomux_v3_cfg_t const epdc_disable_pads[] = {

378

MX6_PAD_EIM_A16__GPIO2_IO22,

378

MX6_PAD_EIM_A16__GPIO2_IO22,

379

MX6_PAD_EIM_DA10__GPIO3_IO10,

379

MX6_PAD_EIM_DA10__GPIO3_IO10,

380

MX6_PAD_EIM_DA12__GPIO3_IO12,

380

MX6_PAD_EIM_DA12__GPIO3_IO12,

381

MX6_PAD_EIM_DA11__GPIO3_IO11,

381

MX6_PAD_EIM_DA11__GPIO3_IO11,

382

MX6_PAD_EIM_LBA__GPIO2_IO27,

382

MX6_PAD_EIM_LBA__GPIO2_IO27,

383

MX6_PAD_EIM_EB2__GPIO2_IO30,

383

MX6_PAD_EIM_EB2__GPIO2_IO30,

384

MX6_PAD_EIM_CS0__GPIO2_IO23,

384

MX6_PAD_EIM_CS0__GPIO2_IO23,

385

MX6_PAD_EIM_RW__GPIO2_IO26,

385

MX6_PAD_EIM_RW__GPIO2_IO26,

386

MX6_PAD_EIM_A21__GPIO2_IO17,

386

MX6_PAD_EIM_A21__GPIO2_IO17,

387

MX6_PAD_EIM_A22__GPIO2_IO16,

387

MX6_PAD_EIM_A22__GPIO2_IO16,

388

MX6_PAD_EIM_A23__GPIO6_IO06,

388

MX6_PAD_EIM_A23__GPIO6_IO06,

389

MX6_PAD_EIM_A24__GPIO5_IO04,

389

MX6_PAD_EIM_A24__GPIO5_IO04,

390

MX6_PAD_EIM_D31__GPIO3_IO31,

390

MX6_PAD_EIM_D31__GPIO3_IO31,

391

MX6_PAD_EIM_D27__GPIO3_IO27,

391

MX6_PAD_EIM_D27__GPIO3_IO27,

392

MX6_PAD_EIM_DA1__GPIO3_IO01,

392

MX6_PAD_EIM_DA1__GPIO3_IO01,

393

MX6_PAD_EIM_EB1__GPIO2_IO29,

393

MX6_PAD_EIM_EB1__GPIO2_IO29,

394

MX6_PAD_EIM_DA2__GPIO3_IO02,

394

MX6_PAD_EIM_DA2__GPIO3_IO02,

395

MX6_PAD_EIM_DA4__GPIO3_IO04,

395

MX6_PAD_EIM_DA4__GPIO3_IO04,

396

MX6_PAD_EIM_DA5__GPIO3_IO05,

396

MX6_PAD_EIM_DA5__GPIO3_IO05,

397

MX6_PAD_EIM_DA6__GPIO3_IO06,

397

MX6_PAD_EIM_DA6__GPIO3_IO06,

398

};

398

};

399

#endif

399

#endif

400

401

static void setup_iomux_uart1(void)

401

static void setup_iomux_uart1(void)

402

{

402

{

403

imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));

403

imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));

404

}

404

}

405

406

static void setup_iomux_uart2(void)

406

static void setup_iomux_uart2(void)

407

{

407

{

408

imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));

408

imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));

409

}

409

}

410

411

static void setup_iomux_uart4(void)

411

static void setup_iomux_uart4(void)

412

{

412

{

413

imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));

413

imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));

414

}

414

}

415

416

static void setup_iomux_uart5(void)

416

static void setup_iomux_uart5(void)

417

{

417

{

418

imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));

418

imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));

419

}

419

}

420

421

static void setup_iomux_wdt(void)

421

static void setup_iomux_wdt(void)

422

{

422

{

423

imx_iomux_v3_setup_multiple_pads(wdt_pads, ARRAY_SIZE(wdt_pads));

423

imx_iomux_v3_setup_multiple_pads(wdt_pads, ARRAY_SIZE(wdt_pads));

424

425

/* Set HW_WDT as Output High */

425

/* Set HW_WDT as Output High */

426

gpio_direction_output(IMX_GPIO_NR(3, 16) , 1);

426

gpio_direction_output(IMX_GPIO_NR(3, 16) , 1);

427

}

427

}

428

429

static void setup_iomux_reset_out(void)

429

static void setup_iomux_reset_out(void)

430

{

430

{

431

imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));

431

imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));

432

433

/* Set CPU RESET_OUT as Output */

433

/* Set CPU RESET_OUT as Output */

434

gpio_direction_output(IMX_GPIO_NR(6, 16) , 0);

434

gpio_direction_output(IMX_GPIO_NR(6, 16) , 0);

435

}

435

}

436

437

static void setup_spi1(void)

437

static void setup_spi1(void)

438

{

438

{

439

imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));

439

imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));

440

gpio_direction_output(IMX_GPIO_NR(4, 9), 0);

440

gpio_direction_output(IMX_GPIO_NR(4, 9), 0);

441

gpio_direction_output(IMX_GPIO_NR(4, 10), 0);

441

gpio_direction_output(IMX_GPIO_NR(4, 10), 0);

442

}

442

}

443

444

static void setup_flexcan1(void)

444

static void setup_flexcan1(void)

445

{

445

{

446

imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads));

446

imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads));

447

}

447

}

448

449

static void setup_flexcan2(void)

449

static void setup_flexcan2(void)

450

{

450

{

451

imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads));

451

imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads));

452

}

452

}

453

454

static void setup_gpios(void)

454

static void setup_gpios(void)

455

{

455

{

456

imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));

456

imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));

457

gpio_direction_output(IMX_GPIO_NR(6, 11), 0);

457

gpio_direction_output(IMX_GPIO_NR(6, 11), 0);

458

gpio_direction_output(IMX_GPIO_NR(2, 02), 0);

458

gpio_direction_output(IMX_GPIO_NR(2, 02), 0);

459

gpio_direction_output(IMX_GPIO_NR(2, 06), 0);

459

gpio_direction_output(IMX_GPIO_NR(2, 06), 0);

460

gpio_direction_output(IMX_GPIO_NR(2, 03), 0);

460

gpio_direction_output(IMX_GPIO_NR(2, 03), 0);

461

gpio_direction_output(IMX_GPIO_NR(2, 07), 0);

461

gpio_direction_output(IMX_GPIO_NR(2, 07), 0);

462

gpio_direction_input(IMX_GPIO_NR(6, 14));

462

gpio_direction_input(IMX_GPIO_NR(6, 14));

463

gpio_direction_input(IMX_GPIO_NR(6, 07));

463

gpio_direction_input(IMX_GPIO_NR(6, 07));

464

gpio_direction_input(IMX_GPIO_NR(2, 04));

464

gpio_direction_input(IMX_GPIO_NR(2, 04));

465

gpio_direction_input(IMX_GPIO_NR(2, 00));

465

gpio_direction_input(IMX_GPIO_NR(2, 00));

466

gpio_direction_input(IMX_GPIO_NR(2, 05));

466

gpio_direction_input(IMX_GPIO_NR(2, 05));

467

gpio_direction_input(IMX_GPIO_NR(6, 8));

467

gpio_direction_input(IMX_GPIO_NR(6, 8));

468

}

468

}

469

470

#ifdef CONFIG_FSL_ESDHC

470

#ifdef CONFIG_FSL_ESDHC

471

struct fsl_esdhc_cfg usdhc_cfg[3] = {

471

struct fsl_esdhc_cfg usdhc_cfg[3] = {

472

{USDHC2_BASE_ADDR},

472

{USDHC2_BASE_ADDR},

473

{USDHC3_BASE_ADDR},

473

{USDHC3_BASE_ADDR},

474

{USDHC4_BASE_ADDR},

474

{USDHC4_BASE_ADDR},

475

};

475

};

476

477

int mmc_get_env_devno(void)

477

int mmc_get_env_devno(void)

478

{

478

{

479

u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);

479

u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);

480

u32 dev_no;

480

u32 dev_no;

481

u32 bootsel;

481

u32 bootsel;

482

483

bootsel = (soc_sbmr & 0x000000FF) >> 6 ;

483

bootsel = (soc_sbmr & 0x000000FF) >> 6 ;

484

485

/* If not boot from sd/mmc, use default value */

485

/* If not boot from sd/mmc, use default value */

486

if (bootsel != 1)

486

if (bootsel != 1)

487

return CONFIG_SYS_MMC_ENV_DEV;

487

return CONFIG_SYS_MMC_ENV_DEV;

488

489

/* BOOT_CFG2[3] and BOOT_CFG2[4] */

489

/* BOOT_CFG2[3] and BOOT_CFG2[4] */

490

dev_no = (soc_sbmr & 0x00001800) >> 11;

490

dev_no = (soc_sbmr & 0x00001800) >> 11;

491

492

/* need ubstract 1 to map to the mmc device id

492

/* need ubstract 1 to map to the mmc device id

493

* see the comments in board_mmc_init function

493

* see the comments in board_mmc_init function

494

*/

494

*/

495

496

dev_no--;

496

dev_no--;

497

498

return dev_no;

498

return dev_no;

499

}

499

}

500

501

int mmc_map_to_kernel_blk(int dev_no)

501

int mmc_map_to_kernel_blk(int dev_no)

502

{

502

{

503

return dev_no + 1;

503

return dev_no + 1;

504

}

504

}

505

506

#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 28)

506

#define USDHC2_CD_GPIO IMX_GPIO_NR(1, 28)

507

/*#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)*/

507

/*#define USDHC3_CD_GPIO IMX_GPIO_NR(2, 0)*/

508

509

int board_mmc_getcd(struct mmc *mmc)

509

int board_mmc_getcd(struct mmc *mmc)

510

{

510

{

511

struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;

511

struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;

512

int ret = 0;

512

int ret = 0;

513

514

switch (cfg->esdhc_base) {

514

switch (cfg->esdhc_base) {

515

case USDHC2_BASE_ADDR:

515

case USDHC2_BASE_ADDR:

516

ret = !gpio_get_value(USDHC2_CD_GPIO);

516

ret = !gpio_get_value(USDHC2_CD_GPIO);

517

break;

517

break;

518

case USDHC3_BASE_ADDR:

518

case USDHC3_BASE_ADDR:

519

/*ret = !gpio_get_value(USDHC3_CD_GPIO);*/

519

/*ret = !gpio_get_value(USDHC3_CD_GPIO);*/

520

break;

520

break;

521

case USDHC4_BASE_ADDR:

521

case USDHC4_BASE_ADDR:

522

ret = 1; /* eMMC/uSDHC4 is always present */

522

ret = 1; /* eMMC/uSDHC4 is always present */

523

break;

523

break;

524

}

524

}

525

526

return ret;

526

return ret;

527

}

527

}

528

529

int board_mmc_init(bd_t *bis)

529

int board_mmc_init(bd_t *bis)

530

{

530

{

531

s32 status = 0;

531

s32 status = 0;

532

int i;

532

int i;

533

534

/*

534

/*

535

* According to the board_mmc_init() the following map is done:

535

* According to the board_mmc_init() the following map is done:

536

* (U-boot device node) (Physical Port)

536

* (U-boot device node) (Physical Port)

537

* mmc0 SDIO

537

* mmc0 SDIO

538

* mmc1 SDMMC

538

* mmc1 SDMMC

539

* mmc2 eMMC

539

* mmc2 eMMC

540

*/

540

*/

541

for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

541

for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {

542

switch (i) {

542

switch (i) {

543

case 0:

543

case 0:

544

imx_iomux_v3_setup_multiple_pads(

544

imx_iomux_v3_setup_multiple_pads(

545

usdhc2_pads, ARRAY_SIZE(usdhc2_pads));

545

usdhc2_pads, ARRAY_SIZE(usdhc2_pads));

546

gpio_direction_output(IMX_GPIO_NR(1, 18), 1);

546

gpio_direction_output(IMX_GPIO_NR(1, 18), 1);

547

gpio_direction_input(USDHC2_CD_GPIO);

547

gpio_direction_input(USDHC2_CD_GPIO);

548

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);

548

usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);

549

break;

549

break;

550

case 1:

550

case 1:

551

imx_iomux_v3_setup_multiple_pads(

551

imx_iomux_v3_setup_multiple_pads(

552

usdhc3_pads, ARRAY_SIZE(usdhc3_pads));

552

usdhc3_pads, ARRAY_SIZE(usdhc3_pads));

553

/*gpio_direction_input(USDHC3_CD_GPIO);*/

553

/*gpio_direction_input(USDHC3_CD_GPIO);*/

554

usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

554

usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);

555

break;

555

break;

556

case 2:

556

case 2:

557

imx_iomux_v3_setup_multiple_pads(

557

imx_iomux_v3_setup_multiple_pads(

558

usdhc4_pads, ARRAY_SIZE(usdhc4_pads));

558

usdhc4_pads, ARRAY_SIZE(usdhc4_pads));

559

usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);

559

usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);

560

break;

560

break;

561

default:

561

default:

562

printf("Warning: you configured more USDHC controllers"

562

printf("Warning: you configured more USDHC controllers"

563

"(%d) then supported by the board (%d)\n",

563

"(%d) then supported by the board (%d)\n",

564

i + 1, CONFIG_SYS_FSL_USDHC_NUM);

564

i + 1, CONFIG_SYS_FSL_USDHC_NUM);

565

return status;

565

return status;

566

}

566

}

567

568

status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);

568

status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);

569

}

569

}

570

571

return status;

571

return status;

572

}

572

}

573

574

int check_mmc_autodetect(void)

574

int check_mmc_autodetect(void)

575

{

575

{

576

char *autodetect_str = getenv("mmcautodetect");

576

char *autodetect_str = getenv("mmcautodetect");

577

578

if ((autodetect_str != NULL) &&

578

if ((autodetect_str != NULL) &&

579

(strcmp(autodetect_str, "yes") == 0)) {

579

(strcmp(autodetect_str, "yes") == 0)) {

580

return 1;

580

return 1;

581

}

581

}

582

583

return 0;

583

return 0;

584

}

584

}

585

586

void board_late_mmc_env_init(void)

586

void board_late_mmc_env_init(void)

587

{

587

{

588

char cmd[32];

588

char cmd[32];

589

char mmcblk[32];

589

char mmcblk[32];

590

u32 dev_no = mmc_get_env_devno();

590

u32 dev_no = mmc_get_env_devno();

591

592

if (!check_mmc_autodetect())

592

if (!check_mmc_autodetect())

593

return;

593

return;

594

595

setenv_ulong("mmcdev", dev_no);

595

setenv_ulong("mmcdev", dev_no);

596

597

/* Set mmcblk env */

597

/* Set mmcblk env */

598

sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",

598

sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",

599

mmc_map_to_kernel_blk(dev_no));

599

mmc_map_to_kernel_blk(dev_no));

600

setenv("mmcroot", mmcblk);

600

setenv("mmcroot", mmcblk);

601

602

sprintf(cmd, "mmc dev %d", dev_no);

602

sprintf(cmd, "mmc dev %d", dev_no);

603

run_command(cmd, 0);

603

run_command(cmd, 0);

604

}

604

}

605

#endif

605

#endif

606

607

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

607

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

608

#ifdef CONFIG_SPLASH_SCREEN

608

#ifdef CONFIG_SPLASH_SCREEN

609

extern int mmc_get_env_devno(void);

609

extern int mmc_get_env_devno(void);

610

int setup_splash_img(void)

610

int setup_splash_img(void)

611

{

611

{

612

#ifdef CONFIG_SPLASH_IS_IN_MMC

612

#ifdef CONFIG_SPLASH_IS_IN_MMC

613

int mmc_dev = mmc_get_env_devno();

613

int mmc_dev = mmc_get_env_devno();

614

ulong offset = CONFIG_SPLASH_IMG_OFFSET;

614

ulong offset = CONFIG_SPLASH_IMG_OFFSET;

615

ulong size = CONFIG_SPLASH_IMG_SIZE;

615

ulong size = CONFIG_SPLASH_IMG_SIZE;

616

ulong addr = 0;

616

ulong addr = 0;

617

char *s = NULL;

617

char *s = NULL;

618

struct mmc *mmc = find_mmc_device(mmc_dev);

618

struct mmc *mmc = find_mmc_device(mmc_dev);

619

uint blk_start, blk_cnt, n;

619

uint blk_start, blk_cnt, n;

620

621

s = getenv("splashimage");

621

s = getenv("splashimage");

622

623

if (NULL == s) {

623

if (NULL == s) {

624

puts("env splashimage not found!\n");

624

puts("env splashimage not found!\n");

625

return -1;

625

return -1;

626

}

626

}

627

addr = simple_strtoul(s, NULL, 16);

627

addr = simple_strtoul(s, NULL, 16);

628

629

if (!mmc) {

629

if (!mmc) {

630

printf("MMC Device %d not found\n", mmc_dev);

630

printf("MMC Device %d not found\n", mmc_dev);

631

return -1;

631

return -1;

632

}

632

}

633

634

if (mmc_init(mmc)) {

634

if (mmc_init(mmc)) {

635

puts("MMC init failed\n");

635

puts("MMC init failed\n");

636

return -1;

636

return -1;

637

}

637

}

638

639

blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;

639

blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;

640

blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;

640

blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;

641

n = mmc->block_dev.block_read(mmc_dev, blk_start,

641

n = mmc->block_dev.block_read(mmc_dev, blk_start,

642

blk_cnt, (u_char *)addr);

642

blk_cnt, (u_char *)addr);

643

flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);

643

flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);

644

645

return (n == blk_cnt) ? 0 : -1;

645

return (n == blk_cnt) ? 0 : -1;

646

#endif

646

#endif

647

648

return 0;

648

return 0;

649

}

649

}

650

#endif

650

#endif

651

652

vidinfo_t panel_info = {

652

vidinfo_t panel_info = {

653

.vl_refresh = 85,

653

.vl_refresh = 85,

654

.vl_col = 800,

654

.vl_col = 800,

655

.vl_row = 600,

655

.vl_row = 600,

656

.vl_pixclock = 26666667,

656

.vl_pixclock = 26666667,

657

.vl_left_margin = 8,

657

.vl_left_margin = 8,

658

.vl_right_margin = 100,

658

.vl_right_margin = 100,

659

.vl_upper_margin = 4,

659

.vl_upper_margin = 4,

660

.vl_lower_margin = 8,

660

.vl_lower_margin = 8,

661

.vl_hsync = 4,

661

.vl_hsync = 4,

662

.vl_vsync = 1,

662

.vl_vsync = 1,

663

.vl_sync = 0,

663

.vl_sync = 0,

664

.vl_mode = 0,

664

.vl_mode = 0,

665

.vl_flag = 0,

665

.vl_flag = 0,

666

.vl_bpix = 3,

666

.vl_bpix = 3,

667

.cmap = 0,

667

.cmap = 0,

668

};

668

};

669

670

struct epdc_timing_params panel_timings = {

670

struct epdc_timing_params panel_timings = {

671

.vscan_holdoff = 4,

671

.vscan_holdoff = 4,

672

.sdoed_width = 10,

672

.sdoed_width = 10,

673

.sdoed_delay = 20,

673

.sdoed_delay = 20,

674

.sdoez_width = 10,

674

.sdoez_width = 10,

675

.sdoez_delay = 20,

675

.sdoez_delay = 20,

676

.gdclk_hp_offs = 419,

676

.gdclk_hp_offs = 419,

677

.gdsp_offs = 20,

677

.gdsp_offs = 20,

678

.gdoe_offs = 0,

678

.gdoe_offs = 0,

679

.gdclk_offs = 5,

679

.gdclk_offs = 5,

680

.num_ce = 1,

680

.num_ce = 1,

681

};

681

};

682

683

static void setup_epdc_power(void)

683

static void setup_epdc_power(void)

684

{

684

{

685

/* Setup epdc voltage */

685

/* Setup epdc voltage */

686

687

/* EIM_A17 - GPIO2[21] for PWR_GOOD status */

687

/* EIM_A17 - GPIO2[21] for PWR_GOOD status */

688

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |

688

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |

689

MUX_PAD_CTRL(EPDC_PAD_CTRL));

689

MUX_PAD_CTRL(EPDC_PAD_CTRL));

690

/* Set as input */

690

/* Set as input */

691

gpio_direction_input(IMX_GPIO_NR(2, 21));

691

gpio_direction_input(IMX_GPIO_NR(2, 21));

692

693

/* EIM_D17 - GPIO3[17] for VCOM control */

693

/* EIM_D17 - GPIO3[17] for VCOM control */

694

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |

694

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |

695

MUX_PAD_CTRL(EPDC_PAD_CTRL));

695

MUX_PAD_CTRL(EPDC_PAD_CTRL));

696

697

/* Set as output */

697

/* Set as output */

698

gpio_direction_output(IMX_GPIO_NR(3, 17), 1);

698

gpio_direction_output(IMX_GPIO_NR(3, 17), 1);

699

700

/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */

700

/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */

701

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |

701

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |

702

MUX_PAD_CTRL(EPDC_PAD_CTRL));

702

MUX_PAD_CTRL(EPDC_PAD_CTRL));

703

/* Set as output */

703

/* Set as output */

704

gpio_direction_output(IMX_GPIO_NR(3, 20), 1);

704

gpio_direction_output(IMX_GPIO_NR(3, 20), 1);

705

706

/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */

706

/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */

707

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |

707

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |

708

MUX_PAD_CTRL(EPDC_PAD_CTRL));

708

MUX_PAD_CTRL(EPDC_PAD_CTRL));

709

/* Set as output */

709

/* Set as output */

710

gpio_direction_output(IMX_GPIO_NR(2, 20), 1);

710

gpio_direction_output(IMX_GPIO_NR(2, 20), 1);

711

}

711

}

712

713

int setup_waveform_file(void)

713

int setup_waveform_file(void)

714

{

714

{

715

#ifdef CONFIG_WAVEFORM_FILE_IN_MMC

715

#ifdef CONFIG_WAVEFORM_FILE_IN_MMC

716

int mmc_dev = mmc_get_env_devno();

716

int mmc_dev = mmc_get_env_devno();

717

ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;

717

ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;

718

ulong size = CONFIG_WAVEFORM_FILE_SIZE;

718

ulong size = CONFIG_WAVEFORM_FILE_SIZE;

719

ulong addr = CONFIG_WAVEFORM_BUF_ADDR;

719

ulong addr = CONFIG_WAVEFORM_BUF_ADDR;

720

struct mmc *mmc = find_mmc_device(mmc_dev);

720

struct mmc *mmc = find_mmc_device(mmc_dev);

721

uint blk_start, blk_cnt, n;

721

uint blk_start, blk_cnt, n;

722

723

if (!mmc) {

723

if (!mmc) {

724

printf("MMC Device %d not found\n", mmc_dev);

724

printf("MMC Device %d not found\n", mmc_dev);

725

return -1;

725

return -1;

726

}

726

}

727

728

if (mmc_init(mmc)) {

728

if (mmc_init(mmc)) {

729

puts("MMC init failed\n");

729

puts("MMC init failed\n");

730

return -1;

730

return -1;

731

}

731

}

732

733

blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;

733

blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;

734

blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;

734

blk_cnt = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;

735

n = mmc->block_dev.block_read(mmc_dev, blk_start,

735

n = mmc->block_dev.block_read(mmc_dev, blk_start,

736

blk_cnt, (u_char *)addr);

736

blk_cnt, (u_char *)addr);

737

flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);

737

flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);

738

739

return (n == blk_cnt) ? 0 : -1;

739

return (n == blk_cnt) ? 0 : -1;

740

#else

740

#else

741

return -1;

741

return -1;

742

#endif

742

#endif

743

}

743

}

744

745

static void epdc_enable_pins(void)

745

static void epdc_enable_pins(void)

746

{

746

{

747

/* epdc iomux settings */

747

/* epdc iomux settings */

748

imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,

748

imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,

749

ARRAY_SIZE(epdc_enable_pads));

749

ARRAY_SIZE(epdc_enable_pads));

750

}

750

}

751

752

static void epdc_disable_pins(void)

752

static void epdc_disable_pins(void)

753

{

753

{

754

/* Configure MUX settings for EPDC pins to GPIO */

754

/* Configure MUX settings for EPDC pins to GPIO */

755

imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,

755

imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,

756

ARRAY_SIZE(epdc_disable_pads));

756

ARRAY_SIZE(epdc_disable_pads));

757

}

757

}

758

759

static void setup_epdc(void)

759

static void setup_epdc(void)

760

{

760

{

761

unsigned int reg;

761

unsigned int reg;

762

struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

762

struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

763

764

/*** epdc Maxim PMIC settings ***/

764

/*** epdc Maxim PMIC settings ***/

765

766

/* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */

766

/* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */

767

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |

767

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |

768

MUX_PAD_CTRL(EPDC_PAD_CTRL));

768

MUX_PAD_CTRL(EPDC_PAD_CTRL));

769

770

/* EPDC VCOM0 - GPIO3[17] for VCOM control */

770

/* EPDC VCOM0 - GPIO3[17] for VCOM control */

771

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |

771

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |

772

MUX_PAD_CTRL(EPDC_PAD_CTRL));

772

MUX_PAD_CTRL(EPDC_PAD_CTRL));

773

774

/* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */

774

/* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */

775

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |

775

imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |

776

MUX_PAD_CTRL(EPDC_PAD_CTRL));

776

MUX_PAD_CTRL(EPDC_PAD_CTRL));

777

778

/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */

778

/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */

779

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |

779

imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |

780

MUX_PAD_CTRL(EPDC_PAD_CTRL));

780

MUX_PAD_CTRL(EPDC_PAD_CTRL));

781

782

/*** Set pixel clock rates for EPDC ***/

782

/*** Set pixel clock rates for EPDC ***/

783

784

/* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */

784

/* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */

785

reg = readl(&ccm_regs->cscdr3);

785

reg = readl(&ccm_regs->cscdr3);

786

reg &= ~0x7C000;

786

reg &= ~0x7C000;

787

reg |= (1 << 16) | (1 << 14);

787

reg |= (1 << 16) | (1 << 14);

788

writel(reg, &ccm_regs->cscdr3);

788

writel(reg, &ccm_regs->cscdr3);

789

790

/* EPDC AXI clk enable */

790

/* EPDC AXI clk enable */

791

reg = readl(&ccm_regs->CCGR3);

791

reg = readl(&ccm_regs->CCGR3);

792

reg |= 0x00C0;

792

reg |= 0x00C0;

793

writel(reg, &ccm_regs->CCGR3);

793

writel(reg, &ccm_regs->CCGR3);

794

795

/* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */

795

/* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */

796

reg = readl(&ccm_regs->cscdr2);

796

reg = readl(&ccm_regs->cscdr2);

797

reg &= ~0x3FE00;

797

reg &= ~0x3FE00;

798

reg |= (2 << 15) | (5 << 12);

798

reg |= (2 << 15) | (5 << 12);

799

writel(reg, &ccm_regs->cscdr2);

799

writel(reg, &ccm_regs->cscdr2);

800

801

/* PLL5 enable (defaults to 650) */

801

/* PLL5 enable (defaults to 650) */

802

reg = readl(&ccm_regs->analog_pll_video);

802

reg = readl(&ccm_regs->analog_pll_video);

803

reg &= ~((1 << 16) | (1 << 12));

803

reg &= ~((1 << 16) | (1 << 12));

804

reg |= (1 << 13);

804

reg |= (1 << 13);

805

writel(reg, &ccm_regs->analog_pll_video);

805

writel(reg, &ccm_regs->analog_pll_video);

806

807

/* EPDC PIX clk enable */

807

/* EPDC PIX clk enable */

808

reg = readl(&ccm_regs->CCGR3);

808

reg = readl(&ccm_regs->CCGR3);

809

reg |= 0x0C00;

809

reg |= 0x0C00;

810

writel(reg, &ccm_regs->CCGR3);

810

writel(reg, &ccm_regs->CCGR3);

811

812

panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;

812

panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;

813

panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;

813

panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;

814

815

panel_info.epdc_data.wv_modes.mode_init = 0;

815

panel_info.epdc_data.wv_modes.mode_init = 0;

816

panel_info.epdc_data.wv_modes.mode_du = 1;

816

panel_info.epdc_data.wv_modes.mode_du = 1;

817

panel_info.epdc_data.wv_modes.mode_gc4 = 3;

817

panel_info.epdc_data.wv_modes.mode_gc4 = 3;

818

panel_info.epdc_data.wv_modes.mode_gc8 = 2;

818

panel_info.epdc_data.wv_modes.mode_gc8 = 2;

819

panel_info.epdc_data.wv_modes.mode_gc16 = 2;

819

panel_info.epdc_data.wv_modes.mode_gc16 = 2;

820

panel_info.epdc_data.wv_modes.mode_gc32 = 2;

820

panel_info.epdc_data.wv_modes.mode_gc32 = 2;

821

822

panel_info.epdc_data.epdc_timings = panel_timings;

822

panel_info.epdc_data.epdc_timings = panel_timings;

823

824

setup_epdc_power();

824

setup_epdc_power();

825

826

/* Assign fb_base */

826

/* Assign fb_base */

827

gd->fb_base = CONFIG_FB_BASE;

827

gd->fb_base = CONFIG_FB_BASE;

828

}

828

}

829

830

void epdc_power_on(void)

830

void epdc_power_on(void)

831

{

831

{

832

unsigned int reg;

832

unsigned int reg;

833

struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;

833

struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;

834

835

/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */

835

/* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */

836

gpio_set_value(IMX_GPIO_NR(2, 20), 1);

836

gpio_set_value(IMX_GPIO_NR(2, 20), 1);

837

udelay(1000);

837

udelay(1000);

838

839

/* Enable epdc signal pin */

839

/* Enable epdc signal pin */

840

epdc_enable_pins();

840

epdc_enable_pins();

841

842

/* Set PMIC Wakeup to high - enable Display power */

842

/* Set PMIC Wakeup to high - enable Display power */

843

gpio_set_value(IMX_GPIO_NR(3, 20), 1);

843

gpio_set_value(IMX_GPIO_NR(3, 20), 1);

844

845

/* Wait for PWRGOOD == 1 */

845

/* Wait for PWRGOOD == 1 */

846

while (1) {

846

while (1) {

847

reg = readl(&gpio_regs->gpio_psr);

847

reg = readl(&gpio_regs->gpio_psr);

848

if (!(reg & (1 << 21)))

848

if (!(reg & (1 << 21)))

849

break;

849

break;

850

851

udelay(100);

851

udelay(100);

852

}

852

}

853

854

/* Enable VCOM */

854

/* Enable VCOM */

855

gpio_set_value(IMX_GPIO_NR(3, 17), 1);

855

gpio_set_value(IMX_GPIO_NR(3, 17), 1);

856

857

udelay(500);

857

udelay(500);

858

}

858

}

859

860

void epdc_power_off(void)

860

void epdc_power_off(void)

861

{

861

{

862

/* Set PMIC Wakeup to low - disable Display power */

862

/* Set PMIC Wakeup to low - disable Display power */

863

gpio_set_value(IMX_GPIO_NR(3, 20), 0);

863

gpio_set_value(IMX_GPIO_NR(3, 20), 0);

864

865

/* Disable VCOM */

865

/* Disable VCOM */

866

gpio_set_value(IMX_GPIO_NR(3, 17), 0);

866

gpio_set_value(IMX_GPIO_NR(3, 17), 0);

867

868

epdc_disable_pins();

868

epdc_disable_pins();

869

870

/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */

870

/* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */

871

gpio_set_value(IMX_GPIO_NR(2, 20), 0);

871

gpio_set_value(IMX_GPIO_NR(2, 20), 0);

872

}

872

}

873

#endif

873

#endif

874

875

#if defined(CONFIG_VIDEO_IPUV3)

875

#if defined(CONFIG_VIDEO_IPUV3)

876

877

static iomux_v3_cfg_t const backlight_pads[] = {

877

static iomux_v3_cfg_t const backlight_pads[] = {

878

/* Backlight Enable for RGB: S127 */

878

/* Backlight Enable for RGB: S127 */

879

MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),

879

MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),

880

#define BACKLIGHT_EN IMX_GPIO_NR(1, 00)

880

#define BACKLIGHT_EN IMX_GPIO_NR(1, 00)

881

/* PWM Backlight Control: S141 */

881

/* PWM Backlight Control: S141 */

882

883

/* Backlight Enable for LVDS: S127 */

883

/* Backlight Enable for LVDS: S127 */

884

MX6_PAD_GPIO_1__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),

884

MX6_PAD_GPIO_1__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),

885

/* LCD VDD Enable(for parallel LCD): S133 */

885

/* LCD VDD Enable(for parallel LCD): S133 */

886

MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),

886

MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),

887

#define LCD_VDD_EN IMX_GPIO_NR(1, 02)

887

#define LCD_VDD_EN IMX_GPIO_NR(1, 02)

888

};

888

};

889

890

static iomux_v3_cfg_t const rgb_pads[] = {

890

static iomux_v3_cfg_t const rgb_pads[] = {

891

MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),

891

MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),

892

MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL),

892

MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL),

893

MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(LCD_PAD_CTRL),

893

MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(LCD_PAD_CTRL),

894

MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(LCD_PAD_CTRL),

894

MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(LCD_PAD_CTRL),

895

MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), /* DISP0_DRDY */

895

MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), /* DISP0_DRDY */

896

MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),

896

MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),

897

MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),

897

MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),

898

MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),

898

MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),

899

MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),

899

MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),

900

MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),

900

MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),

901

MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),

901

MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),

902

MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),

902

MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),

903

MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),

903

MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),

904

MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),

904

MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),

905

MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),

905

MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),

906

MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),

906

MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),

907

MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),

907

MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),

908

MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),

908

MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),

909

MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),

909

MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),

910

MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),

910

MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),

911

MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),

911

MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),

912

MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),

912

MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),

913

MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),

913

MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),

914

MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),

914

MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),

915

MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),

915

MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),

916

MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),

916

MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),

917

MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),

917

MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),

918

MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),

918

MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),

919

MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),

919

MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),

920

};

920

};

921

922

struct display_info_t {

922

struct display_info_t {

923

int bus;

923

int bus;

924

int addr;

924

int addr;

925

int pixfmt;

925

int pixfmt;

926

int (*detect)(struct display_info_t const *dev);

926

int (*detect)(struct display_info_t const *dev);

927

void (*enable)(struct display_info_t const *dev);

927

void (*enable)(struct display_info_t const *dev);

928

struct fb_videomode mode;

928

struct fb_videomode mode;

929

};

929

};

930

931

/*static void disable_lvds(struct display_info_t const *dev)

931

/*static void disable_lvds(struct display_info_t const *dev)

932

{

932

{

933

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

933

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

934

935

int reg = readl(&iomux->gpr[2]);

935

int reg = readl(&iomux->gpr[2]);

936

937

reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |

937

reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |

938

IOMUXC_GPR2_LVDS_CH1_MODE_MASK);

938

IOMUXC_GPR2_LVDS_CH1_MODE_MASK);

939

940

writel(reg, &iomux->gpr[2]);

940

writel(reg, &iomux->gpr[2]);

941

}*/

941

}*/

942

943

/*static void do_enable_hdmi(struct display_info_t const *dev)

943

/*static void do_enable_hdmi(struct display_info_t const *dev)

944

{

944

{

945

disable_lvds(dev);

945

disable_lvds(dev);

946

imx_enable_hdmi_phy();

946

imx_enable_hdmi_phy();

947

}

947

}

948

949

static void enable_rgb(struct display_info_t const *dev)

949

static void enable_rgb(struct display_info_t const *dev)

950

{

950

{

951

imx_iomux_v3_setup_multiple_pads(

951

imx_iomux_v3_setup_multiple_pads(

952

rgb_pads,

952

rgb_pads,

953

ARRAY_SIZE(rgb_pads));

953

ARRAY_SIZE(rgb_pads));

954

}*/

954

}*/

955

956

static struct display_info_t const displays[] = {{

956

static struct display_info_t const displays[] = {{

957

.bus = -1,

957

.bus = -1,

958

.addr = 0,

958

.addr = 0,

959

.pixfmt = IPU_PIX_FMT_RGB24,

959

.pixfmt = IPU_PIX_FMT_RGB24,

960

.detect = NULL,

960

.detect = NULL,

961

/*.enable = do_enable_hdmi,*/

961

/*.enable = do_enable_hdmi,*/

962

.enable = NULL,

962

.enable = NULL,

963

.mode = {

963

.mode = {

964

.name = "HDMI",

964

.name = "HDMI",

965

.refresh = 60,

965

.refresh = 60,

966

.xres = 640,

966

.xres = 640,

967

.yres = 480,

967

.yres = 480,

968

.pixclock = 39721,

968

.pixclock = 39721,

969

.left_margin = 48,

969

.left_margin = 48,

970

.right_margin = 16,

970

.right_margin = 16,

971

.upper_margin = 33,

971

.upper_margin = 33,

972

.lower_margin = 10,

972

.lower_margin = 10,

973

.hsync_len = 96,

973

.hsync_len = 96,

974

.vsync_len = 2,

974

.vsync_len = 2,

975

.sync = 0,

975

.sync = 0,

976

.vmode = FB_VMODE_NONINTERLACED

976

.vmode = FB_VMODE_NONINTERLACED

977

} }, {

977

} }, {

978

.bus = -1,

978

.bus = -1,

979

.addr = 0,

979

.addr = 0,

980

.pixfmt = IPU_PIX_FMT_LVDS666,

980

.pixfmt = IPU_PIX_FMT_LVDS666,

981

.detect = NULL,

981

.detect = NULL,

982

.enable = NULL,

982

.enable = NULL,

983

.mode = {

983

.mode = {

984

.name = "Hannstar-XGA",

984

.name = "Hannstar-XGA",

985

.refresh = 60,

985

.refresh = 60,

986

.xres = 1024,

986

.xres = 1024,

987

.yres = 768,

987

.yres = 768,

988

.pixclock = 15385,

988

.pixclock = 15385,

989

.left_margin = 220,

989

.left_margin = 220,

990

.right_margin = 40,

990

.right_margin = 40,

991

.upper_margin = 21,

991

.upper_margin = 21,

992

.lower_margin = 7,

992

.lower_margin = 7,

993

.hsync_len = 60,

993

.hsync_len = 60,

994

.vsync_len = 10,

994

.vsync_len = 10,

995

.sync = FB_SYNC_EXT,

995

.sync = FB_SYNC_EXT,

996

.vmode = FB_VMODE_NONINTERLACED

996

.vmode = FB_VMODE_NONINTERLACED

997

} }, {

997

} }, {

998

.bus = -1,

998

.bus = -1,

999

.addr = 0,

999

.addr = 0,

1000

.pixfmt = IPU_PIX_FMT_RGB24,

1000

.pixfmt = IPU_PIX_FMT_RGB24,

1001

.detect = NULL,

1001

.detect = NULL,

1002

.enable = NULL,

1002

.enable = NULL,

1003

.mode = {

1003

.mode = {

1004

.name = "wvga-rgb",

1004

.name = "wvga-rgb",

1005

.refresh = 57,

1005

.refresh = 57,

1006

.xres = 800,

1006

.xres = 800,

1007

.yres = 480,

1007

.yres = 480,

1008

.pixclock = 37037,

1008

.pixclock = 37037,

1009

.left_margin = 40,

1009

.left_margin = 40,

1010

.right_margin = 60,

1010

.right_margin = 60,

1011

.upper_margin = 10,

1011

.upper_margin = 10,

1012

.lower_margin = 10,

1012

.lower_margin = 10,

1013

.hsync_len = 20,

1013

.hsync_len = 20,

1014

.vsync_len = 10,

1014

.vsync_len = 10,

1015

.sync = 0,

1015

.sync = 0,

1016

.vmode = FB_VMODE_NONINTERLACED

1016

.vmode = FB_VMODE_NONINTERLACED

1017

} } };

1017

} } };

1018

1019

int board_video_skip(void)

1019

int board_video_skip(void)

1020

{

1020

{

1021

int i;

1021

int i;

1022

int ret;

1022

int ret;

1023

char const *panel = getenv("panel");

1023

char const *panel = getenv("panel");

1024

if (!panel) {

1024

if (!panel) {

1025

for (i = 0; i < ARRAY_SIZE(displays); i++) {

1025

for (i = 0; i < ARRAY_SIZE(displays); i++) {

1026

struct display_info_t const *dev = displays+i;

1026

struct display_info_t const *dev = displays+i;

1027

if (dev->detect && dev->detect(dev)) {

1027

if (dev->detect && dev->detect(dev)) {

1028

panel = dev->mode.name;

1028

panel = dev->mode.name;

1029

printf("auto-detected panel %s\n", panel);

1029

printf("auto-detected panel %s\n", panel);

1030

break;

1030

break;

1031

}

1031

}

1032

}

1032

}

1033

if (!panel) {

1033

if (!panel) {

1034

panel = displays[0].mode.name;

1034

panel = displays[0].mode.name;

1035

printf("No panel detected: default to %s\n", panel);

1035

printf("No panel detected: default to %s\n", panel);

1036

i = 0;

1036

i = 0;

1037

}

1037

}

1038

} else {

1038

} else {

1039

for (i = 0; i < ARRAY_SIZE(displays); i++) {

1039

for (i = 0; i < ARRAY_SIZE(displays); i++) {

1040

if (!strcmp(panel, displays[i].mode.name))

1040

if (!strcmp(panel, displays[i].mode.name))

1041

break;

1041

break;

1042

}

1042

}

1043

}

1043

}

1044

if (i < ARRAY_SIZE(displays)) {

1044

if (i < ARRAY_SIZE(displays)) {

1045

ret = ipuv3_fb_init(&displays[i].mode, 0,

1045

ret = ipuv3_fb_init(&displays[i].mode, 0,

1046

displays[i].pixfmt);

1046

displays[i].pixfmt);

1047

if (!ret) {

1047

if (!ret) {

1048

if (displays[i].enable)

1048

if (displays[i].enable)

1049

displays[i].enable(displays+i);

1049

displays[i].enable(displays+i);

1050

printf("Display: %s (%ux%u)\n",

1050

printf("Display: %s (%ux%u)\n",

1051

displays[i].mode.name,

1051

displays[i].mode.name,

1052

displays[i].mode.xres,

1052

displays[i].mode.xres,

1053

displays[i].mode.yres);

1053

displays[i].mode.yres);

1054

} else

1054

} else

1055

printf("LCD %s cannot be configured: %d\n",

1055

printf("LCD %s cannot be configured: %d\n",

1056

displays[i].mode.name, ret);

1056

displays[i].mode.name, ret);

1057

} else {

1057

} else {

1058

printf("unsupported panel %s\n", panel);

1058

printf("unsupported panel %s\n", panel);

1059

return -EINVAL;

1059

return -EINVAL;

1060

}

1060

}

1061

1062

return 0;

1062

return 0;

1063

}

1063

}

1064

1065

static void setup_display(void)

1065

static void setup_display(void)

1066

{

1066

{

1067

struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

1067

struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

1068

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

1068

struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;

1069

int reg;

1069

int reg;

1070

1071

/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */

1071

/* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */

1072

imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));

1072

imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));

1073

1074

enable_ipu_clock();

1074

enable_ipu_clock();

1075

imx_setup_hdmi();

1075

imx_setup_hdmi();

1076

1077

/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */

1077

/* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */

1078

reg = readl(&mxc_ccm->CCGR3);

1078

reg = readl(&mxc_ccm->CCGR3);

1079

reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;

1079

reg |= MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;

1080

writel(reg, &mxc_ccm->CCGR3);

1080

writel(reg, &mxc_ccm->CCGR3);

1081

1082

/* set LDB0, LDB1 clk select to 011/011 */

1082

/* set LDB0, LDB1 clk select to 011/011 */

1083

reg = readl(&mxc_ccm->cs2cdr);

1083

reg = readl(&mxc_ccm->cs2cdr);

1084

reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK

1084

reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK

1085

| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);

1085

| MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);

1086

reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)

1086

reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)

1087

| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);

1087

| (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);

1088

writel(reg, &mxc_ccm->cs2cdr);

1088

writel(reg, &mxc_ccm->cs2cdr);

1089

1090

reg = readl(&mxc_ccm->cscmr2);

1090

reg = readl(&mxc_ccm->cscmr2);

1091

reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;

1091

reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;

1092

writel(reg, &mxc_ccm->cscmr2);

1092

writel(reg, &mxc_ccm->cscmr2);

1093

1094

reg = readl(&mxc_ccm->chsccdr);

1094

reg = readl(&mxc_ccm->chsccdr);

1095

reg |= (CHSCCDR_CLK_SEL_LDB_DI0

1095

reg |= (CHSCCDR_CLK_SEL_LDB_DI0

1096

<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);

1096

<< MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);

1097

reg |= (CHSCCDR_CLK_SEL_LDB_DI0

1097

reg |= (CHSCCDR_CLK_SEL_LDB_DI0

1098

<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);

1098

<< MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);

1099

writel(reg, &mxc_ccm->chsccdr);

1099

writel(reg, &mxc_ccm->chsccdr);

1100

1101

reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES

1101

reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES

1102

| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW

1102

| IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW

1103

| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW

1103

| IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW

1104

| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG

1104

| IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG

1105

| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT

1105

| IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT

1106

| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG

1106

| IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG

1107

| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT

1107

| IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT

1108

| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED

1108

| IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED

1109

| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;

1109

| IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;

1110

writel(reg, &iomux->gpr[2]);

1110

writel(reg, &iomux->gpr[2]);

1111

1112

reg = readl(&iomux->gpr[3]);

1112

reg = readl(&iomux->gpr[3]);

1113

reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK

1113

reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK

1114

| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))

1114

| IOMUXC_GPR3_HDMI_MUX_CTL_MASK))

1115

| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0

1115

| (IOMUXC_GPR3_MUX_SRC_IPU1_DI0

1116

<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);

1116

<< IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);

1117

writel(reg, &iomux->gpr[3]);

1117

writel(reg, &iomux->gpr[3]);

1118

/* backlights off until needed */

1118

/* backlights off until needed */

1119

1120

imx_iomux_v3_setup_multiple_pads(backlight_pads,

1120

imx_iomux_v3_setup_multiple_pads(backlight_pads,

1121

ARRAY_SIZE(backlight_pads));

1121

ARRAY_SIZE(backlight_pads));

1122

/*gpio_direction_input(BACKLIGHT_EN);*/

1122

/*gpio_direction_input(BACKLIGHT_EN);*/

1123

/* turn on backlight */

1123

/* turn on backlight */

1124

gpio_direction_output(BACKLIGHT_EN, 1);

1124

gpio_direction_output(BACKLIGHT_EN, 1);

1125

gpio_direction_output(LCD_VDD_EN, 1);

1125

gpio_direction_output(LCD_VDD_EN, 1);

1126

/* enable backlight PWM 2 */

1126

/* enable backlight PWM 2 */

1127

if (pwm_init(1, 0, 0))

1127

if (pwm_init(1, 0, 0))

1128

goto error;

1128

goto error;

1129

/* duty cycle 500ns, period: 3000ns */

1129

/* duty cycle 500ns, period: 3000ns */

1130

if (pwm_config(1, 1000, 3000))

1130

if (pwm_config(1, 1000, 3000))

1131

goto error;

1131

goto error;

1132

if (pwm_enable(1))

1132

if (pwm_enable(1))

1133

goto error;

1133

goto error;

1134

return;

1134

return;

1135

1136

error:

1136

error:

1137

puts("error init pwm for backlight\n");

1137

puts("error init pwm for backlight\n");

1138

return;

1138

return;

1139

}

1139

}

1140

#endif /* CONFIG_VIDEO_IPUV3 */

1140

#endif /* CONFIG_VIDEO_IPUV3 */

1141

1142

/*

1142

/*

1143

* Do not overwrite the console

1143

* Do not overwrite the console

1144

* Use always serial for U-Boot console

1144

* Use always serial for U-Boot console

1145

*/

1145

*/

1146

int overwrite_console(void)

1146

int overwrite_console(void)

1147

{

1147

{

1148

return 1;

1148

return 1;

1149

}

1149

}

1150

1151

int board_eth_init(bd_t *bis)

1151

int board_eth_init(bd_t *bis)

1152

{

1152

{

1153

#if defined(CONFIG_MAC_ADDR_IN_EEPROM)

1153

#if defined(CONFIG_MAC_ADDR_IN_EEPROM)

1154

1155

uchar env_enetaddr[6];

1155

uchar env_enetaddr[6];

1156

int enetaddr_found;

1156

int enetaddr_found;

1157

1158

enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);

1158

enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);

1159

1160

uint8_t enetaddr[8];

1160

uint8_t enetaddr[8];

1161

int eeprom_mac_read;

1161

int eeprom_mac_read;

1162

1163

/* Read Ethernet MAC address from EEPROM */

1163

/* Read Ethernet MAC address from EEPROM */

1164

eeprom_mac_read = smarcfimx6_read_mac_address(enetaddr);

1164

eeprom_mac_read = smarcfimx6_read_mac_address(enetaddr);

1165

1166

/*

1166

/*

1167

* MAC address not present in the environment

1167

* MAC address not present in the environment

1168

* try and read the MAC address from EEPROM flash

1168

* try and read the MAC address from EEPROM flash

1169

* and set it.

1169

* and set it.

1170

*/

1170

*/

1171

if (!enetaddr_found) {

1171

if (!enetaddr_found) {

1172

if (eeprom_mac_read)

1172

if (eeprom_mac_read)

1173

/* Set Ethernet MAC address from EEPROM */

1173

/* Set Ethernet MAC address from EEPROM */

1174

smarcfimx6_sync_env_enetaddr(enetaddr);

1174

smarcfimx6_sync_env_enetaddr(enetaddr);

1175

} else {

1175

} else {

1176

/*

1176

/*

1177

* MAC address present in environment compare it with

1177

* MAC address present in environment compare it with

1178

* the MAC address in EEPROM and warn on mismatch

1178

* the MAC address in EEPROM and warn on mismatch

1179

*/

1179

*/

1180

if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))

1180

if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))

1181

printf("Warning: MAC address in EEPROM don't match "

1181

printf("Warning: MAC address in EEPROM don't match "

1182

"with the MAC address in the environment\n");

1182

"with the MAC address in the environment\n");

1183

printf("Default using MAC address from environment\n");

1183

printf("Default using MAC address from environment\n");

1184

}

1184

}

1185

1186

#endif

1186

#endif

1187

1188

setup_iomux_enet();

1188

setup_iomux_enet();

1189

setup_pcie();

1189

setup_pcie();

1190

1191

return cpu_eth_init(bis);

1191

return cpu_eth_init(bis);

1192

}

1192

}

1193

1194

int board_early_init_f(void)

1194

int board_early_init_f(void)

1195

{

1195

{

1196

setup_iomux_wdt();

1196

setup_iomux_wdt();

1197

setup_iomux_reset_out();

1197

setup_iomux_reset_out();

1198

setup_iomux_uart1();

1198

setup_iomux_uart1();

1199

setup_iomux_uart2();

1199

setup_iomux_uart2();

1200

setup_iomux_uart4();

1200

setup_iomux_uart4();

1201

setup_iomux_uart5();

1201

setup_iomux_uart5();

1202

#if defined(CONFIG_VIDEO_IPUV3)

1202

#if defined(CONFIG_VIDEO_IPUV3)

1203

setup_display();

1203

setup_display();

1204

#endif

1204

#endif

1205

1206

#ifdef CONFIG_SYS_USE_SPINOR

1206

#ifdef CONFIG_SYS_USE_SPINOR

1207

/*Unlock SPI Flash*/

1207

/*Unlock SPI Flash*/

1208

gpio_direction_output(IMX_GPIO_NR(4,20), 1);

1208

gpio_direction_output(IMX_GPIO_NR(4,20), 1);

1209

udelay(100);

1210

setup_spinor();

1209

setup_spinor();

1211

/*Lock SPI Flash and Free SPI0*/

1210

/*Lock SPI Flash and Free SPI0*/

1212

gpio_direction_output(IMX_GPIO_NR(4,20), 0);

1211

gpio_direction_output(IMX_GPIO_NR(4,20), 0);

1213

#endif

1212

#endif

1214

1213

1215

setup_spi1();

1214

setup_spi1();

1216

setup_flexcan1();

1215

setup_flexcan1();

1217

setup_flexcan2();

1216

setup_flexcan2();

1218

setup_gpios();

1217

setup_gpios();

1219

1218

1220

#ifdef CONFIG_CMD_SATA

1219

#ifdef CONFIG_CMD_SATA

1221

setup_sata();

1220

setup_sata();

1222

#endif

1221

#endif

1223

1222

1224

return 0;

1223

return 0;

1225

}

1224

}

1226

1225

1227

int board_init(void)

1226

int board_init(void)

1228

{

1227

{

1229

/* address of boot parameters */

1228

/* address of boot parameters */

1230

gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

1229

gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;

1231

1230

1232

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

1231

#if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)

1233

setup_epdc();

1232

setup_epdc();

1234

#endif

1233

#endif

1235

1234

1236

#ifdef CONFIG_SYS_I2C_MXC

1235

#ifdef CONFIG_SYS_I2C_MXC

1237

setup_i2c(2, CONFIG_SYS_I2C_SPEED,

1236

setup_i2c(2, CONFIG_SYS_I2C_SPEED,

1238

0x70, &i2c_pad_info3);

1237

0x70, &i2c_pad_info3);

1239

1238

1240

/* Configure I2C switch (PCA9546) to enable channel 0. */

1239

/* Configure I2C switch (PCA9546) to enable channel 0. */

1241

i2c_set_bus_num(2);

1240

i2c_set_bus_num(2);

1242

uint8_t i2cbuf;

1241

uint8_t i2cbuf;

1243

i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE;

1242

i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE;

1244

if (i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 0,

1243

if (i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 0,

1245

CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1)) {

1244

CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1)) {

1246

printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9546_ADDR);

1245

printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9546_ADDR);

1247

return 1;

1246

return 1;

1248

}

1247

}

1249

1248

1250

#endif

1249

#endif

1251

return 0;

1250

return 0;

1252

}

1251

}

1253

1252

1254

#ifdef CONFIG_CMD_BMODE

1253

#ifdef CONFIG_CMD_BMODE

1255

static const struct boot_mode board_boot_modes[] = {

1254

static const struct boot_mode board_boot_modes[] = {

1256

/* 4 bit bus width */

1255

/* 4 bit bus width */

1257

{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},

1256

{"sd2", MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},

1258

{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},

1257

{"sd3", MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},

1259

/* 8 bit bus width */

1258

/* 8 bit bus width */

1260

{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},

1259

{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},

1261

{NULL, 0},

1260

{NULL, 0},

1262

};

1261

};

1263

#endif

1262

#endif

1264

1263

1265

int board_late_init(void)

1264

int board_late_init(void)

1266

{

1265

{

1267

// Make sure we enable ECSPI2 clock

1266

// Make sure we enable ECSPI2 clock

1268

int reg;

1267

int reg;

1269

struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

1268

struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;

1270

reg = readl(&mxc_ccm->CCGR1);

1269

reg = readl(&mxc_ccm->CCGR1);

1271

reg |= MXC_CCM_CCGR1_ECSPI2S_MASK;

1270

reg |= MXC_CCM_CCGR1_ECSPI2S_MASK;

1272

writel(reg, &mxc_ccm->CCGR1);

1271

writel(reg, &mxc_ccm->CCGR1);

1273

#ifdef CONFIG_CMD_BMODE

1272

#ifdef CONFIG_CMD_BMODE

1274

add_board_boot_modes(board_boot_modes);

1273

add_board_boot_modes(board_boot_modes);

1275

#endif

1274

#endif

1276

1275

1277

#ifdef CONFIG_ENV_IS_IN_MMC

1276

#ifdef CONFIG_ENV_IS_IN_MMC

1278

board_late_mmc_env_init();

1277

board_late_mmc_env_init();

1279

#endif

1278

#endif

1280

return 0;

1279

return 0;

1281

}

1280

}

1282

1281

1283

int checkboard(void)

1282

int checkboard(void)

1284

{

1283

{

1285

setup_i2c(0, CONFIG_SYS_I2C_SPEED,

1284

setup_i2c(0, CONFIG_SYS_I2C_SPEED,

1286

0x50, &i2c_pad_info1);

1285

0x50, &i2c_pad_info1);

1287

1286

1288

struct smarcfimx6_id header;

1287

struct smarcfimx6_id header;

1289

1288

1290

if (read_eeprom(&header) < 0)

1289

if (read_eeprom(&header) < 0)

1291

puts("Could not get board ID.\n");

1290

puts("Could not get board ID.\n");

1292

1291

1293

if (revision_is_00a0(&header)) {

1292

if (revision_is_00a0(&header)) {

1294

puts("Board: SMARC-FiMX6 Rev.00A0\n");

1293

puts("Board: SMARC-FiMX6 Rev.00A0\n");

1295

1294

1296

return 0;

1295

return 0;

1297

} else if (revision_is_00b0(&header)) {

1296

} else if (revision_is_00b0(&header)) {

1298

puts("Board: SMARC-FiMX6 Rev.00B0\n");

1297

puts("Board: SMARC-FiMX6 Rev.00B0\n");

1299

1298

1300

return 0;

1299

return 0;

1301

} else if (revision_is_00c0(&header)) {

1300

} else if (revision_is_00c0(&header)) {

1302

puts("Board: SMARC-FiMX6 Rev.00C0\n");

1301

puts("Board: SMARC-FiMX6 Rev.00C0\n");

1303

1302

1304

return 0;

1303

return 0;

1305

} else {

1304

} else {

1306

puts("Board: SMARC-FiMX6, Cannot find Revision number from EEPROM\n");

1305

puts("Board: SMARC-FiMX6, Cannot find Revision number from EEPROM\n");

1307

1306

1308

return 0;

1307

return 0;

1309

}

1308

}

1310

1309

1311

}

1310

}

1312

1311

1313

#ifdef CONFIG_FASTBOOT

1312

#ifdef CONFIG_FASTBOOT

1314

1313

1315

void board_fastboot_setup(void)

1314

void board_fastboot_setup(void)

1316

{

1315

{

1317

switch (get_boot_device()) {

1316

switch (get_boot_device()) {

1318

#if defined(CONFIG_FASTBOOT_STORAGE_SATA)

1317

#if defined(CONFIG_FASTBOOT_STORAGE_SATA)

1319

case SATA_BOOT:

1318

case SATA_BOOT:

1320

if (!getenv("fastboot_dev"))

1319

if (!getenv("fastboot_dev"))

1321

setenv("fastboot_dev", "sata");

1320

setenv("fastboot_dev", "sata");

1322

if (!getenv("bootcmd"))

1321

if (!getenv("bootcmd"))

1323

setenv("bootcmd", "booti sata");

1322

setenv("bootcmd", "booti sata");

1324

break;

1323

break;

1325

#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/

1324

#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/

1326

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1325

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1327

case SD2_BOOT:

1326

case SD2_BOOT:

1328

case MMC2_BOOT:

1327

case MMC2_BOOT:

1329

if (!getenv("fastboot_dev"))

1328

if (!getenv("fastboot_dev"))

1330

setenv("fastboot_dev", "mmc0");

1329

setenv("fastboot_dev", "mmc0");

1331

if (!getenv("bootcmd"))

1330

if (!getenv("bootcmd"))

1332

setenv("bootcmd", "booti mmc0");

1331

setenv("bootcmd", "booti mmc0");

1333

break;

1332

break;

1334

case SD3_BOOT:

1333

case SD3_BOOT:

1335

case MMC3_BOOT:

1334

case MMC3_BOOT:

1336

if (!getenv("fastboot_dev"))

1335

if (!getenv("fastboot_dev"))

1337

setenv("fastboot_dev", "mmc1");

1336

setenv("fastboot_dev", "mmc1");

1338

if (!getenv("bootcmd"))

1337

if (!getenv("bootcmd"))

1339

setenv("bootcmd", "booti mmc1");

1338

setenv("bootcmd", "booti mmc1");

1340

break;

1339

break;

1341

case MMC4_BOOT:

1340

case MMC4_BOOT:

1342

if (!getenv("fastboot_dev"))

1341

if (!getenv("fastboot_dev"))

1343

setenv("fastboot_dev", "mmc2");

1342

setenv("fastboot_dev", "mmc2");

1344

if (!getenv("bootcmd"))

1343

if (!getenv("bootcmd"))

1345

setenv("bootcmd", "booti mmc2");

1344

setenv("bootcmd", "booti mmc2");

1346

break;

1345

break;

1347

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1346

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1348

default:

1347

default:

1349

printf("unsupported boot devices\n");

1348

printf("unsupported boot devices\n");

1350

break;

1349

break;

1351

}

1350

}

1352

1351

1353

}

1352

}

1354

1353

1355

#ifdef CONFIG_ANDROID_RECOVERY

1354

#ifdef CONFIG_ANDROID_RECOVERY

1356

1355

1357

#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)

1356

#define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)

1358

iomux_v3_cfg_t const recovery_key_pads[] = {

1357

iomux_v3_cfg_t const recovery_key_pads[] = {

1359

(MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),

1358

(MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),

1360

};

1359

};

1361

1360

1362

int check_recovery_cmd_file(void)

1361

int check_recovery_cmd_file(void)

1363

{

1362

{

1364

int button_pressed = 0;

1363

int button_pressed = 0;

1365

int recovery_mode = 0;

1364

int recovery_mode = 0;

1366

1365

1367

recovery_mode = recovery_check_and_clean_flag();

1366

recovery_mode = recovery_check_and_clean_flag();

1368

1367

1369

/* Check Recovery Combo Button press or not. */

1368

/* Check Recovery Combo Button press or not. */

1370

imx_iomux_v3_setup_multiple_pads(recovery_key_pads,

1369

imx_iomux_v3_setup_multiple_pads(recovery_key_pads,

1371

ARRAY_SIZE(recovery_key_pads));

1370

ARRAY_SIZE(recovery_key_pads));

1372

1371

1373

gpio_direction_input(GPIO_VOL_DN_KEY);

1372

gpio_direction_input(GPIO_VOL_DN_KEY);

1374

1373

1375

if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */

1374

if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */

1376

button_pressed = 1;

1375

button_pressed = 1;

1377

printf("Recovery key pressed\n");

1376

printf("Recovery key pressed\n");

1378

}

1377

}

1379

1378

1380

return recovery_mode || button_pressed;

1379

return recovery_mode || button_pressed;

1381

}

1380

}

1382

1381

1383

void board_recovery_setup(void)

1382

void board_recovery_setup(void)

1384

{

1383

{

1385

int bootdev = get_boot_device();

1384

int bootdev = get_boot_device();

1386

1385

1387

switch (bootdev) {

1386

switch (bootdev) {

1388

#if defined(CONFIG_FASTBOOT_STORAGE_SATA)

1387

#if defined(CONFIG_FASTBOOT_STORAGE_SATA)

1389

case SATA_BOOT:

1388

case SATA_BOOT:

1390

if (!getenv("bootcmd_android_recovery"))

1389

if (!getenv("bootcmd_android_recovery"))

1391

setenv("bootcmd_android_recovery",

1390

setenv("bootcmd_android_recovery",

1392

"booti sata recovery");

1391

"booti sata recovery");

1393

break;

1392

break;

1394

#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/

1393

#endif /*CONFIG_FASTBOOT_STORAGE_SATA*/

1395

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1394

#if defined(CONFIG_FASTBOOT_STORAGE_MMC)

1396

case SD2_BOOT:

1395

case SD2_BOOT:

1397

case MMC2_BOOT:

1396

case MMC2_BOOT:

1398

if (!getenv("bootcmd_android_recovery"))

1397

if (!getenv("bootcmd_android_recovery"))

1399

setenv("bootcmd_android_recovery",

1398

setenv("bootcmd_android_recovery",

1400

"booti mmc0 recovery");

1399

"booti mmc0 recovery");

1401

break;

1400

break;

1402

case SD3_BOOT:

1401

case SD3_BOOT:

1403

case MMC3_BOOT:

1402

case MMC3_BOOT:

1404

if (!getenv("bootcmd_android_recovery"))

1403

if (!getenv("bootcmd_android_recovery"))

1405

setenv("bootcmd_android_recovery",

1404

setenv("bootcmd_android_recovery",

1406

"booti mmc1 recovery");

1405

"booti mmc1 recovery");

1407

break;

1406

break;

1408

case MMC4_BOOT:

1407

case MMC4_BOOT:

1409

if (!getenv("bootcmd_android_recovery"))

1408

if (!getenv("bootcmd_android_recovery"))

1410

setenv("bootcmd_android_recovery",

1409

setenv("bootcmd_android_recovery",

1411

"booti mmc2 recovery");

1410

"booti mmc2 recovery");

1412

break;

1411

break;

1413

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1412

#endif /*CONFIG_FASTBOOT_STORAGE_MMC*/

1414

default:

1413

default:

1415

printf("Unsupported bootup device for recovery: dev: %d\n",

1414

printf("Unsupported bootup device for recovery: dev: %d\n",

1416

bootdev);

1415

bootdev);

1417

return;

1416

return;

1418

}

1417

}

1419

1418

1420

printf("setup env for recovery..\n");

1419

printf("setup env for recovery..\n");

1421

setenv("bootcmd", "run bootcmd_android_recovery");

1420

setenv("bootcmd", "run bootcmd_android_recovery");

1422

}

1421

}

1423

1422

1424

#endif /*CONFIG_ANDROID_RECOVERY*/

1423

#endif /*CONFIG_ANDROID_RECOVERY*/

1425

1424

1426

#endif /*CONFIG_FASTBOOT*/

1425

#endif /*CONFIG_FASTBOOT*/

1427

1426

1428

#ifdef CONFIG_IMX_UDC

1427

#ifdef CONFIG_IMX_UDC

1429

iomux_v3_cfg_t const otg_udc_pads[] = {

1428

iomux_v3_cfg_t const otg_udc_pads[] = {

1430

(MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP)),

1429

(MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP)),

1431

};

1430

};

1432

void udc_pins_setting(void)

1431

void udc_pins_setting(void)

1433

{

1432

{

1434

imx_iomux_v3_setup_multiple_pads(otg_udc_pads,

1433

imx_iomux_v3_setup_multiple_pads(otg_udc_pads,

1435

ARRAY_SIZE(otg_udc_pads));

1434

ARRAY_SIZE(otg_udc_pads));

1436

1435

1437

/*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/

1436

/*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/

1438

mxc_iomux_set_gpr_register(1, 13, 1, 0);

1437

mxc_iomux_set_gpr_register(1, 13, 1, 0);

1439

}

1438

}

1440

#endif /*CONFIG_IMX_UDC*/

1439

#endif /*CONFIG_IMX_UDC*/

1441

1440

1442

#ifdef CONFIG_USB_EHCI_MX6

1441

#ifdef CONFIG_USB_EHCI_MX6

1443

iomux_v3_cfg_t const usb_otg_pads[] = {

1442

iomux_v3_cfg_t const usb_otg_pads[] = {

1444

MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),

1443

MX6_PAD_ENET_TXD0__GPIO1_IO30 | MUX_PAD_CTRL(WEAK_PULLUP),

1445

MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),

1444

MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP),

1446

/* OTG Power enable */

1445

/* OTG Power enable */

1447

MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(OUTPUT_40OHM),

1446

MX6_PAD_ENET_TXD1__GPIO1_IO29 | MUX_PAD_CTRL(OUTPUT_40OHM),

1448

};

1447

};

1449

1448

1450

iomux_v3_cfg_t const usb_hc1_pads[] = {

1449

iomux_v3_cfg_t const usb_hc1_pads[] = {

1451

MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(WEAK_PULLUP),

1450

MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(WEAK_PULLUP),

1452

/* USB1 Power enable */

1451

/* USB1 Power enable */

1453

MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(OUTPUT_40OHM),

1452

MX6_PAD_ENET_RXD1__GPIO1_IO26 | MUX_PAD_CTRL(OUTPUT_40OHM),

1454

};

1453

};

1455

1454

1456

int board_ehci_hcd_init(int port)

1455

int board_ehci_hcd_init(int port)

1457

{

1456

{

1458

switch (port) {

1457

switch (port) {

1459

case 0:

1458

case 0:

1460

imx_iomux_v3_setup_multiple_pads(usb_otg_pads,

1459

imx_iomux_v3_setup_multiple_pads(usb_otg_pads,

1461

ARRAY_SIZE(usb_otg_pads));

1460

ARRAY_SIZE(usb_otg_pads));

1462

1461

1463

/*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/

1462

/*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/

1464

mxc_iomux_set_gpr_register(1, 13, 1, 0);

1463

mxc_iomux_set_gpr_register(1, 13, 1, 0);

1465

break;

1464

break;

1466

case 1:

1465

case 1:

1467

imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,

1466

imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,

1468

ARRAY_SIZE(usb_hc1_pads));

1467

ARRAY_SIZE(usb_hc1_pads));

1469

break;

1468

break;

1470

default:

1469

default:

1471

printf("MXC USB port %d not yet supported\n", port);

1470

printf("MXC USB port %d not yet supported\n", port);

1472

return 1;

1471

return 1;

1473

}

1472

}

1474

return 0;

1473

return 0;

1475

}

1474

}

1476

1475

1477

int board_ehci_power(int port, int on)

1476

int board_ehci_power(int port, int on)

1478

{

1477

{

1479

switch (port) {

1478

switch (port) {

1480

case 0:

1479

case 0:

1481

/* Set USB OTG Over Current */

1480

/* Set USB OTG Over Current */

1482

gpio_direction_input(IMX_GPIO_NR(1, 30));

1481

gpio_direction_input(IMX_GPIO_NR(1, 30));

1483

/* Trun On USB OTG Power */

1482

/* Trun On USB OTG Power */

1484

gpio_direction_output(IMX_GPIO_NR(1, 29),1);

1483

gpio_direction_output(IMX_GPIO_NR(1, 29),1);

1485

break;

1484

break;

1486

case 1:

1485

case 1:

1487

if (on){

1486

if (on){

1488

/* Set USB1 Over Current */

1487

/* Set USB1 Over Current */

1489

gpio_direction_input(IMX_GPIO_NR(1, 27));

1488

gpio_direction_input(IMX_GPIO_NR(1, 27));

1490

/* Trun On USB1 Power */

1489

/* Trun On USB1 Power */

1491

gpio_direction_output(IMX_GPIO_NR(1, 26),1);

1490

gpio_direction_output(IMX_GPIO_NR(1, 26),1);

1492

}

1491

}

1493

else

1492

else

1494

gpio_direction_output(IMX_GPIO_NR(1, 26), 0);

1493

gpio_direction_output(IMX_GPIO_NR(1, 26), 0);

1495

break;

1494

break;

1496

default:

1495

default:

1497

printf("MXC USB port %d not yet supported\n", port);

1496

printf("MXC USB port %d not yet supported\n", port);

1498

return 1;

1497

return 1;

1499

}

1498

}

1500

return 0;

1499

return 0;

1501

}

1500

}

1502

#endif

1501

#endif

1503

1502

GITLAB

Remove delay when spi_nor is unlocked or the Test# will not work

 /*
  * Copyright (C) 2012-2014 Freescale Semiconductor, Inc.
  *
  * Author: Fabio Estevam <fabio.estevam@freescale.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */
 #include <common.h>
 #include <asm/io.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/imx-regs.h>
 #include <asm/arch/crm_regs.h>
 #include <asm/arch/iomux.h>
 #include <asm/arch/mx6-pins.h>
 #include <asm/errno.h>
 #include <asm/gpio.h>
 #include <asm/imx-common/iomux-v3.h>
 #include <asm/imx-common/boot_mode.h>
 #include <mmc.h>
 #include <fsl_esdhc.h>
 #include <miiphy.h>
 #include <netdev.h>
 #include <phy.h>
 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
 #include <lcd.h>
 #include <mxc_epdc_fb.h>
 #endif
 #include <asm/arch/mxc_hdmi.h>
 #include <linux/fb.h>
 #include <ipu_pixfmt.h>
 #include <asm/io.h>
 #include <asm/arch/sys_proto.h>
 #include <pwm.h>
 #ifdef CONFIG_SYS_I2C_MXC
 #include <i2c.h>
 #include <asm/imx-common/mxc_i2c.h>
 #endif
 #include "smarcfimx6.h"
 #ifdef CONFIG_CMD_SATA
 #include <asm/imx-common/sata.h>
 #endif
 #ifdef CONFIG_FASTBOOT
 #include <fastboot.h>
 #ifdef CONFIG_ANDROID_RECOVERY
 #include <recovery.h>
 #endif
 #endif /*CONFIG_FASTBOOT*/
 DECLARE_GLOBAL_DATA_PTR;
 #define UART_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP |			\
 	PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm |			\
 	PAD_CTL_SRE_FAST  | PAD_CTL_HYS)
 #define ENET_PAD_CTRL  (PAD_CTL_PUS_100K_UP |			\
 	PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 #define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
 		      PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 #define LCD_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_HIGH | \
                       PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
 #define I2C_PAD_CTRL	(PAD_CTL_PKE | PAD_CTL_PUE |		\
 	PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED |		\
 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS |			\
 	PAD_CTL_ODE | PAD_CTL_SRE_FAST)
 #define EPDC_PAD_CTRL    (PAD_CTL_PKE | PAD_CTL_SPEED_MED |	\
 	PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
 #define WEAK_PULLUP     (PAD_CTL_PUS_100K_UP |                  \
         PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS |   \
         PAD_CTL_SRE_SLOW)
 #ifdef CONFIG_SYS_I2C_MXC
 #define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
 #define OUTPUT_40OHM (PAD_CTL_SPEED_MED|PAD_CTL_DSE_40ohm)
 /*
  * Read header information from EEPROM into global structure.
  */
 static int read_eeprom(struct smarcfimx6_id *header)
 {
         /* Check if baseboard eeprom is available */
         if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
                 puts("Could not probe the EEPROM; something fundamentally "
                         "wrong on the I2C bus.\n");
                 return -ENODEV;
         }
         /* read the eeprom using i2c */
         if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, (uchar *)header,
                      sizeof(struct smarcfimx6_id))) {
                 puts("Could not read the EEPROM; something fundamentally"
                         " wrong on the I2C bus.\n");
                 return -EIO;
         }
         if (header->magic != 0xEE3355AA) {
                 /*
                  * read the eeprom using i2c again,
                  * but use only a 1 byte address
                  */
                 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
                              sizeof(struct smarcfimx6_id))) {
                         puts("Could not read the EEPROM; something "
                                 "fundamentally wrong on the I2C bus.\n");
                         return -EIO;
                 }
                 if (header->magic != 0xEE3355AA) {
                         printf("Incorrect magic number (0x%x) in EEPROM\n",
                                         header->magic);
                         return -EINVAL;
                 }
         }
         return 0;
 }
 /*I2C1 I2C_PM*/
 struct i2c_pads_info i2c_pad_info1 = {
         .scl = {
                 .i2c_mode = MX6_PAD_EIM_D21__I2C1_SCL | PC,
                 .gpio_mode = MX6_PAD_EIM_D21__GPIO3_IO21 | PC,
                 .gp = IMX_GPIO_NR(3, 21)
         },
         .sda = {
                 .i2c_mode = MX6_PAD_EIM_D28__I2C1_SDA | PC,
                 .gpio_mode = MX6_PAD_EIM_D28__GPIO3_IO28 | PC,
                 .gp = IMX_GPIO_NR(3, 28)
         }
 };
 /* I2C2 HDMI */
 struct i2c_pads_info i2c_pad_info2 = {
 	.scl = {
 		.i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC,
 		.gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC,
 		.gp = IMX_GPIO_NR(4, 12)
 	},
 	.sda = {
 		.i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC,
 		.gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC,
 		.gp = IMX_GPIO_NR(4, 13)
 	}
 };
 /* I2C3 TCA9546APWR */
 struct i2c_pads_info i2c_pad_info3 = {
         .scl = {
                 .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC,
                 .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC,
                 .gp = IMX_GPIO_NR(3, 17)
         },
         .sda = {
                 .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC,
                 .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC,
                 .gp = IMX_GPIO_NR(3, 18)
         }
 };
 #endif
 int dram_init(void)
 {
 	gd->ram_size = ((ulong)CONFIG_DDR_MB * 1024 * 1024);
 	return 0;
 }
 /* SER0/UART1 */
 iomux_v3_cfg_t const uart1_pads[] = {
 	MX6_PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 	MX6_PAD_EIM_D20__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX6_PAD_EIM_D19__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* SER1/UART2 */
 iomux_v3_cfg_t const uart2_pads[] = {
         MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* SER2/UART4 */
 iomux_v3_cfg_t const uart4_pads[] = {
         MX6_PAD_CSI0_DAT12__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX6_PAD_CSI0_DAT13__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX6_PAD_CSI0_DAT16__UART4_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX6_PAD_CSI0_DAT17__UART4_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 /* SER3/UART5 Debug Port */
 iomux_v3_cfg_t const uart5_pads[] = {
         MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
         MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL),
 };
 iomux_v3_cfg_t const wdt_pads[] = {
         MX6_PAD_EIM_D16__GPIO3_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 iomux_v3_cfg_t const reset_out_pads[] = {
         MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),
 };
 iomux_v3_cfg_t const enet_pads[] = {
 	MX6_PAD_ENET_MDIO__ENET_MDIO		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_MDC__ENET_MDC		| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TXC__RGMII_TXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD0__RGMII_TD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD1__RGMII_TD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD2__RGMII_TD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TD3__RGMII_TD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_ENET_REF_CLK__ENET_TX_CLK	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RXC__RGMII_RXC	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD0__RGMII_RD0	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD1__RGMII_RD1	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD2__RGMII_RD2	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RD3__RGMII_RD3	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 	MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL	| MUX_PAD_CTRL(ENET_PAD_CTRL),
 };
 static void setup_iomux_enet(void)
 {
 	imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads));
 	gpio_direction_input(IMX_GPIO_NR(4, 11));
 }
 /* SDIO */
 iomux_v3_cfg_t const usdhc2_pads[] = {
 	MX6_PAD_SD2_CLK__SD2_CLK	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_CMD__SD2_CMD	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_DAT0__SD2_DATA0	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_DAT1__SD2_DATA1	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_DAT2__SD2_DATA2	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD2_DAT3__SD2_DATA3	| MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_ENET_TX_EN__GPIO1_IO28	| MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */
 	MX6_PAD_ENET_CRS_DV__GPIO1_IO25  | MUX_PAD_CTRL(NO_PAD_CTRL), /* WP */
         MX6_PAD_SD1_CMD__GPIO1_IO18  | MUX_PAD_CTRL(NO_PAD_CTRL), /* SDIO_PWR_EN */
 };
 /* SDMMC */
 iomux_v3_cfg_t const usdhc3_pads[] = {
 	MX6_PAD_SD3_CLK__SD3_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_CMD__SD3_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
         MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 /* eMMC */
 iomux_v3_cfg_t const usdhc4_pads[] = {
 	MX6_PAD_SD4_CLK__SD4_CLK   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_CMD__SD4_CMD   | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT1__SD4_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT2__SD4_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT3__SD4_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT4__SD4_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT5__SD4_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT6__SD4_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 	MX6_PAD_SD4_DAT7__SD4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 #ifdef CONFIG_SYS_USE_SPINOR
 /* SPI0 */
 iomux_v3_cfg_t const ecspi2_pads[] = {
 	MX6_PAD_CSI0_DAT8__ECSPI2_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_CSI0_DAT10__ECSPI2_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_CSI0_DAT9__ECSPI2_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
 	MX6_PAD_CSI0_DAT11__GPIO5_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL),	/*SS0#*/
         MX6_PAD_EIM_D24__ECSPI2_SS2 | MUX_PAD_CTRL(NO_PAD_CTRL),	/*SS2#*/
         MX6_PAD_EIM_D25__ECSPI2_SS3 | MUX_PAD_CTRL(NO_PAD_CTRL),	/*SS3#*/
 };
 static void setup_spinor(void)
 {
 	imx_iomux_v3_setup_multiple_pads(ecspi2_pads, ARRAY_SIZE(ecspi2_pads));
 }
 #endif
 /* SPI1 */
 	iomux_v3_cfg_t const ecspi1_pads[] = {
         MX6_PAD_KEY_COL0__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX6_PAD_KEY_COL1__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX6_PAD_KEY_ROW0__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
         MX6_PAD_KEY_ROW1__ECSPI1_SS0 | MUX_PAD_CTRL(NO_PAD_CTRL),	/*SS0#*/
         MX6_PAD_KEY_COL2__ECSPI1_SS1 | MUX_PAD_CTRL(NO_PAD_CTRL),	/*SS1#*/
 };
 iomux_v3_cfg_t const pcie_pads[] = {
 	MX6_PAD_SD1_DAT1__GPIO1_IO17 | MUX_PAD_CTRL(NO_PAD_CTRL),	/* PCIe Present */
 	MX6_PAD_SD1_CLK__GPIO1_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL),	/* RESET */
         MX6_PAD_SD1_DAT0__GPIO1_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL),       /* PCIe Clock Request */
 };
 static void setup_pcie(void)
 {
 	imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
 	gpio_direction_input(IMX_GPIO_NR(1, 16));
 	gpio_direction_input(IMX_GPIO_NR(1, 17));
         gpio_direction_input(IMX_GPIO_NR(1, 19));
         gpio_direction_output(IMX_GPIO_NR(1,20), 0);
 }
 iomux_v3_cfg_t const di0_pads[] = {
         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK,        /* DISP0_CLK */
         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02,               /* DISP0_HSYNC */
         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03,               /* DISP0_VSYNC */
 };
 /* CAN0/FLEXCAN1 */
 iomux_v3_cfg_t const flexcan1_pads[] = {
         MX6_PAD_GPIO_7__FLEXCAN1_TX | MUX_PAD_CTRL(WEAK_PULLUP),
         MX6_PAD_GPIO_8__FLEXCAN1_RX | MUX_PAD_CTRL(WEAK_PULLUP),
 };
 /* CAN1/FLEXCAN2 */
 iomux_v3_cfg_t const flexcan2_pads[] = {
         MX6_PAD_KEY_COL4__FLEXCAN2_TX | MUX_PAD_CTRL(WEAK_PULLUP),
         MX6_PAD_KEY_ROW4__FLEXCAN2_RX | MUX_PAD_CTRL(WEAK_PULLUP),
 };
 /* GPIOs */
 iomux_v3_cfg_t const gpios_pads[] = {
         MX6_PAD_NANDF_CS0__GPIO6_IO11 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO0 */
         MX6_PAD_NANDF_D2__GPIO2_IO02 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO1 */
         MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO2 */
         MX6_PAD_NANDF_D3__GPIO2_IO03 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO3 */
         MX6_PAD_NANDF_D7__GPIO2_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO4 */
         MX6_PAD_NANDF_CS1__GPIO6_IO14 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO6 */
         MX6_PAD_NANDF_CLE__GPIO6_IO07 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO7 */
         MX6_PAD_NANDF_D4__GPIO2_IO04 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO8 */
         MX6_PAD_NANDF_D0__GPIO2_IO00 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO9 */
         MX6_PAD_NANDF_D5__GPIO2_IO05 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO10 */
         MX6_PAD_NANDF_ALE__GPIO6_IO08 | MUX_PAD_CTRL(WEAK_PULLUP), /* GPIO11 */
 };
 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
 static iomux_v3_cfg_t const epdc_enable_pads[] = {
 	MX6_PAD_EIM_A16__EPDC_DATA00	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA10__EPDC_DATA01	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA12__EPDC_DATA02	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA11__EPDC_DATA03	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_LBA__EPDC_DATA04	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_EB2__EPDC_DATA05	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_CS0__EPDC_DATA06	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_RW__EPDC_DATA07	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_A21__EPDC_GDCLK	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_A22__EPDC_GDSP	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_A23__EPDC_GDOE	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_A24__EPDC_GDRL	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_D31__EPDC_SDCLK_P	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_D27__EPDC_SDOE	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA1__EPDC_SDLE	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_EB1__EPDC_SDSHR	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA2__EPDC_BDR0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA4__EPDC_SDCE0	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA5__EPDC_SDCE1	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 	MX6_PAD_EIM_DA6__EPDC_SDCE2	| MUX_PAD_CTRL(EPDC_PAD_CTRL),
 };
 static iomux_v3_cfg_t const epdc_disable_pads[] = {
 	MX6_PAD_EIM_A16__GPIO2_IO22,
 	MX6_PAD_EIM_DA10__GPIO3_IO10,
 	MX6_PAD_EIM_DA12__GPIO3_IO12,
 	MX6_PAD_EIM_DA11__GPIO3_IO11,
 	MX6_PAD_EIM_LBA__GPIO2_IO27,
 	MX6_PAD_EIM_EB2__GPIO2_IO30,
 	MX6_PAD_EIM_CS0__GPIO2_IO23,
 	MX6_PAD_EIM_RW__GPIO2_IO26,
 	MX6_PAD_EIM_A21__GPIO2_IO17,
 	MX6_PAD_EIM_A22__GPIO2_IO16,
 	MX6_PAD_EIM_A23__GPIO6_IO06,
 	MX6_PAD_EIM_A24__GPIO5_IO04,
 	MX6_PAD_EIM_D31__GPIO3_IO31,
 	MX6_PAD_EIM_D27__GPIO3_IO27,
 	MX6_PAD_EIM_DA1__GPIO3_IO01,
 	MX6_PAD_EIM_EB1__GPIO2_IO29,
 	MX6_PAD_EIM_DA2__GPIO3_IO02,
 	MX6_PAD_EIM_DA4__GPIO3_IO04,
 	MX6_PAD_EIM_DA5__GPIO3_IO05,
 	MX6_PAD_EIM_DA6__GPIO3_IO06,
 };
 #endif
 static void setup_iomux_uart1(void)
 {
 	imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
 }
 static void setup_iomux_uart2(void)
 {
         imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads));
 }
 static void setup_iomux_uart4(void)
 {
         imx_iomux_v3_setup_multiple_pads(uart4_pads, ARRAY_SIZE(uart4_pads));
 }
 static void setup_iomux_uart5(void)
 {
         imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads));
 }
 static void setup_iomux_wdt(void)
 {
         imx_iomux_v3_setup_multiple_pads(wdt_pads, ARRAY_SIZE(wdt_pads));
         /* Set HW_WDT as Output High */
         gpio_direction_output(IMX_GPIO_NR(3, 16) , 1);
 }
 static void setup_iomux_reset_out(void)
 {
         imx_iomux_v3_setup_multiple_pads(reset_out_pads, ARRAY_SIZE(reset_out_pads));
         /* Set CPU RESET_OUT as Output */
         gpio_direction_output(IMX_GPIO_NR(6, 16) , 0);
 }
 static void setup_spi1(void)
 {
         imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
         gpio_direction_output(IMX_GPIO_NR(4, 9), 0);
         gpio_direction_output(IMX_GPIO_NR(4, 10), 0);
 }
 static void setup_flexcan1(void)
 {
         imx_iomux_v3_setup_multiple_pads(flexcan1_pads, ARRAY_SIZE(flexcan1_pads));
 }
 static void setup_flexcan2(void)
 {
         imx_iomux_v3_setup_multiple_pads(flexcan2_pads, ARRAY_SIZE(flexcan2_pads));
 }
 static void setup_gpios(void)
 {
         imx_iomux_v3_setup_multiple_pads(gpios_pads, ARRAY_SIZE(gpios_pads));
         gpio_direction_output(IMX_GPIO_NR(6, 11), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 02), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 06), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 03), 0);
         gpio_direction_output(IMX_GPIO_NR(2, 07), 0);
         gpio_direction_input(IMX_GPIO_NR(6, 14));
         gpio_direction_input(IMX_GPIO_NR(6, 07));
         gpio_direction_input(IMX_GPIO_NR(2, 04));
         gpio_direction_input(IMX_GPIO_NR(2, 00));
         gpio_direction_input(IMX_GPIO_NR(2, 05));
         gpio_direction_input(IMX_GPIO_NR(6, 8));
 }
 #ifdef CONFIG_FSL_ESDHC
 struct fsl_esdhc_cfg usdhc_cfg[3] = {
 	{USDHC2_BASE_ADDR},
 	{USDHC3_BASE_ADDR},
 	{USDHC4_BASE_ADDR},
 };
 int mmc_get_env_devno(void)
 {
 	u32 soc_sbmr = readl(SRC_BASE_ADDR + 0x4);
 	u32 dev_no;
 	u32 bootsel;
 	bootsel = (soc_sbmr & 0x000000FF) >> 6 ;
 	/* If not boot from sd/mmc, use default value */
 	if (bootsel != 1)
 		return CONFIG_SYS_MMC_ENV_DEV;
 	/* BOOT_CFG2[3] and BOOT_CFG2[4] */
 	dev_no = (soc_sbmr & 0x00001800) >> 11;
 	/* need ubstract 1 to map to the mmc device id
 	 * see the comments in board_mmc_init function
 	 */
 	dev_no--;
 	return dev_no;
 }
 int mmc_map_to_kernel_blk(int dev_no)
 {
 	return dev_no + 1;
 }
 #define USDHC2_CD_GPIO	IMX_GPIO_NR(1, 28)
 /*#define USDHC3_CD_GPIO	IMX_GPIO_NR(2, 0)*/
 int board_mmc_getcd(struct mmc *mmc)
 {
 	struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
 	int ret = 0;
 	switch (cfg->esdhc_base) {
 	case USDHC2_BASE_ADDR:
 		ret = !gpio_get_value(USDHC2_CD_GPIO);
 		break;
 	case USDHC3_BASE_ADDR:
 		/*ret = !gpio_get_value(USDHC3_CD_GPIO);*/
 		break;
 	case USDHC4_BASE_ADDR:
 		ret = 1; /* eMMC/uSDHC4 is always present */
 		break;
 	}
 	return ret;
 }
 int board_mmc_init(bd_t *bis)
 {
 	s32 status = 0;
 	int i;
 	/*
 	 * According to the board_mmc_init() the following map is done:
 	 * (U-boot device node)    (Physical Port)
 	 * mmc0                    SDIO
 	 * mmc1                    SDMMC
 	 * mmc2                    eMMC
 	 */
 	for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
 		switch (i) {
 		case 0:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
                         gpio_direction_output(IMX_GPIO_NR(1, 18), 1);
 			gpio_direction_input(USDHC2_CD_GPIO);
 			usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
 			break;
 		case 1:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
 			/*gpio_direction_input(USDHC3_CD_GPIO);*/
 			usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
 			break;
 		case 2:
 			imx_iomux_v3_setup_multiple_pads(
 				usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
 			usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
 			break;
 		default:
 			printf("Warning: you configured more USDHC controllers"
 			       "(%d) then supported by the board (%d)\n",
 			       i + 1, CONFIG_SYS_FSL_USDHC_NUM);
 			return status;
 		}
 		status |= fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
 	}
 	return status;
 }
 int check_mmc_autodetect(void)
 {
 	char *autodetect_str = getenv("mmcautodetect");
 	if ((autodetect_str != NULL) &&
 		(strcmp(autodetect_str, "yes") == 0)) {
 		return 1;
 	}
 	return 0;
 }
 void board_late_mmc_env_init(void)
 {
 	char cmd[32];
 	char mmcblk[32];
 	u32 dev_no = mmc_get_env_devno();
 	if (!check_mmc_autodetect())
 		return;
 	setenv_ulong("mmcdev", dev_no);
 	/* Set mmcblk env */
 	sprintf(mmcblk, "/dev/mmcblk%dp2 rootwait rw",
 		mmc_map_to_kernel_blk(dev_no));
 	setenv("mmcroot", mmcblk);
 	sprintf(cmd, "mmc dev %d", dev_no);
 	run_command(cmd, 0);
 }
 #endif
 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
 #ifdef CONFIG_SPLASH_SCREEN
 extern int mmc_get_env_devno(void);
 int setup_splash_img(void)
 {
 #ifdef CONFIG_SPLASH_IS_IN_MMC
 	int mmc_dev = mmc_get_env_devno();
 	ulong offset = CONFIG_SPLASH_IMG_OFFSET;
 	ulong size = CONFIG_SPLASH_IMG_SIZE;
 	ulong addr = 0;
 	char *s = NULL;
 	struct mmc *mmc = find_mmc_device(mmc_dev);
 	uint blk_start, blk_cnt, n;
 	s = getenv("splashimage");
 	if (NULL == s) {
 		puts("env splashimage not found!\n");
 		return -1;
 	}
 	addr = simple_strtoul(s, NULL, 16);
 	if (!mmc) {
 		printf("MMC Device %d not found\n", mmc_dev);
 		return -1;
 	}
 	if (mmc_init(mmc)) {
 		puts("MMC init failed\n");
 		return -1;
 	}
 	blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
 	blk_cnt   = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
 	n = mmc->block_dev.block_read(mmc_dev, blk_start,
 					blk_cnt, (u_char *)addr);
 	flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
 	return (n == blk_cnt) ? 0 : -1;
 #endif
 	return 0;
 }
 #endif
 vidinfo_t panel_info = {
 	.vl_refresh = 85,
 	.vl_col = 800,
 	.vl_row = 600,
 	.vl_pixclock = 26666667,
 	.vl_left_margin = 8,
 	.vl_right_margin = 100,
 	.vl_upper_margin = 4,
 	.vl_lower_margin = 8,
 	.vl_hsync = 4,
 	.vl_vsync = 1,
 	.vl_sync = 0,
 	.vl_mode = 0,
 	.vl_flag = 0,
 	.vl_bpix = 3,
 	.cmap = 0,
 };
 struct epdc_timing_params panel_timings = {
 	.vscan_holdoff = 4,
 	.sdoed_width = 10,
 	.sdoed_delay = 20,
 	.sdoez_width = 10,
 	.sdoez_delay = 20,
 	.gdclk_hp_offs = 419,
 	.gdsp_offs = 20,
 	.gdoe_offs = 0,
 	.gdclk_offs = 5,
 	.num_ce = 1,
 };
 static void setup_epdc_power(void)
 {
 	/* Setup epdc voltage */
 	/* EIM_A17 - GPIO2[21] for PWR_GOOD status */
 	imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as input */
 	gpio_direction_input(IMX_GPIO_NR(2, 21));
 	/* EIM_D17 - GPIO3[17] for VCOM control */
 	imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_direction_output(IMX_GPIO_NR(3, 17), 1);
 	/* EIM_D20 - GPIO3[20] for EPD PMIC WAKEUP */
 	imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_direction_output(IMX_GPIO_NR(3, 20), 1);
 	/* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
 	imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |
 				MUX_PAD_CTRL(EPDC_PAD_CTRL));
 	/* Set as output */
 	gpio_direction_output(IMX_GPIO_NR(2, 20), 1);
 }
 int setup_waveform_file(void)
 {
 #ifdef CONFIG_WAVEFORM_FILE_IN_MMC
 	int mmc_dev = mmc_get_env_devno();
 	ulong offset = CONFIG_WAVEFORM_FILE_OFFSET;
 	ulong size = CONFIG_WAVEFORM_FILE_SIZE;
 	ulong addr = CONFIG_WAVEFORM_BUF_ADDR;
 	struct mmc *mmc = find_mmc_device(mmc_dev);
 	uint blk_start, blk_cnt, n;
 	if (!mmc) {
 		printf("MMC Device %d not found\n", mmc_dev);
 		return -1;
 	}
 	if (mmc_init(mmc)) {
 		puts("MMC init failed\n");
 		return -1;
 	}
 	blk_start = ALIGN(offset, mmc->read_bl_len) / mmc->read_bl_len;
 	blk_cnt   = ALIGN(size, mmc->read_bl_len) / mmc->read_bl_len;
 	n = mmc->block_dev.block_read(mmc_dev, blk_start,
 				      blk_cnt, (u_char *)addr);
 	flush_cache((ulong)addr, blk_cnt * mmc->read_bl_len);
 	return (n == blk_cnt) ? 0 : -1;
 #else
 	return -1;
 #endif
 }
 static void epdc_enable_pins(void)
 {
         /* epdc iomux settings */
         imx_iomux_v3_setup_multiple_pads(epdc_enable_pads,
                                 ARRAY_SIZE(epdc_enable_pads));
 }
 static void epdc_disable_pins(void)
 {
         /* Configure MUX settings for EPDC pins to GPIO */
         imx_iomux_v3_setup_multiple_pads(epdc_disable_pads,
                                 ARRAY_SIZE(epdc_disable_pads));
 }
 static void setup_epdc(void)
 {
         unsigned int reg;
         struct mxc_ccm_reg *ccm_regs = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
         /*** epdc Maxim PMIC settings ***/
         /* EPDC PWRSTAT - GPIO2[21] for PWR_GOOD status */
         imx_iomux_v3_setup_pad(MX6_PAD_EIM_A17__GPIO2_IO21 |
                                 MUX_PAD_CTRL(EPDC_PAD_CTRL));
         /* EPDC VCOM0 - GPIO3[17] for VCOM control */
         imx_iomux_v3_setup_pad(MX6_PAD_EIM_D17__GPIO3_IO17 |
                                 MUX_PAD_CTRL(EPDC_PAD_CTRL));
         /* UART4 TXD - GPIO3[20] for EPD PMIC WAKEUP */
         imx_iomux_v3_setup_pad(MX6_PAD_EIM_D20__GPIO3_IO20 |
                                 MUX_PAD_CTRL(EPDC_PAD_CTRL));
         /* EIM_A18 - GPIO2[20] for EPD PWR CTL0 */
         imx_iomux_v3_setup_pad(MX6_PAD_EIM_A18__GPIO2_IO20 |
                                 MUX_PAD_CTRL(EPDC_PAD_CTRL));
         /*** Set pixel clock rates for EPDC ***/
         /* EPDC AXI clk (IPU2_CLK) from PFD_400M, set to 396/2 = 198MHz */
         reg = readl(&ccm_regs->cscdr3);
         reg &= ~0x7C000;
         reg |= (1 << 16) | (1 << 14);
         writel(reg, &ccm_regs->cscdr3);
         /* EPDC AXI clk enable */
         reg = readl(&ccm_regs->CCGR3);
         reg |= 0x00C0;
         writel(reg, &ccm_regs->CCGR3);
         /* EPDC PIX clk (IPU2_DI1_CLK) from PLL5, set to 650/4/6 = ~27MHz */
         reg = readl(&ccm_regs->cscdr2);
         reg &= ~0x3FE00;
         reg |= (2 << 15) | (5 << 12);
         writel(reg, &ccm_regs->cscdr2);
         /* PLL5 enable (defaults to 650) */
         reg = readl(&ccm_regs->analog_pll_video);
         reg &= ~((1 << 16) | (1 << 12));
         reg |= (1 << 13);
         writel(reg, &ccm_regs->analog_pll_video);
         /* EPDC PIX clk enable */
         reg = readl(&ccm_regs->CCGR3);
         reg |= 0x0C00;
         writel(reg, &ccm_regs->CCGR3);
         panel_info.epdc_data.working_buf_addr = CONFIG_WORKING_BUF_ADDR;
         panel_info.epdc_data.waveform_buf_addr = CONFIG_WAVEFORM_BUF_ADDR;
         panel_info.epdc_data.wv_modes.mode_init = 0;
         panel_info.epdc_data.wv_modes.mode_du = 1;
         panel_info.epdc_data.wv_modes.mode_gc4 = 3;
         panel_info.epdc_data.wv_modes.mode_gc8 = 2;
         panel_info.epdc_data.wv_modes.mode_gc16 = 2;
         panel_info.epdc_data.wv_modes.mode_gc32 = 2;
         panel_info.epdc_data.epdc_timings = panel_timings;
         setup_epdc_power();
         /* Assign fb_base */
         gd->fb_base = CONFIG_FB_BASE;
 }
 void epdc_power_on(void)
 {
         unsigned int reg;
         struct gpio_regs *gpio_regs = (struct gpio_regs *)GPIO2_BASE_ADDR;
         /* Set EPD_PWR_CTL0 to high - enable EINK_VDD (3.15) */
         gpio_set_value(IMX_GPIO_NR(2, 20), 1);
         udelay(1000);
         /* Enable epdc signal pin */
         epdc_enable_pins();
         /* Set PMIC Wakeup to high - enable Display power */
         gpio_set_value(IMX_GPIO_NR(3, 20), 1);
         /* Wait for PWRGOOD == 1 */
         while (1) {
                 reg = readl(&gpio_regs->gpio_psr);
                 if (!(reg & (1 << 21)))
                         break;
                 udelay(100);
         }
         /* Enable VCOM */
         gpio_set_value(IMX_GPIO_NR(3, 17), 1);
         udelay(500);
 }
 void epdc_power_off(void)
 {
         /* Set PMIC Wakeup to low - disable Display power */
         gpio_set_value(IMX_GPIO_NR(3, 20), 0);
         /* Disable VCOM */
         gpio_set_value(IMX_GPIO_NR(3, 17), 0);
         epdc_disable_pins();
         /* Set EPD_PWR_CTL0 to low - disable EINK_VDD (3.15) */
         gpio_set_value(IMX_GPIO_NR(2, 20), 0);
 }
 #endif
 #if defined(CONFIG_VIDEO_IPUV3)
 static iomux_v3_cfg_t const backlight_pads[] = {
         /* Backlight Enable for RGB: S127 */
         MX6_PAD_GPIO_0__GPIO1_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL),
 #define BACKLIGHT_EN IMX_GPIO_NR(1, 00)
         /* PWM Backlight Control: S141 */
         /* Backlight Enable for LVDS: S127 */
         MX6_PAD_GPIO_1__PWM2_OUT | MUX_PAD_CTRL(NO_PAD_CTRL),
         /* LCD VDD Enable(for parallel LCD): S133 */
         MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL),
 #define LCD_VDD_EN IMX_GPIO_NR(1, 02)
 };
 static iomux_v3_cfg_t const rgb_pads[] = {
         MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15 | MUX_PAD_CTRL(LCD_PAD_CTRL), /* DISP0_DRDY */
         MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 | MUX_PAD_CTRL(LCD_PAD_CTRL),
         MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 | MUX_PAD_CTRL(LCD_PAD_CTRL),
 };
 struct display_info_t {
         int     bus;
         int     addr;
         int     pixfmt;
         int     (*detect)(struct display_info_t const *dev);
         void    (*enable)(struct display_info_t const *dev);
         struct  fb_videomode mode;
 };
 /*static void disable_lvds(struct display_info_t const *dev)
 {
         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
         int reg = readl(&iomux->gpr[2]);
         reg &= ~(IOMUXC_GPR2_LVDS_CH0_MODE_MASK |
                  IOMUXC_GPR2_LVDS_CH1_MODE_MASK);
         writel(reg, &iomux->gpr[2]);
 }*/
 /*static void do_enable_hdmi(struct display_info_t const *dev)
 {
         disable_lvds(dev);
         imx_enable_hdmi_phy();
 }
 static void enable_rgb(struct display_info_t const *dev)
 {
         imx_iomux_v3_setup_multiple_pads(
                 rgb_pads,
                  ARRAY_SIZE(rgb_pads));
 }*/
 static struct display_info_t const displays[] = {{
         .bus    = -1,
         .addr   = 0,
         .pixfmt = IPU_PIX_FMT_RGB24,
         .detect = NULL,
         /*.enable = do_enable_hdmi,*/
 	.enable = NULL,
         .mode   = {
                 .name           = "HDMI",
                 .refresh        = 60,
                 .xres           = 640,
                 .yres           = 480,
                 .pixclock       = 39721,
                 .left_margin    = 48,
                 .right_margin   = 16,
                 .upper_margin   = 33,
                 .lower_margin   = 10,
                 .hsync_len      = 96,
                 .vsync_len      = 2,
                 .sync           = 0,
                 .vmode          = FB_VMODE_NONINTERLACED
 } }, {
         .bus    = -1,
         .addr   = 0,
         .pixfmt = IPU_PIX_FMT_LVDS666,
         .detect = NULL,
         .enable = NULL,
         .mode   = {
                 .name           = "Hannstar-XGA",
                 .refresh        = 60,
                 .xres           = 1024,
                 .yres           = 768,
                 .pixclock       = 15385,
                 .left_margin    = 220,
                 .right_margin   = 40,
                 .upper_margin   = 21,
                 .lower_margin   = 7,
                 .hsync_len      = 60,
                 .vsync_len      = 10,
                 .sync           = FB_SYNC_EXT,
                 .vmode          = FB_VMODE_NONINTERLACED
 } }, {
         .bus    = -1,
         .addr   = 0,
         .pixfmt = IPU_PIX_FMT_RGB24,
         .detect = NULL,
         .enable = NULL,
         .mode   = {
                 .name           = "wvga-rgb",
                 .refresh        = 57,
                 .xres           = 800,
                 .yres           = 480,
                 .pixclock       = 37037,
                 .left_margin    = 40,
                 .right_margin   = 60,
                 .upper_margin   = 10,
                 .lower_margin   = 10,
                 .hsync_len      = 20,
                 .vsync_len      = 10,
                 .sync           = 0,
                 .vmode          = FB_VMODE_NONINTERLACED
 } } };
 int board_video_skip(void)
 {
         int i;
         int ret;
         char const *panel = getenv("panel");
         if (!panel) {
                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
                         struct display_info_t const *dev = displays+i;
                         if (dev->detect && dev->detect(dev)) {
                                 panel = dev->mode.name;
                                 printf("auto-detected panel %s\n", panel);
                                 break;
                         }
                 }
                 if (!panel) {
                         panel = displays[0].mode.name;
                         printf("No panel detected: default to %s\n", panel);
                         i = 0;
                 }
         } else {
                 for (i = 0; i < ARRAY_SIZE(displays); i++) {
                         if (!strcmp(panel, displays[i].mode.name))
                                 break;
                 }
         }
         if (i < ARRAY_SIZE(displays)) {
                 ret = ipuv3_fb_init(&displays[i].mode, 0,
                                     displays[i].pixfmt);
                 if (!ret) {
                         if (displays[i].enable)
                                 displays[i].enable(displays+i);
                         printf("Display: %s (%ux%u)\n",
                                displays[i].mode.name,
                                displays[i].mode.xres,
                                displays[i].mode.yres);
                 } else
                         printf("LCD %s cannot be configured: %d\n",
                                displays[i].mode.name, ret);
         } else {
                 printf("unsupported panel %s\n", panel);
                 return -EINVAL;
         }
         return 0;
 }
 static void setup_display(void)
 {
         struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
         struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR;
         int reg;
         /* Setup HSYNC, VSYNC, DISP_CLK for debugging purposes */
         imx_iomux_v3_setup_multiple_pads(di0_pads, ARRAY_SIZE(di0_pads));
         enable_ipu_clock();
         imx_setup_hdmi();
         /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */
         reg = readl(&mxc_ccm->CCGR3);
         reg |=  MXC_CCM_CCGR3_LDB_DI0_MASK | MXC_CCM_CCGR3_LDB_DI1_MASK;
         writel(reg, &mxc_ccm->CCGR3);
         /* set LDB0, LDB1 clk select to 011/011 */
         reg = readl(&mxc_ccm->cs2cdr);
         reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK
                  | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK);
         reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET)
               | (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET);
         writel(reg, &mxc_ccm->cs2cdr);
         reg = readl(&mxc_ccm->cscmr2);
         reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV;
         writel(reg, &mxc_ccm->cscmr2);
         reg = readl(&mxc_ccm->chsccdr);
         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
                 << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET);
         reg |= (CHSCCDR_CLK_SEL_LDB_DI0
                 << MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET);
         writel(reg, &mxc_ccm->chsccdr);
         reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES
              | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW
              | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW
              | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG
              | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT
              | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG
              | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT
              | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED
              | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0;
         writel(reg, &iomux->gpr[2]);
         reg = readl(&iomux->gpr[3]);
         reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK
                         | IOMUXC_GPR3_HDMI_MUX_CTL_MASK))
             | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0
                << IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET);
         writel(reg, &iomux->gpr[3]);
         /* backlights off until needed */
         imx_iomux_v3_setup_multiple_pads(backlight_pads,
                                          ARRAY_SIZE(backlight_pads));
         /*gpio_direction_input(BACKLIGHT_EN);*/
 	/* turn on backlight */
         gpio_direction_output(BACKLIGHT_EN, 1);
         gpio_direction_output(LCD_VDD_EN, 1);
         /* enable backlight PWM 2 */
         if (pwm_init(1, 0, 0))
                 goto error;
         /* duty cycle 500ns, period: 3000ns */
         if (pwm_config(1, 1000, 3000))
                 goto error;
         if (pwm_enable(1))
                 goto error;
         return;
 error:
         puts("error init pwm for backlight\n");
         return;
 }
 #endif /* CONFIG_VIDEO_IPUV3 */
 /*
  * Do not overwrite the console
  * Use always serial for U-Boot console
  */
 int overwrite_console(void)
 {
 	return 1;
 }
 int board_eth_init(bd_t *bis)
 {
 #if defined(CONFIG_MAC_ADDR_IN_EEPROM)
         uchar env_enetaddr[6];
         int enetaddr_found;
         enetaddr_found = eth_getenv_enetaddr("ethaddr", env_enetaddr);
         uint8_t enetaddr[8];
         int eeprom_mac_read;
         /* Read Ethernet MAC address from EEPROM */
         eeprom_mac_read = smarcfimx6_read_mac_address(enetaddr);
         /*
          * MAC address not present in the environment
          * try and read the MAC address from EEPROM flash
          * and set it.
          */
         if (!enetaddr_found) {
                 if (eeprom_mac_read)
                         /* Set Ethernet MAC address from EEPROM */
                         smarcfimx6_sync_env_enetaddr(enetaddr);
         } else {
                 /*
                  * MAC address present in environment compare it with
                  * the MAC address in EEPROM and warn on mismatch
                  */
                 if (eeprom_mac_read && memcmp(enetaddr, env_enetaddr, 6))
                         printf("Warning: MAC address in EEPROM don't match "
                                         "with the MAC address in the environment\n");
                         printf("Default using MAC address from environment\n");
         }
 #endif
 	setup_iomux_enet();
 	setup_pcie();
 	return cpu_eth_init(bis);
 }
 int board_early_init_f(void)
 {
         setup_iomux_wdt();
         setup_iomux_reset_out();
         setup_iomux_uart1();
         setup_iomux_uart2();
         setup_iomux_uart4();
         setup_iomux_uart5();
 #if defined(CONFIG_VIDEO_IPUV3)
 	setup_display();
 #endif
 #ifdef CONFIG_SYS_USE_SPINOR
         /*Unlock SPI Flash*/
         gpio_direction_output(IMX_GPIO_NR(4,20), 1);
-        udelay(100);
         setup_spinor();
         /*Lock SPI Flash and Free SPI0*/
         gpio_direction_output(IMX_GPIO_NR(4,20), 0);
 #endif
         setup_spi1();
 	setup_flexcan1();
 	setup_flexcan2();
 	setup_gpios();
 #ifdef CONFIG_CMD_SATA
 	setup_sata();
 #endif
 	return 0;
 }
 int board_init(void)
 {
 	/* address of boot parameters */
 	gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
 #if defined(CONFIG_MX6DL) && defined(CONFIG_MXC_EPDC)
 	setup_epdc();
 #endif
 #ifdef CONFIG_SYS_I2C_MXC
         setup_i2c(2, CONFIG_SYS_I2C_SPEED,
                         0x70, &i2c_pad_info3);
         /* Configure I2C switch (PCA9546) to enable channel 0. */
 	i2c_set_bus_num(2);
 	uint8_t i2cbuf;
         i2cbuf = CONFIG_SYS_I2C_PCA9546_ENABLE;
         if (i2c_write(CONFIG_SYS_I2C_PCA9546_ADDR, 0,
                       CONFIG_SYS_I2C_PCA9546_ADDR_LEN, &i2cbuf, 1)) {
                 printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9546_ADDR);
                 return 1;
         }
 #endif
 	return 0;
 }
 #ifdef CONFIG_CMD_BMODE
 static const struct boot_mode board_boot_modes[] = {
 	/* 4 bit bus width */
 	{"sd2",	 MAKE_CFGVAL(0x40, 0x28, 0x00, 0x00)},
 	{"sd3",	 MAKE_CFGVAL(0x40, 0x30, 0x00, 0x00)},
 	/* 8 bit bus width */
 	{"emmc", MAKE_CFGVAL(0x60, 0x58, 0x00, 0x00)},
 	{NULL,	 0},
 };
 #endif
 int board_late_init(void)
 {
        // Make sure we enable ECSPI2 clock
        int reg;
        struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
        reg = readl(&mxc_ccm->CCGR1);
        reg |=  MXC_CCM_CCGR1_ECSPI2S_MASK;
        writel(reg, &mxc_ccm->CCGR1);
 #ifdef CONFIG_CMD_BMODE
 	add_board_boot_modes(board_boot_modes);
 #endif
 #ifdef CONFIG_ENV_IS_IN_MMC
 	board_late_mmc_env_init();
 #endif
 	return 0;
 }
 int checkboard(void)
 {
         setup_i2c(0, CONFIG_SYS_I2C_SPEED,
                         0x50, &i2c_pad_info1);
         struct smarcfimx6_id header;
         if (read_eeprom(&header) < 0)
         puts("Could not get board ID.\n");
         if (revision_is_00a0(&header)) {
         puts("Board: SMARC-FiMX6 Rev.00A0\n");
         return 0;
         } else if (revision_is_00b0(&header)) {
         puts("Board: SMARC-FiMX6 Rev.00B0\n");
         return 0;
         } else if (revision_is_00c0(&header)) {
         puts("Board: SMARC-FiMX6 Rev.00C0\n");
         return 0;
         } else {
         puts("Board: SMARC-FiMX6, Cannot find Revision number from EEPROM\n");
         return 0;
         }
 }
 #ifdef CONFIG_FASTBOOT
 void board_fastboot_setup(void)
 {
 	switch (get_boot_device()) {
 #if defined(CONFIG_FASTBOOT_STORAGE_SATA)
 	case SATA_BOOT:
 		if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "sata");
 		if (!getenv("bootcmd"))
 			setenv("bootcmd", "booti sata");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
 	case SD2_BOOT:
 	case MMC2_BOOT:
 	    if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc0");
 	    if (!getenv("bootcmd"))
 			setenv("bootcmd", "booti mmc0");
 	    break;
 	case SD3_BOOT:
 	case MMC3_BOOT:
 	    if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc1");
 	    if (!getenv("bootcmd"))
 			setenv("bootcmd", "booti mmc1");
 	    break;
 	case MMC4_BOOT:
 	    if (!getenv("fastboot_dev"))
 			setenv("fastboot_dev", "mmc2");
 	    if (!getenv("bootcmd"))
 			setenv("bootcmd", "booti mmc2");
 	    break;
 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
 	default:
 		printf("unsupported boot devices\n");
 		break;
 	}
 }
 #ifdef CONFIG_ANDROID_RECOVERY
 #define GPIO_VOL_DN_KEY IMX_GPIO_NR(1, 5)
 iomux_v3_cfg_t const recovery_key_pads[] = {
 	(MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL)),
 };
 int check_recovery_cmd_file(void)
 {
     int button_pressed = 0;
     int recovery_mode = 0;
     recovery_mode = recovery_check_and_clean_flag();
     /* Check Recovery Combo Button press or not. */
 	imx_iomux_v3_setup_multiple_pads(recovery_key_pads,
 			ARRAY_SIZE(recovery_key_pads));
     gpio_direction_input(GPIO_VOL_DN_KEY);
     if (gpio_get_value(GPIO_VOL_DN_KEY) == 0) { /* VOL_DN key is low assert */
 		button_pressed = 1;
 		printf("Recovery key pressed\n");
     }
     return recovery_mode || button_pressed;
 }
 void board_recovery_setup(void)
 {
 	int bootdev = get_boot_device();
 	switch (bootdev) {
 #if defined(CONFIG_FASTBOOT_STORAGE_SATA)
 	case SATA_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery",
 				"booti sata recovery");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_SATA*/
 #if defined(CONFIG_FASTBOOT_STORAGE_MMC)
 	case SD2_BOOT:
 	case MMC2_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery",
 				"booti mmc0 recovery");
 		break;
 	case SD3_BOOT:
 	case MMC3_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery",
 				"booti mmc1 recovery");
 		break;
 	case MMC4_BOOT:
 		if (!getenv("bootcmd_android_recovery"))
 			setenv("bootcmd_android_recovery",
 				"booti mmc2 recovery");
 		break;
 #endif /*CONFIG_FASTBOOT_STORAGE_MMC*/
 	default:
 		printf("Unsupported bootup device for recovery: dev: %d\n",
 			bootdev);
 		return;
 	}
 	printf("setup env for recovery..\n");
 	setenv("bootcmd", "run bootcmd_android_recovery");
 }
 #endif /*CONFIG_ANDROID_RECOVERY*/
 #endif /*CONFIG_FASTBOOT*/
 #ifdef CONFIG_IMX_UDC
 iomux_v3_cfg_t const otg_udc_pads[] = {
 	(MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(WEAK_PULLUP)),
 };
 void udc_pins_setting(void)
 {
 	imx_iomux_v3_setup_multiple_pads(otg_udc_pads,
 			ARRAY_SIZE(otg_udc_pads));
 	/*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/
     mxc_iomux_set_gpr_register(1, 13, 1, 0);
 }
 #endif /*CONFIG_IMX_UDC*/
 #ifdef CONFIG_USB_EHCI_MX6
 iomux_v3_cfg_t const usb_otg_pads[] = {
 	MX6_PAD_ENET_TXD0__GPIO1_IO30	| MUX_PAD_CTRL(WEAK_PULLUP),
 	MX6_PAD_ENET_RX_ER__USB_OTG_ID	| MUX_PAD_CTRL(WEAK_PULLUP),
         /* OTG Power enable */
         MX6_PAD_ENET_TXD1__GPIO1_IO29	| MUX_PAD_CTRL(OUTPUT_40OHM),
 };
 iomux_v3_cfg_t const usb_hc1_pads[] = {
         MX6_PAD_ENET_RXD0__GPIO1_IO27   | MUX_PAD_CTRL(WEAK_PULLUP),
         /* USB1 Power enable */
         MX6_PAD_ENET_RXD1__GPIO1_IO26   | MUX_PAD_CTRL(OUTPUT_40OHM),
 };
 int board_ehci_hcd_init(int port)
 {
 	switch (port) {
 	case 0:
 		imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
 			ARRAY_SIZE(usb_otg_pads));
 		/*set daisy chain for otg_pin_id on 6q. for 6dl, this bit is reserved*/
 		mxc_iomux_set_gpr_register(1, 13, 1, 0);
 		break;
 	case 1:
 		imx_iomux_v3_setup_multiple_pads(usb_hc1_pads,
 			ARRAY_SIZE(usb_hc1_pads));
 		break;
 	default:
 		printf("MXC USB port %d not yet supported\n", port);
 		return 1;
 	}
 	return 0;
 }
 int board_ehci_power(int port, int on)
 {
 	switch (port) {
 	case 0:
                 	/* Set USB OTG Over Current */
                 	gpio_direction_input(IMX_GPIO_NR(1, 30));
                 	/* Trun On USB OTG Power */
                 	gpio_direction_output(IMX_GPIO_NR(1, 29),1);
 		break;
 	case 1:
 		if (on){
                 	/* Set USB1 Over Current */
                 	gpio_direction_input(IMX_GPIO_NR(1, 27));
                 	/* Trun On USB1 Power */
                 	gpio_direction_output(IMX_GPIO_NR(1, 26),1);
 			}
 		else
 			gpio_direction_output(IMX_GPIO_NR(1, 26), 0);
 		break;
 	default:
 		printf("MXC USB port %d not yet supported\n", port);
 		return 1;
 	}
 	return 0;
 }
 #endif