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Commit 178210847f7d8492c6aa1d39867d99538be0e7d4

Authored by Rob Herring
Committed by Tom Rini
1 parent 124e9fa132
Exists in master and in 56 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

ahci: handle COMINIT received during spin-up 

Some Intel SSDs can send a COMINIT after the initial COMRESET. This causes
the link to go down and we need to re-initialize the link.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>

Showing 1 changed file with 12 additions and 0 deletions Inline Diff

drivers/block/ahci.c
Diff comments   View file @ 1782108
1 /* 1 /*
2 * Copyright (C) Freescale Semiconductor, Inc. 2006. 2 * Copyright (C) Freescale Semiconductor, Inc. 2006.
3 * Author: Jason Jin<Jason.jin@freescale.com> 3 * Author: Jason Jin<Jason.jin@freescale.com>
4 * Zhang Wei<wei.zhang@freescale.com> 4 * Zhang Wei<wei.zhang@freescale.com>
5 * 5 *
6 * SPDX-License-Identifier: GPL-2.0+ 6 * SPDX-License-Identifier: GPL-2.0+
7 * 7 *
8 * with the reference on libata and ahci drvier in kernel 8 * with the reference on libata and ahci drvier in kernel
9 */ 9 */
10 #include <common.h> 10 #include <common.h>
11 11
12 #include <command.h> 12 #include <command.h>
13 #include <pci.h> 13 #include <pci.h>
14 #include <asm/processor.h> 14 #include <asm/processor.h>
15 #include <asm/errno.h> 15 #include <asm/errno.h>
16 #include <asm/io.h> 16 #include <asm/io.h>
17 #include <malloc.h> 17 #include <malloc.h>
18 #include <scsi.h> 18 #include <scsi.h>
19 #include <ata.h> 19 #include <ata.h>
20 #include <linux/ctype.h> 20 #include <linux/ctype.h>
21 #include <ahci.h> 21 #include <ahci.h>
22 22
23 static int ata_io_flush(u8 port); 23 static int ata_io_flush(u8 port);
24 24
25 struct ahci_probe_ent *probe_ent = NULL; 25 struct ahci_probe_ent *probe_ent = NULL;
26 hd_driveid_t *ataid[AHCI_MAX_PORTS]; 26 hd_driveid_t *ataid[AHCI_MAX_PORTS];
27 27
28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0) 28 #define writel_with_flush(a,b) do { writel(a,b); readl(b); } while (0)
29 29
30 /* 30 /*
31 * Some controllers limit number of blocks they can read/write at once. 31 * Some controllers limit number of blocks they can read/write at once.
32 * Contemporary SSD devices work much faster if the read/write size is aligned 32 * Contemporary SSD devices work much faster if the read/write size is aligned
33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if 33 * to a power of 2. Let's set default to 128 and allowing to be overwritten if
34 * needed. 34 * needed.
35 */ 35 */
36 #ifndef MAX_SATA_BLOCKS_READ_WRITE 36 #ifndef MAX_SATA_BLOCKS_READ_WRITE
37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80 37 #define MAX_SATA_BLOCKS_READ_WRITE 0x80
38 #endif 38 #endif
39 39
40 /* Maximum timeouts for each event */ 40 /* Maximum timeouts for each event */
41 #define WAIT_MS_SPINUP 10000 41 #define WAIT_MS_SPINUP 10000
42 #define WAIT_MS_DATAIO 5000 42 #define WAIT_MS_DATAIO 5000
43 #define WAIT_MS_FLUSH 5000 43 #define WAIT_MS_FLUSH 5000
44 #define WAIT_MS_LINKUP 4 44 #define WAIT_MS_LINKUP 4
45 45
46 static inline u32 ahci_port_base(u32 base, u32 port) 46 static inline u32 ahci_port_base(u32 base, u32 port)
47 { 47 {
48 return base + 0x100 + (port * 0x80); 48 return base + 0x100 + (port * 0x80);
49 } 49 }
50 50
51 51
52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base, 52 static void ahci_setup_port(struct ahci_ioports *port, unsigned long base,
53 unsigned int port_idx) 53 unsigned int port_idx)
54 { 54 {
55 base = ahci_port_base(base, port_idx); 55 base = ahci_port_base(base, port_idx);
56 56
57 port->cmd_addr = base; 57 port->cmd_addr = base;
58 port->scr_addr = base + PORT_SCR; 58 port->scr_addr = base + PORT_SCR;
59 } 59 }
60 60
61 61
62 #define msleep(a) udelay(a * 1000) 62 #define msleep(a) udelay(a * 1000)
63 63
64 static void ahci_dcache_flush_range(unsigned begin, unsigned len) 64 static void ahci_dcache_flush_range(unsigned begin, unsigned len)
65 { 65 {
66 const unsigned long start = begin; 66 const unsigned long start = begin;
67 const unsigned long end = start + len; 67 const unsigned long end = start + len;
68 68
69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end); 69 debug("%s: flush dcache: [%#lx, %#lx)\n", __func__, start, end);
70 flush_dcache_range(start, end); 70 flush_dcache_range(start, end);
71 } 71 }
72 72
73 /* 73 /*
74 * SATA controller DMAs to physical RAM. Ensure data from the 74 * SATA controller DMAs to physical RAM. Ensure data from the
75 * controller is invalidated from dcache; next access comes from 75 * controller is invalidated from dcache; next access comes from
76 * physical RAM. 76 * physical RAM.
77 */ 77 */
78 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len) 78 static void ahci_dcache_invalidate_range(unsigned begin, unsigned len)
79 { 79 {
80 const unsigned long start = begin; 80 const unsigned long start = begin;
81 const unsigned long end = start + len; 81 const unsigned long end = start + len;
82 82
83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end); 83 debug("%s: invalidate dcache: [%#lx, %#lx)\n", __func__, start, end);
84 invalidate_dcache_range(start, end); 84 invalidate_dcache_range(start, end);
85 } 85 }
86 86
87 /* 87 /*
88 * Ensure data for SATA controller is flushed out of dcache and 88 * Ensure data for SATA controller is flushed out of dcache and
89 * written to physical memory. 89 * written to physical memory.
90 */ 90 */
91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp) 91 static void ahci_dcache_flush_sata_cmd(struct ahci_ioports *pp)
92 { 92 {
93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot, 93 ahci_dcache_flush_range((unsigned long)pp->cmd_slot,
94 AHCI_PORT_PRIV_DMA_SZ); 94 AHCI_PORT_PRIV_DMA_SZ);
95 } 95 }
96 96
97 static int waiting_for_cmd_completed(volatile u8 *offset, 97 static int waiting_for_cmd_completed(volatile u8 *offset,
98 int timeout_msec, 98 int timeout_msec,
99 u32 sign) 99 u32 sign)
100 { 100 {
101 int i; 101 int i;
102 u32 status; 102 u32 status;
103 103
104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++) 104 for (i = 0; ((status = readl(offset)) & sign) && i < timeout_msec; i++)
105 msleep(1); 105 msleep(1);
106 106
107 return (i < timeout_msec) ? 0 : -1; 107 return (i < timeout_msec) ? 0 : -1;
108 } 108 }
109 109
110 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port) 110 int __weak ahci_link_up(struct ahci_probe_ent *probe_ent, u8 port)
111 { 111 {
112 u32 tmp; 112 u32 tmp;
113 int j = 0; 113 int j = 0;
114 u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio; 114 u8 *port_mmio = (u8 *)probe_ent->port[port].port_mmio;
115 115
116 /* 116 /*
117 * Bring up SATA link. 117 * Bring up SATA link.
118 * SATA link bringup time is usually less than 1 ms; only very 118 * SATA link bringup time is usually less than 1 ms; only very
119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms. 119 * rarely has it taken between 1-2 ms. Never seen it above 2 ms.
120 */ 120 */
121 while (j < WAIT_MS_LINKUP) { 121 while (j < WAIT_MS_LINKUP) {
122 tmp = readl(port_mmio + PORT_SCR_STAT); 122 tmp = readl(port_mmio + PORT_SCR_STAT);
123 tmp &= PORT_SCR_STAT_DET_MASK; 123 tmp &= PORT_SCR_STAT_DET_MASK;
124 if (tmp == PORT_SCR_STAT_DET_PHYRDY) 124 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
125 return 0; 125 return 0;
126 udelay(1000); 126 udelay(1000);
127 j++; 127 j++;
128 } 128 }
129 return 1; 129 return 1;
130 } 130 }
131 131
132 static int ahci_host_init(struct ahci_probe_ent *probe_ent) 132 static int ahci_host_init(struct ahci_probe_ent *probe_ent)
133 { 133 {
134 #ifndef CONFIG_SCSI_AHCI_PLAT 134 #ifndef CONFIG_SCSI_AHCI_PLAT
135 pci_dev_t pdev = probe_ent->dev; 135 pci_dev_t pdev = probe_ent->dev;
136 u16 tmp16; 136 u16 tmp16;
137 unsigned short vendor; 137 unsigned short vendor;
138 #endif 138 #endif
139 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; 139 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
140 u32 tmp, cap_save, cmd; 140 u32 tmp, cap_save, cmd;
141 int i, j, ret; 141 int i, j, ret;
142 volatile u8 *port_mmio; 142 volatile u8 *port_mmio;
143 u32 port_map; 143 u32 port_map;
144 144
145 debug("ahci_host_init: start\n"); 145 debug("ahci_host_init: start\n");
146 146
147 cap_save = readl(mmio + HOST_CAP); 147 cap_save = readl(mmio + HOST_CAP);
148 cap_save &= ((1 << 28) | (1 << 17)); 148 cap_save &= ((1 << 28) | (1 << 17));
149 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */ 149 cap_save |= (1 << 27); /* Staggered Spin-up. Not needed. */
150 150
151 /* global controller reset */ 151 /* global controller reset */
152 tmp = readl(mmio + HOST_CTL); 152 tmp = readl(mmio + HOST_CTL);
153 if ((tmp & HOST_RESET) == 0) 153 if ((tmp & HOST_RESET) == 0)
154 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL); 154 writel_with_flush(tmp | HOST_RESET, mmio + HOST_CTL);
155 155
156 /* reset must complete within 1 second, or 156 /* reset must complete within 1 second, or
157 * the hardware should be considered fried. 157 * the hardware should be considered fried.
158 */ 158 */
159 i = 1000; 159 i = 1000;
160 do { 160 do {
161 udelay(1000); 161 udelay(1000);
162 tmp = readl(mmio + HOST_CTL); 162 tmp = readl(mmio + HOST_CTL);
163 if (!i--) { 163 if (!i--) {
164 debug("controller reset failed (0x%x)\n", tmp); 164 debug("controller reset failed (0x%x)\n", tmp);
165 return -1; 165 return -1;
166 } 166 }
167 } while (tmp & HOST_RESET); 167 } while (tmp & HOST_RESET);
168 168
169 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL); 169 writel_with_flush(HOST_AHCI_EN, mmio + HOST_CTL);
170 writel(cap_save, mmio + HOST_CAP); 170 writel(cap_save, mmio + HOST_CAP);
171 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL); 171 writel_with_flush(0xf, mmio + HOST_PORTS_IMPL);
172 172
173 #ifndef CONFIG_SCSI_AHCI_PLAT 173 #ifndef CONFIG_SCSI_AHCI_PLAT
174 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); 174 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
175 175
176 if (vendor == PCI_VENDOR_ID_INTEL) { 176 if (vendor == PCI_VENDOR_ID_INTEL) {
177 u16 tmp16; 177 u16 tmp16;
178 pci_read_config_word(pdev, 0x92, &tmp16); 178 pci_read_config_word(pdev, 0x92, &tmp16);
179 tmp16 |= 0xf; 179 tmp16 |= 0xf;
180 pci_write_config_word(pdev, 0x92, tmp16); 180 pci_write_config_word(pdev, 0x92, tmp16);
181 } 181 }
182 #endif 182 #endif
183 probe_ent->cap = readl(mmio + HOST_CAP); 183 probe_ent->cap = readl(mmio + HOST_CAP);
184 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL); 184 probe_ent->port_map = readl(mmio + HOST_PORTS_IMPL);
185 port_map = probe_ent->port_map; 185 port_map = probe_ent->port_map;
186 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1; 186 probe_ent->n_ports = (probe_ent->cap & 0x1f) + 1;
187 187
188 debug("cap 0x%x port_map 0x%x n_ports %d\n", 188 debug("cap 0x%x port_map 0x%x n_ports %d\n",
189 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports); 189 probe_ent->cap, probe_ent->port_map, probe_ent->n_ports);
190 190
191 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID) 191 if (probe_ent->n_ports > CONFIG_SYS_SCSI_MAX_SCSI_ID)
192 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID; 192 probe_ent->n_ports = CONFIG_SYS_SCSI_MAX_SCSI_ID;
193 193
194 for (i = 0; i < probe_ent->n_ports; i++) { 194 for (i = 0; i < probe_ent->n_ports; i++) {
195 if (!(port_map & (1 << i))) 195 if (!(port_map & (1 << i)))
196 continue; 196 continue;
197 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i); 197 probe_ent->port[i].port_mmio = ahci_port_base((u32) mmio, i);
198 port_mmio = (u8 *) probe_ent->port[i].port_mmio; 198 port_mmio = (u8 *) probe_ent->port[i].port_mmio;
199 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i); 199 ahci_setup_port(&probe_ent->port[i], (unsigned long)mmio, i);
200 200
201 /* make sure port is not active */ 201 /* make sure port is not active */
202 tmp = readl(port_mmio + PORT_CMD); 202 tmp = readl(port_mmio + PORT_CMD);
203 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 203 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
204 PORT_CMD_FIS_RX | PORT_CMD_START)) { 204 PORT_CMD_FIS_RX | PORT_CMD_START)) {
205 debug("Port %d is active. Deactivating.\n", i); 205 debug("Port %d is active. Deactivating.\n", i);
206 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON | 206 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
207 PORT_CMD_FIS_RX | PORT_CMD_START); 207 PORT_CMD_FIS_RX | PORT_CMD_START);
208 writel_with_flush(tmp, port_mmio + PORT_CMD); 208 writel_with_flush(tmp, port_mmio + PORT_CMD);
209 209
210 /* spec says 500 msecs for each bit, so 210 /* spec says 500 msecs for each bit, so
211 * this is slightly incorrect. 211 * this is slightly incorrect.
212 */ 212 */
213 msleep(500); 213 msleep(500);
214 } 214 }
215 215
216 /* Add the spinup command to whatever mode bits may 216 /* Add the spinup command to whatever mode bits may
217 * already be on in the command register. 217 * already be on in the command register.
218 */ 218 */
219 cmd = readl(port_mmio + PORT_CMD); 219 cmd = readl(port_mmio + PORT_CMD);
220 cmd |= PORT_CMD_FIS_RX; 220 cmd |= PORT_CMD_FIS_RX;
221 cmd |= PORT_CMD_SPIN_UP; 221 cmd |= PORT_CMD_SPIN_UP;
222 writel_with_flush(cmd, port_mmio + PORT_CMD); 222 writel_with_flush(cmd, port_mmio + PORT_CMD);
223 223
224 /* Bring up SATA link. */ 224 /* Bring up SATA link. */
225 ret = ahci_link_up(probe_ent, i); 225 ret = ahci_link_up(probe_ent, i);
226 if (ret) { 226 if (ret) {
227 printf("SATA link %d timeout.\n", i); 227 printf("SATA link %d timeout.\n", i);
228 continue; 228 continue;
229 } else { 229 } else {
230 debug("SATA link ok.\n"); 230 debug("SATA link ok.\n");
231 } 231 }
232 232
233 /* Clear error status */ 233 /* Clear error status */
234 tmp = readl(port_mmio + PORT_SCR_ERR); 234 tmp = readl(port_mmio + PORT_SCR_ERR);
235 if (tmp) 235 if (tmp)
236 writel(tmp, port_mmio + PORT_SCR_ERR); 236 writel(tmp, port_mmio + PORT_SCR_ERR);
237 237
238 debug("Spinning up device on SATA port %d... ", i); 238 debug("Spinning up device on SATA port %d... ", i);
239 239
240 j = 0; 240 j = 0;
241 while (j < WAIT_MS_SPINUP) { 241 while (j < WAIT_MS_SPINUP) {
242 tmp = readl(port_mmio + PORT_TFDATA); 242 tmp = readl(port_mmio + PORT_TFDATA);
243 if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ))) 243 if (!(tmp & (ATA_STAT_BUSY | ATA_STAT_DRQ)))
244 break; 244 break;
245 udelay(1000); 245 udelay(1000);
246 tmp = readl(port_mmio + PORT_SCR_STAT);
247 tmp &= PORT_SCR_STAT_DET_MASK;
248 if (tmp == PORT_SCR_STAT_DET_PHYRDY)
249 break;
246 j++; 250 j++;
247 } 251 }
252
253 tmp = readl(port_mmio + PORT_SCR_STAT) & PORT_SCR_STAT_DET_MASK;
254 if (tmp == PORT_SCR_STAT_DET_COMINIT) {
255 debug("SATA link %d down (COMINIT received), retrying...\n", i);
256 i--;
257 continue;
258 }
259
248 printf("Target spinup took %d ms.\n", j); 260 printf("Target spinup took %d ms.\n", j);
249 if (j == WAIT_MS_SPINUP) 261 if (j == WAIT_MS_SPINUP)
250 debug("timeout.\n"); 262 debug("timeout.\n");
251 else 263 else
252 debug("ok.\n"); 264 debug("ok.\n");
253 265
254 tmp = readl(port_mmio + PORT_SCR_ERR); 266 tmp = readl(port_mmio + PORT_SCR_ERR);
255 debug("PORT_SCR_ERR 0x%x\n", tmp); 267 debug("PORT_SCR_ERR 0x%x\n", tmp);
256 writel(tmp, port_mmio + PORT_SCR_ERR); 268 writel(tmp, port_mmio + PORT_SCR_ERR);
257 269
258 /* ack any pending irq events for this port */ 270 /* ack any pending irq events for this port */
259 tmp = readl(port_mmio + PORT_IRQ_STAT); 271 tmp = readl(port_mmio + PORT_IRQ_STAT);
260 debug("PORT_IRQ_STAT 0x%x\n", tmp); 272 debug("PORT_IRQ_STAT 0x%x\n", tmp);
261 if (tmp) 273 if (tmp)
262 writel(tmp, port_mmio + PORT_IRQ_STAT); 274 writel(tmp, port_mmio + PORT_IRQ_STAT);
263 275
264 writel(1 << i, mmio + HOST_IRQ_STAT); 276 writel(1 << i, mmio + HOST_IRQ_STAT);
265 277
266 /* set irq mask (enables interrupts) */ 278 /* set irq mask (enables interrupts) */
267 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK); 279 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
268 280
269 /* register linkup ports */ 281 /* register linkup ports */
270 tmp = readl(port_mmio + PORT_SCR_STAT); 282 tmp = readl(port_mmio + PORT_SCR_STAT);
271 debug("SATA port %d status: 0x%x\n", i, tmp); 283 debug("SATA port %d status: 0x%x\n", i, tmp);
272 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY) 284 if ((tmp & PORT_SCR_STAT_DET_MASK) == PORT_SCR_STAT_DET_PHYRDY)
273 probe_ent->link_port_map |= (0x01 << i); 285 probe_ent->link_port_map |= (0x01 << i);
274 } 286 }
275 287
276 tmp = readl(mmio + HOST_CTL); 288 tmp = readl(mmio + HOST_CTL);
277 debug("HOST_CTL 0x%x\n", tmp); 289 debug("HOST_CTL 0x%x\n", tmp);
278 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL); 290 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
279 tmp = readl(mmio + HOST_CTL); 291 tmp = readl(mmio + HOST_CTL);
280 debug("HOST_CTL 0x%x\n", tmp); 292 debug("HOST_CTL 0x%x\n", tmp);
281 #ifndef CONFIG_SCSI_AHCI_PLAT 293 #ifndef CONFIG_SCSI_AHCI_PLAT
282 pci_read_config_word(pdev, PCI_COMMAND, &tmp16); 294 pci_read_config_word(pdev, PCI_COMMAND, &tmp16);
283 tmp |= PCI_COMMAND_MASTER; 295 tmp |= PCI_COMMAND_MASTER;
284 pci_write_config_word(pdev, PCI_COMMAND, tmp16); 296 pci_write_config_word(pdev, PCI_COMMAND, tmp16);
285 #endif 297 #endif
286 return 0; 298 return 0;
287 } 299 }
288 300
289 301
290 static void ahci_print_info(struct ahci_probe_ent *probe_ent) 302 static void ahci_print_info(struct ahci_probe_ent *probe_ent)
291 { 303 {
292 #ifndef CONFIG_SCSI_AHCI_PLAT 304 #ifndef CONFIG_SCSI_AHCI_PLAT
293 pci_dev_t pdev = probe_ent->dev; 305 pci_dev_t pdev = probe_ent->dev;
294 u16 cc; 306 u16 cc;
295 #endif 307 #endif
296 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base; 308 volatile u8 *mmio = (volatile u8 *)probe_ent->mmio_base;
297 u32 vers, cap, cap2, impl, speed; 309 u32 vers, cap, cap2, impl, speed;
298 const char *speed_s; 310 const char *speed_s;
299 const char *scc_s; 311 const char *scc_s;
300 312
301 vers = readl(mmio + HOST_VERSION); 313 vers = readl(mmio + HOST_VERSION);
302 cap = probe_ent->cap; 314 cap = probe_ent->cap;
303 cap2 = readl(mmio + HOST_CAP2); 315 cap2 = readl(mmio + HOST_CAP2);
304 impl = probe_ent->port_map; 316 impl = probe_ent->port_map;
305 317
306 speed = (cap >> 20) & 0xf; 318 speed = (cap >> 20) & 0xf;
307 if (speed == 1) 319 if (speed == 1)
308 speed_s = "1.5"; 320 speed_s = "1.5";
309 else if (speed == 2) 321 else if (speed == 2)
310 speed_s = "3"; 322 speed_s = "3";
311 else if (speed == 3) 323 else if (speed == 3)
312 speed_s = "6"; 324 speed_s = "6";
313 else 325 else
314 speed_s = "?"; 326 speed_s = "?";
315 327
316 #ifdef CONFIG_SCSI_AHCI_PLAT 328 #ifdef CONFIG_SCSI_AHCI_PLAT
317 scc_s = "SATA"; 329 scc_s = "SATA";
318 #else 330 #else
319 pci_read_config_word(pdev, 0x0a, &cc); 331 pci_read_config_word(pdev, 0x0a, &cc);
320 if (cc == 0x0101) 332 if (cc == 0x0101)
321 scc_s = "IDE"; 333 scc_s = "IDE";
322 else if (cc == 0x0106) 334 else if (cc == 0x0106)
323 scc_s = "SATA"; 335 scc_s = "SATA";
324 else if (cc == 0x0104) 336 else if (cc == 0x0104)
325 scc_s = "RAID"; 337 scc_s = "RAID";
326 else 338 else
327 scc_s = "unknown"; 339 scc_s = "unknown";
328 #endif 340 #endif
329 printf("AHCI %02x%02x.%02x%02x " 341 printf("AHCI %02x%02x.%02x%02x "
330 "%u slots %u ports %s Gbps 0x%x impl %s mode\n", 342 "%u slots %u ports %s Gbps 0x%x impl %s mode\n",
331 (vers >> 24) & 0xff, 343 (vers >> 24) & 0xff,
332 (vers >> 16) & 0xff, 344 (vers >> 16) & 0xff,
333 (vers >> 8) & 0xff, 345 (vers >> 8) & 0xff,
334 vers & 0xff, 346 vers & 0xff,
335 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s); 347 ((cap >> 8) & 0x1f) + 1, (cap & 0x1f) + 1, speed_s, impl, scc_s);
336 348
337 printf("flags: " 349 printf("flags: "
338 "%s%s%s%s%s%s%s" 350 "%s%s%s%s%s%s%s"
339 "%s%s%s%s%s%s%s" 351 "%s%s%s%s%s%s%s"
340 "%s%s%s%s%s%s\n", 352 "%s%s%s%s%s%s\n",
341 cap & (1 << 31) ? "64bit " : "", 353 cap & (1 << 31) ? "64bit " : "",
342 cap & (1 << 30) ? "ncq " : "", 354 cap & (1 << 30) ? "ncq " : "",
343 cap & (1 << 28) ? "ilck " : "", 355 cap & (1 << 28) ? "ilck " : "",
344 cap & (1 << 27) ? "stag " : "", 356 cap & (1 << 27) ? "stag " : "",
345 cap & (1 << 26) ? "pm " : "", 357 cap & (1 << 26) ? "pm " : "",
346 cap & (1 << 25) ? "led " : "", 358 cap & (1 << 25) ? "led " : "",
347 cap & (1 << 24) ? "clo " : "", 359 cap & (1 << 24) ? "clo " : "",
348 cap & (1 << 19) ? "nz " : "", 360 cap & (1 << 19) ? "nz " : "",
349 cap & (1 << 18) ? "only " : "", 361 cap & (1 << 18) ? "only " : "",
350 cap & (1 << 17) ? "pmp " : "", 362 cap & (1 << 17) ? "pmp " : "",
351 cap & (1 << 16) ? "fbss " : "", 363 cap & (1 << 16) ? "fbss " : "",
352 cap & (1 << 15) ? "pio " : "", 364 cap & (1 << 15) ? "pio " : "",
353 cap & (1 << 14) ? "slum " : "", 365 cap & (1 << 14) ? "slum " : "",
354 cap & (1 << 13) ? "part " : "", 366 cap & (1 << 13) ? "part " : "",
355 cap & (1 << 7) ? "ccc " : "", 367 cap & (1 << 7) ? "ccc " : "",
356 cap & (1 << 6) ? "ems " : "", 368 cap & (1 << 6) ? "ems " : "",
357 cap & (1 << 5) ? "sxs " : "", 369 cap & (1 << 5) ? "sxs " : "",
358 cap2 & (1 << 2) ? "apst " : "", 370 cap2 & (1 << 2) ? "apst " : "",
359 cap2 & (1 << 1) ? "nvmp " : "", 371 cap2 & (1 << 1) ? "nvmp " : "",
360 cap2 & (1 << 0) ? "boh " : ""); 372 cap2 & (1 << 0) ? "boh " : "");
361 } 373 }
362 374
363 #ifndef CONFIG_SCSI_AHCI_PLAT 375 #ifndef CONFIG_SCSI_AHCI_PLAT
364 static int ahci_init_one(pci_dev_t pdev) 376 static int ahci_init_one(pci_dev_t pdev)
365 { 377 {
366 u16 vendor; 378 u16 vendor;
367 int rc; 379 int rc;
368 380
369 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS); 381 memset((void *)ataid, 0, sizeof(hd_driveid_t *) * AHCI_MAX_PORTS);
370 382
371 probe_ent = malloc(sizeof(struct ahci_probe_ent)); 383 probe_ent = malloc(sizeof(struct ahci_probe_ent));
372 memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); 384 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
373 probe_ent->dev = pdev; 385 probe_ent->dev = pdev;
374 386
375 probe_ent->host_flags = ATA_FLAG_SATA 387 probe_ent->host_flags = ATA_FLAG_SATA
376 | ATA_FLAG_NO_LEGACY 388 | ATA_FLAG_NO_LEGACY
377 | ATA_FLAG_MMIO 389 | ATA_FLAG_MMIO
378 | ATA_FLAG_PIO_DMA 390 | ATA_FLAG_PIO_DMA
379 | ATA_FLAG_NO_ATAPI; 391 | ATA_FLAG_NO_ATAPI;
380 probe_ent->pio_mask = 0x1f; 392 probe_ent->pio_mask = 0x1f;
381 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 393 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
382 394
383 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base); 395 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &probe_ent->mmio_base);
384 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base); 396 debug("ahci mmio_base=0x%08x\n", probe_ent->mmio_base);
385 397
386 /* Take from kernel: 398 /* Take from kernel:
387 * JMicron-specific fixup: 399 * JMicron-specific fixup:
388 * make sure we're in AHCI mode 400 * make sure we're in AHCI mode
389 */ 401 */
390 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor); 402 pci_read_config_word(pdev, PCI_VENDOR_ID, &vendor);
391 if (vendor == 0x197b) 403 if (vendor == 0x197b)
392 pci_write_config_byte(pdev, 0x41, 0xa1); 404 pci_write_config_byte(pdev, 0x41, 0xa1);
393 405
394 /* initialize adapter */ 406 /* initialize adapter */
395 rc = ahci_host_init(probe_ent); 407 rc = ahci_host_init(probe_ent);
396 if (rc) 408 if (rc)
397 goto err_out; 409 goto err_out;
398 410
399 ahci_print_info(probe_ent); 411 ahci_print_info(probe_ent);
400 412
401 return 0; 413 return 0;
402 414
403 err_out: 415 err_out:
404 return rc; 416 return rc;
405 } 417 }
406 #endif 418 #endif
407 419
408 #define MAX_DATA_BYTE_COUNT (4*1024*1024) 420 #define MAX_DATA_BYTE_COUNT (4*1024*1024)
409 421
410 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len) 422 static int ahci_fill_sg(u8 port, unsigned char *buf, int buf_len)
411 { 423 {
412 struct ahci_ioports *pp = &(probe_ent->port[port]); 424 struct ahci_ioports *pp = &(probe_ent->port[port]);
413 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg; 425 struct ahci_sg *ahci_sg = pp->cmd_tbl_sg;
414 u32 sg_count; 426 u32 sg_count;
415 int i; 427 int i;
416 428
417 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1; 429 sg_count = ((buf_len - 1) / MAX_DATA_BYTE_COUNT) + 1;
418 if (sg_count > AHCI_MAX_SG) { 430 if (sg_count > AHCI_MAX_SG) {
419 printf("Error:Too much sg!\n"); 431 printf("Error:Too much sg!\n");
420 return -1; 432 return -1;
421 } 433 }
422 434
423 for (i = 0; i < sg_count; i++) { 435 for (i = 0; i < sg_count; i++) {
424 ahci_sg->addr = 436 ahci_sg->addr =
425 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT); 437 cpu_to_le32((u32) buf + i * MAX_DATA_BYTE_COUNT);
426 ahci_sg->addr_hi = 0; 438 ahci_sg->addr_hi = 0;
427 ahci_sg->flags_size = cpu_to_le32(0x3fffff & 439 ahci_sg->flags_size = cpu_to_le32(0x3fffff &
428 (buf_len < MAX_DATA_BYTE_COUNT 440 (buf_len < MAX_DATA_BYTE_COUNT
429 ? (buf_len - 1) 441 ? (buf_len - 1)
430 : (MAX_DATA_BYTE_COUNT - 1))); 442 : (MAX_DATA_BYTE_COUNT - 1)));
431 ahci_sg++; 443 ahci_sg++;
432 buf_len -= MAX_DATA_BYTE_COUNT; 444 buf_len -= MAX_DATA_BYTE_COUNT;
433 } 445 }
434 446
435 return sg_count; 447 return sg_count;
436 } 448 }
437 449
438 450
439 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts) 451 static void ahci_fill_cmd_slot(struct ahci_ioports *pp, u32 opts)
440 { 452 {
441 pp->cmd_slot->opts = cpu_to_le32(opts); 453 pp->cmd_slot->opts = cpu_to_le32(opts);
442 pp->cmd_slot->status = 0; 454 pp->cmd_slot->status = 0;
443 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff); 455 pp->cmd_slot->tbl_addr = cpu_to_le32(pp->cmd_tbl & 0xffffffff);
444 pp->cmd_slot->tbl_addr_hi = 0; 456 pp->cmd_slot->tbl_addr_hi = 0;
445 } 457 }
446 458
447 459
448 #ifdef CONFIG_AHCI_SETFEATURES_XFER 460 #ifdef CONFIG_AHCI_SETFEATURES_XFER
449 static void ahci_set_feature(u8 port) 461 static void ahci_set_feature(u8 port)
450 { 462 {
451 struct ahci_ioports *pp = &(probe_ent->port[port]); 463 struct ahci_ioports *pp = &(probe_ent->port[port]);
452 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; 464 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
453 u32 cmd_fis_len = 5; /* five dwords */ 465 u32 cmd_fis_len = 5; /* five dwords */
454 u8 fis[20]; 466 u8 fis[20];
455 467
456 /* set feature */ 468 /* set feature */
457 memset(fis, 0, sizeof(fis)); 469 memset(fis, 0, sizeof(fis));
458 fis[0] = 0x27; 470 fis[0] = 0x27;
459 fis[1] = 1 << 7; 471 fis[1] = 1 << 7;
460 fis[2] = ATA_CMD_SETF; 472 fis[2] = ATA_CMD_SETF;
461 fis[3] = SETFEATURES_XFER; 473 fis[3] = SETFEATURES_XFER;
462 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01; 474 fis[12] = __ilog2(probe_ent->udma_mask + 1) + 0x40 - 0x01;
463 475
464 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis)); 476 memcpy((unsigned char *)pp->cmd_tbl, fis, sizeof(fis));
465 ahci_fill_cmd_slot(pp, cmd_fis_len); 477 ahci_fill_cmd_slot(pp, cmd_fis_len);
466 ahci_dcache_flush_sata_cmd(pp); 478 ahci_dcache_flush_sata_cmd(pp);
467 writel(1, port_mmio + PORT_CMD_ISSUE); 479 writel(1, port_mmio + PORT_CMD_ISSUE);
468 readl(port_mmio + PORT_CMD_ISSUE); 480 readl(port_mmio + PORT_CMD_ISSUE);
469 481
470 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 482 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
471 WAIT_MS_DATAIO, 0x1)) { 483 WAIT_MS_DATAIO, 0x1)) {
472 printf("set feature error on port %d!\n", port); 484 printf("set feature error on port %d!\n", port);
473 } 485 }
474 } 486 }
475 #endif 487 #endif
476 488
477 489
478 static int ahci_port_start(u8 port) 490 static int ahci_port_start(u8 port)
479 { 491 {
480 struct ahci_ioports *pp = &(probe_ent->port[port]); 492 struct ahci_ioports *pp = &(probe_ent->port[port]);
481 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; 493 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
482 u32 port_status; 494 u32 port_status;
483 u32 mem; 495 u32 mem;
484 496
485 debug("Enter start port: %d\n", port); 497 debug("Enter start port: %d\n", port);
486 port_status = readl(port_mmio + PORT_SCR_STAT); 498 port_status = readl(port_mmio + PORT_SCR_STAT);
487 debug("Port %d status: %x\n", port, port_status); 499 debug("Port %d status: %x\n", port, port_status);
488 if ((port_status & 0xf) != 0x03) { 500 if ((port_status & 0xf) != 0x03) {
489 printf("No Link on this port!\n"); 501 printf("No Link on this port!\n");
490 return -1; 502 return -1;
491 } 503 }
492 504
493 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048); 505 mem = (u32) malloc(AHCI_PORT_PRIV_DMA_SZ + 2048);
494 if (!mem) { 506 if (!mem) {
495 free(pp); 507 free(pp);
496 printf("No mem for table!\n"); 508 printf("No mem for table!\n");
497 return -ENOMEM; 509 return -ENOMEM;
498 } 510 }
499 511
500 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */ 512 mem = (mem + 0x800) & (~0x7ff); /* Aligned to 2048-bytes */
501 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ); 513 memset((u8 *) mem, 0, AHCI_PORT_PRIV_DMA_SZ);
502 514
503 /* 515 /*
504 * First item in chunk of DMA memory: 32-slot command table, 516 * First item in chunk of DMA memory: 32-slot command table,
505 * 32 bytes each in size 517 * 32 bytes each in size
506 */ 518 */
507 pp->cmd_slot = 519 pp->cmd_slot =
508 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem); 520 (struct ahci_cmd_hdr *)(uintptr_t)virt_to_phys((void *)mem);
509 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot); 521 debug("cmd_slot = 0x%x\n", (unsigned)pp->cmd_slot);
510 mem += (AHCI_CMD_SLOT_SZ + 224); 522 mem += (AHCI_CMD_SLOT_SZ + 224);
511 523
512 /* 524 /*
513 * Second item: Received-FIS area 525 * Second item: Received-FIS area
514 */ 526 */
515 pp->rx_fis = virt_to_phys((void *)mem); 527 pp->rx_fis = virt_to_phys((void *)mem);
516 mem += AHCI_RX_FIS_SZ; 528 mem += AHCI_RX_FIS_SZ;
517 529
518 /* 530 /*
519 * Third item: data area for storing a single command 531 * Third item: data area for storing a single command
520 * and its scatter-gather table 532 * and its scatter-gather table
521 */ 533 */
522 pp->cmd_tbl = virt_to_phys((void *)mem); 534 pp->cmd_tbl = virt_to_phys((void *)mem);
523 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl); 535 debug("cmd_tbl_dma = 0x%x\n", pp->cmd_tbl);
524 536
525 mem += AHCI_CMD_TBL_HDR; 537 mem += AHCI_CMD_TBL_HDR;
526 pp->cmd_tbl_sg = 538 pp->cmd_tbl_sg =
527 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem); 539 (struct ahci_sg *)(uintptr_t)virt_to_phys((void *)mem);
528 540
529 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR); 541 writel_with_flush((u32) pp->cmd_slot, port_mmio + PORT_LST_ADDR);
530 542
531 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR); 543 writel_with_flush(pp->rx_fis, port_mmio + PORT_FIS_ADDR);
532 544
533 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX | 545 writel_with_flush(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
534 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP | 546 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
535 PORT_CMD_START, port_mmio + PORT_CMD); 547 PORT_CMD_START, port_mmio + PORT_CMD);
536 548
537 debug("Exit start port %d\n", port); 549 debug("Exit start port %d\n", port);
538 550
539 return 0; 551 return 0;
540 } 552 }
541 553
542 554
543 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf, 555 static int ahci_device_data_io(u8 port, u8 *fis, int fis_len, u8 *buf,
544 int buf_len, u8 is_write) 556 int buf_len, u8 is_write)
545 { 557 {
546 558
547 struct ahci_ioports *pp = &(probe_ent->port[port]); 559 struct ahci_ioports *pp = &(probe_ent->port[port]);
548 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; 560 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
549 u32 opts; 561 u32 opts;
550 u32 port_status; 562 u32 port_status;
551 int sg_count; 563 int sg_count;
552 564
553 debug("Enter %s: for port %d\n", __func__, port); 565 debug("Enter %s: for port %d\n", __func__, port);
554 566
555 if (port > probe_ent->n_ports) { 567 if (port > probe_ent->n_ports) {
556 printf("Invalid port number %d\n", port); 568 printf("Invalid port number %d\n", port);
557 return -1; 569 return -1;
558 } 570 }
559 571
560 port_status = readl(port_mmio + PORT_SCR_STAT); 572 port_status = readl(port_mmio + PORT_SCR_STAT);
561 if ((port_status & 0xf) != 0x03) { 573 if ((port_status & 0xf) != 0x03) {
562 debug("No Link on port %d!\n", port); 574 debug("No Link on port %d!\n", port);
563 return -1; 575 return -1;
564 } 576 }
565 577
566 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len); 578 memcpy((unsigned char *)pp->cmd_tbl, fis, fis_len);
567 579
568 sg_count = ahci_fill_sg(port, buf, buf_len); 580 sg_count = ahci_fill_sg(port, buf, buf_len);
569 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6); 581 opts = (fis_len >> 2) | (sg_count << 16) | (is_write << 6);
570 ahci_fill_cmd_slot(pp, opts); 582 ahci_fill_cmd_slot(pp, opts);
571 583
572 ahci_dcache_flush_sata_cmd(pp); 584 ahci_dcache_flush_sata_cmd(pp);
573 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len); 585 ahci_dcache_flush_range((unsigned)buf, (unsigned)buf_len);
574 586
575 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 587 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
576 588
577 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 589 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
578 WAIT_MS_DATAIO, 0x1)) { 590 WAIT_MS_DATAIO, 0x1)) {
579 printf("timeout exit!\n"); 591 printf("timeout exit!\n");
580 return -1; 592 return -1;
581 } 593 }
582 594
583 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len); 595 ahci_dcache_invalidate_range((unsigned)buf, (unsigned)buf_len);
584 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status); 596 debug("%s: %d byte transferred.\n", __func__, pp->cmd_slot->status);
585 597
586 return 0; 598 return 0;
587 } 599 }
588 600
589 601
590 static char *ata_id_strcpy(u16 *target, u16 *src, int len) 602 static char *ata_id_strcpy(u16 *target, u16 *src, int len)
591 { 603 {
592 int i; 604 int i;
593 for (i = 0; i < len / 2; i++) 605 for (i = 0; i < len / 2; i++)
594 target[i] = swab16(src[i]); 606 target[i] = swab16(src[i]);
595 return (char *)target; 607 return (char *)target;
596 } 608 }
597 609
598 610
599 static void dump_ataid(hd_driveid_t *ataid) 611 static void dump_ataid(hd_driveid_t *ataid)
600 { 612 {
601 debug("(49)ataid->capability = 0x%x\n", ataid->capability); 613 debug("(49)ataid->capability = 0x%x\n", ataid->capability);
602 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid); 614 debug("(53)ataid->field_valid =0x%x\n", ataid->field_valid);
603 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword); 615 debug("(63)ataid->dma_mword = 0x%x\n", ataid->dma_mword);
604 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes); 616 debug("(64)ataid->eide_pio_modes = 0x%x\n", ataid->eide_pio_modes);
605 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth); 617 debug("(75)ataid->queue_depth = 0x%x\n", ataid->queue_depth);
606 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num); 618 debug("(80)ataid->major_rev_num = 0x%x\n", ataid->major_rev_num);
607 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num); 619 debug("(81)ataid->minor_rev_num = 0x%x\n", ataid->minor_rev_num);
608 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1); 620 debug("(82)ataid->command_set_1 = 0x%x\n", ataid->command_set_1);
609 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2); 621 debug("(83)ataid->command_set_2 = 0x%x\n", ataid->command_set_2);
610 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse); 622 debug("(84)ataid->cfsse = 0x%x\n", ataid->cfsse);
611 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1); 623 debug("(85)ataid->cfs_enable_1 = 0x%x\n", ataid->cfs_enable_1);
612 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2); 624 debug("(86)ataid->cfs_enable_2 = 0x%x\n", ataid->cfs_enable_2);
613 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default); 625 debug("(87)ataid->csf_default = 0x%x\n", ataid->csf_default);
614 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra); 626 debug("(88)ataid->dma_ultra = 0x%x\n", ataid->dma_ultra);
615 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config); 627 debug("(93)ataid->hw_config = 0x%x\n", ataid->hw_config);
616 } 628 }
617 629
618 630
619 /* 631 /*
620 * SCSI INQUIRY command operation. 632 * SCSI INQUIRY command operation.
621 */ 633 */
622 static int ata_scsiop_inquiry(ccb *pccb) 634 static int ata_scsiop_inquiry(ccb *pccb)
623 { 635 {
624 static const u8 hdr[] = { 636 static const u8 hdr[] = {
625 0, 637 0,
626 0, 638 0,
627 0x5, /* claim SPC-3 version compatibility */ 639 0x5, /* claim SPC-3 version compatibility */
628 2, 640 2,
629 95 - 4, 641 95 - 4,
630 }; 642 };
631 u8 fis[20]; 643 u8 fis[20];
632 u8 *tmpid; 644 u8 *tmpid;
633 u8 port; 645 u8 port;
634 646
635 /* Clean ccb data buffer */ 647 /* Clean ccb data buffer */
636 memset(pccb->pdata, 0, pccb->datalen); 648 memset(pccb->pdata, 0, pccb->datalen);
637 649
638 memcpy(pccb->pdata, hdr, sizeof(hdr)); 650 memcpy(pccb->pdata, hdr, sizeof(hdr));
639 651
640 if (pccb->datalen <= 35) 652 if (pccb->datalen <= 35)
641 return 0; 653 return 0;
642 654
643 memset(fis, 0, sizeof(fis)); 655 memset(fis, 0, sizeof(fis));
644 /* Construct the FIS */ 656 /* Construct the FIS */
645 fis[0] = 0x27; /* Host to device FIS. */ 657 fis[0] = 0x27; /* Host to device FIS. */
646 fis[1] = 1 << 7; /* Command FIS. */ 658 fis[1] = 1 << 7; /* Command FIS. */
647 fis[2] = ATA_CMD_IDENT; /* Command byte. */ 659 fis[2] = ATA_CMD_IDENT; /* Command byte. */
648 660
649 /* Read id from sata */ 661 /* Read id from sata */
650 port = pccb->target; 662 port = pccb->target;
651 if (!(tmpid = malloc(sizeof(hd_driveid_t)))) 663 if (!(tmpid = malloc(sizeof(hd_driveid_t))))
652 return -ENOMEM; 664 return -ENOMEM;
653 665
654 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid, 666 if (ahci_device_data_io(port, (u8 *) &fis, sizeof(fis), tmpid,
655 sizeof(hd_driveid_t), 0)) { 667 sizeof(hd_driveid_t), 0)) {
656 debug("scsi_ahci: SCSI inquiry command failure.\n"); 668 debug("scsi_ahci: SCSI inquiry command failure.\n");
657 free(tmpid); 669 free(tmpid);
658 return -EIO; 670 return -EIO;
659 } 671 }
660 672
661 if (ataid[port]) 673 if (ataid[port])
662 free(ataid[port]); 674 free(ataid[port]);
663 ataid[port] = (hd_driveid_t *) tmpid; 675 ataid[port] = (hd_driveid_t *) tmpid;
664 676
665 memcpy(&pccb->pdata[8], "ATA ", 8); 677 memcpy(&pccb->pdata[8], "ATA ", 8);
666 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16); 678 ata_id_strcpy((u16 *) &pccb->pdata[16], (u16 *)ataid[port]->model, 16);
667 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4); 679 ata_id_strcpy((u16 *) &pccb->pdata[32], (u16 *)ataid[port]->fw_rev, 4);
668 680
669 dump_ataid(ataid[port]); 681 dump_ataid(ataid[port]);
670 return 0; 682 return 0;
671 } 683 }
672 684
673 685
674 /* 686 /*
675 * SCSI READ10/WRITE10 command operation. 687 * SCSI READ10/WRITE10 command operation.
676 */ 688 */
677 static int ata_scsiop_read_write(ccb *pccb, u8 is_write) 689 static int ata_scsiop_read_write(ccb *pccb, u8 is_write)
678 { 690 {
679 u32 lba = 0; 691 u32 lba = 0;
680 u16 blocks = 0; 692 u16 blocks = 0;
681 u8 fis[20]; 693 u8 fis[20];
682 u8 *user_buffer = pccb->pdata; 694 u8 *user_buffer = pccb->pdata;
683 u32 user_buffer_size = pccb->datalen; 695 u32 user_buffer_size = pccb->datalen;
684 696
685 /* Retrieve the base LBA number from the ccb structure. */ 697 /* Retrieve the base LBA number from the ccb structure. */
686 memcpy(&lba, pccb->cmd + 2, sizeof(lba)); 698 memcpy(&lba, pccb->cmd + 2, sizeof(lba));
687 lba = be32_to_cpu(lba); 699 lba = be32_to_cpu(lba);
688 700
689 /* 701 /*
690 * And the number of blocks. 702 * And the number of blocks.
691 * 703 *
692 * For 10-byte and 16-byte SCSI R/W commands, transfer 704 * For 10-byte and 16-byte SCSI R/W commands, transfer
693 * length 0 means transfer 0 block of data. 705 * length 0 means transfer 0 block of data.
694 * However, for ATA R/W commands, sector count 0 means 706 * However, for ATA R/W commands, sector count 0 means
695 * 256 or 65536 sectors, not 0 sectors as in SCSI. 707 * 256 or 65536 sectors, not 0 sectors as in SCSI.
696 * 708 *
697 * WARNING: one or two older ATA drives treat 0 as 0... 709 * WARNING: one or two older ATA drives treat 0 as 0...
698 */ 710 */
699 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]); 711 blocks = (((u16)pccb->cmd[7]) << 8) | ((u16) pccb->cmd[8]);
700 712
701 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n", 713 debug("scsi_ahci: %s %d blocks starting from lba 0x%x\n",
702 is_write ? "write" : "read", (unsigned)lba, blocks); 714 is_write ? "write" : "read", (unsigned)lba, blocks);
703 715
704 /* Preset the FIS */ 716 /* Preset the FIS */
705 memset(fis, 0, sizeof(fis)); 717 memset(fis, 0, sizeof(fis));
706 fis[0] = 0x27; /* Host to device FIS. */ 718 fis[0] = 0x27; /* Host to device FIS. */
707 fis[1] = 1 << 7; /* Command FIS. */ 719 fis[1] = 1 << 7; /* Command FIS. */
708 /* Command byte (read/write). */ 720 /* Command byte (read/write). */
709 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT; 721 fis[2] = is_write ? ATA_CMD_WRITE_EXT : ATA_CMD_READ_EXT;
710 722
711 while (blocks) { 723 while (blocks) {
712 u16 now_blocks; /* number of blocks per iteration */ 724 u16 now_blocks; /* number of blocks per iteration */
713 u32 transfer_size; /* number of bytes per iteration */ 725 u32 transfer_size; /* number of bytes per iteration */
714 726
715 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks); 727 now_blocks = min(MAX_SATA_BLOCKS_READ_WRITE, blocks);
716 728
717 transfer_size = ATA_BLOCKSIZE * now_blocks; 729 transfer_size = ATA_BLOCKSIZE * now_blocks;
718 if (transfer_size > user_buffer_size) { 730 if (transfer_size > user_buffer_size) {
719 printf("scsi_ahci: Error: buffer too small.\n"); 731 printf("scsi_ahci: Error: buffer too small.\n");
720 return -EIO; 732 return -EIO;
721 } 733 }
722 734
723 /* LBA48 SATA command but only use 32bit address range within 735 /* LBA48 SATA command but only use 32bit address range within
724 * that. The next smaller command range (28bit) is too small. 736 * that. The next smaller command range (28bit) is too small.
725 */ 737 */
726 fis[4] = (lba >> 0) & 0xff; 738 fis[4] = (lba >> 0) & 0xff;
727 fis[5] = (lba >> 8) & 0xff; 739 fis[5] = (lba >> 8) & 0xff;
728 fis[6] = (lba >> 16) & 0xff; 740 fis[6] = (lba >> 16) & 0xff;
729 fis[7] = 1 << 6; /* device reg: set LBA mode */ 741 fis[7] = 1 << 6; /* device reg: set LBA mode */
730 fis[8] = ((lba >> 24) & 0xff); 742 fis[8] = ((lba >> 24) & 0xff);
731 fis[3] = 0xe0; /* features */ 743 fis[3] = 0xe0; /* features */
732 744
733 /* Block (sector) count */ 745 /* Block (sector) count */
734 fis[12] = (now_blocks >> 0) & 0xff; 746 fis[12] = (now_blocks >> 0) & 0xff;
735 fis[13] = (now_blocks >> 8) & 0xff; 747 fis[13] = (now_blocks >> 8) & 0xff;
736 748
737 /* Read/Write from ahci */ 749 /* Read/Write from ahci */
738 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis), 750 if (ahci_device_data_io(pccb->target, (u8 *) &fis, sizeof(fis),
739 user_buffer, user_buffer_size, 751 user_buffer, user_buffer_size,
740 is_write)) { 752 is_write)) {
741 debug("scsi_ahci: SCSI %s10 command failure.\n", 753 debug("scsi_ahci: SCSI %s10 command failure.\n",
742 is_write ? "WRITE" : "READ"); 754 is_write ? "WRITE" : "READ");
743 return -EIO; 755 return -EIO;
744 } 756 }
745 757
746 /* If this transaction is a write, do a following flush. 758 /* If this transaction is a write, do a following flush.
747 * Writes in u-boot are so rare, and the logic to know when is 759 * Writes in u-boot are so rare, and the logic to know when is
748 * the last write and do a flush only there is sufficiently 760 * the last write and do a flush only there is sufficiently
749 * difficult. Just do a flush after every write. This incurs, 761 * difficult. Just do a flush after every write. This incurs,
750 * usually, one extra flush when the rare writes do happen. 762 * usually, one extra flush when the rare writes do happen.
751 */ 763 */
752 if (is_write) { 764 if (is_write) {
753 if (-EIO == ata_io_flush(pccb->target)) 765 if (-EIO == ata_io_flush(pccb->target))
754 return -EIO; 766 return -EIO;
755 } 767 }
756 user_buffer += transfer_size; 768 user_buffer += transfer_size;
757 user_buffer_size -= transfer_size; 769 user_buffer_size -= transfer_size;
758 blocks -= now_blocks; 770 blocks -= now_blocks;
759 lba += now_blocks; 771 lba += now_blocks;
760 } 772 }
761 773
762 return 0; 774 return 0;
763 } 775 }
764 776
765 777
766 /* 778 /*
767 * SCSI READ CAPACITY10 command operation. 779 * SCSI READ CAPACITY10 command operation.
768 */ 780 */
769 static int ata_scsiop_read_capacity10(ccb *pccb) 781 static int ata_scsiop_read_capacity10(ccb *pccb)
770 { 782 {
771 u32 cap; 783 u32 cap;
772 u32 block_size; 784 u32 block_size;
773 785
774 if (!ataid[pccb->target]) { 786 if (!ataid[pccb->target]) {
775 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. " 787 printf("scsi_ahci: SCSI READ CAPACITY10 command failure. "
776 "\tNo ATA info!\n" 788 "\tNo ATA info!\n"
777 "\tPlease run SCSI commmand INQUIRY firstly!\n"); 789 "\tPlease run SCSI commmand INQUIRY firstly!\n");
778 return -EPERM; 790 return -EPERM;
779 } 791 }
780 792
781 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); 793 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
782 if (cap == 0xfffffff) { 794 if (cap == 0xfffffff) {
783 unsigned short *cap48 = ataid[pccb->target]->lba48_capacity; 795 unsigned short *cap48 = ataid[pccb->target]->lba48_capacity;
784 if (cap48[2] || cap48[3]) { 796 if (cap48[2] || cap48[3]) {
785 cap = 0xffffffff; 797 cap = 0xffffffff;
786 } else { 798 } else {
787 cap = (le16_to_cpu(cap48[1]) << 16) | 799 cap = (le16_to_cpu(cap48[1]) << 16) |
788 (le16_to_cpu(cap48[0])); 800 (le16_to_cpu(cap48[0]));
789 } 801 }
790 } 802 }
791 803
792 cap = cpu_to_be32(cap); 804 cap = cpu_to_be32(cap);
793 memcpy(pccb->pdata, &cap, sizeof(cap)); 805 memcpy(pccb->pdata, &cap, sizeof(cap));
794 806
795 block_size = cpu_to_be32((u32)512); 807 block_size = cpu_to_be32((u32)512);
796 memcpy(&pccb->pdata[4], &block_size, 4); 808 memcpy(&pccb->pdata[4], &block_size, 4);
797 809
798 return 0; 810 return 0;
799 } 811 }
800 812
801 813
802 /* 814 /*
803 * SCSI READ CAPACITY16 command operation. 815 * SCSI READ CAPACITY16 command operation.
804 */ 816 */
805 static int ata_scsiop_read_capacity16(ccb *pccb) 817 static int ata_scsiop_read_capacity16(ccb *pccb)
806 { 818 {
807 u64 cap; 819 u64 cap;
808 u64 block_size; 820 u64 block_size;
809 821
810 if (!ataid[pccb->target]) { 822 if (!ataid[pccb->target]) {
811 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. " 823 printf("scsi_ahci: SCSI READ CAPACITY16 command failure. "
812 "\tNo ATA info!\n" 824 "\tNo ATA info!\n"
813 "\tPlease run SCSI commmand INQUIRY firstly!\n"); 825 "\tPlease run SCSI commmand INQUIRY firstly!\n");
814 return -EPERM; 826 return -EPERM;
815 } 827 }
816 828
817 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity); 829 cap = le32_to_cpu(ataid[pccb->target]->lba_capacity);
818 if (cap == 0xfffffff) { 830 if (cap == 0xfffffff) {
819 memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap)); 831 memcpy(&cap, ataid[pccb->target]->lba48_capacity, sizeof(cap));
820 cap = le64_to_cpu(cap); 832 cap = le64_to_cpu(cap);
821 } 833 }
822 834
823 cap = cpu_to_be64(cap); 835 cap = cpu_to_be64(cap);
824 memcpy(pccb->pdata, &cap, sizeof(cap)); 836 memcpy(pccb->pdata, &cap, sizeof(cap));
825 837
826 block_size = cpu_to_be64((u64)512); 838 block_size = cpu_to_be64((u64)512);
827 memcpy(&pccb->pdata[8], &block_size, 8); 839 memcpy(&pccb->pdata[8], &block_size, 8);
828 840
829 return 0; 841 return 0;
830 } 842 }
831 843
832 844
833 /* 845 /*
834 * SCSI TEST UNIT READY command operation. 846 * SCSI TEST UNIT READY command operation.
835 */ 847 */
836 static int ata_scsiop_test_unit_ready(ccb *pccb) 848 static int ata_scsiop_test_unit_ready(ccb *pccb)
837 { 849 {
838 return (ataid[pccb->target]) ? 0 : -EPERM; 850 return (ataid[pccb->target]) ? 0 : -EPERM;
839 } 851 }
840 852
841 853
842 int scsi_exec(ccb *pccb) 854 int scsi_exec(ccb *pccb)
843 { 855 {
844 int ret; 856 int ret;
845 857
846 switch (pccb->cmd[0]) { 858 switch (pccb->cmd[0]) {
847 case SCSI_READ10: 859 case SCSI_READ10:
848 ret = ata_scsiop_read_write(pccb, 0); 860 ret = ata_scsiop_read_write(pccb, 0);
849 break; 861 break;
850 case SCSI_WRITE10: 862 case SCSI_WRITE10:
851 ret = ata_scsiop_read_write(pccb, 1); 863 ret = ata_scsiop_read_write(pccb, 1);
852 break; 864 break;
853 case SCSI_RD_CAPAC10: 865 case SCSI_RD_CAPAC10:
854 ret = ata_scsiop_read_capacity10(pccb); 866 ret = ata_scsiop_read_capacity10(pccb);
855 break; 867 break;
856 case SCSI_RD_CAPAC16: 868 case SCSI_RD_CAPAC16:
857 ret = ata_scsiop_read_capacity16(pccb); 869 ret = ata_scsiop_read_capacity16(pccb);
858 break; 870 break;
859 case SCSI_TST_U_RDY: 871 case SCSI_TST_U_RDY:
860 ret = ata_scsiop_test_unit_ready(pccb); 872 ret = ata_scsiop_test_unit_ready(pccb);
861 break; 873 break;
862 case SCSI_INQUIRY: 874 case SCSI_INQUIRY:
863 ret = ata_scsiop_inquiry(pccb); 875 ret = ata_scsiop_inquiry(pccb);
864 break; 876 break;
865 default: 877 default:
866 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]); 878 printf("Unsupport SCSI command 0x%02x\n", pccb->cmd[0]);
867 return false; 879 return false;
868 } 880 }
869 881
870 if (ret) { 882 if (ret) {
871 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret); 883 debug("SCSI command 0x%02x ret errno %d\n", pccb->cmd[0], ret);
872 return false; 884 return false;
873 } 885 }
874 return true; 886 return true;
875 887
876 } 888 }
877 889
878 890
879 void scsi_low_level_init(int busdevfunc) 891 void scsi_low_level_init(int busdevfunc)
880 { 892 {
881 int i; 893 int i;
882 u32 linkmap; 894 u32 linkmap;
883 895
884 #ifndef CONFIG_SCSI_AHCI_PLAT 896 #ifndef CONFIG_SCSI_AHCI_PLAT
885 ahci_init_one(busdevfunc); 897 ahci_init_one(busdevfunc);
886 #endif 898 #endif
887 899
888 linkmap = probe_ent->link_port_map; 900 linkmap = probe_ent->link_port_map;
889 901
890 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { 902 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
891 if (((linkmap >> i) & 0x01)) { 903 if (((linkmap >> i) & 0x01)) {
892 if (ahci_port_start((u8) i)) { 904 if (ahci_port_start((u8) i)) {
893 printf("Can not start port %d\n", i); 905 printf("Can not start port %d\n", i);
894 continue; 906 continue;
895 } 907 }
896 #ifdef CONFIG_AHCI_SETFEATURES_XFER 908 #ifdef CONFIG_AHCI_SETFEATURES_XFER
897 ahci_set_feature((u8) i); 909 ahci_set_feature((u8) i);
898 #endif 910 #endif
899 } 911 }
900 } 912 }
901 } 913 }
902 914
903 #ifdef CONFIG_SCSI_AHCI_PLAT 915 #ifdef CONFIG_SCSI_AHCI_PLAT
904 int ahci_init(u32 base) 916 int ahci_init(u32 base)
905 { 917 {
906 int i, rc = 0; 918 int i, rc = 0;
907 u32 linkmap; 919 u32 linkmap;
908 920
909 memset(ataid, 0, sizeof(ataid)); 921 memset(ataid, 0, sizeof(ataid));
910 922
911 probe_ent = malloc(sizeof(struct ahci_probe_ent)); 923 probe_ent = malloc(sizeof(struct ahci_probe_ent));
912 memset(probe_ent, 0, sizeof(struct ahci_probe_ent)); 924 memset(probe_ent, 0, sizeof(struct ahci_probe_ent));
913 925
914 probe_ent->host_flags = ATA_FLAG_SATA 926 probe_ent->host_flags = ATA_FLAG_SATA
915 | ATA_FLAG_NO_LEGACY 927 | ATA_FLAG_NO_LEGACY
916 | ATA_FLAG_MMIO 928 | ATA_FLAG_MMIO
917 | ATA_FLAG_PIO_DMA 929 | ATA_FLAG_PIO_DMA
918 | ATA_FLAG_NO_ATAPI; 930 | ATA_FLAG_NO_ATAPI;
919 probe_ent->pio_mask = 0x1f; 931 probe_ent->pio_mask = 0x1f;
920 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */ 932 probe_ent->udma_mask = 0x7f; /*Fixme,assume to support UDMA6 */
921 933
922 probe_ent->mmio_base = base; 934 probe_ent->mmio_base = base;
923 935
924 /* initialize adapter */ 936 /* initialize adapter */
925 rc = ahci_host_init(probe_ent); 937 rc = ahci_host_init(probe_ent);
926 if (rc) 938 if (rc)
927 goto err_out; 939 goto err_out;
928 940
929 ahci_print_info(probe_ent); 941 ahci_print_info(probe_ent);
930 942
931 linkmap = probe_ent->link_port_map; 943 linkmap = probe_ent->link_port_map;
932 944
933 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) { 945 for (i = 0; i < CONFIG_SYS_SCSI_MAX_SCSI_ID; i++) {
934 if (((linkmap >> i) & 0x01)) { 946 if (((linkmap >> i) & 0x01)) {
935 if (ahci_port_start((u8) i)) { 947 if (ahci_port_start((u8) i)) {
936 printf("Can not start port %d\n", i); 948 printf("Can not start port %d\n", i);
937 continue; 949 continue;
938 } 950 }
939 #ifdef CONFIG_AHCI_SETFEATURES_XFER 951 #ifdef CONFIG_AHCI_SETFEATURES_XFER
940 ahci_set_feature((u8) i); 952 ahci_set_feature((u8) i);
941 #endif 953 #endif
942 } 954 }
943 } 955 }
944 err_out: 956 err_out:
945 return rc; 957 return rc;
946 } 958 }
947 #endif 959 #endif
948 960
949 /* 961 /*
950 * In the general case of generic rotating media it makes sense to have a 962 * In the general case of generic rotating media it makes sense to have a
951 * flush capability. It probably even makes sense in the case of SSDs because 963 * flush capability. It probably even makes sense in the case of SSDs because
952 * one cannot always know for sure what kind of internal cache/flush mechanism 964 * one cannot always know for sure what kind of internal cache/flush mechanism
953 * is embodied therein. At first it was planned to invoke this after the last 965 * is embodied therein. At first it was planned to invoke this after the last
954 * write to disk and before rebooting. In practice, knowing, a priori, which 966 * write to disk and before rebooting. In practice, knowing, a priori, which
955 * is the last write is difficult. Because writing to the disk in u-boot is 967 * is the last write is difficult. Because writing to the disk in u-boot is
956 * very rare, this flush command will be invoked after every block write. 968 * very rare, this flush command will be invoked after every block write.
957 */ 969 */
958 static int ata_io_flush(u8 port) 970 static int ata_io_flush(u8 port)
959 { 971 {
960 u8 fis[20]; 972 u8 fis[20];
961 struct ahci_ioports *pp = &(probe_ent->port[port]); 973 struct ahci_ioports *pp = &(probe_ent->port[port]);
962 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio; 974 volatile u8 *port_mmio = (volatile u8 *)pp->port_mmio;
963 u32 cmd_fis_len = 5; /* five dwords */ 975 u32 cmd_fis_len = 5; /* five dwords */
964 976
965 /* Preset the FIS */ 977 /* Preset the FIS */
966 memset(fis, 0, 20); 978 memset(fis, 0, 20);
967 fis[0] = 0x27; /* Host to device FIS. */ 979 fis[0] = 0x27; /* Host to device FIS. */
968 fis[1] = 1 << 7; /* Command FIS. */ 980 fis[1] = 1 << 7; /* Command FIS. */
969 fis[2] = ATA_CMD_FLUSH_EXT; 981 fis[2] = ATA_CMD_FLUSH_EXT;
970 982
971 memcpy((unsigned char *)pp->cmd_tbl, fis, 20); 983 memcpy((unsigned char *)pp->cmd_tbl, fis, 20);
972 ahci_fill_cmd_slot(pp, cmd_fis_len); 984 ahci_fill_cmd_slot(pp, cmd_fis_len);
973 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE); 985 writel_with_flush(1, port_mmio + PORT_CMD_ISSUE);
974 986
975 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE, 987 if (waiting_for_cmd_completed(port_mmio + PORT_CMD_ISSUE,
976 WAIT_MS_FLUSH, 0x1)) { 988 WAIT_MS_FLUSH, 0x1)) {
977 debug("scsi_ahci: flush command timeout on port %d.\n", port); 989 debug("scsi_ahci: flush command timeout on port %d.\n", port);
978 return -EIO; 990 return -EIO;
979 } 991 }
980 992
981 return 0; 993 return 0;
982 } 994 }
983 995
984 996
985 void scsi_bus_reset(void) 997 void scsi_bus_reset(void)
986 { 998 {
987 /*Not implement*/ 999 /*Not implement*/
988 } 1000 }
989 1001
990 1002
991 void scsi_print_error(ccb * pccb) 1003 void scsi_print_error(ccb * pccb)
992 { 1004 {
993 /*The ahci error info can be read in the ahci driver*/ 1005 /*The ahci error info can be read in the ahci driver*/
994 } 1006 }
995 1007