Eric Lee / smarc-uboot

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Commit 1951c33999f3abcabd29fe9bd04736bb646f59b6

Authored by Biwen Li
Committed by Priyanka Jain
1 parent c0e10b1d4f
Exists in smarc_8mq_lf_v2020.04 and in 4 other branches pitx_8mp_lf_v2020.04, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc_8mp_lf_v2020.04

configs: ls1028a: enable CONFIG_MPC8XXX_GPIO 

Enable CONFIG_MPC8XXX_GPIO for SoC LS1028A

Signed-off-by: Biwen Li <biwen.li@nxp.com>

Showing 1 changed file with 10 additions and 0 deletions Inline Diff

include/configs/ls1028a_common.h
Diff comments   View file @ 1951c33
1 /* SPDX-License-Identifier: GPL-2.0+ */ 1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* 2 /*
3 * Copyright 2019-2020 NXP 3 * Copyright 2019-2020 NXP
4 */ 4 */
5 5
6 #ifndef __L1028A_COMMON_H 6 #ifndef __L1028A_COMMON_H
7 #define __L1028A_COMMON_H 7 #define __L1028A_COMMON_H
8 8
9 #define CONFIG_REMAKE_ELF 9 #define CONFIG_REMAKE_ELF
10 #define CONFIG_FSL_LAYERSCAPE 10 #define CONFIG_FSL_LAYERSCAPE
11 #define CONFIG_MP 11 #define CONFIG_MP
12 12
13 #include <asm/arch/stream_id_lsch3.h> 13 #include <asm/arch/stream_id_lsch3.h>
14 #include <asm/arch/config.h> 14 #include <asm/arch/config.h>
15 #include <asm/arch/soc.h> 15 #include <asm/arch/soc.h>
16 16
17 /* Link Definitions */ 17 /* Link Definitions */
18 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE 18 #define CONFIG_SYS_INIT_SP_ADDR CONFIG_SYS_TEXT_BASE
19 19
20 #define CONFIG_SKIP_LOWLEVEL_INIT 20 #define CONFIG_SKIP_LOWLEVEL_INIT
21 21
22 #define CONFIG_VERY_BIG_RAM 22 #define CONFIG_VERY_BIG_RAM
23 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL 23 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
24 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 24 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE 25 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
26 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL 26 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
27 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1 27 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS 1
28 28
29 #define CONFIG_CMD_MEMTEST 29 #define CONFIG_CMD_MEMTEST
30 #define CONFIG_SYS_MEMTEST_START 0x80000000 30 #define CONFIG_SYS_MEMTEST_START 0x80000000
31 #define CONFIG_SYS_MEMTEST_END 0x9fffffff 31 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
32 32
33 /* 33 /*
34 * SMP Definitinos 34 * SMP Definitinos
35 */ 35 */
36 #define CPU_RELEASE_ADDR secondary_boot_func 36 #define CPU_RELEASE_ADDR secondary_boot_func
37 37
38 /* Generic Timer Definitions */ 38 /* Generic Timer Definitions */
39 #define COUNTER_FREQUENCY 25000000 /* 25MHz */ 39 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
40 40
41 /* Size of malloc() pool */ 41 /* Size of malloc() pool */
42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024) 42 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2048 * 1024)
43 43
44 /* GPIO */
45 #ifdef CONFIG_DM_GPIO
46 #ifndef CONFIG_MPC8XXX_GPIO
47 #define CONFIG_MPC8XXX_GPIO
48 #endif
49 #ifndef CONFIG_CMD_GPIO
50 #define CONFIG_CMD_GPIO
51 #endif
52 #endif
53
44 /* I2C */ 54 /* I2C */
45 #ifndef CONFIG_DM_I2C 55 #ifndef CONFIG_DM_I2C
46 #define CONFIG_SYS_I2C 56 #define CONFIG_SYS_I2C
47 #endif 57 #endif
48 58
49 /* Serial Port */ 59 /* Serial Port */
50 #define CONFIG_CONS_INDEX 1 60 #define CONFIG_CONS_INDEX 1
51 #define CONFIG_SYS_NS16550_SERIAL 61 #define CONFIG_SYS_NS16550_SERIAL
52 #define CONFIG_SYS_NS16550_REG_SIZE 1 62 #define CONFIG_SYS_NS16550_REG_SIZE 1
53 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) 63 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2)
54 64
55 #define CONFIG_BAUDRATE 115200 65 #define CONFIG_BAUDRATE 115200
56 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } 66 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
57 67
58 /* Miscellaneous configurable options */ 68 /* Miscellaneous configurable options */
59 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000) 69 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
60 70
61 /* Physical Memory Map */ 71 /* Physical Memory Map */
62 #define CONFIG_CHIP_SELECTS_PER_CTRL 4 72 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
63 73
64 #define CONFIG_HWCONFIG 74 #define CONFIG_HWCONFIG
65 #define HWCONFIG_BUFFER_SIZE 128 75 #define HWCONFIG_BUFFER_SIZE 128
66 76
67 /* Allow to overwrite serial and ethaddr */ 77 /* Allow to overwrite serial and ethaddr */
68 #define CONFIG_ENV_OVERWRITE 78 #define CONFIG_ENV_OVERWRITE
69 79
70 #define BOOT_TARGET_DEVICES(func) \ 80 #define BOOT_TARGET_DEVICES(func) \
71 func(MMC, mmc, 0) \ 81 func(MMC, mmc, 0) \
72 func(MMC, mmc, 1) \ 82 func(MMC, mmc, 1) \
73 func(USB, usb, 0) \ 83 func(USB, usb, 0) \
74 func(DHCP, dhcp, na) 84 func(DHCP, dhcp, na)
75 #include <config_distro_bootcmd.h> 85 #include <config_distro_bootcmd.h>
76 86
77 #undef CONFIG_BOOTCOMMAND 87 #undef CONFIG_BOOTCOMMAND
78 88
79 #define XSPI_NOR_BOOTCOMMAND \ 89 #define XSPI_NOR_BOOTCOMMAND \
80 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \ 90 "run xspi_hdploadcmd; run distro_bootcmd; run xspi_bootcmd; " \
81 "env exists secureboot && esbc_halt;;" 91 "env exists secureboot && esbc_halt;;"
82 #define SD_BOOTCOMMAND \ 92 #define SD_BOOTCOMMAND \
83 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \ 93 "run sd_hdploadcmd; run distro_bootcmd;run sd_bootcmd; " \
84 "env exists secureboot && esbc_halt;" 94 "env exists secureboot && esbc_halt;"
85 #define SD2_BOOTCOMMAND \ 95 #define SD2_BOOTCOMMAND \
86 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \ 96 "run emmc_hdploadcmd; run distro_bootcmd;run emmc_bootcmd; " \
87 "env exists secureboot && esbc_halt;" 97 "env exists secureboot && esbc_halt;"
88 98
89 /* Monitor Command Prompt */ 99 /* Monitor Command Prompt */
90 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ 100 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
91 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ 101 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
92 sizeof(CONFIG_SYS_PROMPT) + 16) 102 sizeof(CONFIG_SYS_PROMPT) + 16)
93 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ 103 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
94 104
95 #ifndef CONFIG_CMDLINE_EDITING 105 #ifndef CONFIG_CMDLINE_EDITING
96 #define CONFIG_CMDLINE_EDITING 1 106 #define CONFIG_CMDLINE_EDITING 1
97 #endif 107 #endif
98 108
99 #define CONFIG_SYS_MAXARGS 64 /* max command args */ 109 #define CONFIG_SYS_MAXARGS 64 /* max command args */
100 110
101 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ 111 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
102 112
103 /* MMC */ 113 /* MMC */
104 #ifdef CONFIG_MMC 114 #ifdef CONFIG_MMC
105 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 115 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
106 #endif 116 #endif
107 117
108 #define CONFIG_SYS_MMC_ENV_DEV 0 118 #define CONFIG_SYS_MMC_ENV_DEV 0
109 #define OCRAM_NONSECURE_SIZE 0x00010000 119 #define OCRAM_NONSECURE_SIZE 0x00010000
110 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 120 #define CONFIG_SYS_FSL_QSPI_BASE 0x20000000
111 121
112 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 122 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
113 123
114 /* I2C bus multiplexer */ 124 /* I2C bus multiplexer */
115 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ 125 #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/
116 #define I2C_MUX_CH_DEFAULT 0x8 126 #define I2C_MUX_CH_DEFAULT 0x8
117 127
118 /* EEPROM */ 128 /* EEPROM */
119 #define CONFIG_ID_EEPROM 129 #define CONFIG_ID_EEPROM
120 #define CONFIG_SYS_I2C_EEPROM_NXID 130 #define CONFIG_SYS_I2C_EEPROM_NXID
121 #define CONFIG_SYS_EEPROM_BUS_NUM 0 131 #define CONFIG_SYS_EEPROM_BUS_NUM 0
122 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 132 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
123 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 133 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 134 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
125 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 135 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
126 136
127 /* DisplayPort */ 137 /* DisplayPort */
128 #define DP_PWD_EN_DEFAULT_MASK 0x8 138 #define DP_PWD_EN_DEFAULT_MASK 0x8
129 139
130 #ifdef CONFIG_NXP_ESBC 140 #ifdef CONFIG_NXP_ESBC
131 #include <asm/fsl_secure_boot.h> 141 #include <asm/fsl_secure_boot.h>
132 #endif 142 #endif
133 143
134 /* Ethernet */ 144 /* Ethernet */
135 /* smallest ENETC BD ring has 8 entries */ 145 /* smallest ENETC BD ring has 8 entries */
136 #define CONFIG_SYS_RX_ETH_BUFFER 8 146 #define CONFIG_SYS_RX_ETH_BUFFER 8
137 147
138 #endif /* __L1028A_COMMON_H */ 148 #endif /* __L1028A_COMMON_H */
139 149