Eric Lee / smarc-uboot

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Commit 1b387ef55c7a10a87814f3d8ffc04b62fbfc150e

Authored by Wolfgang Denk
Committed by Tom Rini
1 parent 9346d54366
Exists in master and in 56 other branches 8qm-imx_v2020.04_5.4.70_2.3.0, emb_lf-6.6.52-2.2.0, emb_lf_v2022.04, emb_lf_v2023.04, emb_lf_v2024.04, imx_v2015.04_4.1.15_1.0.0_ga, pitx_8mp_lf_v2020.04, smarc-8m-android-10.0.0_2.6.0, smarc-8m-android-11.0.0_2.0.0, smarc-8mp-android-11.0.0_2.0.0, smarc-emmc-imx_v2014.04_3.10.53_1.1.0_ga, smarc-emmc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx-l5.0.0_1.0.0-ga, smarc-imx6_v2018.03_4.14.98_2.0.0_ga, smarc-imx7_v2017.03_4.9.11_1.0.0_ga, smarc-imx7_v2018.03_4.14.98_2.0.0_ga, smarc-imx_v2014.04_3.14.28_1.0.0_ga, smarc-imx_v2015.04_4.1.15_1.0.0_ga, smarc-imx_v2017.03_4.9.11_1.0.0_ga, smarc-imx_v2017.03_4.9.88_2.0.0_ga, smarc-imx_v2017.03_o8.1.0_1.3.0_8m, smarc-imx_v2018.03_4.14.78_1.0.0_ga, smarc-m6.0.1_2.1.0-ga, smarc-n7.1.2_2.0.0-ga, smarc-rel_imx_4.1.15_2.0.0_ga, smarc_8m-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8m-imx_v2019.04_4.19.35_1.1.0, smarc_8m_00d0-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2018.03_4.14.98_2.0.0_ga, smarc_8mm-imx_v2019.04_4.19.35_1.1.0, smarc_8mm-imx_v2020.04_5.4.24_2.1.0, smarc_8mp_lf_v2020.04, smarc_8mq-imx_v2020.04_5.4.24_2.1.0, smarc_8mq_lf_v2020.04, ti-u-boot-2015.07, v2013.10, v2013.10-smarct33, v2013.10-smartmen, v2014.01, v2014.04, v2014.04-smarct33, v2014.04-smarct33-emmc, v2014.04-smartmen, v2014.07, v2014.07-smarct33, v2014.07-smartmen, v2015.07-smarct33, v2015.07-smarct33-emmc, v2015.07-smarct4x, v2016.05-dlt, v2016.05-smarct3x, v2016.05-smarct3x-emmc, v2016.05-smarct4x, v2017.01-smarct3x, v2017.01-smarct3x-emmc, v2017.01-smarct4x

SPDX: fix IBM-pibs license identifier 

The SPDX License List version 1.19 now contains an official entry for
the IBM-pibs license.  However, instead of our suggestion "ibm-pibs",
the SPDX License List uses "IBM-pibs", with the following rationale:
"The reason being that all other SPDX License List short identifiers
tend towards using capital letters unless spelling a word.  I'd prefer
to be consistent to this end".

Change the license IDs to use the official name.

Signed-off-by: Wolfgang Denk <wd@denx.de>

Showing 23 changed files with 23 additions and 23 deletions Inline Diff

1 U-Boot is Free Software. It is copyrighted by Wolfgang Denk and 1 U-Boot is Free Software. It is copyrighted by Wolfgang Denk and
2 many others who contributed code (see the actual source code and the 2 many others who contributed code (see the actual source code and the
3 git commit messages for details). You can redistribute U-Boot and/or 3 git commit messages for details). You can redistribute U-Boot and/or
4 modify it under the terms of version 2 of the GNU General Public 4 modify it under the terms of version 2 of the GNU General Public
5 License as published by the Free Software Foundation. Most of it can 5 License as published by the Free Software Foundation. Most of it can
6 also be distributed, at your option, under any later version of the 6 also be distributed, at your option, under any later version of the
7 GNU General Public License -- see individual files for exceptions. 7 GNU General Public License -- see individual files for exceptions.
8 8
9 NOTE! This license does *not* cover the so-called "standalone" 9 NOTE! This license does *not* cover the so-called "standalone"
10 applications that use U-Boot services by means of the jump table 10 applications that use U-Boot services by means of the jump table
11 provided by U-Boot exactly for this purpose - this is merely 11 provided by U-Boot exactly for this purpose - this is merely
12 considered normal use of U-Boot, and does *not* fall under the 12 considered normal use of U-Boot, and does *not* fall under the
13 heading of "derived work" -- see file Licenses/Exceptions for 13 heading of "derived work" -- see file Licenses/Exceptions for
14 details. 14 details.
15 15
16 Also note that the GPL and the other licenses are copyrighted by 16 Also note that the GPL and the other licenses are copyrighted by
17 the Free Software Foundation and other organizations, but the 17 the Free Software Foundation and other organizations, but the
18 instance of code that they refer to (the U-Boot source code) is 18 instance of code that they refer to (the U-Boot source code) is
19 copyrighted by me and others who actually wrote it. 19 copyrighted by me and others who actually wrote it.
20 -- Wolfgang Denk 20 -- Wolfgang Denk
21 21
22 22
23 Like many other projects, U-Boot has a tradition of including big 23 Like many other projects, U-Boot has a tradition of including big
24 blocks of License headers in all files. This not only blows up the 24 blocks of License headers in all files. This not only blows up the
25 source code with mostly redundant information, but also makes it very 25 source code with mostly redundant information, but also makes it very
26 difficult to generate License Clearing Reports. An additional problem 26 difficult to generate License Clearing Reports. An additional problem
27 is that even the same licenses are referred to by a number of 27 is that even the same licenses are referred to by a number of
28 slightly varying text blocks (full, abbreviated, different 28 slightly varying text blocks (full, abbreviated, different
29 indentation, line wrapping and/or white space, with obsolete address 29 indentation, line wrapping and/or white space, with obsolete address
30 information, ...) which makes automatic processing a nightmare. 30 information, ...) which makes automatic processing a nightmare.
31 31
32 To make this easier, such license headers in the source files will be 32 To make this easier, such license headers in the source files will be
33 replaced with a single line reference to Unique License Identifiers 33 replaced with a single line reference to Unique License Identifiers
34 as defined by the Linux Foundation's SPDX project [1]. For example, 34 as defined by the Linux Foundation's SPDX project [1]. For example,
35 in a source file the full "GPL v2.0 or later" header text will be 35 in a source file the full "GPL v2.0 or later" header text will be
36 replaced by a single line: 36 replaced by a single line:
37 37
38 SPDX-License-Identifier: GPL-2.0+ 38 SPDX-License-Identifier: GPL-2.0+
39 39
40 We use the SPDX Unique License Identifiers here; these are available 40 We use the SPDX Unique License Identifiers here; these are available
41 at [2]. 41 at [2].
42 42
43 [1] http://spdx.org/ 43 [1] http://spdx.org/
44 [2] http://spdx.org/licenses/ 44 [2] http://spdx.org/licenses/
45 45
46 Full name SPDX Identifier OSI Approved File name URI 46 Full name SPDX Identifier OSI Approved File name URI
47 ======================================================================================================================================= 47 =======================================================================================================================================
48 GNU General Public License v2.0 only GPL-2.0 Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt 48 GNU General Public License v2.0 only GPL-2.0 Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt
49 GNU General Public License v2.0 or later GPL-2.0+ Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt 49 GNU General Public License v2.0 or later GPL-2.0+ Y gpl-2.0.txt http://www.gnu.org/licenses/gpl-2.0.txt
50 GNU Library General Public License v2 or later LGPL-2.0+ Y lgpl-2.0.txt http://www.gnu.org/licenses/old-licenses/lgpl-2.0.txt 50 GNU Library General Public License v2 or later LGPL-2.0+ Y lgpl-2.0.txt http://www.gnu.org/licenses/old-licenses/lgpl-2.0.txt
51 GNU Lesser General Public License v2.1 or later LGPL-2.1+ Y lgpl-2.1.txt http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt 51 GNU Lesser General Public License v2.1 or later LGPL-2.1+ Y lgpl-2.1.txt http://www.gnu.org/licenses/old-licenses/lgpl-2.1.txt
52 eCos license version 2.0 eCos-2.0 eCos-2.0.txt http://www.gnu.org/licenses/ecos-license.html 52 eCos license version 2.0 eCos-2.0 eCos-2.0.txt http://www.gnu.org/licenses/ecos-license.html
53 BSD 2-Clause License BSD-2-Clause Y bsd-2-clause.txt http://spdx.org/licenses/BSD-2-Clause 53 BSD 2-Clause License BSD-2-Clause Y bsd-2-clause.txt http://spdx.org/licenses/BSD-2-Clause
54 BSD 3-clause "New" or "Revised" License BSD-3-Clause Y bsd-3-clause.txt http://spdx.org/licenses/BSD-3-Clause#licenseText 54 BSD 3-clause "New" or "Revised" License BSD-3-Clause Y bsd-3-clause.txt http://spdx.org/licenses/BSD-3-Clause#licenseText
55 IBM PIBS (PowerPC Initialization and ibm-pibs ibm-pibs.txt 55 IBM PIBS (PowerPC Initialization and IBM-pibs ibm-pibs.txt
56 Boot Software) license 56 Boot Software) license
57 57
arch/powerpc/cpu/ppc4xx/4xx_pci.c
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 * 3 *
4 * File Name: 405gp_pci.c 4 * File Name: 405gp_pci.c
5 * 5 *
6 * Function: Initialization code for the 405GP PCI Configuration regs. 6 * Function: Initialization code for the 405GP PCI Configuration regs.
7 * 7 *
8 * Author: Mark Game 8 * Author: Mark Game
9 * 9 *
10 * Change Activity- 10 * Change Activity-
11 * 11 *
12 * Date Description of Change BY 12 * Date Description of Change BY
13 * --------- --------------------- --- 13 * --------- --------------------- ---
14 * 09-Sep-98 Created MCG 14 * 09-Sep-98 Created MCG
15 * 02-Nov-98 Removed External arbiter selected message JWB 15 * 02-Nov-98 Removed External arbiter selected message JWB
16 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB 16 * 27-Nov-98 Zero out PTMBAR2 and disable in PTM2MS JWB
17 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG 17 * 04-Jan-99 Zero out other unused PMM and PTM regs. Change bus scan MCG
18 * from (0 to n) to (1 to n). 18 * from (0 to n) to (1 to n).
19 * 17-May-99 Port to Walnut JWB 19 * 17-May-99 Port to Walnut JWB
20 * 17-Jun-99 Updated for VGA support JWB 20 * 17-Jun-99 Updated for VGA support JWB
21 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB 21 * 21-Jun-99 Updated to allow SRAM region to be a target from PCI bus JWB
22 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG 22 * 19-Jul-99 Updated for 405GP pass 1 errata #26 (Low PCI subsequent MCG
23 * target latency timer values are not supported). 23 * target latency timer values are not supported).
24 * Should be fixed in pass 2. 24 * Should be fixed in pass 2.
25 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB 25 * 09-Sep-99 Removed use of PTM2 since the SRAM region no longer needs JWB
26 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS. 26 * to be a PCI target. Zero out PTMBAR2 and disable in PTM2MS.
27 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB 27 * 10-Dec-99 Updated PCI_Write_CFG_Reg for pass2 errata #6 JWB
28 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not 28 * 11-Jan-00 Ensure PMMxMAs disabled before setting PMMxLAs. This is not
29 * really required after a reset since PMMxMAs are already 29 * really required after a reset since PMMxMAs are already
30 * disabled but is a good practice nonetheless. JWB 30 * disabled but is a good practice nonetheless. JWB
31 * 12-Jun-01 stefan.roese@esd-electronics.com 31 * 12-Jun-01 stefan.roese@esd-electronics.com
32 * - PCI host/adapter handling reworked 32 * - PCI host/adapter handling reworked
33 * 09-Jul-01 stefan.roese@esd-electronics.com 33 * 09-Jul-01 stefan.roese@esd-electronics.com
34 * - PCI host now configures from device 0 (not 1) to max_dev, 34 * - PCI host now configures from device 0 (not 1) to max_dev,
35 * (host configures itself) 35 * (host configures itself)
36 * - On CPCI-405 pci base address and size is generated from 36 * - On CPCI-405 pci base address and size is generated from
37 * SDRAM and FLASH size (CFG regs not used anymore) 37 * SDRAM and FLASH size (CFG regs not used anymore)
38 * - Some minor changes for CPCI-405-A (adapter version) 38 * - Some minor changes for CPCI-405-A (adapter version)
39 * 14-Sep-01 stefan.roese@esd-electronics.com 39 * 14-Sep-01 stefan.roese@esd-electronics.com
40 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup 40 * - CONFIG_PCI_SCAN_SHOW added to print pci devices upon startup
41 * 28-Sep-01 stefan.roese@esd-electronics.com 41 * 28-Sep-01 stefan.roese@esd-electronics.com
42 * - Changed pci master configuration for linux compatibility 42 * - Changed pci master configuration for linux compatibility
43 * (no need for bios_fixup() anymore) 43 * (no need for bios_fixup() anymore)
44 * 26-Feb-02 stefan.roese@esd-electronics.com 44 * 26-Feb-02 stefan.roese@esd-electronics.com
45 * - Bug fixed in pci configuration (Andrew May) 45 * - Bug fixed in pci configuration (Andrew May)
46 * - Removed pci class code init for CPCI405 board 46 * - Removed pci class code init for CPCI405 board
47 * 15-May-02 stefan.roese@esd-electronics.com 47 * 15-May-02 stefan.roese@esd-electronics.com
48 * - New vga device handling 48 * - New vga device handling
49 * 29-May-02 stefan.roese@esd-electronics.com 49 * 29-May-02 stefan.roese@esd-electronics.com
50 * - PCI class code init added (if defined) 50 * - PCI class code init added (if defined)
51 *----------------------------------------------------------------------------*/ 51 *----------------------------------------------------------------------------*/
52 52
53 #include <common.h> 53 #include <common.h>
54 #include <command.h> 54 #include <command.h>
55 #include <asm/4xx_pci.h> 55 #include <asm/4xx_pci.h>
56 #include <asm/processor.h> 56 #include <asm/processor.h>
57 #include <asm/io.h> 57 #include <asm/io.h>
58 #include <pci.h> 58 #include <pci.h>
59 59
60 #ifdef CONFIG_PCI 60 #ifdef CONFIG_PCI
61 61
62 DECLARE_GLOBAL_DATA_PTR; 62 DECLARE_GLOBAL_DATA_PTR;
63 63
64 #if defined(CONFIG_405GP) || defined(CONFIG_405EP) 64 #if defined(CONFIG_405GP) || defined(CONFIG_405EP)
65 65
66 #if defined(CONFIG_PMC405) 66 #if defined(CONFIG_PMC405)
67 ushort pmc405_pci_subsys_deviceid(void); 67 ushort pmc405_pci_subsys_deviceid(void);
68 #endif 68 #endif
69 69
70 /*#define DEBUG*/ 70 /*#define DEBUG*/
71 71
72 /* 72 /*
73 * Board-specific pci initialization 73 * Board-specific pci initialization
74 * Platform code can reimplement pci_pre_init() if needed 74 * Platform code can reimplement pci_pre_init() if needed
75 */ 75 */
76 int __pci_pre_init(struct pci_controller *hose) 76 int __pci_pre_init(struct pci_controller *hose)
77 { 77 {
78 #if defined(CONFIG_405EP) 78 #if defined(CONFIG_405EP)
79 /* 79 /*
80 * Enable the internal PCI arbiter by default. 80 * Enable the internal PCI arbiter by default.
81 * 81 *
82 * On 405EP CPUs the internal arbiter can be controlled 82 * On 405EP CPUs the internal arbiter can be controlled
83 * by the I2C strapping EEPROM. If you want to do so 83 * by the I2C strapping EEPROM. If you want to do so
84 * or if you want to disable the arbiter pci_pre_init() 84 * or if you want to disable the arbiter pci_pre_init()
85 * must be reimplemented without enabling the arbiter. 85 * must be reimplemented without enabling the arbiter.
86 * The arbiter is enabled in this place because of 86 * The arbiter is enabled in this place because of
87 * compatibility reasons. 87 * compatibility reasons.
88 */ 88 */
89 mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN); 89 mtdcr(CPC0_PCI, mfdcr(CPC0_PCI) | CPC0_PCI_ARBIT_EN);
90 #endif /* CONFIG_405EP */ 90 #endif /* CONFIG_405EP */
91 91
92 return 1; 92 return 1;
93 } 93 }
94 int pci_pre_init(struct pci_controller *hose) 94 int pci_pre_init(struct pci_controller *hose)
95 __attribute__((weak, alias("__pci_pre_init"))); 95 __attribute__((weak, alias("__pci_pre_init")));
96 96
97 int __is_pci_host(struct pci_controller *hose) 97 int __is_pci_host(struct pci_controller *hose)
98 { 98 {
99 #if defined(CONFIG_405GP) 99 #if defined(CONFIG_405GP)
100 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN) 100 if (mfdcr(CPC0_PSR) & PSR_PCI_ARBIT_EN)
101 return 1; 101 return 1;
102 #elif defined (CONFIG_405EP) 102 #elif defined (CONFIG_405EP)
103 if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN) 103 if (mfdcr(CPC0_PCI) & CPC0_PCI_ARBIT_EN)
104 return 1; 104 return 1;
105 #endif 105 #endif
106 return 0; 106 return 0;
107 } 107 }
108 int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host"))); 108 int is_pci_host(struct pci_controller *hose) __attribute__((weak, alias("__is_pci_host")));
109 109
110 /*-----------------------------------------------------------------------------+ 110 /*-----------------------------------------------------------------------------+
111 * pci_init. Initializes the 405GP PCI Configuration regs. 111 * pci_init. Initializes the 405GP PCI Configuration regs.
112 *-----------------------------------------------------------------------------*/ 112 *-----------------------------------------------------------------------------*/
113 void pci_405gp_init(struct pci_controller *hose) 113 void pci_405gp_init(struct pci_controller *hose)
114 { 114 {
115 int i, reg_num = 0; 115 int i, reg_num = 0;
116 bd_t *bd = gd->bd; 116 bd_t *bd = gd->bd;
117 117
118 unsigned short temp_short; 118 unsigned short temp_short;
119 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI}; 119 unsigned long ptmpcila[2] = {CONFIG_SYS_PCI_PTM1PCI, CONFIG_SYS_PCI_PTM2PCI};
120 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE) 120 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
121 char *ptmla_str, *ptmms_str; 121 char *ptmla_str, *ptmms_str;
122 #endif 122 #endif
123 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA}; 123 unsigned long ptmla[2] = {CONFIG_SYS_PCI_PTM1LA, CONFIG_SYS_PCI_PTM2LA};
124 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS}; 124 unsigned long ptmms[2] = {CONFIG_SYS_PCI_PTM1MS, CONFIG_SYS_PCI_PTM2MS};
125 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405) 125 #if defined(CONFIG_PIP405) || defined (CONFIG_MIP405)
126 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0}; 126 unsigned long pmmla[3] = {0x80000000, 0xA0000000, 0};
127 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0}; 127 unsigned long pmmma[3] = {0xE0000001, 0xE0000001, 0};
128 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0}; 128 unsigned long pmmpcila[3] = {0x80000000, 0x00000000, 0};
129 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0}; 129 unsigned long pmmpciha[3] = {0x00000000, 0x00000000, 0};
130 #else 130 #else
131 unsigned long pmmla[3] = {0x80000000, 0,0}; 131 unsigned long pmmla[3] = {0x80000000, 0,0};
132 unsigned long pmmma[3] = {0xC0000001, 0,0}; 132 unsigned long pmmma[3] = {0xC0000001, 0,0};
133 unsigned long pmmpcila[3] = {0x80000000, 0,0}; 133 unsigned long pmmpcila[3] = {0x80000000, 0,0};
134 unsigned long pmmpciha[3] = {0x00000000, 0,0}; 134 unsigned long pmmpciha[3] = {0x00000000, 0,0};
135 #endif 135 #endif
136 #ifdef CONFIG_PCI_PNP 136 #ifdef CONFIG_PCI_PNP
137 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) 137 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
138 char *s; 138 char *s;
139 #endif 139 #endif
140 #endif 140 #endif
141 141
142 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE) 142 #if defined(CONFIG_PCI_4xx_PTM_OVERWRITE)
143 ptmla_str = getenv("ptm1la"); 143 ptmla_str = getenv("ptm1la");
144 ptmms_str = getenv("ptm1ms"); 144 ptmms_str = getenv("ptm1ms");
145 if(NULL != ptmla_str && NULL != ptmms_str ) { 145 if(NULL != ptmla_str && NULL != ptmms_str ) {
146 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16); 146 ptmla[0] = simple_strtoul (ptmla_str, NULL, 16);
147 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16); 147 ptmms[0] = simple_strtoul (ptmms_str, NULL, 16);
148 } 148 }
149 149
150 ptmla_str = getenv("ptm2la"); 150 ptmla_str = getenv("ptm2la");
151 ptmms_str = getenv("ptm2ms"); 151 ptmms_str = getenv("ptm2ms");
152 if(NULL != ptmla_str && NULL != ptmms_str ) { 152 if(NULL != ptmla_str && NULL != ptmms_str ) {
153 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16); 153 ptmla[1] = simple_strtoul (ptmla_str, NULL, 16);
154 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16); 154 ptmms[1] = simple_strtoul (ptmms_str, NULL, 16);
155 } 155 }
156 #endif 156 #endif
157 157
158 /* 158 /*
159 * Register the hose 159 * Register the hose
160 */ 160 */
161 hose->first_busno = 0; 161 hose->first_busno = 0;
162 hose->last_busno = 0xff; 162 hose->last_busno = 0xff;
163 163
164 /* ISA/PCI I/O space */ 164 /* ISA/PCI I/O space */
165 pci_set_region(hose->regions + reg_num++, 165 pci_set_region(hose->regions + reg_num++,
166 MIN_PCI_PCI_IOADDR, 166 MIN_PCI_PCI_IOADDR,
167 MIN_PLB_PCI_IOADDR, 167 MIN_PLB_PCI_IOADDR,
168 0x10000, 168 0x10000,
169 PCI_REGION_IO); 169 PCI_REGION_IO);
170 170
171 /* PCI I/O space */ 171 /* PCI I/O space */
172 pci_set_region(hose->regions + reg_num++, 172 pci_set_region(hose->regions + reg_num++,
173 0x00800000, 173 0x00800000,
174 0xe8800000, 174 0xe8800000,
175 0x03800000, 175 0x03800000,
176 PCI_REGION_IO); 176 PCI_REGION_IO);
177 177
178 reg_num = 2; 178 reg_num = 2;
179 179
180 /* Memory spaces */ 180 /* Memory spaces */
181 for (i=0; i<2; i++) 181 for (i=0; i<2; i++)
182 if (ptmms[i] & 1) 182 if (ptmms[i] & 1)
183 { 183 {
184 if (!i) hose->pci_fb = hose->regions + reg_num; 184 if (!i) hose->pci_fb = hose->regions + reg_num;
185 185
186 pci_set_region(hose->regions + reg_num++, 186 pci_set_region(hose->regions + reg_num++,
187 ptmpcila[i], ptmla[i], 187 ptmpcila[i], ptmla[i],
188 ~(ptmms[i] & 0xfffff000) + 1, 188 ~(ptmms[i] & 0xfffff000) + 1,
189 PCI_REGION_MEM | 189 PCI_REGION_MEM |
190 PCI_REGION_SYS_MEMORY); 190 PCI_REGION_SYS_MEMORY);
191 } 191 }
192 192
193 /* PCI memory spaces */ 193 /* PCI memory spaces */
194 for (i=0; i<3; i++) 194 for (i=0; i<3; i++)
195 if (pmmma[i] & 1) 195 if (pmmma[i] & 1)
196 { 196 {
197 pci_set_region(hose->regions + reg_num++, 197 pci_set_region(hose->regions + reg_num++,
198 pmmpcila[i], pmmla[i], 198 pmmpcila[i], pmmla[i],
199 ~(pmmma[i] & 0xfffff000) + 1, 199 ~(pmmma[i] & 0xfffff000) + 1,
200 PCI_REGION_MEM); 200 PCI_REGION_MEM);
201 } 201 }
202 202
203 hose->region_count = reg_num; 203 hose->region_count = reg_num;
204 204
205 pci_setup_indirect(hose, 205 pci_setup_indirect(hose,
206 PCICFGADR, 206 PCICFGADR,
207 PCICFGDATA); 207 PCICFGDATA);
208 208
209 if (hose->pci_fb) 209 if (hose->pci_fb)
210 pciauto_region_init(hose->pci_fb); 210 pciauto_region_init(hose->pci_fb);
211 211
212 /* Let board change/modify hose & do initial checks */ 212 /* Let board change/modify hose & do initial checks */
213 if (pci_pre_init(hose) == 0) { 213 if (pci_pre_init(hose) == 0) {
214 printf("PCI: Board-specific initialization failed.\n"); 214 printf("PCI: Board-specific initialization failed.\n");
215 printf("PCI: Configuration aborted.\n"); 215 printf("PCI: Configuration aborted.\n");
216 return; 216 return;
217 } 217 }
218 218
219 pci_register_hose(hose); 219 pci_register_hose(hose);
220 220
221 /*--------------------------------------------------------------------------+ 221 /*--------------------------------------------------------------------------+
222 * 405GP PCI Master configuration. 222 * 405GP PCI Master configuration.
223 * Map one 512 MB range of PLB/processor addresses to PCI memory space. 223 * Map one 512 MB range of PLB/processor addresses to PCI memory space.
224 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF 224 * PLB address 0x80000000-0xBFFFFFFF ==> PCI address 0x80000000-0xBFFFFFFF
225 * Use byte reversed out routines to handle endianess. 225 * Use byte reversed out routines to handle endianess.
226 *--------------------------------------------------------------------------*/ 226 *--------------------------------------------------------------------------*/
227 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */ 227 out32r(PMM0MA, (pmmma[0]&~0x1)); /* disable, configure PMMxLA, PMMxPCILA first */
228 out32r(PMM0LA, pmmla[0]); 228 out32r(PMM0LA, pmmla[0]);
229 out32r(PMM0PCILA, pmmpcila[0]); 229 out32r(PMM0PCILA, pmmpcila[0]);
230 out32r(PMM0PCIHA, pmmpciha[0]); 230 out32r(PMM0PCIHA, pmmpciha[0]);
231 out32r(PMM0MA, pmmma[0]); 231 out32r(PMM0MA, pmmma[0]);
232 232
233 /*--------------------------------------------------------------------------+ 233 /*--------------------------------------------------------------------------+
234 * PMM1 is not used. Initialize them to zero. 234 * PMM1 is not used. Initialize them to zero.
235 *--------------------------------------------------------------------------*/ 235 *--------------------------------------------------------------------------*/
236 out32r(PMM1MA, (pmmma[1]&~0x1)); 236 out32r(PMM1MA, (pmmma[1]&~0x1));
237 out32r(PMM1LA, pmmla[1]); 237 out32r(PMM1LA, pmmla[1]);
238 out32r(PMM1PCILA, pmmpcila[1]); 238 out32r(PMM1PCILA, pmmpcila[1]);
239 out32r(PMM1PCIHA, pmmpciha[1]); 239 out32r(PMM1PCIHA, pmmpciha[1]);
240 out32r(PMM1MA, pmmma[1]); 240 out32r(PMM1MA, pmmma[1]);
241 241
242 /*--------------------------------------------------------------------------+ 242 /*--------------------------------------------------------------------------+
243 * PMM2 is not used. Initialize them to zero. 243 * PMM2 is not used. Initialize them to zero.
244 *--------------------------------------------------------------------------*/ 244 *--------------------------------------------------------------------------*/
245 out32r(PMM2MA, (pmmma[2]&~0x1)); 245 out32r(PMM2MA, (pmmma[2]&~0x1));
246 out32r(PMM2LA, pmmla[2]); 246 out32r(PMM2LA, pmmla[2]);
247 out32r(PMM2PCILA, pmmpcila[2]); 247 out32r(PMM2PCILA, pmmpcila[2]);
248 out32r(PMM2PCIHA, pmmpciha[2]); 248 out32r(PMM2PCIHA, pmmpciha[2]);
249 out32r(PMM2MA, pmmma[2]); 249 out32r(PMM2MA, pmmma[2]);
250 250
251 /*--------------------------------------------------------------------------+ 251 /*--------------------------------------------------------------------------+
252 * 405GP PCI Target configuration. (PTM1) 252 * 405GP PCI Target configuration. (PTM1)
253 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway. 253 * Note: PTM1MS is hardwire enabled but we set the enable bit anyway.
254 *--------------------------------------------------------------------------*/ 254 *--------------------------------------------------------------------------*/
255 out32r(PTM1LA, ptmla[0]); /* insert address */ 255 out32r(PTM1LA, ptmla[0]); /* insert address */
256 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */ 256 out32r(PTM1MS, ptmms[0]); /* insert size, enable bit is 1 */
257 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]); 257 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_1, ptmpcila[0]);
258 258
259 /*--------------------------------------------------------------------------+ 259 /*--------------------------------------------------------------------------+
260 * 405GP PCI Target configuration. (PTM2) 260 * 405GP PCI Target configuration. (PTM2)
261 *--------------------------------------------------------------------------*/ 261 *--------------------------------------------------------------------------*/
262 out32r(PTM2LA, ptmla[1]); /* insert address */ 262 out32r(PTM2LA, ptmla[1]); /* insert address */
263 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]); 263 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, ptmpcila[1]);
264 264
265 if (ptmms[1] == 0) 265 if (ptmms[1] == 0)
266 { 266 {
267 out32r(PTM2MS, 0x00000001); /* set enable bit */ 267 out32r(PTM2MS, 0x00000001); /* set enable bit */
268 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000); 268 pci_write_config_dword(PCIDEVID_405GP, PCI_BASE_ADDRESS_2, 0x00000000);
269 out32r(PTM2MS, 0x00000000); /* disable */ 269 out32r(PTM2MS, 0x00000000); /* disable */
270 } 270 }
271 else 271 else
272 { 272 {
273 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */ 273 out32r(PTM2MS, ptmms[1]); /* insert size, enable bit is 1 */
274 } 274 }
275 275
276 /* 276 /*
277 * Insert Subsystem Vendor and Device ID 277 * Insert Subsystem Vendor and Device ID
278 */ 278 */
279 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID); 279 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_VENDOR_ID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
280 #ifdef CONFIG_CPCI405 280 #ifdef CONFIG_CPCI405
281 if (is_pci_host(hose)) 281 if (is_pci_host(hose))
282 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); 282 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
283 else 283 else
284 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2); 284 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID2);
285 #else 285 #else
286 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); 286 pci_write_config_word(PCIDEVID_405GP, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
287 #endif 287 #endif
288 288
289 /* 289 /*
290 * Insert Class-code 290 * Insert Class-code
291 */ 291 */
292 #ifdef CONFIG_SYS_PCI_CLASSCODE 292 #ifdef CONFIG_SYS_PCI_CLASSCODE
293 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE); 293 pci_write_config_word(PCIDEVID_405GP, PCI_CLASS_SUB_CODE, CONFIG_SYS_PCI_CLASSCODE);
294 #endif /* CONFIG_SYS_PCI_CLASSCODE */ 294 #endif /* CONFIG_SYS_PCI_CLASSCODE */
295 295
296 /*--------------------------------------------------------------------------+ 296 /*--------------------------------------------------------------------------+
297 * If PCI speed = 66MHz, set 66MHz capable bit. 297 * If PCI speed = 66MHz, set 66MHz capable bit.
298 *--------------------------------------------------------------------------*/ 298 *--------------------------------------------------------------------------*/
299 if (bd->bi_pci_busfreq >= 66000000) { 299 if (bd->bi_pci_busfreq >= 66000000) {
300 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short); 300 pci_read_config_word(PCIDEVID_405GP, PCI_STATUS, &temp_short);
301 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ)); 301 pci_write_config_word(PCIDEVID_405GP,PCI_STATUS,(temp_short|PCI_STATUS_66MHZ));
302 } 302 }
303 303
304 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER) 304 #if (CONFIG_PCI_HOST != PCI_HOST_ADAPTER)
305 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) 305 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
306 if (is_pci_host(hose) || 306 if (is_pci_host(hose) ||
307 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) 307 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
308 #endif 308 #endif
309 { 309 {
310 /*--------------------------------------------------------------------------+ 310 /*--------------------------------------------------------------------------+
311 * Write the 405GP PCI Configuration regs. 311 * Write the 405GP PCI Configuration regs.
312 * Enable 405GP to be a master on the PCI bus (PMM). 312 * Enable 405GP to be a master on the PCI bus (PMM).
313 * Enable 405GP to act as a PCI memory target (PTM). 313 * Enable 405GP to act as a PCI memory target (PTM).
314 *--------------------------------------------------------------------------*/ 314 *--------------------------------------------------------------------------*/
315 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short); 315 pci_read_config_word(PCIDEVID_405GP, PCI_COMMAND, &temp_short);
316 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short | 316 pci_write_config_word(PCIDEVID_405GP, PCI_COMMAND, temp_short |
317 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); 317 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
318 } 318 }
319 #endif 319 #endif
320 320
321 #if defined(CONFIG_405EP) 321 #if defined(CONFIG_405EP)
322 /* 322 /*
323 * on ppc405ep vendor/device id is not set 323 * on ppc405ep vendor/device id is not set
324 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!) 324 * The user manual says 0x1014 (IBM) / 0x0156 (405GP!)
325 * are the correct values. 325 * are the correct values.
326 */ 326 */
327 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM); 327 pci_write_config_word(PCIDEVID_405GP, PCI_VENDOR_ID, PCI_VENDOR_ID_IBM);
328 pci_write_config_word(PCIDEVID_405GP, 328 pci_write_config_word(PCIDEVID_405GP,
329 PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP); 329 PCI_DEVICE_ID, PCI_DEVICE_ID_IBM_405GP);
330 #endif 330 #endif
331 331
332 /* 332 /*
333 * Set HCE bit (Host Configuration Enabled) 333 * Set HCE bit (Host Configuration Enabled)
334 */ 334 */
335 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short); 335 pci_read_config_word(PCIDEVID_405GP, PCIBRDGOPT2, &temp_short);
336 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001)); 336 pci_write_config_word(PCIDEVID_405GP, PCIBRDGOPT2, (temp_short | 0x0001));
337 337
338 #ifdef CONFIG_PCI_PNP 338 #ifdef CONFIG_PCI_PNP
339 /*--------------------------------------------------------------------------+ 339 /*--------------------------------------------------------------------------+
340 * Scan the PCI bus and configure devices found. 340 * Scan the PCI bus and configure devices found.
341 *--------------------------------------------------------------------------*/ 341 *--------------------------------------------------------------------------*/
342 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO) 342 #if (CONFIG_PCI_HOST == PCI_HOST_AUTO)
343 if (is_pci_host(hose) || 343 if (is_pci_host(hose) ||
344 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0))) 344 (((s = getenv("pciscan")) != NULL) && (strcmp(s, "yes") == 0)))
345 #endif 345 #endif
346 { 346 {
347 #ifdef CONFIG_PCI_SCAN_SHOW 347 #ifdef CONFIG_PCI_SCAN_SHOW
348 printf("PCI: Bus Dev VenId DevId Class Int\n"); 348 printf("PCI: Bus Dev VenId DevId Class Int\n");
349 #endif 349 #endif
350 hose->last_busno = pci_hose_scan(hose); 350 hose->last_busno = pci_hose_scan(hose);
351 } 351 }
352 #endif /* CONFIG_PCI_PNP */ 352 #endif /* CONFIG_PCI_PNP */
353 353
354 } 354 }
355 355
356 /* 356 /*
357 * drivers/pci/pci.c skips every host bridge but the 405GP since it could 357 * drivers/pci/pci.c skips every host bridge but the 405GP since it could
358 * be set as an Adapter. 358 * be set as an Adapter.
359 * 359 *
360 * I (Andrew May) don't know what we should do here, but I don't want 360 * I (Andrew May) don't know what we should do here, but I don't want
361 * the auto setup of a PCI device disabling what is done pci_405gp_init 361 * the auto setup of a PCI device disabling what is done pci_405gp_init
362 * as has happened before. 362 * as has happened before.
363 */ 363 */
364 void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev, 364 void pci_405gp_setup_bridge(struct pci_controller *hose, pci_dev_t dev,
365 struct pci_config_table *entry) 365 struct pci_config_table *entry)
366 { 366 {
367 #ifdef DEBUG 367 #ifdef DEBUG
368 printf("405gp_setup_bridge\n"); 368 printf("405gp_setup_bridge\n");
369 #endif 369 #endif
370 } 370 }
371 371
372 /* 372 /*
373 * 373 *
374 */ 374 */
375 375
376 void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev) 376 void pci_405gp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
377 { 377 {
378 unsigned char int_line = 0xff; 378 unsigned char int_line = 0xff;
379 379
380 /* 380 /*
381 * Write pci interrupt line register (cpci405 specific) 381 * Write pci interrupt line register (cpci405 specific)
382 */ 382 */
383 switch (PCI_DEV(dev) & 0x03) 383 switch (PCI_DEV(dev) & 0x03)
384 { 384 {
385 case 0: 385 case 0:
386 int_line = 27 + 2; 386 int_line = 27 + 2;
387 break; 387 break;
388 case 1: 388 case 1:
389 int_line = 27 + 3; 389 int_line = 27 + 3;
390 break; 390 break;
391 case 2: 391 case 2:
392 int_line = 27 + 0; 392 int_line = 27 + 0;
393 break; 393 break;
394 case 3: 394 case 3:
395 int_line = 27 + 1; 395 int_line = 27 + 1;
396 break; 396 break;
397 } 397 }
398 398
399 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); 399 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
400 } 400 }
401 401
402 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev, 402 void pci_405gp_setup_vga(struct pci_controller *hose, pci_dev_t dev,
403 struct pci_config_table *entry) 403 struct pci_config_table *entry)
404 { 404 {
405 unsigned int cmdstat = 0; 405 unsigned int cmdstat = 0;
406 406
407 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io); 407 pciauto_setup_device(hose, dev, 6, hose->pci_mem, hose->pci_prefetch, hose->pci_io);
408 408
409 /* always enable io space on vga boards */ 409 /* always enable io space on vga boards */
410 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat); 410 pci_hose_read_config_dword(hose, dev, PCI_COMMAND, &cmdstat);
411 cmdstat |= PCI_COMMAND_IO; 411 cmdstat |= PCI_COMMAND_IO;
412 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat); 412 pci_hose_write_config_dword(hose, dev, PCI_COMMAND, cmdstat);
413 } 413 }
414 414
415 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3)) 415 #if !(defined(CONFIG_PIP405) || defined (CONFIG_MIP405)) && !(defined (CONFIG_SC3))
416 416
417 /* 417 /*
418 *As is these functs get called out of flash Not a horrible 418 *As is these functs get called out of flash Not a horrible
419 *thing, but something to keep in mind. (no statics?) 419 *thing, but something to keep in mind. (no statics?)
420 */ 420 */
421 static struct pci_config_table pci_405gp_config_table[] = { 421 static struct pci_config_table pci_405gp_config_table[] = {
422 /*if VendID is 0 it terminates the table search (ie Walnut)*/ 422 /*if VendID is 0 it terminates the table search (ie Walnut)*/
423 #ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID 423 #ifdef CONFIG_SYS_PCI_SUBSYS_VENDORID
424 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST, 424 {CONFIG_SYS_PCI_SUBSYS_VENDORID, PCI_ANY_ID, PCI_CLASS_BRIDGE_HOST,
425 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge}, 425 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_bridge},
426 #endif 426 #endif
427 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA, 427 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_DISPLAY_VGA,
428 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, 428 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
429 429
430 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA, 430 {PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA,
431 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga}, 431 PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, pci_405gp_setup_vga},
432 432
433 { } 433 { }
434 }; 434 };
435 435
436 static struct pci_controller hose = { 436 static struct pci_controller hose = {
437 fixup_irq: pci_405gp_fixup_irq, 437 fixup_irq: pci_405gp_fixup_irq,
438 config_table: pci_405gp_config_table, 438 config_table: pci_405gp_config_table,
439 }; 439 };
440 440
441 void pci_init_board(void) 441 void pci_init_board(void)
442 { 442 {
443 /*we want the ptrs to RAM not flash (ie don't use init list)*/ 443 /*we want the ptrs to RAM not flash (ie don't use init list)*/
444 hose.fixup_irq = pci_405gp_fixup_irq; 444 hose.fixup_irq = pci_405gp_fixup_irq;
445 hose.config_table = pci_405gp_config_table; 445 hose.config_table = pci_405gp_config_table;
446 pci_405gp_init(&hose); 446 pci_405gp_init(&hose);
447 } 447 }
448 448
449 #endif 449 #endif
450 450
451 #endif /* CONFIG_405GP */ 451 #endif /* CONFIG_405GP */
452 452
453 /*-----------------------------------------------------------------------------+ 453 /*-----------------------------------------------------------------------------+
454 * CONFIG_440 454 * CONFIG_440
455 *-----------------------------------------------------------------------------*/ 455 *-----------------------------------------------------------------------------*/
456 #if defined(CONFIG_440) 456 #if defined(CONFIG_440)
457 457
458 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT) 458 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
459 static struct pci_controller ppc440_hose = {0}; 459 static struct pci_controller ppc440_hose = {0};
460 #endif 460 #endif
461 461
462 /* 462 /*
463 * This routine is called to determine if a pci scan should be 463 * This routine is called to determine if a pci scan should be
464 * performed. With various hardware environments (especially cPCI and 464 * performed. With various hardware environments (especially cPCI and
465 * PPMC) it's insufficient to depend on the state of the arbiter enable 465 * PPMC) it's insufficient to depend on the state of the arbiter enable
466 * bit in the strap register, or generic host/adapter assumptions. 466 * bit in the strap register, or generic host/adapter assumptions.
467 * 467 *
468 * Rather than hard-code a bad assumption in the general 440 code, the 468 * Rather than hard-code a bad assumption in the general 440 code, the
469 * 440 pci code requires the board to decide at runtime. 469 * 440 pci code requires the board to decide at runtime.
470 * 470 *
471 * Return 0 for adapter mode, non-zero for host (monarch) mode. 471 * Return 0 for adapter mode, non-zero for host (monarch) mode.
472 * 472 *
473 * Weak default implementation: "Normal" boards implement the PCI 473 * Weak default implementation: "Normal" boards implement the PCI
474 * host functionality. This can be overridden for PCI adapter boards. 474 * host functionality. This can be overridden for PCI adapter boards.
475 */ 475 */
476 int __is_pci_host(struct pci_controller *hose) 476 int __is_pci_host(struct pci_controller *hose)
477 { 477 {
478 return 1; 478 return 1;
479 } 479 }
480 int is_pci_host(struct pci_controller *hose) 480 int is_pci_host(struct pci_controller *hose)
481 __attribute__((weak, alias("__is_pci_host"))); 481 __attribute__((weak, alias("__is_pci_host")));
482 482
483 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ 483 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
484 defined(CONFIG_440GR) || defined(CONFIG_440GRX) 484 defined(CONFIG_440GR) || defined(CONFIG_440GRX)
485 485
486 #if defined(CONFIG_SYS_PCI_TARGET_INIT) 486 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
487 /* 487 /*
488 * pci_target_init 488 * pci_target_init
489 * 489 *
490 * The bootstrap configuration provides default settings for the pci 490 * The bootstrap configuration provides default settings for the pci
491 * inbound map (PIM). But the bootstrap config choices are limited and 491 * inbound map (PIM). But the bootstrap config choices are limited and
492 * may not be sufficient for a given board. 492 * may not be sufficient for a given board.
493 */ 493 */
494 void __pci_target_init(struct pci_controller *hose) 494 void __pci_target_init(struct pci_controller *hose)
495 { 495 {
496 /* 496 /*
497 * Set up Direct MMIO registers 497 * Set up Direct MMIO registers
498 */ 498 */
499 499
500 /* 500 /*
501 * PowerPC440 EP PCI Master configuration. 501 * PowerPC440 EP PCI Master configuration.
502 * Map one 1Gig range of PLB/processor addresses to PCI memory space. 502 * Map one 1Gig range of PLB/processor addresses to PCI memory space.
503 * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF 503 * PLB address 0xA0000000-0xDFFFFFFF ==> PCI address 0xA0000000-0xDFFFFFFF
504 * Use byte reversed out routines to handle endianess. 504 * Use byte reversed out routines to handle endianess.
505 * Make this region non-prefetchable. 505 * Make this region non-prefetchable.
506 */ 506 */
507 /* PMM0 Mask/Attribute - disabled b4 setting */ 507 /* PMM0 Mask/Attribute - disabled b4 setting */
508 out_le32((void *)PCIL0_PMM0MA, 0x00000000); 508 out_le32((void *)PCIL0_PMM0MA, 0x00000000);
509 /* PMM0 Local Address */ 509 /* PMM0 Local Address */
510 out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE); 510 out_le32((void *)PCIL0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);
511 /* PMM0 PCI Low Address */ 511 /* PMM0 PCI Low Address */
512 out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); 512 out_le32((void *)PCIL0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
513 /* PMM0 PCI High Address */ 513 /* PMM0 PCI High Address */
514 out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000); 514 out_le32((void *)PCIL0_PMM0PCIHA, 0x00000000);
515 /* 512M + No prefetching, and enable region */ 515 /* 512M + No prefetching, and enable region */
516 out_le32((void *)PCIL0_PMM0MA, 0xE0000001); 516 out_le32((void *)PCIL0_PMM0MA, 0xE0000001);
517 517
518 /* PMM1 Mask/Attribute - disabled b4 setting */ 518 /* PMM1 Mask/Attribute - disabled b4 setting */
519 out_le32((void *)PCIL0_PMM1MA, 0x00000000); 519 out_le32((void *)PCIL0_PMM1MA, 0x00000000);
520 /* PMM1 Local Address */ 520 /* PMM1 Local Address */
521 out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); 521 out_le32((void *)PCIL0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);
522 /* PMM1 PCI Low Address */ 522 /* PMM1 PCI Low Address */
523 out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); 523 out_le32((void *)PCIL0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
524 /* PMM1 PCI High Address */ 524 /* PMM1 PCI High Address */
525 out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000); 525 out_le32((void *)PCIL0_PMM1PCIHA, 0x00000000);
526 /* 512M + No prefetching, and enable region */ 526 /* 512M + No prefetching, and enable region */
527 out_le32((void *)PCIL0_PMM1MA, 0xE0000001); 527 out_le32((void *)PCIL0_PMM1MA, 0xE0000001);
528 528
529 out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */ 529 out_le32((void *)PCIL0_PTM1MS, 0x00000001); /* Memory Size/Attribute */
530 out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */ 530 out_le32((void *)PCIL0_PTM1LA, 0); /* Local Addr. Reg */
531 out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */ 531 out_le32((void *)PCIL0_PTM2MS, 0); /* Memory Size/Attribute */
532 out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */ 532 out_le32((void *)PCIL0_PTM2LA, 0); /* Local Addr. Reg */
533 533
534 /* 534 /*
535 * Set up Configuration registers 535 * Set up Configuration registers
536 */ 536 */
537 537
538 /* Program the board's subsystem id/vendor id */ 538 /* Program the board's subsystem id/vendor id */
539 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID, 539 pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
540 CONFIG_SYS_PCI_SUBSYS_VENDORID); 540 CONFIG_SYS_PCI_SUBSYS_VENDORID);
541 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID); 541 pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
542 542
543 /* Configure command register as bus master */ 543 /* Configure command register as bus master */
544 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER); 544 pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
545 545
546 /* 240nS PCI clock */ 546 /* 240nS PCI clock */
547 pci_write_config_word(0, PCI_LATENCY_TIMER, 1); 547 pci_write_config_word(0, PCI_LATENCY_TIMER, 1);
548 548
549 /* No error reporting */ 549 /* No error reporting */
550 pci_write_config_word(0, PCI_ERREN, 0); 550 pci_write_config_word(0, PCI_ERREN, 0);
551 551
552 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101); 552 pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
553 } 553 }
554 #endif /* CONFIG_SYS_PCI_TARGET_INIT */ 554 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
555 555
556 /* 556 /*
557 * pci_pre_init 557 * pci_pre_init
558 * 558 *
559 * This routine is called just prior to registering the hose and gives 559 * This routine is called just prior to registering the hose and gives
560 * the board the opportunity to check things. Returning a value of zero 560 * the board the opportunity to check things. Returning a value of zero
561 * indicates that things are bad & PCI initialization should be aborted. 561 * indicates that things are bad & PCI initialization should be aborted.
562 * 562 *
563 * Different boards may wish to customize the pci controller structure 563 * Different boards may wish to customize the pci controller structure
564 * (add regions, override default access routines, etc) or perform 564 * (add regions, override default access routines, etc) or perform
565 * certain pre-initialization actions. 565 * certain pre-initialization actions.
566 * 566 *
567 */ 567 */
568 int __pci_pre_init(struct pci_controller *hose) 568 int __pci_pre_init(struct pci_controller *hose)
569 { 569 {
570 u32 reg; 570 u32 reg;
571 571
572 /* 572 /*
573 * Set priority for all PLB3 devices to 0. 573 * Set priority for all PLB3 devices to 0.
574 * Set PLB3 arbiter to fair mode. 574 * Set PLB3 arbiter to fair mode.
575 */ 575 */
576 mfsdr(SDR0_AMP1, reg); 576 mfsdr(SDR0_AMP1, reg);
577 mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00); 577 mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00);
578 reg = mfdcr(PLB3A0_ACR); 578 reg = mfdcr(PLB3A0_ACR);
579 mtdcr(PLB3A0_ACR, reg | 0x80000000); 579 mtdcr(PLB3A0_ACR, reg | 0x80000000);
580 580
581 /* 581 /*
582 * Set priority for all PLB4 devices to 0. 582 * Set priority for all PLB4 devices to 0.
583 */ 583 */
584 mfsdr(SDR0_AMP0, reg); 584 mfsdr(SDR0_AMP0, reg);
585 mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00); 585 mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00);
586 reg = mfdcr(PLB4A0_ACR) | 0xa0000000; 586 reg = mfdcr(PLB4A0_ACR) | 0xa0000000;
587 mtdcr(PLB4A0_ACR, reg); 587 mtdcr(PLB4A0_ACR, reg);
588 588
589 /* 589 /*
590 * Set Nebula PLB4 arbiter to fair mode. 590 * Set Nebula PLB4 arbiter to fair mode.
591 */ 591 */
592 /* Segment0 */ 592 /* Segment0 */
593 reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR; 593 reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
594 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED; 594 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
595 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP; 595 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
596 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP; 596 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
597 mtdcr(PLB4A0_ACR, reg); 597 mtdcr(PLB4A0_ACR, reg);
598 598
599 /* Segment1 */ 599 /* Segment1 */
600 reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR; 600 reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR;
601 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED; 601 reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED;
602 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP; 602 reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP;
603 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP; 603 reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP;
604 mtdcr(PLB4A1_ACR, reg); 604 mtdcr(PLB4A1_ACR, reg);
605 605
606 #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ) 606 #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ)
607 hose->fixup_irq = board_pci_fixup_irq; 607 hose->fixup_irq = board_pci_fixup_irq;
608 #endif 608 #endif
609 609
610 return 1; 610 return 1;
611 } 611 }
612 612
613 #else /* defined(CONFIG_440EP) ... */ 613 #else /* defined(CONFIG_440EP) ... */
614 614
615 #if defined(CONFIG_SYS_PCI_TARGET_INIT) 615 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
616 void __pci_target_init(struct pci_controller * hose) 616 void __pci_target_init(struct pci_controller * hose)
617 { 617 {
618 /* 618 /*
619 * Disable everything 619 * Disable everything
620 */ 620 */
621 out_le32((void *)PCIL0_PIM0SA, 0); /* disable */ 621 out_le32((void *)PCIL0_PIM0SA, 0); /* disable */
622 out_le32((void *)PCIL0_PIM1SA, 0); /* disable */ 622 out_le32((void *)PCIL0_PIM1SA, 0); /* disable */
623 out_le32((void *)PCIL0_PIM2SA, 0); /* disable */ 623 out_le32((void *)PCIL0_PIM2SA, 0); /* disable */
624 out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */ 624 out_le32((void *)PCIL0_EROMBA, 0); /* disable expansion rom */
625 625
626 /* 626 /*
627 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 627 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
628 * strapping options do not support sizes such as 128/256 MB. 628 * strapping options do not support sizes such as 128/256 MB.
629 */ 629 */
630 out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE); 630 out_le32((void *)PCIL0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
631 out_le32((void *)PCIL0_PIM0LAH, 0); 631 out_le32((void *)PCIL0_PIM0LAH, 0);
632 out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1); 632 out_le32((void *)PCIL0_PIM0SA, ~(gd->ram_size - 1) | 1);
633 out_le32((void *)PCIL0_BAR0, 0); 633 out_le32((void *)PCIL0_BAR0, 0);
634 634
635 /* 635 /*
636 * Program the board's subsystem id/vendor id 636 * Program the board's subsystem id/vendor id
637 */ 637 */
638 out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID); 638 out_le16((void *)PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
639 out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID); 639 out_le16((void *)PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
640 640
641 out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) | 641 out_le16((void *)PCIL0_CMD, in_le16((void *)PCIL0_CMD) |
642 PCI_COMMAND_MEMORY); 642 PCI_COMMAND_MEMORY);
643 } 643 }
644 #endif /* CONFIG_SYS_PCI_TARGET_INIT */ 644 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
645 645
646 int __pci_pre_init(struct pci_controller *hose) 646 int __pci_pre_init(struct pci_controller *hose)
647 { 647 {
648 /* 648 /*
649 * This board is always configured as the host & requires the 649 * This board is always configured as the host & requires the
650 * PCI arbiter to be enabled. 650 * PCI arbiter to be enabled.
651 */ 651 */
652 if (!pci_arbiter_enabled()) { 652 if (!pci_arbiter_enabled()) {
653 printf("PCI: PCI Arbiter disabled!\n"); 653 printf("PCI: PCI Arbiter disabled!\n");
654 return 0; 654 return 0;
655 } 655 }
656 656
657 return 1; 657 return 1;
658 } 658 }
659 659
660 #endif /* defined(CONFIG_440EP) ... */ 660 #endif /* defined(CONFIG_440EP) ... */
661 661
662 #if defined(CONFIG_SYS_PCI_TARGET_INIT) 662 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
663 void pci_target_init(struct pci_controller * hose) 663 void pci_target_init(struct pci_controller * hose)
664 __attribute__((weak, alias("__pci_target_init"))); 664 __attribute__((weak, alias("__pci_target_init")));
665 #endif /* CONFIG_SYS_PCI_TARGET_INIT */ 665 #endif /* CONFIG_SYS_PCI_TARGET_INIT */
666 666
667 int pci_pre_init(struct pci_controller *hose) 667 int pci_pre_init(struct pci_controller *hose)
668 __attribute__((weak, alias("__pci_pre_init"))); 668 __attribute__((weak, alias("__pci_pre_init")));
669 669
670 #if defined(CONFIG_SYS_PCI_MASTER_INIT) 670 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
671 void __pci_master_init(struct pci_controller *hose) 671 void __pci_master_init(struct pci_controller *hose)
672 { 672 {
673 u16 reg; 673 u16 reg;
674 674
675 /* 675 /*
676 * Write the PowerPC440 EP PCI Configuration regs. 676 * Write the PowerPC440 EP PCI Configuration regs.
677 * Enable PowerPC440 EP to be a master on the PCI bus (PMM). 677 * Enable PowerPC440 EP to be a master on the PCI bus (PMM).
678 * Enable PowerPC440 EP to act as a PCI memory target (PTM). 678 * Enable PowerPC440 EP to act as a PCI memory target (PTM).
679 */ 679 */
680 pci_read_config_word(0, PCI_COMMAND, &reg); 680 pci_read_config_word(0, PCI_COMMAND, &reg);
681 pci_write_config_word(0, PCI_COMMAND, reg | 681 pci_write_config_word(0, PCI_COMMAND, reg |
682 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); 682 PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
683 } 683 }
684 void pci_master_init(struct pci_controller *hose) 684 void pci_master_init(struct pci_controller *hose)
685 __attribute__((weak, alias("__pci_master_init"))); 685 __attribute__((weak, alias("__pci_master_init")));
686 #endif /* CONFIG_SYS_PCI_MASTER_INIT */ 686 #endif /* CONFIG_SYS_PCI_MASTER_INIT */
687 687
688 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT) 688 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
689 static int pci_440_init (struct pci_controller *hose) 689 static int pci_440_init (struct pci_controller *hose)
690 { 690 {
691 int reg_num = 0; 691 int reg_num = 0;
692 692
693 #ifndef CONFIG_DISABLE_PISE_TEST 693 #ifndef CONFIG_DISABLE_PISE_TEST
694 /*--------------------------------------------------------------------------+ 694 /*--------------------------------------------------------------------------+
695 * The PCI initialization sequence enable bit must be set ... if not abort 695 * The PCI initialization sequence enable bit must be set ... if not abort
696 * pci setup since updating the bit requires chip reset. 696 * pci setup since updating the bit requires chip reset.
697 *--------------------------------------------------------------------------*/ 697 *--------------------------------------------------------------------------*/
698 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) 698 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE)
699 unsigned long strap; 699 unsigned long strap;
700 700
701 mfsdr(SDR0_SDSTP1,strap); 701 mfsdr(SDR0_SDSTP1,strap);
702 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) { 702 if ((strap & SDR0_SDSTP1_PISE_MASK) == 0) {
703 printf("PCI: SDR0_STRP1[PISE] not set.\n"); 703 printf("PCI: SDR0_STRP1[PISE] not set.\n");
704 printf("PCI: Configuration aborted.\n"); 704 printf("PCI: Configuration aborted.\n");
705 return -1; 705 return -1;
706 } 706 }
707 #elif defined(CONFIG_440GP) 707 #elif defined(CONFIG_440GP)
708 unsigned long strap; 708 unsigned long strap;
709 709
710 strap = mfdcr(CPC0_STRP1); 710 strap = mfdcr(CPC0_STRP1);
711 if ((strap & CPC0_STRP1_PISE_MASK) == 0) { 711 if ((strap & CPC0_STRP1_PISE_MASK) == 0) {
712 printf("PCI: CPC0_STRP1[PISE] not set.\n"); 712 printf("PCI: CPC0_STRP1[PISE] not set.\n");
713 printf("PCI: Configuration aborted.\n"); 713 printf("PCI: Configuration aborted.\n");
714 return -1; 714 return -1;
715 } 715 }
716 #endif 716 #endif
717 #endif /* CONFIG_DISABLE_PISE_TEST */ 717 #endif /* CONFIG_DISABLE_PISE_TEST */
718 718
719 /*--------------------------------------------------------------------------+ 719 /*--------------------------------------------------------------------------+
720 * PCI controller init 720 * PCI controller init
721 *--------------------------------------------------------------------------*/ 721 *--------------------------------------------------------------------------*/
722 hose->first_busno = 0; 722 hose->first_busno = 0;
723 hose->last_busno = 0; 723 hose->last_busno = 0;
724 724
725 /* PCI I/O space */ 725 /* PCI I/O space */
726 pci_set_region(hose->regions + reg_num++, 726 pci_set_region(hose->regions + reg_num++,
727 0x00000000, 727 0x00000000,
728 PCIL0_IOBASE, 728 PCIL0_IOBASE,
729 0x10000, 729 0x10000,
730 PCI_REGION_IO); 730 PCI_REGION_IO);
731 731
732 /* PCI memory space */ 732 /* PCI memory space */
733 pci_set_region(hose->regions + reg_num++, 733 pci_set_region(hose->regions + reg_num++,
734 CONFIG_SYS_PCI_TARGBASE, 734 CONFIG_SYS_PCI_TARGBASE,
735 CONFIG_SYS_PCI_MEMBASE, 735 CONFIG_SYS_PCI_MEMBASE,
736 #ifdef CONFIG_SYS_PCI_MEMSIZE 736 #ifdef CONFIG_SYS_PCI_MEMSIZE
737 CONFIG_SYS_PCI_MEMSIZE, 737 CONFIG_SYS_PCI_MEMSIZE,
738 #else 738 #else
739 0x10000000, 739 0x10000000,
740 #endif 740 #endif
741 PCI_REGION_MEM ); 741 PCI_REGION_MEM );
742 742
743 #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \ 743 #if defined(CONFIG_PCI_SYS_MEM_BUS) && defined(CONFIG_PCI_SYS_MEM_PHYS) && \
744 defined(CONFIG_PCI_SYS_MEM_SIZE) 744 defined(CONFIG_PCI_SYS_MEM_SIZE)
745 /* System memory space */ 745 /* System memory space */
746 pci_set_region(hose->regions + reg_num++, 746 pci_set_region(hose->regions + reg_num++,
747 CONFIG_PCI_SYS_MEM_BUS, 747 CONFIG_PCI_SYS_MEM_BUS,
748 CONFIG_PCI_SYS_MEM_PHYS, 748 CONFIG_PCI_SYS_MEM_PHYS,
749 CONFIG_PCI_SYS_MEM_SIZE, 749 CONFIG_PCI_SYS_MEM_SIZE,
750 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY ); 750 PCI_REGION_MEM | PCI_REGION_SYS_MEMORY );
751 #endif 751 #endif
752 752
753 hose->region_count = reg_num; 753 hose->region_count = reg_num;
754 754
755 pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA); 755 pci_setup_indirect(hose, PCIL0_CFGADR, PCIL0_CFGDATA);
756 756
757 /* Let board change/modify hose & do initial checks */ 757 /* Let board change/modify hose & do initial checks */
758 if (pci_pre_init(hose) == 0) { 758 if (pci_pre_init(hose) == 0) {
759 printf("PCI: Board-specific initialization failed.\n"); 759 printf("PCI: Board-specific initialization failed.\n");
760 printf("PCI: Configuration aborted.\n"); 760 printf("PCI: Configuration aborted.\n");
761 return -1; 761 return -1;
762 } 762 }
763 763
764 pci_register_hose( hose ); 764 pci_register_hose( hose );
765 765
766 /*--------------------------------------------------------------------------+ 766 /*--------------------------------------------------------------------------+
767 * PCI target init 767 * PCI target init
768 *--------------------------------------------------------------------------*/ 768 *--------------------------------------------------------------------------*/
769 #if defined(CONFIG_SYS_PCI_TARGET_INIT) 769 #if defined(CONFIG_SYS_PCI_TARGET_INIT)
770 pci_target_init(hose); /* Let board setup pci target */ 770 pci_target_init(hose); /* Let board setup pci target */
771 #else 771 #else
772 out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID ); 772 out16r( PCIL0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
773 out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID ); 773 out16r( PCIL0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_ID );
774 out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */ 774 out16r( PCIL0_CLS, 0x00060000 ); /* Bridge, host bridge */
775 #endif 775 #endif
776 776
777 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ 777 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
778 defined(CONFIG_460EX) || defined(CONFIG_460GT) 778 defined(CONFIG_460EX) || defined(CONFIG_460GT)
779 out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ 779 out32r( PCIL0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */
780 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ 780 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */
781 #elif defined(PCIL0_BRDGOPT1) 781 #elif defined(PCIL0_BRDGOPT1)
782 out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */ 782 out32r( PCIL0_BRDGOPT1, 0x10000060 ); /* PLB Rq pri highest */
783 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */ 783 out32r( PCIL0_BRDGOPT2, in32(PCIL0_BRDGOPT2) | 1 ); /* Enable host config */
784 #endif 784 #endif
785 785
786 /*--------------------------------------------------------------------------+ 786 /*--------------------------------------------------------------------------+
787 * PCI master init: default is one 256MB region for PCI memory: 787 * PCI master init: default is one 256MB region for PCI memory:
788 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE 788 * 0x3_00000000 - 0x3_0FFFFFFF ==> CONFIG_SYS_PCI_MEMBASE
789 *--------------------------------------------------------------------------*/ 789 *--------------------------------------------------------------------------*/
790 #if defined(CONFIG_SYS_PCI_MASTER_INIT) 790 #if defined(CONFIG_SYS_PCI_MASTER_INIT)
791 pci_master_init(hose); /* Let board setup pci master */ 791 pci_master_init(hose); /* Let board setup pci master */
792 #else 792 #else
793 out32r( PCIL0_POM0SA, 0 ); /* disable */ 793 out32r( PCIL0_POM0SA, 0 ); /* disable */
794 out32r( PCIL0_POM1SA, 0 ); /* disable */ 794 out32r( PCIL0_POM1SA, 0 ); /* disable */
795 out32r( PCIL0_POM2SA, 0 ); /* disable */ 795 out32r( PCIL0_POM2SA, 0 ); /* disable */
796 #if defined(CONFIG_440SPE) 796 #if defined(CONFIG_440SPE)
797 out32r( PCIL0_POM0LAL, 0x10000000 ); 797 out32r( PCIL0_POM0LAL, 0x10000000 );
798 out32r( PCIL0_POM0LAH, 0x0000000c ); 798 out32r( PCIL0_POM0LAH, 0x0000000c );
799 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) 799 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
800 out32r( PCIL0_POM0LAL, 0x20000000 ); 800 out32r( PCIL0_POM0LAL, 0x20000000 );
801 out32r( PCIL0_POM0LAH, 0x0000000c ); 801 out32r( PCIL0_POM0LAH, 0x0000000c );
802 #else 802 #else
803 out32r( PCIL0_POM0LAL, 0x00000000 ); 803 out32r( PCIL0_POM0LAL, 0x00000000 );
804 out32r( PCIL0_POM0LAH, 0x00000003 ); 804 out32r( PCIL0_POM0LAH, 0x00000003 );
805 #endif 805 #endif
806 out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE ); 806 out32r( PCIL0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE );
807 out32r( PCIL0_POM0PCIAH, 0x00000000 ); 807 out32r( PCIL0_POM0PCIAH, 0x00000000 );
808 out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */ 808 out32r( PCIL0_POM0SA, 0xf0000001 ); /* 256MB, enabled */
809 out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 ); 809 out32r( PCIL0_STS, in32r( PCIL0_STS ) & ~0x0000fff8 );
810 #endif 810 #endif
811 811
812 /*--------------------------------------------------------------------------+ 812 /*--------------------------------------------------------------------------+
813 * PCI host configuration -- we don't make any assumptions here ... the 813 * PCI host configuration -- we don't make any assumptions here ... the
814 * _board_must_indicate_ what to do -- there's just too many runtime 814 * _board_must_indicate_ what to do -- there's just too many runtime
815 * scenarios in environments like cPCI, PPMC, etc. to make a determination 815 * scenarios in environments like cPCI, PPMC, etc. to make a determination
816 * based on hard-coded values or state of arbiter enable. 816 * based on hard-coded values or state of arbiter enable.
817 *--------------------------------------------------------------------------*/ 817 *--------------------------------------------------------------------------*/
818 if (is_pci_host(hose)) { 818 if (is_pci_host(hose)) {
819 #ifdef CONFIG_PCI_SCAN_SHOW 819 #ifdef CONFIG_PCI_SCAN_SHOW
820 printf("PCI: Bus Dev VenId DevId Class Int\n"); 820 printf("PCI: Bus Dev VenId DevId Class Int\n");
821 #endif 821 #endif
822 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ 822 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \
823 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) 823 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX)
824 out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER); 824 out16r( PCIL0_CMD, in16r( PCIL0_CMD ) | PCI_COMMAND_MASTER);
825 #endif 825 #endif
826 hose->last_busno = pci_hose_scan(hose); 826 hose->last_busno = pci_hose_scan(hose);
827 } 827 }
828 return hose->last_busno; 828 return hose->last_busno;
829 } 829 }
830 #endif 830 #endif
831 831
832 void pci_init_board(void) 832 void pci_init_board(void)
833 { 833 {
834 int busno = 0; 834 int busno = 0;
835 835
836 /* 836 /*
837 * Only init PCI when either master or target functionality 837 * Only init PCI when either master or target functionality
838 * is selected. 838 * is selected.
839 */ 839 */
840 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT) 840 #if defined(CONFIG_SYS_PCI_MASTER_INIT) || defined(CONFIG_SYS_PCI_TARGET_INIT)
841 busno = pci_440_init(&ppc440_hose); 841 busno = pci_440_init(&ppc440_hose);
842 if (busno < 0) 842 if (busno < 0)
843 return; 843 return;
844 #endif 844 #endif
845 #if (defined(CONFIG_440SPE) || \ 845 #if (defined(CONFIG_440SPE) || \
846 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \ 846 defined(CONFIG_460EX) || defined(CONFIG_460GT)) && \
847 !defined(CONFIG_PCI_DISABLE_PCIE) 847 !defined(CONFIG_PCI_DISABLE_PCIE)
848 pcie_setup_hoses(busno + 1); 848 pcie_setup_hoses(busno + 1);
849 #endif 849 #endif
850 } 850 }
851 851
852 #endif /* CONFIG_440 */ 852 #endif /* CONFIG_440 */
853 853
854 #if defined(CONFIG_405EX) 854 #if defined(CONFIG_405EX)
855 void pci_init_board(void) 855 void pci_init_board(void)
856 { 856 {
857 #ifdef CONFIG_PCI_SCAN_SHOW 857 #ifdef CONFIG_PCI_SCAN_SHOW
858 printf("PCI: Bus Dev VenId DevId Class Int\n"); 858 printf("PCI: Bus Dev VenId DevId Class Int\n");
859 #endif 859 #endif
860 pcie_setup_hoses(0); 860 pcie_setup_hoses(0);
861 } 861 }
862 #endif /* CONFIG_405EX */ 862 #endif /* CONFIG_405EX */
863 863
864 #endif /* CONFIG_PCI */ 864 #endif /* CONFIG_PCI */
865 865
arch/powerpc/cpu/ppc4xx/4xx_uart.c
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * (C) Copyright 2000-2006 2 * (C) Copyright 2000-2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 * 4 *
5 * (C) Copyright 2010 5 * (C) Copyright 2010
6 * Stefan Roese, DENX Software Engineering, sr@denx.de. 6 * Stefan Roese, DENX Software Engineering, sr@denx.de.
7 * 7 *
8 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 8 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <commproc.h> 12 #include <commproc.h>
13 #include <asm/processor.h> 13 #include <asm/processor.h>
14 #include <asm/io.h> 14 #include <asm/io.h>
15 #include <watchdog.h> 15 #include <watchdog.h>
16 #include <asm/ppc4xx.h> 16 #include <asm/ppc4xx.h>
17 17
18 DECLARE_GLOBAL_DATA_PTR; 18 DECLARE_GLOBAL_DATA_PTR;
19 19
20 #if defined(CONFIG_405GP) || \ 20 #if defined(CONFIG_405GP) || \
21 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ 21 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
22 defined(CONFIG_405EX) || defined(CONFIG_440) 22 defined(CONFIG_405EX) || defined(CONFIG_440)
23 23
24 #if defined(CONFIG_440) 24 #if defined(CONFIG_440)
25 25
26 #if defined(CONFIG_440GP) 26 #if defined(CONFIG_440GP)
27 #define CR0_MASK 0x3fff0000 27 #define CR0_MASK 0x3fff0000
28 #define CR0_EXTCLK_ENA 0x00600000 28 #define CR0_EXTCLK_ENA 0x00600000
29 #define CR0_UDIV_POS 16 29 #define CR0_UDIV_POS 16
30 #define UDIV_SUBTRACT 1 30 #define UDIV_SUBTRACT 1
31 #define UART0_SDR CPC0_CR0 31 #define UART0_SDR CPC0_CR0
32 #define MFREG(a, d) d = mfdcr(a) 32 #define MFREG(a, d) d = mfdcr(a)
33 #define MTREG(a, d) mtdcr(a, d) 33 #define MTREG(a, d) mtdcr(a, d)
34 #else /* #if defined(CONFIG_440GP) */ 34 #else /* #if defined(CONFIG_440GP) */
35 /* all other 440 PPC's access clock divider via sdr register */ 35 /* all other 440 PPC's access clock divider via sdr register */
36 #define CR0_MASK 0xdfffffff 36 #define CR0_MASK 0xdfffffff
37 #define CR0_EXTCLK_ENA 0x00800000 37 #define CR0_EXTCLK_ENA 0x00800000
38 #define CR0_UDIV_POS 0 38 #define CR0_UDIV_POS 0
39 #define UDIV_SUBTRACT 0 39 #define UDIV_SUBTRACT 0
40 #define UART0_SDR SDR0_UART0 40 #define UART0_SDR SDR0_UART0
41 #define UART1_SDR SDR0_UART1 41 #define UART1_SDR SDR0_UART1
42 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ 42 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
43 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ 43 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
44 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ 44 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
45 defined(CONFIG_460EX) || defined(CONFIG_460GT) 45 defined(CONFIG_460EX) || defined(CONFIG_460GT)
46 #define UART2_SDR SDR0_UART2 46 #define UART2_SDR SDR0_UART2
47 #endif 47 #endif
48 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ 48 #if defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \
49 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ 49 defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \
50 defined(CONFIG_460EX) || defined(CONFIG_460GT) 50 defined(CONFIG_460EX) || defined(CONFIG_460GT)
51 #define UART3_SDR SDR0_UART3 51 #define UART3_SDR SDR0_UART3
52 #endif 52 #endif
53 #define MFREG(a, d) mfsdr(a, d) 53 #define MFREG(a, d) mfsdr(a, d)
54 #define MTREG(a, d) mtsdr(a, d) 54 #define MTREG(a, d) mtsdr(a, d)
55 #endif /* #if defined(CONFIG_440GP) */ 55 #endif /* #if defined(CONFIG_440GP) */
56 #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) 56 #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ)
57 #define UCR0_MASK 0x0000007f 57 #define UCR0_MASK 0x0000007f
58 #define UCR1_MASK 0x00007f00 58 #define UCR1_MASK 0x00007f00
59 #define UCR0_UDIV_POS 0 59 #define UCR0_UDIV_POS 0
60 #define UCR1_UDIV_POS 8 60 #define UCR1_UDIV_POS 8
61 #define UDIV_MAX 127 61 #define UDIV_MAX 127
62 #elif defined(CONFIG_405EX) 62 #elif defined(CONFIG_405EX)
63 #define MFREG(a, d) mfsdr(a, d) 63 #define MFREG(a, d) mfsdr(a, d)
64 #define MTREG(a, d) mtsdr(a, d) 64 #define MTREG(a, d) mtsdr(a, d)
65 #define CR0_MASK 0x000000ff 65 #define CR0_MASK 0x000000ff
66 #define CR0_EXTCLK_ENA 0x00800000 66 #define CR0_EXTCLK_ENA 0x00800000
67 #define CR0_UDIV_POS 0 67 #define CR0_UDIV_POS 0
68 #define UDIV_SUBTRACT 0 68 #define UDIV_SUBTRACT 0
69 #define UART0_SDR SDR0_UART0 69 #define UART0_SDR SDR0_UART0
70 #define UART1_SDR SDR0_UART1 70 #define UART1_SDR SDR0_UART1
71 #else /* CONFIG_405GP */ 71 #else /* CONFIG_405GP */
72 #define CR0_MASK 0x00001fff 72 #define CR0_MASK 0x00001fff
73 #define CR0_EXTCLK_ENA 0x000000c0 73 #define CR0_EXTCLK_ENA 0x000000c0
74 #define CR0_UDIV_POS 1 74 #define CR0_UDIV_POS 1
75 #define UDIV_MAX 32 75 #define UDIV_MAX 32
76 #endif 76 #endif
77 77
78 #if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK) 78 #if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
79 #error "External serial clock not supported on AMCC PPC405EP!" 79 #error "External serial clock not supported on AMCC PPC405EP!"
80 #endif 80 #endif
81 81
82 #if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \ 82 #if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \
83 defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) 83 defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
84 /* 84 /*
85 * For some SoC's, the cpu clock is on divider chain A, UART on 85 * For some SoC's, the cpu clock is on divider chain A, UART on
86 * divider chain B ... so cpu clock is irrelevant. Get the 86 * divider chain B ... so cpu clock is irrelevant. Get the
87 * "optimized" values that are subject to the 1/2 opb clock 87 * "optimized" values that are subject to the 1/2 opb clock
88 * constraint. 88 * constraint.
89 */ 89 */
90 static u16 serial_bdiv(int baudrate, u32 *udiv) 90 static u16 serial_bdiv(int baudrate, u32 *udiv)
91 { 91 {
92 sys_info_t sysinfo; 92 sys_info_t sysinfo;
93 u32 div; /* total divisor udiv * bdiv */ 93 u32 div; /* total divisor udiv * bdiv */
94 u32 umin; /* minimum udiv */ 94 u32 umin; /* minimum udiv */
95 u16 diff; /* smallest diff */ 95 u16 diff; /* smallest diff */
96 u16 idiff; /* current diff */ 96 u16 idiff; /* current diff */
97 u16 ibdiv; /* current bdiv */ 97 u16 ibdiv; /* current bdiv */
98 u32 i; 98 u32 i;
99 u32 est; /* current estimate */ 99 u32 est; /* current estimate */
100 u32 max; 100 u32 max;
101 #if defined(CONFIG_405EZ) 101 #if defined(CONFIG_405EZ)
102 u32 cpr_pllc; 102 u32 cpr_pllc;
103 u32 plloutb; 103 u32 plloutb;
104 u32 reg; 104 u32 reg;
105 #endif 105 #endif
106 106
107 get_sys_info(&sysinfo); 107 get_sys_info(&sysinfo);
108 108
109 #if defined(CONFIG_405EZ) 109 #if defined(CONFIG_405EZ)
110 /* check the pll feedback source */ 110 /* check the pll feedback source */
111 mfcpr(CPR0_PLLC, cpr_pllc); 111 mfcpr(CPR0_PLLC, cpr_pllc);
112 plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? 112 plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ?
113 sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * 113 sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) *
114 sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB); 114 sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB);
115 div = plloutb / (16 * baudrate); /* total divisor */ 115 div = plloutb / (16 * baudrate); /* total divisor */
116 umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ 116 umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */
117 max = 256; /* highest possible */ 117 max = 256; /* highest possible */
118 #else /* 405EZ */ 118 #else /* 405EZ */
119 div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ 119 div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */
120 umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ 120 umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */
121 max = 32; /* highest possible */ 121 max = 32; /* highest possible */
122 #endif /* 405EZ */ 122 #endif /* 405EZ */
123 123
124 *udiv = diff = max; 124 *udiv = diff = max;
125 125
126 /* 126 /*
127 * i is the test udiv value -- start with the largest 127 * i is the test udiv value -- start with the largest
128 * possible (max) to minimize serial clock and constrain 128 * possible (max) to minimize serial clock and constrain
129 * search to umin. 129 * search to umin.
130 */ 130 */
131 for (i = max; i > umin; i--) { 131 for (i = max; i > umin; i--) {
132 ibdiv = div / i; 132 ibdiv = div / i;
133 est = i * ibdiv; 133 est = i * ibdiv;
134 idiff = (est > div) ? (est - div) : (div - est); 134 idiff = (est > div) ? (est - div) : (div - est);
135 if (idiff == 0) { 135 if (idiff == 0) {
136 *udiv = i; 136 *udiv = i;
137 break; /* can't do better */ 137 break; /* can't do better */
138 } else if (idiff < diff) { 138 } else if (idiff < diff) {
139 *udiv = i; /* best so far */ 139 *udiv = i; /* best so far */
140 diff = idiff; /* update lowest diff*/ 140 diff = idiff; /* update lowest diff*/
141 } 141 }
142 } 142 }
143 143
144 #if defined(CONFIG_405EZ) 144 #if defined(CONFIG_405EZ)
145 mfcpr(CPR0_PERD0, reg); 145 mfcpr(CPR0_PERD0, reg);
146 reg &= ~0x0000ffff; 146 reg &= ~0x0000ffff;
147 reg |= ((*udiv - 0) << 8) | (*udiv - 0); 147 reg |= ((*udiv - 0) << 8) | (*udiv - 0);
148 mtcpr(CPR0_PERD0, reg); 148 mtcpr(CPR0_PERD0, reg);
149 #endif 149 #endif
150 150
151 return div / *udiv; 151 return div / *udiv;
152 } 152 }
153 #endif /* #if (defined(CONFIG_405EP) ... */ 153 #endif /* #if (defined(CONFIG_405EP) ... */
154 154
155 /* 155 /*
156 * This function returns the UART clock used by the common 156 * This function returns the UART clock used by the common
157 * NS16550 driver. Additionally the SoC internal divisors for 157 * NS16550 driver. Additionally the SoC internal divisors for
158 * optimal UART baudrate are configured. 158 * optimal UART baudrate are configured.
159 */ 159 */
160 int get_serial_clock(void) 160 int get_serial_clock(void)
161 { 161 {
162 u32 clk; 162 u32 clk;
163 u32 udiv; 163 u32 udiv;
164 #if !defined(CONFIG_405EZ) 164 #if !defined(CONFIG_405EZ)
165 u32 reg; 165 u32 reg;
166 #endif 166 #endif
167 #if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) 167 #if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK)
168 PPC4xx_SYS_INFO sys_info; 168 PPC4xx_SYS_INFO sys_info;
169 #endif 169 #endif
170 170
171 /* 171 /*
172 * Programming of the internal divisors is SoC specific. 172 * Programming of the internal divisors is SoC specific.
173 * Let's handle this in some #ifdef's for the SoC's. 173 * Let's handle this in some #ifdef's for the SoC's.
174 */ 174 */
175 175
176 #if defined(CONFIG_405GP) 176 #if defined(CONFIG_405GP)
177 reg = mfdcr(CPC0_CR0) & ~CR0_MASK; 177 reg = mfdcr(CPC0_CR0) & ~CR0_MASK;
178 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK 178 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
179 clk = CONFIG_SYS_EXT_SERIAL_CLOCK; 179 clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
180 udiv = 1; 180 udiv = 1;
181 reg |= CR0_EXTCLK_ENA; 181 reg |= CR0_EXTCLK_ENA;
182 #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */ 182 #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
183 clk = gd->cpu_clk; 183 clk = gd->cpu_clk;
184 #ifdef CONFIG_SYS_405_UART_ERRATA_59 184 #ifdef CONFIG_SYS_405_UART_ERRATA_59
185 udiv = 31; /* Errata 59: stuck at 31 */ 185 udiv = 31; /* Errata 59: stuck at 31 */
186 #else /* CONFIG_SYS_405_UART_ERRATA_59 */ 186 #else /* CONFIG_SYS_405_UART_ERRATA_59 */
187 { 187 {
188 u32 tmp = CONFIG_SYS_BASE_BAUD * 16; 188 u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
189 189
190 udiv = (clk + tmp / 2) / tmp; 190 udiv = (clk + tmp / 2) / tmp;
191 } 191 }
192 if (udiv > UDIV_MAX) /* max. n bits for udiv */ 192 if (udiv > UDIV_MAX) /* max. n bits for udiv */
193 udiv = UDIV_MAX; 193 udiv = UDIV_MAX;
194 #endif /* CONFIG_SYS_405_UART_ERRATA_59 */ 194 #endif /* CONFIG_SYS_405_UART_ERRATA_59 */
195 #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */ 195 #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
196 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ 196 reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */
197 mtdcr (CPC0_CR0, reg); 197 mtdcr (CPC0_CR0, reg);
198 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK 198 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
199 clk = CONFIG_SYS_EXT_SERIAL_CLOCK; 199 clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
200 #else 200 #else
201 clk = CONFIG_SYS_BASE_BAUD * 16; 201 clk = CONFIG_SYS_BASE_BAUD * 16;
202 #endif 202 #endif
203 #endif 203 #endif
204 204
205 #if defined(CONFIG_405EP) 205 #if defined(CONFIG_405EP)
206 { 206 {
207 u32 tmp = CONFIG_SYS_BASE_BAUD * 16; 207 u32 tmp = CONFIG_SYS_BASE_BAUD * 16;
208 208
209 reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); 209 reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK);
210 clk = gd->cpu_clk; 210 clk = gd->cpu_clk;
211 udiv = (clk + tmp / 2) / tmp; 211 udiv = (clk + tmp / 2) / tmp;
212 if (udiv > UDIV_MAX) /* max. n bits for udiv */ 212 if (udiv > UDIV_MAX) /* max. n bits for udiv */
213 udiv = UDIV_MAX; 213 udiv = UDIV_MAX;
214 } 214 }
215 reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */ 215 reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */
216 reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */ 216 reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */
217 mtdcr(CPC0_UCR, reg); 217 mtdcr(CPC0_UCR, reg);
218 clk = CONFIG_SYS_BASE_BAUD * 16; 218 clk = CONFIG_SYS_BASE_BAUD * 16;
219 #endif /* CONFIG_405EP */ 219 #endif /* CONFIG_405EP */
220 220
221 #if defined(CONFIG_405EX) || defined(CONFIG_440) 221 #if defined(CONFIG_405EX) || defined(CONFIG_440)
222 MFREG(UART0_SDR, reg); 222 MFREG(UART0_SDR, reg);
223 reg &= ~CR0_MASK; 223 reg &= ~CR0_MASK;
224 224
225 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK 225 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
226 reg |= CR0_EXTCLK_ENA; 226 reg |= CR0_EXTCLK_ENA;
227 udiv = 1; 227 udiv = 1;
228 clk = CONFIG_SYS_EXT_SERIAL_CLOCK; 228 clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
229 #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */ 229 #else /* CONFIG_SYS_EXT_SERIAL_CLOCK */
230 clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16; 230 clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
231 #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */ 231 #endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */
232 232
233 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ 233 reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */
234 234
235 /* 235 /*
236 * Configure input clock to baudrate generator for all 236 * Configure input clock to baudrate generator for all
237 * available serial ports here 237 * available serial ports here
238 */ 238 */
239 MTREG(UART0_SDR, reg); 239 MTREG(UART0_SDR, reg);
240 #if defined(UART1_SDR) 240 #if defined(UART1_SDR)
241 MTREG(UART1_SDR, reg); 241 MTREG(UART1_SDR, reg);
242 #endif 242 #endif
243 #if defined(UART2_SDR) 243 #if defined(UART2_SDR)
244 MTREG(UART2_SDR, reg); 244 MTREG(UART2_SDR, reg);
245 #endif 245 #endif
246 #if defined(UART3_SDR) 246 #if defined(UART3_SDR)
247 MTREG(UART3_SDR, reg); 247 MTREG(UART3_SDR, reg);
248 #endif 248 #endif
249 #endif /* CONFIG_405EX ... */ 249 #endif /* CONFIG_405EX ... */
250 250
251 #if defined(CONFIG_405EZ) 251 #if defined(CONFIG_405EZ)
252 clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16; 252 clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16;
253 #endif /* CONFIG_405EZ */ 253 #endif /* CONFIG_405EZ */
254 254
255 /* 255 /*
256 * Correct UART frequency in bd-info struct now that 256 * Correct UART frequency in bd-info struct now that
257 * the UART divisor is available 257 * the UART divisor is available
258 */ 258 */
259 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK 259 #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK
260 gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK; 260 gd->arch.uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK;
261 #else 261 #else
262 get_sys_info(&sys_info); 262 get_sys_info(&sys_info);
263 gd->arch.uart_clk = sys_info.freqUART / udiv; 263 gd->arch.uart_clk = sys_info.freqUART / udiv;
264 #endif 264 #endif
265 265
266 return clk; 266 return clk;
267 } 267 }
268 #endif /* CONFIG_405GP */ 268 #endif /* CONFIG_405GP */
269 269
arch/powerpc/cpu/ppc4xx/miiphy.c
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 /*-----------------------------------------------------------------------------+ 4 /*-----------------------------------------------------------------------------+
5 | 5 |
6 | File Name: miiphy.c 6 | File Name: miiphy.c
7 | 7 |
8 | Function: This module has utilities for accessing the MII PHY through 8 | Function: This module has utilities for accessing the MII PHY through
9 | the EMAC3 macro. 9 | the EMAC3 macro.
10 | 10 |
11 | Author: Mark Wisner 11 | Author: Mark Wisner
12 | 12 |
13 +-----------------------------------------------------------------------------*/ 13 +-----------------------------------------------------------------------------*/
14 14
15 /* define DEBUG for debugging output (obviously ;-)) */ 15 /* define DEBUG for debugging output (obviously ;-)) */
16 #if 0 16 #if 0
17 #define DEBUG 17 #define DEBUG
18 #endif 18 #endif
19 19
20 #include <common.h> 20 #include <common.h>
21 #include <asm/processor.h> 21 #include <asm/processor.h>
22 #include <asm/io.h> 22 #include <asm/io.h>
23 #include <ppc_asm.tmpl> 23 #include <ppc_asm.tmpl>
24 #include <commproc.h> 24 #include <commproc.h>
25 #include <asm/ppc4xx-emac.h> 25 #include <asm/ppc4xx-emac.h>
26 #include <asm/ppc4xx-mal.h> 26 #include <asm/ppc4xx-mal.h>
27 #include <miiphy.h> 27 #include <miiphy.h>
28 28
29 #if !defined(CONFIG_PHY_CLK_FREQ) 29 #if !defined(CONFIG_PHY_CLK_FREQ)
30 #define CONFIG_PHY_CLK_FREQ 0 30 #define CONFIG_PHY_CLK_FREQ 0
31 #endif 31 #endif
32 32
33 /***********************************************************/ 33 /***********************************************************/
34 /* Dump out to the screen PHY regs */ 34 /* Dump out to the screen PHY regs */
35 /***********************************************************/ 35 /***********************************************************/
36 36
37 void miiphy_dump (char *devname, unsigned char addr) 37 void miiphy_dump (char *devname, unsigned char addr)
38 { 38 {
39 unsigned long i; 39 unsigned long i;
40 unsigned short data; 40 unsigned short data;
41 41
42 for (i = 0; i < 0x1A; i++) { 42 for (i = 0; i < 0x1A; i++) {
43 if (miiphy_read (devname, addr, i, &data)) { 43 if (miiphy_read (devname, addr, i, &data)) {
44 printf ("read error for reg %lx\n", i); 44 printf ("read error for reg %lx\n", i);
45 return; 45 return;
46 } 46 }
47 printf ("Phy reg %lx ==> %4x\n", i, data); 47 printf ("Phy reg %lx ==> %4x\n", i, data);
48 48
49 /* jump to the next set of regs */ 49 /* jump to the next set of regs */
50 if (i == 0x07) 50 if (i == 0x07)
51 i = 0x0f; 51 i = 0x0f;
52 52
53 } /* end for loop */ 53 } /* end for loop */
54 } /* end dump */ 54 } /* end dump */
55 55
56 /***********************************************************/ 56 /***********************************************************/
57 /* (Re)start autonegotiation */ 57 /* (Re)start autonegotiation */
58 /***********************************************************/ 58 /***********************************************************/
59 int phy_setup_aneg (char *devname, unsigned char addr) 59 int phy_setup_aneg (char *devname, unsigned char addr)
60 { 60 {
61 u16 bmcr; 61 u16 bmcr;
62 62
63 #if defined(CONFIG_PHY_DYNAMIC_ANEG) 63 #if defined(CONFIG_PHY_DYNAMIC_ANEG)
64 /* 64 /*
65 * Set up advertisement based on capablilities reported by the PHY. 65 * Set up advertisement based on capablilities reported by the PHY.
66 * This should work for both copper and fiber. 66 * This should work for both copper and fiber.
67 */ 67 */
68 u16 bmsr; 68 u16 bmsr;
69 #if defined(CONFIG_PHY_GIGE) 69 #if defined(CONFIG_PHY_GIGE)
70 u16 exsr = 0x0000; 70 u16 exsr = 0x0000;
71 #endif 71 #endif
72 72
73 miiphy_read (devname, addr, MII_BMSR, &bmsr); 73 miiphy_read (devname, addr, MII_BMSR, &bmsr);
74 74
75 #if defined(CONFIG_PHY_GIGE) 75 #if defined(CONFIG_PHY_GIGE)
76 if (bmsr & BMSR_ESTATEN) 76 if (bmsr & BMSR_ESTATEN)
77 miiphy_read (devname, addr, MII_ESTATUS, &exsr); 77 miiphy_read (devname, addr, MII_ESTATUS, &exsr);
78 78
79 if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) { 79 if (exsr & (ESTATUS_1000XF | ESTATUS_1000XH)) {
80 /* 1000BASE-X */ 80 /* 1000BASE-X */
81 u16 anar = 0x0000; 81 u16 anar = 0x0000;
82 82
83 if (exsr & ESTATUS_1000XF) 83 if (exsr & ESTATUS_1000XF)
84 anar |= ADVERTISE_1000XFULL; 84 anar |= ADVERTISE_1000XFULL;
85 85
86 if (exsr & ESTATUS_1000XH) 86 if (exsr & ESTATUS_1000XH)
87 anar |= ADVERTISE_1000XHALF; 87 anar |= ADVERTISE_1000XHALF;
88 88
89 miiphy_write (devname, addr, MII_ADVERTISE, anar); 89 miiphy_write (devname, addr, MII_ADVERTISE, anar);
90 } else 90 } else
91 #endif 91 #endif
92 { 92 {
93 u16 anar, btcr; 93 u16 anar, btcr;
94 94
95 miiphy_read (devname, addr, MII_ADVERTISE, &anar); 95 miiphy_read (devname, addr, MII_ADVERTISE, &anar);
96 anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL | 96 anar &= ~(0x5000 | LPA_100BASE4 | LPA_100FULL |
97 LPA_100HALF | LPA_10FULL | LPA_10HALF); 97 LPA_100HALF | LPA_10FULL | LPA_10HALF);
98 98
99 miiphy_read (devname, addr, MII_CTRL1000, &btcr); 99 miiphy_read (devname, addr, MII_CTRL1000, &btcr);
100 btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD); 100 btcr &= ~(0x00FF | PHY_1000BTCR_1000FD | PHY_1000BTCR_1000HD);
101 101
102 if (bmsr & BMSR_100BASE4) 102 if (bmsr & BMSR_100BASE4)
103 anar |= LPA_100BASE4; 103 anar |= LPA_100BASE4;
104 104
105 if (bmsr & BMSR_100FULL) 105 if (bmsr & BMSR_100FULL)
106 anar |= LPA_100FULL; 106 anar |= LPA_100FULL;
107 107
108 if (bmsr & BMSR_100HALF) 108 if (bmsr & BMSR_100HALF)
109 anar |= LPA_100HALF; 109 anar |= LPA_100HALF;
110 110
111 if (bmsr & BMSR_10FULL) 111 if (bmsr & BMSR_10FULL)
112 anar |= LPA_10FULL; 112 anar |= LPA_10FULL;
113 113
114 if (bmsr & BMSR_10HALF) 114 if (bmsr & BMSR_10HALF)
115 anar |= LPA_10HALF; 115 anar |= LPA_10HALF;
116 116
117 miiphy_write (devname, addr, MII_ADVERTISE, anar); 117 miiphy_write (devname, addr, MII_ADVERTISE, anar);
118 118
119 #if defined(CONFIG_PHY_GIGE) 119 #if defined(CONFIG_PHY_GIGE)
120 if (exsr & ESTATUS_1000_TFULL) 120 if (exsr & ESTATUS_1000_TFULL)
121 btcr |= PHY_1000BTCR_1000FD; 121 btcr |= PHY_1000BTCR_1000FD;
122 122
123 if (exsr & ESTATUS_1000_THALF) 123 if (exsr & ESTATUS_1000_THALF)
124 btcr |= PHY_1000BTCR_1000HD; 124 btcr |= PHY_1000BTCR_1000HD;
125 125
126 miiphy_write (devname, addr, MII_CTRL1000, btcr); 126 miiphy_write (devname, addr, MII_CTRL1000, btcr);
127 #endif 127 #endif
128 } 128 }
129 129
130 #else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ 130 #else /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
131 /* 131 /*
132 * Set up standard advertisement 132 * Set up standard advertisement
133 */ 133 */
134 u16 adv; 134 u16 adv;
135 135
136 miiphy_read (devname, addr, MII_ADVERTISE, &adv); 136 miiphy_read (devname, addr, MII_ADVERTISE, &adv);
137 adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF | 137 adv |= (LPA_LPACK | LPA_100FULL | LPA_100HALF |
138 LPA_10FULL | LPA_10HALF); 138 LPA_10FULL | LPA_10HALF);
139 miiphy_write (devname, addr, MII_ADVERTISE, adv); 139 miiphy_write (devname, addr, MII_ADVERTISE, adv);
140 140
141 miiphy_read (devname, addr, MII_CTRL1000, &adv); 141 miiphy_read (devname, addr, MII_CTRL1000, &adv);
142 adv |= (0x0300); 142 adv |= (0x0300);
143 miiphy_write (devname, addr, MII_CTRL1000, adv); 143 miiphy_write (devname, addr, MII_CTRL1000, adv);
144 144
145 #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */ 145 #endif /* defined(CONFIG_PHY_DYNAMIC_ANEG) */
146 146
147 /* Start/Restart aneg */ 147 /* Start/Restart aneg */
148 miiphy_read (devname, addr, MII_BMCR, &bmcr); 148 miiphy_read (devname, addr, MII_BMCR, &bmcr);
149 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART); 149 bmcr |= (BMCR_ANENABLE | BMCR_ANRESTART);
150 miiphy_write (devname, addr, MII_BMCR, bmcr); 150 miiphy_write (devname, addr, MII_BMCR, bmcr);
151 151
152 return 0; 152 return 0;
153 } 153 }
154 154
155 /***********************************************************/ 155 /***********************************************************/
156 /* read a phy reg and return the value with a rc */ 156 /* read a phy reg and return the value with a rc */
157 /***********************************************************/ 157 /***********************************************************/
158 /* AMCC_TODO: 158 /* AMCC_TODO:
159 * Find out of the choice for the emac for MDIO is from the bridges, 159 * Find out of the choice for the emac for MDIO is from the bridges,
160 * i.e. ZMII or RGMII as approporiate. If the bridges are not used 160 * i.e. ZMII or RGMII as approporiate. If the bridges are not used
161 * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL] 161 * to determine the emac for MDIO, then is the SDR0_ETH_CFG[MDIO_SEL]
162 * used? If so, then this routine below does not apply to the 460EX/GT. 162 * used? If so, then this routine below does not apply to the 460EX/GT.
163 * 163 *
164 * sr: Currently on 460EX only EMAC0 works with MDIO, so we always 164 * sr: Currently on 460EX only EMAC0 works with MDIO, so we always
165 * return EMAC0 offset here 165 * return EMAC0 offset here
166 * vg: For 460EX/460GT if internal GPCS PHY address is specified 166 * vg: For 460EX/460GT if internal GPCS PHY address is specified
167 * return appropriate EMAC offset 167 * return appropriate EMAC offset
168 */ 168 */
169 unsigned int miiphy_getemac_offset(u8 addr) 169 unsigned int miiphy_getemac_offset(u8 addr)
170 { 170 {
171 #if defined(CONFIG_440) && \ 171 #if defined(CONFIG_440) && \
172 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ 172 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
173 !defined(CONFIG_460EX) && !defined(CONFIG_460GT) 173 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
174 unsigned long zmii; 174 unsigned long zmii;
175 unsigned long eoffset; 175 unsigned long eoffset;
176 176
177 /* Need to find out which mdi port we're using */ 177 /* Need to find out which mdi port we're using */
178 zmii = in_be32((void *)ZMII0_FER); 178 zmii = in_be32((void *)ZMII0_FER);
179 179
180 if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0))) 180 if (zmii & (ZMII_FER_MDI << ZMII_FER_V (0)))
181 /* using port 0 */ 181 /* using port 0 */
182 eoffset = 0; 182 eoffset = 0;
183 183
184 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1))) 184 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (1)))
185 /* using port 1 */ 185 /* using port 1 */
186 eoffset = 0x100; 186 eoffset = 0x100;
187 187
188 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2))) 188 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (2)))
189 /* using port 2 */ 189 /* using port 2 */
190 eoffset = 0x400; 190 eoffset = 0x400;
191 191
192 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3))) 192 else if (zmii & (ZMII_FER_MDI << ZMII_FER_V (3)))
193 /* using port 3 */ 193 /* using port 3 */
194 eoffset = 0x600; 194 eoffset = 0x600;
195 195
196 else { 196 else {
197 /* None of the mdi ports are enabled! */ 197 /* None of the mdi ports are enabled! */
198 /* enable port 0 */ 198 /* enable port 0 */
199 zmii |= ZMII_FER_MDI << ZMII_FER_V (0); 199 zmii |= ZMII_FER_MDI << ZMII_FER_V (0);
200 out_be32((void *)ZMII0_FER, zmii); 200 out_be32((void *)ZMII0_FER, zmii);
201 eoffset = 0; 201 eoffset = 0;
202 /* need to soft reset port 0 */ 202 /* need to soft reset port 0 */
203 zmii = in_be32((void *)EMAC0_MR0); 203 zmii = in_be32((void *)EMAC0_MR0);
204 zmii |= EMAC_MR0_SRST; 204 zmii |= EMAC_MR0_SRST;
205 out_be32((void *)EMAC0_MR0, zmii); 205 out_be32((void *)EMAC0_MR0, zmii);
206 } 206 }
207 207
208 return (eoffset); 208 return (eoffset);
209 #else 209 #else
210 210
211 #if defined(CONFIG_405EX) 211 #if defined(CONFIG_405EX)
212 unsigned long rgmii; 212 unsigned long rgmii;
213 int devnum = 1; 213 int devnum = 1;
214 214
215 rgmii = in_be32((void *)RGMII_FER); 215 rgmii = in_be32((void *)RGMII_FER);
216 if (rgmii & (1 << (19 - devnum))) 216 if (rgmii & (1 << (19 - devnum)))
217 return 0x100; 217 return 0x100;
218 #endif 218 #endif
219 219
220 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 220 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
221 u32 eoffset = 0; 221 u32 eoffset = 0;
222 222
223 switch (addr) { 223 switch (addr) {
224 #if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR) 224 #if defined(CONFIG_HAS_ETH1) && defined(CONFIG_GPCS_PHY1_ADDR)
225 case CONFIG_GPCS_PHY1_ADDR: 225 case CONFIG_GPCS_PHY1_ADDR:
226 if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100))) 226 if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x100)))
227 eoffset = 0x100; 227 eoffset = 0x100;
228 break; 228 break;
229 #endif 229 #endif
230 #if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR) 230 #if defined(CONFIG_HAS_ETH2) && defined(CONFIG_GPCS_PHY2_ADDR)
231 case CONFIG_GPCS_PHY2_ADDR: 231 case CONFIG_GPCS_PHY2_ADDR:
232 if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300))) 232 if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x300)))
233 eoffset = 0x300; 233 eoffset = 0x300;
234 break; 234 break;
235 #endif 235 #endif
236 #if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR) 236 #if defined(CONFIG_HAS_ETH3) && defined(CONFIG_GPCS_PHY3_ADDR)
237 case CONFIG_GPCS_PHY3_ADDR: 237 case CONFIG_GPCS_PHY3_ADDR:
238 if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400))) 238 if (addr == EMAC_MR1_IPPA_GET(in_be32((void *)EMAC0_MR1 + 0x400)))
239 eoffset = 0x400; 239 eoffset = 0x400;
240 break; 240 break;
241 #endif 241 #endif
242 default: 242 default:
243 eoffset = 0; 243 eoffset = 0;
244 break; 244 break;
245 } 245 }
246 return eoffset; 246 return eoffset;
247 #endif 247 #endif
248 248
249 return 0; 249 return 0;
250 #endif 250 #endif
251 } 251 }
252 252
253 static int emac_miiphy_wait(u32 emac_reg) 253 static int emac_miiphy_wait(u32 emac_reg)
254 { 254 {
255 u32 sta_reg; 255 u32 sta_reg;
256 int i; 256 int i;
257 257
258 /* wait for completion */ 258 /* wait for completion */
259 i = 0; 259 i = 0;
260 do { 260 do {
261 sta_reg = in_be32((void *)EMAC0_STACR + emac_reg); 261 sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
262 if (i++ > 5) { 262 if (i++ > 5) {
263 debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__, 263 debug("%s [%d]: Timeout! EMAC0_STACR=0x%0x\n", __func__,
264 __LINE__, sta_reg); 264 __LINE__, sta_reg);
265 return -1; 265 return -1;
266 } 266 }
267 udelay(10); 267 udelay(10);
268 } while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK); 268 } while ((sta_reg & EMAC_STACR_OC) == EMAC_STACR_OC_MASK);
269 269
270 return 0; 270 return 0;
271 } 271 }
272 272
273 static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value) 273 static int emac_miiphy_command(u8 addr, u8 reg, int cmd, u16 value)
274 { 274 {
275 u32 emac_reg; 275 u32 emac_reg;
276 u32 sta_reg; 276 u32 sta_reg;
277 277
278 emac_reg = miiphy_getemac_offset(addr); 278 emac_reg = miiphy_getemac_offset(addr);
279 279
280 /* wait for completion */ 280 /* wait for completion */
281 if (emac_miiphy_wait(emac_reg) != 0) 281 if (emac_miiphy_wait(emac_reg) != 0)
282 return -1; 282 return -1;
283 283
284 sta_reg = reg; /* reg address */ 284 sta_reg = reg; /* reg address */
285 285
286 /* set clock (50MHz) and read flags */ 286 /* set clock (50MHz) and read flags */
287 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \ 287 #if defined(CONFIG_440GX) || defined(CONFIG_440SPE) || \
288 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 288 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
289 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 289 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
290 defined(CONFIG_405EX) 290 defined(CONFIG_405EX)
291 #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */ 291 #if defined(CONFIG_IBM_EMAC4_V4) /* EMAC4 V4 changed bit setting */
292 sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd; 292 sta_reg = (sta_reg & ~EMAC_STACR_OP_MASK) | cmd;
293 #else 293 #else
294 sta_reg |= cmd; 294 sta_reg |= cmd;
295 #endif 295 #endif
296 #else 296 #else
297 sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ; 297 sta_reg = (sta_reg | cmd) & ~EMAC_STACR_CLK_100MHZ;
298 #endif 298 #endif
299 299
300 /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */ 300 /* Some boards (mainly 405EP based) define the PHY clock freqency fixed */
301 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; 301 sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ;
302 sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */ 302 sta_reg = sta_reg | ((u32)addr << 5); /* Phy address */
303 sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */ 303 sta_reg = sta_reg | EMAC_STACR_OC_MASK; /* new IBM emac v4 */
304 if (cmd == EMAC_STACR_WRITE) 304 if (cmd == EMAC_STACR_WRITE)
305 memcpy(&sta_reg, &value, 2); /* put in data */ 305 memcpy(&sta_reg, &value, 2); /* put in data */
306 306
307 out_be32((void *)EMAC0_STACR + emac_reg, sta_reg); 307 out_be32((void *)EMAC0_STACR + emac_reg, sta_reg);
308 debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg); 308 debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
309 309
310 /* wait for completion */ 310 /* wait for completion */
311 if (emac_miiphy_wait(emac_reg) != 0) 311 if (emac_miiphy_wait(emac_reg) != 0)
312 return -1; 312 return -1;
313 313
314 debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg); 314 debug("%s [%d]: sta_reg=%08x\n", __func__, __LINE__, sta_reg);
315 if ((sta_reg & EMAC_STACR_PHYE) != 0) 315 if ((sta_reg & EMAC_STACR_PHYE) != 0)
316 return -1; 316 return -1;
317 317
318 return 0; 318 return 0;
319 } 319 }
320 320
321 int emac4xx_miiphy_read (const char *devname, unsigned char addr, unsigned char reg, 321 int emac4xx_miiphy_read (const char *devname, unsigned char addr, unsigned char reg,
322 unsigned short *value) 322 unsigned short *value)
323 { 323 {
324 unsigned long sta_reg; 324 unsigned long sta_reg;
325 unsigned long emac_reg; 325 unsigned long emac_reg;
326 326
327 emac_reg = miiphy_getemac_offset(addr); 327 emac_reg = miiphy_getemac_offset(addr);
328 328
329 if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0) 329 if (emac_miiphy_command(addr, reg, EMAC_STACR_READ, 0) != 0)
330 return -1; 330 return -1;
331 331
332 sta_reg = in_be32((void *)EMAC0_STACR + emac_reg); 332 sta_reg = in_be32((void *)EMAC0_STACR + emac_reg);
333 *value = sta_reg >> 16; 333 *value = sta_reg >> 16;
334 334
335 return 0; 335 return 0;
336 } 336 }
337 337
338 /***********************************************************/ 338 /***********************************************************/
339 /* write a phy reg and return the value with a rc */ 339 /* write a phy reg and return the value with a rc */
340 /***********************************************************/ 340 /***********************************************************/
341 341
342 int emac4xx_miiphy_write (const char *devname, unsigned char addr, unsigned char reg, 342 int emac4xx_miiphy_write (const char *devname, unsigned char addr, unsigned char reg,
343 unsigned short value) 343 unsigned short value)
344 { 344 {
345 return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value); 345 return emac_miiphy_command(addr, reg, EMAC_STACR_WRITE, value);
346 } 346 }
347 347
arch/powerpc/cpu/ppc4xx/start.S
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net> 2 * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se> 3 * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de> 4 * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering 5 * Copyright (C) 2007 Stefan Roese <sr@denx.de>, DENX Software Engineering
6 * Copyright (c) 2008 Nuovation System Designs, LLC 6 * Copyright (c) 2008 Nuovation System Designs, LLC
7 * Grant Erickson <gerickson@nuovations.com> 7 * Grant Erickson <gerickson@nuovations.com>
8 * 8 *
9 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 9 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
10 */ 10 */
11 11
12 /* 12 /*
13 * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards 13 * Startup code for IBM/AMCC PowerPC 4xx (PPC4xx) based boards
14 * 14 *
15 * The following description only applies to the NOR flash style booting. 15 * The following description only applies to the NOR flash style booting.
16 * NAND booting is different. For more details about NAND booting on 4xx 16 * NAND booting is different. For more details about NAND booting on 4xx
17 * take a look at doc/README.nand-boot-ppc440. 17 * take a look at doc/README.nand-boot-ppc440.
18 * 18 *
19 * The CPU starts at address 0xfffffffc (last word in the address space). 19 * The CPU starts at address 0xfffffffc (last word in the address space).
20 * The U-Boot image therefore has to be located in the "upper" area of the 20 * The U-Boot image therefore has to be located in the "upper" area of the
21 * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for 21 * flash (e.g. 512MiB - 0xfff80000 ... 0xffffffff). The default value for
22 * the boot chip-select (CS0) is quite big and covers this area. On the 22 * the boot chip-select (CS0) is quite big and covers this area. On the
23 * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will 23 * 405EX this is for example 0xffe00000 ... 0xffffffff. U-Boot will
24 * reconfigure this CS0 (and other chip-selects as well when configured 24 * reconfigure this CS0 (and other chip-selects as well when configured
25 * this way) in the boot process to the "correct" values matching the 25 * this way) in the boot process to the "correct" values matching the
26 * board layout. 26 * board layout.
27 */ 27 */
28 28
29 #include <asm-offsets.h> 29 #include <asm-offsets.h>
30 #include <config.h> 30 #include <config.h>
31 #include <asm/ppc4xx.h> 31 #include <asm/ppc4xx.h>
32 #include <version.h> 32 #include <version.h>
33 33
34 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 34 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
35 35
36 #include <ppc_asm.tmpl> 36 #include <ppc_asm.tmpl>
37 #include <ppc_defs.h> 37 #include <ppc_defs.h>
38 38
39 #include <asm/cache.h> 39 #include <asm/cache.h>
40 #include <asm/mmu.h> 40 #include <asm/mmu.h>
41 #include <asm/ppc4xx-isram.h> 41 #include <asm/ppc4xx-isram.h>
42 42
43 #ifdef CONFIG_SYS_INIT_DCACHE_CS 43 #ifdef CONFIG_SYS_INIT_DCACHE_CS
44 # if (CONFIG_SYS_INIT_DCACHE_CS == 0) 44 # if (CONFIG_SYS_INIT_DCACHE_CS == 0)
45 # define PBxAP PB1AP 45 # define PBxAP PB1AP
46 # define PBxCR PB0CR 46 # define PBxCR PB0CR
47 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR)) 47 # if (defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))
48 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP 48 # define PBxAP_VAL CONFIG_SYS_EBC_PB0AP
49 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR 49 # define PBxCR_VAL CONFIG_SYS_EBC_PB0CR
50 # endif 50 # endif
51 # endif 51 # endif
52 # if (CONFIG_SYS_INIT_DCACHE_CS == 1) 52 # if (CONFIG_SYS_INIT_DCACHE_CS == 1)
53 # define PBxAP PB1AP 53 # define PBxAP PB1AP
54 # define PBxCR PB1CR 54 # define PBxCR PB1CR
55 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR)) 55 # if (defined(CONFIG_SYS_EBC_PB1AP) && defined(CONFIG_SYS_EBC_PB1CR))
56 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP 56 # define PBxAP_VAL CONFIG_SYS_EBC_PB1AP
57 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR 57 # define PBxCR_VAL CONFIG_SYS_EBC_PB1CR
58 # endif 58 # endif
59 # endif 59 # endif
60 # if (CONFIG_SYS_INIT_DCACHE_CS == 2) 60 # if (CONFIG_SYS_INIT_DCACHE_CS == 2)
61 # define PBxAP PB2AP 61 # define PBxAP PB2AP
62 # define PBxCR PB2CR 62 # define PBxCR PB2CR
63 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR)) 63 # if (defined(CONFIG_SYS_EBC_PB2AP) && defined(CONFIG_SYS_EBC_PB2CR))
64 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP 64 # define PBxAP_VAL CONFIG_SYS_EBC_PB2AP
65 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR 65 # define PBxCR_VAL CONFIG_SYS_EBC_PB2CR
66 # endif 66 # endif
67 # endif 67 # endif
68 # if (CONFIG_SYS_INIT_DCACHE_CS == 3) 68 # if (CONFIG_SYS_INIT_DCACHE_CS == 3)
69 # define PBxAP PB3AP 69 # define PBxAP PB3AP
70 # define PBxCR PB3CR 70 # define PBxCR PB3CR
71 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR)) 71 # if (defined(CONFIG_SYS_EBC_PB3AP) && defined(CONFIG_SYS_EBC_PB3CR))
72 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP 72 # define PBxAP_VAL CONFIG_SYS_EBC_PB3AP
73 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR 73 # define PBxCR_VAL CONFIG_SYS_EBC_PB3CR
74 # endif 74 # endif
75 # endif 75 # endif
76 # if (CONFIG_SYS_INIT_DCACHE_CS == 4) 76 # if (CONFIG_SYS_INIT_DCACHE_CS == 4)
77 # define PBxAP PB4AP 77 # define PBxAP PB4AP
78 # define PBxCR PB4CR 78 # define PBxCR PB4CR
79 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR)) 79 # if (defined(CONFIG_SYS_EBC_PB4AP) && defined(CONFIG_SYS_EBC_PB4CR))
80 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP 80 # define PBxAP_VAL CONFIG_SYS_EBC_PB4AP
81 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR 81 # define PBxCR_VAL CONFIG_SYS_EBC_PB4CR
82 # endif 82 # endif
83 # endif 83 # endif
84 # if (CONFIG_SYS_INIT_DCACHE_CS == 5) 84 # if (CONFIG_SYS_INIT_DCACHE_CS == 5)
85 # define PBxAP PB5AP 85 # define PBxAP PB5AP
86 # define PBxCR PB5CR 86 # define PBxCR PB5CR
87 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR)) 87 # if (defined(CONFIG_SYS_EBC_PB5AP) && defined(CONFIG_SYS_EBC_PB5CR))
88 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP 88 # define PBxAP_VAL CONFIG_SYS_EBC_PB5AP
89 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR 89 # define PBxCR_VAL CONFIG_SYS_EBC_PB5CR
90 # endif 90 # endif
91 # endif 91 # endif
92 # if (CONFIG_SYS_INIT_DCACHE_CS == 6) 92 # if (CONFIG_SYS_INIT_DCACHE_CS == 6)
93 # define PBxAP PB6AP 93 # define PBxAP PB6AP
94 # define PBxCR PB6CR 94 # define PBxCR PB6CR
95 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR)) 95 # if (defined(CONFIG_SYS_EBC_PB6AP) && defined(CONFIG_SYS_EBC_PB6CR))
96 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP 96 # define PBxAP_VAL CONFIG_SYS_EBC_PB6AP
97 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR 97 # define PBxCR_VAL CONFIG_SYS_EBC_PB6CR
98 # endif 98 # endif
99 # endif 99 # endif
100 # if (CONFIG_SYS_INIT_DCACHE_CS == 7) 100 # if (CONFIG_SYS_INIT_DCACHE_CS == 7)
101 # define PBxAP PB7AP 101 # define PBxAP PB7AP
102 # define PBxCR PB7CR 102 # define PBxCR PB7CR
103 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR)) 103 # if (defined(CONFIG_SYS_EBC_PB7AP) && defined(CONFIG_SYS_EBC_PB7CR))
104 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP 104 # define PBxAP_VAL CONFIG_SYS_EBC_PB7AP
105 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR 105 # define PBxCR_VAL CONFIG_SYS_EBC_PB7CR
106 # endif 106 # endif
107 # endif 107 # endif
108 # ifndef PBxAP_VAL 108 # ifndef PBxAP_VAL
109 # define PBxAP_VAL 0 109 # define PBxAP_VAL 0
110 # endif 110 # endif
111 # ifndef PBxCR_VAL 111 # ifndef PBxCR_VAL
112 # define PBxCR_VAL 0 112 # define PBxCR_VAL 0
113 # endif 113 # endif
114 /* 114 /*
115 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB 115 * Memory Bank x (nothingness) initialization CONFIG_SYS_INIT_RAM_ADDR + 64 MiB
116 * used as temporary stack pointer for the primordial stack 116 * used as temporary stack pointer for the primordial stack
117 */ 117 */
118 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR 118 # ifndef CONFIG_SYS_INIT_DCACHE_PBxAR
119 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ 119 # define CONFIG_SYS_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \
120 EBC_BXAP_TWT_ENCODE(7) | \ 120 EBC_BXAP_TWT_ENCODE(7) | \
121 EBC_BXAP_BCE_DISABLE | \ 121 EBC_BXAP_BCE_DISABLE | \
122 EBC_BXAP_BCT_2TRANS | \ 122 EBC_BXAP_BCT_2TRANS | \
123 EBC_BXAP_CSN_ENCODE(0) | \ 123 EBC_BXAP_CSN_ENCODE(0) | \
124 EBC_BXAP_OEN_ENCODE(0) | \ 124 EBC_BXAP_OEN_ENCODE(0) | \
125 EBC_BXAP_WBN_ENCODE(0) | \ 125 EBC_BXAP_WBN_ENCODE(0) | \
126 EBC_BXAP_WBF_ENCODE(0) | \ 126 EBC_BXAP_WBF_ENCODE(0) | \
127 EBC_BXAP_TH_ENCODE(2) | \ 127 EBC_BXAP_TH_ENCODE(2) | \
128 EBC_BXAP_RE_DISABLED | \ 128 EBC_BXAP_RE_DISABLED | \
129 EBC_BXAP_SOR_NONDELAYED | \ 129 EBC_BXAP_SOR_NONDELAYED | \
130 EBC_BXAP_BEM_WRITEONLY | \ 130 EBC_BXAP_BEM_WRITEONLY | \
131 EBC_BXAP_PEN_DISABLED) 131 EBC_BXAP_PEN_DISABLED)
132 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */ 132 # endif /* CONFIG_SYS_INIT_DCACHE_PBxAR */
133 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR 133 # ifndef CONFIG_SYS_INIT_DCACHE_PBxCR
134 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \ 134 # define CONFIG_SYS_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_INIT_RAM_ADDR) | \
135 EBC_BXCR_BS_64MB | \ 135 EBC_BXCR_BS_64MB | \
136 EBC_BXCR_BU_RW | \ 136 EBC_BXCR_BU_RW | \
137 EBC_BXCR_BW_16BIT) 137 EBC_BXCR_BW_16BIT)
138 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */ 138 # endif /* CONFIG_SYS_INIT_DCACHE_PBxCR */
139 # ifndef CONFIG_SYS_INIT_RAM_PATTERN 139 # ifndef CONFIG_SYS_INIT_RAM_PATTERN
140 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD 140 # define CONFIG_SYS_INIT_RAM_PATTERN 0xDEADDEAD
141 # endif 141 # endif
142 #endif /* CONFIG_SYS_INIT_DCACHE_CS */ 142 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
143 143
144 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10))) 144 #if (defined(CONFIG_SYS_INIT_RAM_DCACHE) && (CONFIG_SYS_INIT_RAM_SIZE > (4 << 10)))
145 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE! 145 #error Only 4k of init-ram is supported - please adjust CONFIG_SYS_INIT_RAM_SIZE!
146 #endif 146 #endif
147 147
148 /* 148 /*
149 * Unless otherwise overriden, enable two 128MB cachable instruction regions 149 * Unless otherwise overriden, enable two 128MB cachable instruction regions
150 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering 150 * at CONFIG_SYS_SDRAM_BASE and another 128MB cacheable instruction region covering
151 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions. 151 * NOR flash at CONFIG_SYS_FLASH_BASE. Disable all cacheable data regions.
152 */ 152 */
153 #if !defined(CONFIG_SYS_FLASH_BASE) 153 #if !defined(CONFIG_SYS_FLASH_BASE)
154 /* If not already defined, set it to the "last" 128MByte region */ 154 /* If not already defined, set it to the "last" 128MByte region */
155 # define CONFIG_SYS_FLASH_BASE 0xf8000000 155 # define CONFIG_SYS_FLASH_BASE 0xf8000000
156 #endif 156 #endif
157 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE) 157 #if !defined(CONFIG_SYS_ICACHE_SACR_VALUE)
158 # define CONFIG_SYS_ICACHE_SACR_VALUE \ 158 # define CONFIG_SYS_ICACHE_SACR_VALUE \
159 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \ 159 (PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + ( 0 << 20)) | \
160 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \ 160 PPC_128MB_SACR_VALUE(CONFIG_SYS_SDRAM_BASE + (128 << 20)) | \
161 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE)) 161 PPC_128MB_SACR_VALUE(CONFIG_SYS_FLASH_BASE))
162 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */ 162 #endif /* !defined(CONFIG_SYS_ICACHE_SACR_VALUE) */
163 163
164 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE) 164 #if !defined(CONFIG_SYS_DCACHE_SACR_VALUE)
165 # define CONFIG_SYS_DCACHE_SACR_VALUE \ 165 # define CONFIG_SYS_DCACHE_SACR_VALUE \
166 (0x00000000) 166 (0x00000000)
167 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */ 167 #endif /* !defined(CONFIG_SYS_DCACHE_SACR_VALUE) */
168 168
169 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH) 169 #if !defined(CONFIG_SYS_TLB_FOR_BOOT_FLASH)
170 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */ 170 #define CONFIG_SYS_TLB_FOR_BOOT_FLASH 0 /* use TLB 0 as default */
171 #endif 171 #endif
172 172
173 #define function_prolog(func_name) .text; \ 173 #define function_prolog(func_name) .text; \
174 .align 2; \ 174 .align 2; \
175 .globl func_name; \ 175 .globl func_name; \
176 func_name: 176 func_name:
177 #define function_epilog(func_name) .type func_name,@function; \ 177 #define function_epilog(func_name) .type func_name,@function; \
178 .size func_name,.-func_name 178 .size func_name,.-func_name
179 179
180 /* We don't want the MMU yet. 180 /* We don't want the MMU yet.
181 */ 181 */
182 #undef MSR_KERNEL 182 #undef MSR_KERNEL
183 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */ 183 #define MSR_KERNEL ( MSR_ME ) /* Machine Check */
184 184
185 185
186 .extern ext_bus_cntlr_init 186 .extern ext_bus_cntlr_init
187 #ifdef CONFIG_NAND_U_BOOT 187 #ifdef CONFIG_NAND_U_BOOT
188 .extern reconfig_tlb0 188 .extern reconfig_tlb0
189 #endif 189 #endif
190 190
191 /* 191 /*
192 * Set up GOT: Global Offset Table 192 * Set up GOT: Global Offset Table
193 * 193 *
194 * Use r12 to access the GOT 194 * Use r12 to access the GOT
195 */ 195 */
196 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) 196 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
197 START_GOT 197 START_GOT
198 GOT_ENTRY(_GOT2_TABLE_) 198 GOT_ENTRY(_GOT2_TABLE_)
199 GOT_ENTRY(_FIXUP_TABLE_) 199 GOT_ENTRY(_FIXUP_TABLE_)
200 200
201 GOT_ENTRY(_start) 201 GOT_ENTRY(_start)
202 GOT_ENTRY(_start_of_vectors) 202 GOT_ENTRY(_start_of_vectors)
203 GOT_ENTRY(_end_of_vectors) 203 GOT_ENTRY(_end_of_vectors)
204 GOT_ENTRY(transfer_to_handler) 204 GOT_ENTRY(transfer_to_handler)
205 205
206 GOT_ENTRY(__init_end) 206 GOT_ENTRY(__init_end)
207 GOT_ENTRY(__bss_end) 207 GOT_ENTRY(__bss_end)
208 GOT_ENTRY(__bss_start) 208 GOT_ENTRY(__bss_start)
209 END_GOT 209 END_GOT
210 #endif /* CONFIG_NAND_SPL */ 210 #endif /* CONFIG_NAND_SPL */
211 211
212 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \ 212 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) && \
213 !defined(CONFIG_SPL_BUILD) 213 !defined(CONFIG_SPL_BUILD)
214 /* 214 /*
215 * NAND U-Boot image is started from offset 0 215 * NAND U-Boot image is started from offset 0
216 */ 216 */
217 .text 217 .text
218 #if defined(CONFIG_440) 218 #if defined(CONFIG_440)
219 bl reconfig_tlb0 219 bl reconfig_tlb0
220 #endif 220 #endif
221 GET_GOT 221 GET_GOT
222 bl cpu_init_f /* run low-level CPU init code (from Flash) */ 222 bl cpu_init_f /* run low-level CPU init code (from Flash) */
223 bl board_init_f 223 bl board_init_f
224 /* NOTREACHED - board_init_f() does not return */ 224 /* NOTREACHED - board_init_f() does not return */
225 #endif 225 #endif
226 226
227 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD) 227 #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_BOOT_FROM_XMD)
228 /* 228 /*
229 * 4xx RAM-booting U-Boot image is started from offset 0 229 * 4xx RAM-booting U-Boot image is started from offset 0
230 */ 230 */
231 .text 231 .text
232 bl _start_440 232 bl _start_440
233 #endif 233 #endif
234 234
235 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 235 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
236 /* 236 /*
237 * This is the entry of the real U-Boot from a board port 237 * This is the entry of the real U-Boot from a board port
238 * that supports SPL booting on the PPC4xx. We only need 238 * that supports SPL booting on the PPC4xx. We only need
239 * to call board_init_f() here. Everything else has already 239 * to call board_init_f() here. Everything else has already
240 * been done in the SPL u-boot version. 240 * been done in the SPL u-boot version.
241 */ 241 */
242 GET_GOT /* initialize GOT access */ 242 GET_GOT /* initialize GOT access */
243 bl board_init_f /* run 1st part of board init code (in Flash)*/ 243 bl board_init_f /* run 1st part of board init code (in Flash)*/
244 /* NOTREACHED - board_init_f() does not return */ 244 /* NOTREACHED - board_init_f() does not return */
245 #endif 245 #endif
246 246
247 /* 247 /*
248 * 440 Startup -- on reset only the top 4k of the effective 248 * 440 Startup -- on reset only the top 4k of the effective
249 * address space is mapped in by an entry in the instruction 249 * address space is mapped in by an entry in the instruction
250 * and data shadow TLB. The .bootpg section is located in the 250 * and data shadow TLB. The .bootpg section is located in the
251 * top 4k & does only what's necessary to map in the the rest 251 * top 4k & does only what's necessary to map in the the rest
252 * of the boot rom. Once the boot rom is mapped in we can 252 * of the boot rom. Once the boot rom is mapped in we can
253 * proceed with normal startup. 253 * proceed with normal startup.
254 * 254 *
255 * NOTE: CS0 only covers the top 2MB of the effective address 255 * NOTE: CS0 only covers the top 2MB of the effective address
256 * space after reset. 256 * space after reset.
257 */ 257 */
258 258
259 #if defined(CONFIG_440) 259 #if defined(CONFIG_440)
260 #if !defined(CONFIG_NAND_SPL) 260 #if !defined(CONFIG_NAND_SPL)
261 .section .bootpg,"ax" 261 .section .bootpg,"ax"
262 #endif 262 #endif
263 .globl _start_440 263 .globl _start_440
264 264
265 /**************************************************************************/ 265 /**************************************************************************/
266 _start_440: 266 _start_440:
267 /*--------------------------------------------------------------------+ 267 /*--------------------------------------------------------------------+
268 | 440EPX BUP Change - Hardware team request 268 | 440EPX BUP Change - Hardware team request
269 +--------------------------------------------------------------------*/ 269 +--------------------------------------------------------------------*/
270 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) 270 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
271 sync 271 sync
272 nop 272 nop
273 nop 273 nop
274 #endif 274 #endif
275 /*----------------------------------------------------------------+ 275 /*----------------------------------------------------------------+
276 | Core bug fix. Clear the esr 276 | Core bug fix. Clear the esr
277 +-----------------------------------------------------------------*/ 277 +-----------------------------------------------------------------*/
278 li r0,0 278 li r0,0
279 mtspr SPRN_ESR,r0 279 mtspr SPRN_ESR,r0
280 /*----------------------------------------------------------------*/ 280 /*----------------------------------------------------------------*/
281 /* Clear and set up some registers. */ 281 /* Clear and set up some registers. */
282 /*----------------------------------------------------------------*/ 282 /*----------------------------------------------------------------*/
283 iccci r0,r0 /* NOTE: operands not used for 440 */ 283 iccci r0,r0 /* NOTE: operands not used for 440 */
284 dccci r0,r0 /* NOTE: operands not used for 440 */ 284 dccci r0,r0 /* NOTE: operands not used for 440 */
285 sync 285 sync
286 li r0,0 286 li r0,0
287 mtspr SPRN_SRR0,r0 287 mtspr SPRN_SRR0,r0
288 mtspr SPRN_SRR1,r0 288 mtspr SPRN_SRR1,r0
289 mtspr SPRN_CSRR0,r0 289 mtspr SPRN_CSRR0,r0
290 mtspr SPRN_CSRR1,r0 290 mtspr SPRN_CSRR1,r0
291 /* NOTE: 440GX adds machine check status regs */ 291 /* NOTE: 440GX adds machine check status regs */
292 #if defined(CONFIG_440) && !defined(CONFIG_440GP) 292 #if defined(CONFIG_440) && !defined(CONFIG_440GP)
293 mtspr SPRN_MCSRR0,r0 293 mtspr SPRN_MCSRR0,r0
294 mtspr SPRN_MCSRR1,r0 294 mtspr SPRN_MCSRR1,r0
295 mfspr r1,SPRN_MCSR 295 mfspr r1,SPRN_MCSR
296 mtspr SPRN_MCSR,r1 296 mtspr SPRN_MCSR,r1
297 #endif 297 #endif
298 298
299 /*----------------------------------------------------------------*/ 299 /*----------------------------------------------------------------*/
300 /* CCR0 init */ 300 /* CCR0 init */
301 /*----------------------------------------------------------------*/ 301 /*----------------------------------------------------------------*/
302 /* Disable store gathering & broadcast, guarantee inst/data 302 /* Disable store gathering & broadcast, guarantee inst/data
303 * cache block touch, force load/store alignment 303 * cache block touch, force load/store alignment
304 * (see errata 1.12: 440_33) 304 * (see errata 1.12: 440_33)
305 */ 305 */
306 lis r1,0x0030 /* store gathering & broadcast disable */ 306 lis r1,0x0030 /* store gathering & broadcast disable */
307 ori r1,r1,0x6000 /* cache touch */ 307 ori r1,r1,0x6000 /* cache touch */
308 mtspr SPRN_CCR0,r1 308 mtspr SPRN_CCR0,r1
309 309
310 /*----------------------------------------------------------------*/ 310 /*----------------------------------------------------------------*/
311 /* Initialize debug */ 311 /* Initialize debug */
312 /*----------------------------------------------------------------*/ 312 /*----------------------------------------------------------------*/
313 mfspr r1,SPRN_DBCR0 313 mfspr r1,SPRN_DBCR0
314 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ 314 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */
315 bne skip_debug_init /* if set, don't clear debug register */ 315 bne skip_debug_init /* if set, don't clear debug register */
316 mfspr r1,SPRN_CCR0 316 mfspr r1,SPRN_CCR0
317 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */ 317 ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */
318 mtspr SPRN_CCR0,r1 318 mtspr SPRN_CCR0,r1
319 mtspr SPRN_DBCR0,r0 319 mtspr SPRN_DBCR0,r0
320 mtspr SPRN_DBCR1,r0 320 mtspr SPRN_DBCR1,r0
321 mtspr SPRN_DBCR2,r0 321 mtspr SPRN_DBCR2,r0
322 mtspr SPRN_IAC1,r0 322 mtspr SPRN_IAC1,r0
323 mtspr SPRN_IAC2,r0 323 mtspr SPRN_IAC2,r0
324 mtspr SPRN_IAC3,r0 324 mtspr SPRN_IAC3,r0
325 mtspr SPRN_DAC1,r0 325 mtspr SPRN_DAC1,r0
326 mtspr SPRN_DAC2,r0 326 mtspr SPRN_DAC2,r0
327 mtspr SPRN_DVC1,r0 327 mtspr SPRN_DVC1,r0
328 mtspr SPRN_DVC2,r0 328 mtspr SPRN_DVC2,r0
329 329
330 mfspr r1,SPRN_DBSR 330 mfspr r1,SPRN_DBSR
331 mtspr SPRN_DBSR,r1 /* Clear all valid bits */ 331 mtspr SPRN_DBSR,r1 /* Clear all valid bits */
332 skip_debug_init: 332 skip_debug_init:
333 333
334 #if defined (CONFIG_440SPE) 334 #if defined (CONFIG_440SPE)
335 /*----------------------------------------------------------------+ 335 /*----------------------------------------------------------------+
336 | Initialize Core Configuration Reg1. 336 | Initialize Core Configuration Reg1.
337 | a. ICDPEI: Record even parity. Normal operation. 337 | a. ICDPEI: Record even parity. Normal operation.
338 | b. ICTPEI: Record even parity. Normal operation. 338 | b. ICTPEI: Record even parity. Normal operation.
339 | c. DCTPEI: Record even parity. Normal operation. 339 | c. DCTPEI: Record even parity. Normal operation.
340 | d. DCDPEI: Record even parity. Normal operation. 340 | d. DCDPEI: Record even parity. Normal operation.
341 | e. DCUPEI: Record even parity. Normal operation. 341 | e. DCUPEI: Record even parity. Normal operation.
342 | f. DCMPEI: Record even parity. Normal operation. 342 | f. DCMPEI: Record even parity. Normal operation.
343 | g. FCOM: Normal operation 343 | g. FCOM: Normal operation
344 | h. MMUPEI: Record even parity. Normal operation. 344 | h. MMUPEI: Record even parity. Normal operation.
345 | i. FFF: Flush only as much data as necessary. 345 | i. FFF: Flush only as much data as necessary.
346 | j. TCS: Timebase increments from CPU clock. 346 | j. TCS: Timebase increments from CPU clock.
347 +-----------------------------------------------------------------*/ 347 +-----------------------------------------------------------------*/
348 li r0,0 348 li r0,0
349 mtspr SPRN_CCR1, r0 349 mtspr SPRN_CCR1, r0
350 350
351 /*----------------------------------------------------------------+ 351 /*----------------------------------------------------------------+
352 | Reset the timebase. 352 | Reset the timebase.
353 | The previous write to CCR1 sets the timebase source. 353 | The previous write to CCR1 sets the timebase source.
354 +-----------------------------------------------------------------*/ 354 +-----------------------------------------------------------------*/
355 mtspr SPRN_TBWL, r0 355 mtspr SPRN_TBWL, r0
356 mtspr SPRN_TBWU, r0 356 mtspr SPRN_TBWU, r0
357 #endif 357 #endif
358 358
359 /*----------------------------------------------------------------*/ 359 /*----------------------------------------------------------------*/
360 /* Setup interrupt vectors */ 360 /* Setup interrupt vectors */
361 /*----------------------------------------------------------------*/ 361 /*----------------------------------------------------------------*/
362 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */ 362 mtspr SPRN_IVPR,r0 /* Vectors start at 0x0000_0000 */
363 li r1,0x0100 363 li r1,0x0100
364 mtspr SPRN_IVOR0,r1 /* Critical input */ 364 mtspr SPRN_IVOR0,r1 /* Critical input */
365 li r1,0x0200 365 li r1,0x0200
366 mtspr SPRN_IVOR1,r1 /* Machine check */ 366 mtspr SPRN_IVOR1,r1 /* Machine check */
367 li r1,0x0300 367 li r1,0x0300
368 mtspr SPRN_IVOR2,r1 /* Data storage */ 368 mtspr SPRN_IVOR2,r1 /* Data storage */
369 li r1,0x0400 369 li r1,0x0400
370 mtspr SPRN_IVOR3,r1 /* Instruction storage */ 370 mtspr SPRN_IVOR3,r1 /* Instruction storage */
371 li r1,0x0500 371 li r1,0x0500
372 mtspr SPRN_IVOR4,r1 /* External interrupt */ 372 mtspr SPRN_IVOR4,r1 /* External interrupt */
373 li r1,0x0600 373 li r1,0x0600
374 mtspr SPRN_IVOR5,r1 /* Alignment */ 374 mtspr SPRN_IVOR5,r1 /* Alignment */
375 li r1,0x0700 375 li r1,0x0700
376 mtspr SPRN_IVOR6,r1 /* Program check */ 376 mtspr SPRN_IVOR6,r1 /* Program check */
377 li r1,0x0800 377 li r1,0x0800
378 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */ 378 mtspr SPRN_IVOR7,r1 /* Floating point unavailable */
379 li r1,0x0c00 379 li r1,0x0c00
380 mtspr SPRN_IVOR8,r1 /* System call */ 380 mtspr SPRN_IVOR8,r1 /* System call */
381 li r1,0x0a00 381 li r1,0x0a00
382 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */ 382 mtspr SPRN_IVOR9,r1 /* Auxiliary Processor unavailable */
383 li r1,0x0900 383 li r1,0x0900
384 mtspr SPRN_IVOR10,r1 /* Decrementer */ 384 mtspr SPRN_IVOR10,r1 /* Decrementer */
385 li r1,0x1300 385 li r1,0x1300
386 mtspr SPRN_IVOR13,r1 /* Data TLB error */ 386 mtspr SPRN_IVOR13,r1 /* Data TLB error */
387 li r1,0x1400 387 li r1,0x1400
388 mtspr SPRN_IVOR14,r1 /* Instr TLB error */ 388 mtspr SPRN_IVOR14,r1 /* Instr TLB error */
389 li r1,0x2000 389 li r1,0x2000
390 mtspr SPRN_IVOR15,r1 /* Debug */ 390 mtspr SPRN_IVOR15,r1 /* Debug */
391 391
392 /*----------------------------------------------------------------*/ 392 /*----------------------------------------------------------------*/
393 /* Configure cache regions */ 393 /* Configure cache regions */
394 /*----------------------------------------------------------------*/ 394 /*----------------------------------------------------------------*/
395 mtspr SPRN_INV0,r0 395 mtspr SPRN_INV0,r0
396 mtspr SPRN_INV1,r0 396 mtspr SPRN_INV1,r0
397 mtspr SPRN_INV2,r0 397 mtspr SPRN_INV2,r0
398 mtspr SPRN_INV3,r0 398 mtspr SPRN_INV3,r0
399 mtspr SPRN_DNV0,r0 399 mtspr SPRN_DNV0,r0
400 mtspr SPRN_DNV1,r0 400 mtspr SPRN_DNV1,r0
401 mtspr SPRN_DNV2,r0 401 mtspr SPRN_DNV2,r0
402 mtspr SPRN_DNV3,r0 402 mtspr SPRN_DNV3,r0
403 mtspr SPRN_ITV0,r0 403 mtspr SPRN_ITV0,r0
404 mtspr SPRN_ITV1,r0 404 mtspr SPRN_ITV1,r0
405 mtspr SPRN_ITV2,r0 405 mtspr SPRN_ITV2,r0
406 mtspr SPRN_ITV3,r0 406 mtspr SPRN_ITV3,r0
407 mtspr SPRN_DTV0,r0 407 mtspr SPRN_DTV0,r0
408 mtspr SPRN_DTV1,r0 408 mtspr SPRN_DTV1,r0
409 mtspr SPRN_DTV2,r0 409 mtspr SPRN_DTV2,r0
410 mtspr SPRN_DTV3,r0 410 mtspr SPRN_DTV3,r0
411 411
412 /*----------------------------------------------------------------*/ 412 /*----------------------------------------------------------------*/
413 /* Cache victim limits */ 413 /* Cache victim limits */
414 /*----------------------------------------------------------------*/ 414 /*----------------------------------------------------------------*/
415 /* floors 0, ceiling max to use the entire cache -- nothing locked 415 /* floors 0, ceiling max to use the entire cache -- nothing locked
416 */ 416 */
417 lis r1,0x0001 417 lis r1,0x0001
418 ori r1,r1,0xf800 418 ori r1,r1,0xf800
419 mtspr SPRN_IVLIM,r1 419 mtspr SPRN_IVLIM,r1
420 mtspr SPRN_DVLIM,r1 420 mtspr SPRN_DVLIM,r1
421 421
422 /*----------------------------------------------------------------+ 422 /*----------------------------------------------------------------+
423 |Initialize MMUCR[STID] = 0. 423 |Initialize MMUCR[STID] = 0.
424 +-----------------------------------------------------------------*/ 424 +-----------------------------------------------------------------*/
425 mfspr r0,SPRN_MMUCR 425 mfspr r0,SPRN_MMUCR
426 addis r1,0,0xFFFF 426 addis r1,0,0xFFFF
427 ori r1,r1,0xFF00 427 ori r1,r1,0xFF00
428 and r0,r0,r1 428 and r0,r0,r1
429 mtspr SPRN_MMUCR,r0 429 mtspr SPRN_MMUCR,r0
430 430
431 /*----------------------------------------------------------------*/ 431 /*----------------------------------------------------------------*/
432 /* Clear all TLB entries -- TID = 0, TS = 0 */ 432 /* Clear all TLB entries -- TID = 0, TS = 0 */
433 /*----------------------------------------------------------------*/ 433 /*----------------------------------------------------------------*/
434 addis r0,0,0x0000 434 addis r0,0,0x0000
435 #ifdef CONFIG_SYS_RAMBOOT 435 #ifdef CONFIG_SYS_RAMBOOT
436 li r4,0 /* Start with TLB #0 */ 436 li r4,0 /* Start with TLB #0 */
437 #else 437 #else
438 li r4,1 /* Start with TLB #1 */ 438 li r4,1 /* Start with TLB #1 */
439 #endif 439 #endif
440 li r1,64 /* 64 TLB entries */ 440 li r1,64 /* 64 TLB entries */
441 sub r1,r1,r4 /* calculate last TLB # */ 441 sub r1,r1,r4 /* calculate last TLB # */
442 mtctr r1 442 mtctr r1
443 rsttlb: 443 rsttlb:
444 #ifdef CONFIG_SYS_RAMBOOT 444 #ifdef CONFIG_SYS_RAMBOOT
445 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */ 445 tlbre r3,r4,0 /* Read contents from TLB word #0 to get EPN */
446 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */ 446 rlwinm. r3,r3,0,0xfffffc00 /* Mask EPN */
447 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */ 447 beq tlbnxt /* Skip EPN=0 TLB, this is the SDRAM TLB */
448 #endif 448 #endif
449 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/ 449 tlbwe r0,r4,0 /* Invalidate all entries (V=0)*/
450 tlbwe r0,r4,1 450 tlbwe r0,r4,1
451 tlbwe r0,r4,2 451 tlbwe r0,r4,2
452 tlbnxt: addi r4,r4,1 /* Next TLB */ 452 tlbnxt: addi r4,r4,1 /* Next TLB */
453 bdnz rsttlb 453 bdnz rsttlb
454 454
455 /*----------------------------------------------------------------*/ 455 /*----------------------------------------------------------------*/
456 /* TLB entry setup -- step thru tlbtab */ 456 /* TLB entry setup -- step thru tlbtab */
457 /*----------------------------------------------------------------*/ 457 /*----------------------------------------------------------------*/
458 #if defined(CONFIG_440SPE_REVA) 458 #if defined(CONFIG_440SPE_REVA)
459 /*----------------------------------------------------------------*/ 459 /*----------------------------------------------------------------*/
460 /* We have different TLB tables for revA and rev B of 440SPe */ 460 /* We have different TLB tables for revA and rev B of 440SPe */
461 /*----------------------------------------------------------------*/ 461 /*----------------------------------------------------------------*/
462 mfspr r1, PVR 462 mfspr r1, PVR
463 lis r0,0x5342 463 lis r0,0x5342
464 ori r0,r0,0x1891 464 ori r0,r0,0x1891
465 cmpw r7,r1,r0 465 cmpw r7,r1,r0
466 bne r7,..revA 466 bne r7,..revA
467 bl tlbtabB 467 bl tlbtabB
468 b ..goon 468 b ..goon
469 ..revA: 469 ..revA:
470 bl tlbtabA 470 bl tlbtabA
471 ..goon: 471 ..goon:
472 #else 472 #else
473 bl tlbtab /* Get tlbtab pointer */ 473 bl tlbtab /* Get tlbtab pointer */
474 #endif 474 #endif
475 mr r5,r0 475 mr r5,r0
476 li r1,0x003f /* 64 TLB entries max */ 476 li r1,0x003f /* 64 TLB entries max */
477 mtctr r1 477 mtctr r1
478 li r4,0 /* TLB # */ 478 li r4,0 /* TLB # */
479 479
480 addi r5,r5,-4 480 addi r5,r5,-4
481 1: 481 1:
482 #ifdef CONFIG_SYS_RAMBOOT 482 #ifdef CONFIG_SYS_RAMBOOT
483 tlbre r3,r4,0 /* Read contents from TLB word #0 */ 483 tlbre r3,r4,0 /* Read contents from TLB word #0 */
484 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */ 484 rlwinm. r3,r3,0,0x00000200 /* Mask V (valid) bit */
485 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */ 485 bne tlbnx2 /* Skip V=1 TLB, this is the SDRAM TLB */
486 #endif 486 #endif
487 lwzu r0,4(r5) 487 lwzu r0,4(r5)
488 cmpwi r0,0 488 cmpwi r0,0
489 beq 2f /* 0 marks end */ 489 beq 2f /* 0 marks end */
490 lwzu r1,4(r5) 490 lwzu r1,4(r5)
491 lwzu r2,4(r5) 491 lwzu r2,4(r5)
492 tlbwe r0,r4,0 /* TLB Word 0 */ 492 tlbwe r0,r4,0 /* TLB Word 0 */
493 tlbwe r1,r4,1 /* TLB Word 1 */ 493 tlbwe r1,r4,1 /* TLB Word 1 */
494 tlbwe r2,r4,2 /* TLB Word 2 */ 494 tlbwe r2,r4,2 /* TLB Word 2 */
495 tlbnx2: addi r4,r4,1 /* Next TLB */ 495 tlbnx2: addi r4,r4,1 /* Next TLB */
496 bdnz 1b 496 bdnz 1b
497 497
498 /*----------------------------------------------------------------*/ 498 /*----------------------------------------------------------------*/
499 /* Continue from 'normal' start */ 499 /* Continue from 'normal' start */
500 /*----------------------------------------------------------------*/ 500 /*----------------------------------------------------------------*/
501 2: 501 2:
502 bl 3f 502 bl 3f
503 b _start 503 b _start
504 504
505 3: li r0,0 505 3: li r0,0
506 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */ 506 mtspr SPRN_SRR1,r0 /* Keep things disabled for now */
507 mflr r1 507 mflr r1
508 mtspr SPRN_SRR0,r1 508 mtspr SPRN_SRR0,r1
509 rfi 509 rfi
510 #endif /* CONFIG_440 */ 510 #endif /* CONFIG_440 */
511 511
512 /* 512 /*
513 * r3 - 1st arg to board_init(): IMMP pointer 513 * r3 - 1st arg to board_init(): IMMP pointer
514 * r4 - 2nd arg to board_init(): boot flag 514 * r4 - 2nd arg to board_init(): boot flag
515 */ 515 */
516 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) 516 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
517 .text 517 .text
518 .long 0x27051956 /* U-Boot Magic Number */ 518 .long 0x27051956 /* U-Boot Magic Number */
519 .globl version_string 519 .globl version_string
520 version_string: 520 version_string:
521 .ascii U_BOOT_VERSION_STRING, "\0" 521 .ascii U_BOOT_VERSION_STRING, "\0"
522 522
523 . = EXC_OFF_SYS_RESET 523 . = EXC_OFF_SYS_RESET
524 .globl _start_of_vectors 524 .globl _start_of_vectors
525 _start_of_vectors: 525 _start_of_vectors:
526 526
527 /* Critical input. */ 527 /* Critical input. */
528 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException) 528 CRIT_EXCEPTION(0x100, CritcalInput, UnknownException)
529 529
530 #ifdef CONFIG_440 530 #ifdef CONFIG_440
531 /* Machine check */ 531 /* Machine check */
532 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException) 532 MCK_EXCEPTION(0x200, MachineCheck, MachineCheckException)
533 #else 533 #else
534 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException) 534 CRIT_EXCEPTION(0x200, MachineCheck, MachineCheckException)
535 #endif /* CONFIG_440 */ 535 #endif /* CONFIG_440 */
536 536
537 /* Data Storage exception. */ 537 /* Data Storage exception. */
538 STD_EXCEPTION(0x300, DataStorage, UnknownException) 538 STD_EXCEPTION(0x300, DataStorage, UnknownException)
539 539
540 /* Instruction Storage exception. */ 540 /* Instruction Storage exception. */
541 STD_EXCEPTION(0x400, InstStorage, UnknownException) 541 STD_EXCEPTION(0x400, InstStorage, UnknownException)
542 542
543 /* External Interrupt exception. */ 543 /* External Interrupt exception. */
544 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt) 544 STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
545 545
546 /* Alignment exception. */ 546 /* Alignment exception. */
547 . = 0x600 547 . = 0x600
548 Alignment: 548 Alignment:
549 EXCEPTION_PROLOG(SRR0, SRR1) 549 EXCEPTION_PROLOG(SRR0, SRR1)
550 mfspr r4,DAR 550 mfspr r4,DAR
551 stw r4,_DAR(r21) 551 stw r4,_DAR(r21)
552 mfspr r5,DSISR 552 mfspr r5,DSISR
553 stw r5,_DSISR(r21) 553 stw r5,_DSISR(r21)
554 addi r3,r1,STACK_FRAME_OVERHEAD 554 addi r3,r1,STACK_FRAME_OVERHEAD
555 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE) 555 EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
556 556
557 /* Program check exception */ 557 /* Program check exception */
558 . = 0x700 558 . = 0x700
559 ProgramCheck: 559 ProgramCheck:
560 EXCEPTION_PROLOG(SRR0, SRR1) 560 EXCEPTION_PROLOG(SRR0, SRR1)
561 addi r3,r1,STACK_FRAME_OVERHEAD 561 addi r3,r1,STACK_FRAME_OVERHEAD
562 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException, 562 EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
563 MSR_KERNEL, COPY_EE) 563 MSR_KERNEL, COPY_EE)
564 564
565 #ifdef CONFIG_440 565 #ifdef CONFIG_440
566 STD_EXCEPTION(0x800, FPUnavailable, UnknownException) 566 STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
567 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException) 567 STD_EXCEPTION(0x900, Decrementer, DecrementerPITException)
568 STD_EXCEPTION(0xa00, APU, UnknownException) 568 STD_EXCEPTION(0xa00, APU, UnknownException)
569 #endif 569 #endif
570 STD_EXCEPTION(0xc00, SystemCall, UnknownException) 570 STD_EXCEPTION(0xc00, SystemCall, UnknownException)
571 571
572 #ifdef CONFIG_440 572 #ifdef CONFIG_440
573 STD_EXCEPTION(0x1300, DataTLBError, UnknownException) 573 STD_EXCEPTION(0x1300, DataTLBError, UnknownException)
574 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException) 574 STD_EXCEPTION(0x1400, InstructionTLBError, UnknownException)
575 #else 575 #else
576 STD_EXCEPTION(0x1000, PIT, DecrementerPITException) 576 STD_EXCEPTION(0x1000, PIT, DecrementerPITException)
577 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException) 577 STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
578 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException) 578 STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
579 #endif 579 #endif
580 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException ) 580 CRIT_EXCEPTION(0x2000, DebugBreakpoint, DebugException )
581 581
582 .globl _end_of_vectors 582 .globl _end_of_vectors
583 _end_of_vectors: 583 _end_of_vectors:
584 . = _START_OFFSET 584 . = _START_OFFSET
585 #endif 585 #endif
586 .globl _start 586 .globl _start
587 _start: 587 _start:
588 588
589 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD) 589 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
590 /* 590 /*
591 * This is the entry of the real U-Boot from a board port 591 * This is the entry of the real U-Boot from a board port
592 * that supports SPL booting on the PPC4xx. We only need 592 * that supports SPL booting on the PPC4xx. We only need
593 * to call board_init_f() here. Everything else has already 593 * to call board_init_f() here. Everything else has already
594 * been done in the SPL u-boot version. 594 * been done in the SPL u-boot version.
595 */ 595 */
596 GET_GOT /* initialize GOT access */ 596 GET_GOT /* initialize GOT access */
597 bl board_init_f /* run 1st part of board init code (in Flash)*/ 597 bl board_init_f /* run 1st part of board init code (in Flash)*/
598 /* NOTREACHED - board_init_f() does not return */ 598 /* NOTREACHED - board_init_f() does not return */
599 #endif 599 #endif
600 600
601 /*****************************************************************************/ 601 /*****************************************************************************/
602 #if defined(CONFIG_440) 602 #if defined(CONFIG_440)
603 603
604 /*----------------------------------------------------------------*/ 604 /*----------------------------------------------------------------*/
605 /* Clear and set up some registers. */ 605 /* Clear and set up some registers. */
606 /*----------------------------------------------------------------*/ 606 /*----------------------------------------------------------------*/
607 li r0,0x0000 607 li r0,0x0000
608 lis r1,0xffff 608 lis r1,0xffff
609 mtspr SPRN_DEC,r0 /* prevent dec exceptions */ 609 mtspr SPRN_DEC,r0 /* prevent dec exceptions */
610 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */ 610 mtspr SPRN_TBWL,r0 /* prevent fit & wdt exceptions */
611 mtspr SPRN_TBWU,r0 611 mtspr SPRN_TBWU,r0
612 mtspr SPRN_TSR,r1 /* clear all timer exception status */ 612 mtspr SPRN_TSR,r1 /* clear all timer exception status */
613 mtspr SPRN_TCR,r0 /* disable all */ 613 mtspr SPRN_TCR,r0 /* disable all */
614 mtspr SPRN_ESR,r0 /* clear exception syndrome register */ 614 mtspr SPRN_ESR,r0 /* clear exception syndrome register */
615 mtxer r0 /* clear integer exception register */ 615 mtxer r0 /* clear integer exception register */
616 616
617 /*----------------------------------------------------------------*/ 617 /*----------------------------------------------------------------*/
618 /* Debug setup -- some (not very good) ice's need an event*/ 618 /* Debug setup -- some (not very good) ice's need an event*/
619 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */ 619 /* to establish control :-( Define CONFIG_SYS_INIT_DBCR to the dbsr */
620 /* value you need in this case 0x8cff 0000 should do the trick */ 620 /* value you need in this case 0x8cff 0000 should do the trick */
621 /*----------------------------------------------------------------*/ 621 /*----------------------------------------------------------------*/
622 #if defined(CONFIG_SYS_INIT_DBCR) 622 #if defined(CONFIG_SYS_INIT_DBCR)
623 lis r1,0xffff 623 lis r1,0xffff
624 ori r1,r1,0xffff 624 ori r1,r1,0xffff
625 mtspr SPRN_DBSR,r1 /* Clear all status bits */ 625 mtspr SPRN_DBSR,r1 /* Clear all status bits */
626 lis r0,CONFIG_SYS_INIT_DBCR@h 626 lis r0,CONFIG_SYS_INIT_DBCR@h
627 ori r0,r0,CONFIG_SYS_INIT_DBCR@l 627 ori r0,r0,CONFIG_SYS_INIT_DBCR@l
628 mtspr SPRN_DBCR0,r0 628 mtspr SPRN_DBCR0,r0
629 isync 629 isync
630 #endif 630 #endif
631 631
632 /*----------------------------------------------------------------*/ 632 /*----------------------------------------------------------------*/
633 /* Setup the internal SRAM */ 633 /* Setup the internal SRAM */
634 /*----------------------------------------------------------------*/ 634 /*----------------------------------------------------------------*/
635 li r0,0 635 li r0,0
636 636
637 #ifdef CONFIG_SYS_INIT_RAM_DCACHE 637 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
638 /* Clear Dcache to use as RAM */ 638 /* Clear Dcache to use as RAM */
639 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h 639 addis r3,r0,CONFIG_SYS_INIT_RAM_ADDR@h
640 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l 640 ori r3,r3,CONFIG_SYS_INIT_RAM_ADDR@l
641 addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h 641 addis r4,r0,CONFIG_SYS_INIT_RAM_SIZE@h
642 ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l 642 ori r4,r4,CONFIG_SYS_INIT_RAM_SIZE@l
643 rlwinm. r5,r4,0,27,31 643 rlwinm. r5,r4,0,27,31
644 rlwinm r5,r4,27,5,31 644 rlwinm r5,r4,27,5,31
645 beq ..d_ran 645 beq ..d_ran
646 addi r5,r5,0x0001 646 addi r5,r5,0x0001
647 ..d_ran: 647 ..d_ran:
648 mtctr r5 648 mtctr r5
649 ..d_ag: 649 ..d_ag:
650 dcbz r0,r3 650 dcbz r0,r3
651 addi r3,r3,32 651 addi r3,r3,32
652 bdnz ..d_ag 652 bdnz ..d_ag
653 653
654 /* 654 /*
655 * Lock the init-ram/stack in d-cache, so that other regions 655 * Lock the init-ram/stack in d-cache, so that other regions
656 * may use d-cache as well 656 * may use d-cache as well
657 * Note, that this current implementation locks exactly 4k 657 * Note, that this current implementation locks exactly 4k
658 * of d-cache, so please make sure that you don't define a 658 * of d-cache, so please make sure that you don't define a
659 * bigger init-ram area. Take a look at the lwmon5 440EPx 659 * bigger init-ram area. Take a look at the lwmon5 440EPx
660 * implementation as a reference. 660 * implementation as a reference.
661 */ 661 */
662 msync 662 msync
663 isync 663 isync
664 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */ 664 /* 8. set TFLOOR/NFLOOR to 8 (-> 8*16*32 bytes locked -> 4k) */
665 lis r1,0x0201 665 lis r1,0x0201
666 ori r1,r1,0xf808 666 ori r1,r1,0xf808
667 mtspr SPRN_DVLIM,r1 667 mtspr SPRN_DVLIM,r1
668 lis r1,0x0808 668 lis r1,0x0808
669 ori r1,r1,0x0808 669 ori r1,r1,0x0808
670 mtspr SPRN_DNV0,r1 670 mtspr SPRN_DNV0,r1
671 mtspr SPRN_DNV1,r1 671 mtspr SPRN_DNV1,r1
672 mtspr SPRN_DNV2,r1 672 mtspr SPRN_DNV2,r1
673 mtspr SPRN_DNV3,r1 673 mtspr SPRN_DNV3,r1
674 mtspr SPRN_DTV0,r1 674 mtspr SPRN_DTV0,r1
675 mtspr SPRN_DTV1,r1 675 mtspr SPRN_DTV1,r1
676 mtspr SPRN_DTV2,r1 676 mtspr SPRN_DTV2,r1
677 mtspr SPRN_DTV3,r1 677 mtspr SPRN_DTV3,r1
678 msync 678 msync
679 isync 679 isync
680 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ 680 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
681 681
682 /* 440EP & 440GR are only 440er PPC's without internal SRAM */ 682 /* 440EP & 440GR are only 440er PPC's without internal SRAM */
683 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) 683 #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR)
684 /* not all PPC's have internal SRAM usable as L2-cache */ 684 /* not all PPC's have internal SRAM usable as L2-cache */
685 #if defined(CONFIG_440GX) || \ 685 #if defined(CONFIG_440GX) || \
686 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ 686 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
687 defined(CONFIG_460SX) 687 defined(CONFIG_460SX)
688 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */ 688 mtdcr L2_CACHE_CFG,r0 /* Ensure L2 Cache is off */
689 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 689 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
690 defined(CONFIG_APM821XX) 690 defined(CONFIG_APM821XX)
691 lis r1, 0x0000 691 lis r1, 0x0000
692 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */ 692 ori r1,r1,0x0008 /* Set L2_CACHE_CFG[RDBW]=1 */
693 mtdcr L2_CACHE_CFG,r1 693 mtdcr L2_CACHE_CFG,r1
694 #endif 694 #endif
695 695
696 lis r2,0x7fff 696 lis r2,0x7fff
697 ori r2,r2,0xffff 697 ori r2,r2,0xffff
698 mfdcr r1,ISRAM0_DPC 698 mfdcr r1,ISRAM0_DPC
699 and r1,r1,r2 /* Disable parity check */ 699 and r1,r1,r2 /* Disable parity check */
700 mtdcr ISRAM0_DPC,r1 700 mtdcr ISRAM0_DPC,r1
701 mfdcr r1,ISRAM0_PMEG 701 mfdcr r1,ISRAM0_PMEG
702 and r1,r1,r2 /* Disable pwr mgmt */ 702 and r1,r1,r2 /* Disable pwr mgmt */
703 mtdcr ISRAM0_PMEG,r1 703 mtdcr ISRAM0_PMEG,r1
704 704
705 lis r1,0x8000 /* BAS = 8000_0000 */ 705 lis r1,0x8000 /* BAS = 8000_0000 */
706 #if defined(CONFIG_440GX) || defined(CONFIG_440SP) 706 #if defined(CONFIG_440GX) || defined(CONFIG_440SP)
707 ori r1,r1,0x0980 /* first 64k */ 707 ori r1,r1,0x0980 /* first 64k */
708 mtdcr ISRAM0_SB0CR,r1 708 mtdcr ISRAM0_SB0CR,r1
709 lis r1,0x8001 709 lis r1,0x8001
710 ori r1,r1,0x0980 /* second 64k */ 710 ori r1,r1,0x0980 /* second 64k */
711 mtdcr ISRAM0_SB1CR,r1 711 mtdcr ISRAM0_SB1CR,r1
712 lis r1, 0x8002 712 lis r1, 0x8002
713 ori r1,r1, 0x0980 /* third 64k */ 713 ori r1,r1, 0x0980 /* third 64k */
714 mtdcr ISRAM0_SB2CR,r1 714 mtdcr ISRAM0_SB2CR,r1
715 lis r1, 0x8003 715 lis r1, 0x8003
716 ori r1,r1, 0x0980 /* fourth 64k */ 716 ori r1,r1, 0x0980 /* fourth 64k */
717 mtdcr ISRAM0_SB3CR,r1 717 mtdcr ISRAM0_SB3CR,r1
718 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \ 718 #elif defined(CONFIG_440SPE) || defined(CONFIG_460EX) || \
719 defined(CONFIG_460GT) || defined(CONFIG_APM821XX) 719 defined(CONFIG_460GT) || defined(CONFIG_APM821XX)
720 lis r1,0x0000 /* BAS = X_0000_0000 */ 720 lis r1,0x0000 /* BAS = X_0000_0000 */
721 ori r1,r1,0x0984 /* first 64k */ 721 ori r1,r1,0x0984 /* first 64k */
722 mtdcr ISRAM0_SB0CR,r1 722 mtdcr ISRAM0_SB0CR,r1
723 lis r1,0x0001 723 lis r1,0x0001
724 ori r1,r1,0x0984 /* second 64k */ 724 ori r1,r1,0x0984 /* second 64k */
725 mtdcr ISRAM0_SB1CR,r1 725 mtdcr ISRAM0_SB1CR,r1
726 lis r1, 0x0002 726 lis r1, 0x0002
727 ori r1,r1, 0x0984 /* third 64k */ 727 ori r1,r1, 0x0984 /* third 64k */
728 mtdcr ISRAM0_SB2CR,r1 728 mtdcr ISRAM0_SB2CR,r1
729 lis r1, 0x0003 729 lis r1, 0x0003
730 ori r1,r1, 0x0984 /* fourth 64k */ 730 ori r1,r1, 0x0984 /* fourth 64k */
731 mtdcr ISRAM0_SB3CR,r1 731 mtdcr ISRAM0_SB3CR,r1
732 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 732 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
733 defined(CONFIG_APM821XX) 733 defined(CONFIG_APM821XX)
734 lis r2,0x7fff 734 lis r2,0x7fff
735 ori r2,r2,0xffff 735 ori r2,r2,0xffff
736 mfdcr r1,ISRAM1_DPC 736 mfdcr r1,ISRAM1_DPC
737 and r1,r1,r2 /* Disable parity check */ 737 and r1,r1,r2 /* Disable parity check */
738 mtdcr ISRAM1_DPC,r1 738 mtdcr ISRAM1_DPC,r1
739 mfdcr r1,ISRAM1_PMEG 739 mfdcr r1,ISRAM1_PMEG
740 and r1,r1,r2 /* Disable pwr mgmt */ 740 and r1,r1,r2 /* Disable pwr mgmt */
741 mtdcr ISRAM1_PMEG,r1 741 mtdcr ISRAM1_PMEG,r1
742 742
743 lis r1,0x0004 /* BAS = 4_0004_0000 */ 743 lis r1,0x0004 /* BAS = 4_0004_0000 */
744 ori r1,r1,ISRAM1_SIZE /* ocm size */ 744 ori r1,r1,ISRAM1_SIZE /* ocm size */
745 mtdcr ISRAM1_SB0CR,r1 745 mtdcr ISRAM1_SB0CR,r1
746 #endif 746 #endif
747 #elif defined(CONFIG_460SX) 747 #elif defined(CONFIG_460SX)
748 lis r1,0x0000 /* BAS = 0000_0000 */ 748 lis r1,0x0000 /* BAS = 0000_0000 */
749 ori r1,r1,0x0B84 /* first 128k */ 749 ori r1,r1,0x0B84 /* first 128k */
750 mtdcr ISRAM0_SB0CR,r1 750 mtdcr ISRAM0_SB0CR,r1
751 lis r1,0x0001 751 lis r1,0x0001
752 ori r1,r1,0x0B84 /* second 128k */ 752 ori r1,r1,0x0B84 /* second 128k */
753 mtdcr ISRAM0_SB1CR,r1 753 mtdcr ISRAM0_SB1CR,r1
754 lis r1, 0x0002 754 lis r1, 0x0002
755 ori r1,r1, 0x0B84 /* third 128k */ 755 ori r1,r1, 0x0B84 /* third 128k */
756 mtdcr ISRAM0_SB2CR,r1 756 mtdcr ISRAM0_SB2CR,r1
757 lis r1, 0x0003 757 lis r1, 0x0003
758 ori r1,r1, 0x0B84 /* fourth 128k */ 758 ori r1,r1, 0x0B84 /* fourth 128k */
759 mtdcr ISRAM0_SB3CR,r1 759 mtdcr ISRAM0_SB3CR,r1
760 #elif defined(CONFIG_440GP) 760 #elif defined(CONFIG_440GP)
761 ori r1,r1,0x0380 /* 8k rw */ 761 ori r1,r1,0x0380 /* 8k rw */
762 mtdcr ISRAM0_SB0CR,r1 762 mtdcr ISRAM0_SB0CR,r1
763 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */ 763 mtdcr ISRAM0_SB1CR,r0 /* Disable bank 1 */
764 #endif 764 #endif
765 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */ 765 #endif /* #if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) */
766 766
767 /*----------------------------------------------------------------*/ 767 /*----------------------------------------------------------------*/
768 /* Setup the stack in internal SRAM */ 768 /* Setup the stack in internal SRAM */
769 /*----------------------------------------------------------------*/ 769 /*----------------------------------------------------------------*/
770 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h 770 lis r1,CONFIG_SYS_INIT_RAM_ADDR@h
771 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l 771 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET@l
772 li r0,0 772 li r0,0
773 stwu r0,-4(r1) 773 stwu r0,-4(r1)
774 stwu r0,-4(r1) /* Terminate call chain */ 774 stwu r0,-4(r1) /* Terminate call chain */
775 775
776 stwu r1,-8(r1) /* Save back chain and move SP */ 776 stwu r1,-8(r1) /* Save back chain and move SP */
777 lis r0,RESET_VECTOR@h /* Address of reset vector */ 777 lis r0,RESET_VECTOR@h /* Address of reset vector */
778 ori r0,r0, RESET_VECTOR@l 778 ori r0,r0, RESET_VECTOR@l
779 stwu r1,-8(r1) /* Save back chain and move SP */ 779 stwu r1,-8(r1) /* Save back chain and move SP */
780 stw r0,+12(r1) /* Save return addr (underflow vect) */ 780 stw r0,+12(r1) /* Save return addr (underflow vect) */
781 781
782 #ifdef CONFIG_NAND_SPL 782 #ifdef CONFIG_NAND_SPL
783 bl nand_boot_common /* will not return */ 783 bl nand_boot_common /* will not return */
784 #else 784 #else
785 #ifndef CONFIG_SPL_BUILD 785 #ifndef CONFIG_SPL_BUILD
786 GET_GOT 786 GET_GOT
787 #endif 787 #endif
788 788
789 bl cpu_init_f /* run low-level CPU init code (from Flash) */ 789 bl cpu_init_f /* run low-level CPU init code (from Flash) */
790 bl board_init_f 790 bl board_init_f
791 /* NOTREACHED - board_init_f() does not return */ 791 /* NOTREACHED - board_init_f() does not return */
792 #endif 792 #endif
793 793
794 #endif /* CONFIG_440 */ 794 #endif /* CONFIG_440 */
795 795
796 /*****************************************************************************/ 796 /*****************************************************************************/
797 #if defined(CONFIG_405GP) || \ 797 #if defined(CONFIG_405GP) || \
798 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ 798 defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \
799 defined(CONFIG_405EX) || defined(CONFIG_405) 799 defined(CONFIG_405EX) || defined(CONFIG_405)
800 /*----------------------------------------------------------------------- */ 800 /*----------------------------------------------------------------------- */
801 /* Clear and set up some registers. */ 801 /* Clear and set up some registers. */
802 /*----------------------------------------------------------------------- */ 802 /*----------------------------------------------------------------------- */
803 addi r4,r0,0x0000 803 addi r4,r0,0x0000
804 #if !defined(CONFIG_405EX) 804 #if !defined(CONFIG_405EX)
805 mtspr SPRN_SGR,r4 805 mtspr SPRN_SGR,r4
806 #else 806 #else
807 /* 807 /*
808 * On 405EX, completely clearing the SGR leads to PPC hangup 808 * On 405EX, completely clearing the SGR leads to PPC hangup
809 * upon PCIe configuration access. The PCIe memory regions 809 * upon PCIe configuration access. The PCIe memory regions
810 * need to be guarded! 810 * need to be guarded!
811 */ 811 */
812 lis r3,0x0000 812 lis r3,0x0000
813 ori r3,r3,0x7FFC 813 ori r3,r3,0x7FFC
814 mtspr SPRN_SGR,r3 814 mtspr SPRN_SGR,r3
815 #endif 815 #endif
816 mtspr SPRN_DCWR,r4 816 mtspr SPRN_DCWR,r4
817 mtesr r4 /* clear Exception Syndrome Reg */ 817 mtesr r4 /* clear Exception Syndrome Reg */
818 mttcr r4 /* clear Timer Control Reg */ 818 mttcr r4 /* clear Timer Control Reg */
819 mtxer r4 /* clear Fixed-Point Exception Reg */ 819 mtxer r4 /* clear Fixed-Point Exception Reg */
820 mtevpr r4 /* clear Exception Vector Prefix Reg */ 820 mtevpr r4 /* clear Exception Vector Prefix Reg */
821 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */ 821 addi r4,r0,(0xFFFF-0x10000) /* set r4 to 0xFFFFFFFF (status in the */
822 /* dbsr is cleared by setting bits to 1) */ 822 /* dbsr is cleared by setting bits to 1) */
823 mtdbsr r4 /* clear/reset the dbsr */ 823 mtdbsr r4 /* clear/reset the dbsr */
824 824
825 /* Invalidate the i- and d-caches. */ 825 /* Invalidate the i- and d-caches. */
826 bl invalidate_icache 826 bl invalidate_icache
827 bl invalidate_dcache 827 bl invalidate_dcache
828 828
829 /* Set-up icache cacheability. */ 829 /* Set-up icache cacheability. */
830 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h 830 lis r4, CONFIG_SYS_ICACHE_SACR_VALUE@h
831 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l 831 ori r4, r4, CONFIG_SYS_ICACHE_SACR_VALUE@l
832 mticcr r4 832 mticcr r4
833 isync 833 isync
834 834
835 /* Set-up dcache cacheability. */ 835 /* Set-up dcache cacheability. */
836 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h 836 lis r4, CONFIG_SYS_DCACHE_SACR_VALUE@h
837 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l 837 ori r4, r4, CONFIG_SYS_DCACHE_SACR_VALUE@l
838 mtdccr r4 838 mtdccr r4
839 839
840 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\ 840 #if !(defined(CONFIG_SYS_EBC_PB0AP) && defined(CONFIG_SYS_EBC_PB0CR))\
841 && !defined (CONFIG_XILINX_405) 841 && !defined (CONFIG_XILINX_405)
842 /*----------------------------------------------------------------------- */ 842 /*----------------------------------------------------------------------- */
843 /* Tune the speed and size for flash CS0 */ 843 /* Tune the speed and size for flash CS0 */
844 /*----------------------------------------------------------------------- */ 844 /*----------------------------------------------------------------------- */
845 bl ext_bus_cntlr_init 845 bl ext_bus_cntlr_init
846 #endif 846 #endif
847 847
848 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM)) 848 #if !(defined(CONFIG_SYS_INIT_DCACHE_CS) || defined(CONFIG_SYS_TEMP_STACK_OCM))
849 /* 849 /*
850 * For boards that don't have OCM and can't use the data cache 850 * For boards that don't have OCM and can't use the data cache
851 * for their primordial stack, setup stack here directly after the 851 * for their primordial stack, setup stack here directly after the
852 * SDRAM is initialized in ext_bus_cntlr_init. 852 * SDRAM is initialized in ext_bus_cntlr_init.
853 */ 853 */
854 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h 854 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
855 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */ 855 ori r1,r1,CONFIG_SYS_INIT_SP_OFFSET /* set up the stack in SDRAM */
856 856
857 li r0, 0 /* Make room for stack frame header and */ 857 li r0, 0 /* Make room for stack frame header and */
858 stwu r0, -4(r1) /* clear final stack frame so that */ 858 stwu r0, -4(r1) /* clear final stack frame so that */
859 stwu r0, -4(r1) /* stack backtraces terminate cleanly */ 859 stwu r0, -4(r1) /* stack backtraces terminate cleanly */
860 /* 860 /*
861 * Set up a dummy frame to store reset vector as return address. 861 * Set up a dummy frame to store reset vector as return address.
862 * this causes stack underflow to reset board. 862 * this causes stack underflow to reset board.
863 */ 863 */
864 stwu r1, -8(r1) /* Save back chain and move SP */ 864 stwu r1, -8(r1) /* Save back chain and move SP */
865 lis r0, RESET_VECTOR@h /* Address of reset vector */ 865 lis r0, RESET_VECTOR@h /* Address of reset vector */
866 ori r0, r0, RESET_VECTOR@l 866 ori r0, r0, RESET_VECTOR@l
867 stwu r1, -8(r1) /* Save back chain and move SP */ 867 stwu r1, -8(r1) /* Save back chain and move SP */
868 stw r0, +12(r1) /* Save return addr (underflow vect) */ 868 stw r0, +12(r1) /* Save return addr (underflow vect) */
869 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */ 869 #endif /* !(CONFIG_SYS_INIT_DCACHE_CS || !CONFIG_SYS_TEM_STACK_OCM) */
870 870
871 #if defined(CONFIG_405EP) 871 #if defined(CONFIG_405EP)
872 /*----------------------------------------------------------------------- */ 872 /*----------------------------------------------------------------------- */
873 /* DMA Status, clear to come up clean */ 873 /* DMA Status, clear to come up clean */
874 /*----------------------------------------------------------------------- */ 874 /*----------------------------------------------------------------------- */
875 addis r3,r0, 0xFFFF /* Clear all existing DMA status */ 875 addis r3,r0, 0xFFFF /* Clear all existing DMA status */
876 ori r3,r3, 0xFFFF 876 ori r3,r3, 0xFFFF
877 mtdcr DMASR, r3 877 mtdcr DMASR, r3
878 878
879 bl ppc405ep_init /* do ppc405ep specific init */ 879 bl ppc405ep_init /* do ppc405ep specific init */
880 #endif /* CONFIG_405EP */ 880 #endif /* CONFIG_405EP */
881 881
882 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE) 882 #if defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)
883 #if defined(CONFIG_405EZ) 883 #if defined(CONFIG_405EZ)
884 /******************************************************************** 884 /********************************************************************
885 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 885 * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2
886 *******************************************************************/ 886 *******************************************************************/
887 /* 887 /*
888 * We can map the OCM on the PLB3, so map it at 888 * We can map the OCM on the PLB3, so map it at
889 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000 889 * CONFIG_SYS_OCM_DATA_ADDR + 0x8000
890 */ 890 */
891 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ 891 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
892 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l 892 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
893 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ 893 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
894 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */ 894 mtdcr OCM0_PLBCR1,r3 /* Set PLB Access */
895 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ 895 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
896 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */ 896 mtdcr OCM0_PLBCR2,r3 /* Set PLB Access */
897 isync 897 isync
898 898
899 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ 899 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
900 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l 900 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
901 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ 901 ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */
902 mtdcr OCM0_DSRC1, r3 /* Set Data Side */ 902 mtdcr OCM0_DSRC1, r3 /* Set Data Side */
903 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */ 903 mtdcr OCM0_ISRC1, r3 /* Set Instruction Side */
904 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ 904 ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */
905 mtdcr OCM0_DSRC2, r3 /* Set Data Side */ 905 mtdcr OCM0_DSRC2, r3 /* Set Data Side */
906 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */ 906 mtdcr OCM0_ISRC2, r3 /* Set Instruction Side */
907 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ 907 addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */
908 mtdcr OCM0_DISDPC,r3 908 mtdcr OCM0_DISDPC,r3
909 909
910 isync 910 isync
911 #else /* CONFIG_405EZ */ 911 #else /* CONFIG_405EZ */
912 /******************************************************************** 912 /********************************************************************
913 * Setup OCM - On Chip Memory 913 * Setup OCM - On Chip Memory
914 *******************************************************************/ 914 *******************************************************************/
915 /* Setup OCM */ 915 /* Setup OCM */
916 lis r0, 0x7FFF 916 lis r0, 0x7FFF
917 ori r0, r0, 0xFFFF 917 ori r0, r0, 0xFFFF
918 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */ 918 mfdcr r3, OCM0_ISCNTL /* get instr-side IRAM config */
919 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */ 919 mfdcr r4, OCM0_DSCNTL /* get data-side IRAM config */
920 and r3, r3, r0 /* disable data-side IRAM */ 920 and r3, r3, r0 /* disable data-side IRAM */
921 and r4, r4, r0 /* disable data-side IRAM */ 921 and r4, r4, r0 /* disable data-side IRAM */
922 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */ 922 mtdcr OCM0_ISCNTL, r3 /* set instr-side IRAM config */
923 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */ 923 mtdcr OCM0_DSCNTL, r4 /* set data-side IRAM config */
924 isync 924 isync
925 925
926 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */ 926 lis r3,CONFIG_SYS_OCM_DATA_ADDR@h /* OCM location */
927 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l 927 ori r3,r3,CONFIG_SYS_OCM_DATA_ADDR@l
928 mtdcr OCM0_DSARC, r3 928 mtdcr OCM0_DSARC, r3
929 addis r4, 0, 0xC000 /* OCM data area enabled */ 929 addis r4, 0, 0xC000 /* OCM data area enabled */
930 mtdcr OCM0_DSCNTL, r4 930 mtdcr OCM0_DSCNTL, r4
931 isync 931 isync
932 #endif /* CONFIG_405EZ */ 932 #endif /* CONFIG_405EZ */
933 #endif 933 #endif
934 934
935 /*----------------------------------------------------------------------- */ 935 /*----------------------------------------------------------------------- */
936 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ 936 /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */
937 /*----------------------------------------------------------------------- */ 937 /*----------------------------------------------------------------------- */
938 #ifdef CONFIG_SYS_INIT_DCACHE_CS 938 #ifdef CONFIG_SYS_INIT_DCACHE_CS
939 li r4, PBxAP 939 li r4, PBxAP
940 mtdcr EBC0_CFGADDR, r4 940 mtdcr EBC0_CFGADDR, r4
941 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h 941 lis r4, CONFIG_SYS_INIT_DCACHE_PBxAR@h
942 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l 942 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxAR@l
943 mtdcr EBC0_CFGDATA, r4 943 mtdcr EBC0_CFGDATA, r4
944 944
945 addi r4, 0, PBxCR 945 addi r4, 0, PBxCR
946 mtdcr EBC0_CFGADDR, r4 946 mtdcr EBC0_CFGADDR, r4
947 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h 947 lis r4, CONFIG_SYS_INIT_DCACHE_PBxCR@h
948 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l 948 ori r4, r4, CONFIG_SYS_INIT_DCACHE_PBxCR@l
949 mtdcr EBC0_CFGDATA, r4 949 mtdcr EBC0_CFGDATA, r4
950 950
951 /* 951 /*
952 * Enable the data cache for the 128MB storage access control region 952 * Enable the data cache for the 128MB storage access control region
953 * at CONFIG_SYS_INIT_RAM_ADDR. 953 * at CONFIG_SYS_INIT_RAM_ADDR.
954 */ 954 */
955 mfdccr r4 955 mfdccr r4
956 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h 956 oris r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
957 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l 957 ori r4, r4, PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
958 mtdccr r4 958 mtdccr r4
959 959
960 /* 960 /*
961 * Preallocate data cache lines to be used to avoid a subsequent 961 * Preallocate data cache lines to be used to avoid a subsequent
962 * cache miss and an ensuing machine check exception when exceptions 962 * cache miss and an ensuing machine check exception when exceptions
963 * are enabled. 963 * are enabled.
964 */ 964 */
965 li r0, 0 965 li r0, 0
966 966
967 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h 967 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
968 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l 968 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
969 969
970 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h 970 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
971 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l 971 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
972 972
973 /* 973 /*
974 * Convert the size, in bytes, to the number of cache lines/blocks 974 * Convert the size, in bytes, to the number of cache lines/blocks
975 * to preallocate. 975 * to preallocate.
976 */ 976 */
977 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) 977 clrlwi. r5, r4, (32 - L1_CACHE_SHIFT)
978 srwi r5, r4, L1_CACHE_SHIFT 978 srwi r5, r4, L1_CACHE_SHIFT
979 beq ..load_counter 979 beq ..load_counter
980 addi r5, r5, 0x0001 980 addi r5, r5, 0x0001
981 ..load_counter: 981 ..load_counter:
982 mtctr r5 982 mtctr r5
983 983
984 /* Preallocate the computed number of cache blocks. */ 984 /* Preallocate the computed number of cache blocks. */
985 ..alloc_dcache_block: 985 ..alloc_dcache_block:
986 dcba r0, r3 986 dcba r0, r3
987 addi r3, r3, L1_CACHE_BYTES 987 addi r3, r3, L1_CACHE_BYTES
988 bdnz ..alloc_dcache_block 988 bdnz ..alloc_dcache_block
989 sync 989 sync
990 990
991 /* 991 /*
992 * Load the initial stack pointer and data area and convert the size, 992 * Load the initial stack pointer and data area and convert the size,
993 * in bytes, to the number of words to initialize to a known value. 993 * in bytes, to the number of words to initialize to a known value.
994 */ 994 */
995 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h 995 lis r1, CONFIG_SYS_INIT_RAM_ADDR@h
996 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l 996 ori r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
997 997
998 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h 998 lis r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@h
999 ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l 999 ori r4, r4, (CONFIG_SYS_INIT_RAM_SIZE >> 2)@l
1000 mtctr r4 1000 mtctr r4
1001 1001
1002 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h 1002 lis r2, CONFIG_SYS_INIT_RAM_ADDR@h
1003 ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l 1003 ori r2, r2, CONFIG_SYS_INIT_RAM_SIZE@l
1004 1004
1005 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h 1005 lis r4, CONFIG_SYS_INIT_RAM_PATTERN@h
1006 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l 1006 ori r4, r4, CONFIG_SYS_INIT_RAM_PATTERN@l
1007 1007
1008 ..stackloop: 1008 ..stackloop:
1009 stwu r4, -4(r2) 1009 stwu r4, -4(r2)
1010 bdnz ..stackloop 1010 bdnz ..stackloop
1011 1011
1012 /* 1012 /*
1013 * Make room for stack frame header and clear final stack frame so 1013 * Make room for stack frame header and clear final stack frame so
1014 * that stack backtraces terminate cleanly. 1014 * that stack backtraces terminate cleanly.
1015 */ 1015 */
1016 stwu r0, -4(r1) 1016 stwu r0, -4(r1)
1017 stwu r0, -4(r1) 1017 stwu r0, -4(r1)
1018 1018
1019 /* 1019 /*
1020 * Set up a dummy frame to store reset vector as return address. 1020 * Set up a dummy frame to store reset vector as return address.
1021 * this causes stack underflow to reset board. 1021 * this causes stack underflow to reset board.
1022 */ 1022 */
1023 stwu r1, -8(r1) /* Save back chain and move SP */ 1023 stwu r1, -8(r1) /* Save back chain and move SP */
1024 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */ 1024 addis r0, 0, RESET_VECTOR@h /* Address of reset vector */
1025 ori r0, r0, RESET_VECTOR@l 1025 ori r0, r0, RESET_VECTOR@l
1026 stwu r1, -8(r1) /* Save back chain and move SP */ 1026 stwu r1, -8(r1) /* Save back chain and move SP */
1027 stw r0, +12(r1) /* Save return addr (underflow vect) */ 1027 stw r0, +12(r1) /* Save return addr (underflow vect) */
1028 1028
1029 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \ 1029 #elif defined(CONFIG_SYS_TEMP_STACK_OCM) && \
1030 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE)) 1030 (defined(CONFIG_SYS_OCM_DATA_ADDR) && defined(CONFIG_SYS_OCM_DATA_SIZE))
1031 /* 1031 /*
1032 * Stack in OCM. 1032 * Stack in OCM.
1033 */ 1033 */
1034 1034
1035 /* Set up Stack at top of OCM */ 1035 /* Set up Stack at top of OCM */
1036 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h 1036 lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@h
1037 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l 1037 ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)@l
1038 1038
1039 /* Set up a zeroized stack frame so that backtrace works right */ 1039 /* Set up a zeroized stack frame so that backtrace works right */
1040 li r0, 0 1040 li r0, 0
1041 stwu r0, -4(r1) 1041 stwu r0, -4(r1)
1042 stwu r0, -4(r1) 1042 stwu r0, -4(r1)
1043 1043
1044 /* 1044 /*
1045 * Set up a dummy frame to store reset vector as return address. 1045 * Set up a dummy frame to store reset vector as return address.
1046 * this causes stack underflow to reset board. 1046 * this causes stack underflow to reset board.
1047 */ 1047 */
1048 stwu r1, -8(r1) /* Save back chain and move SP */ 1048 stwu r1, -8(r1) /* Save back chain and move SP */
1049 lis r0, RESET_VECTOR@h /* Address of reset vector */ 1049 lis r0, RESET_VECTOR@h /* Address of reset vector */
1050 ori r0, r0, RESET_VECTOR@l 1050 ori r0, r0, RESET_VECTOR@l
1051 stwu r1, -8(r1) /* Save back chain and move SP */ 1051 stwu r1, -8(r1) /* Save back chain and move SP */
1052 stw r0, +12(r1) /* Save return addr (underflow vect) */ 1052 stw r0, +12(r1) /* Save return addr (underflow vect) */
1053 #endif /* CONFIG_SYS_INIT_DCACHE_CS */ 1053 #endif /* CONFIG_SYS_INIT_DCACHE_CS */
1054 1054
1055 #ifdef CONFIG_NAND_SPL 1055 #ifdef CONFIG_NAND_SPL
1056 bl nand_boot_common /* will not return */ 1056 bl nand_boot_common /* will not return */
1057 #else 1057 #else
1058 GET_GOT /* initialize GOT access */ 1058 GET_GOT /* initialize GOT access */
1059 1059
1060 bl cpu_init_f /* run low-level CPU init code (from Flash) */ 1060 bl cpu_init_f /* run low-level CPU init code (from Flash) */
1061 1061
1062 bl board_init_f /* run first part of init code (from Flash) */ 1062 bl board_init_f /* run first part of init code (from Flash) */
1063 /* NOTREACHED - board_init_f() does not return */ 1063 /* NOTREACHED - board_init_f() does not return */
1064 1064
1065 #endif /* CONFIG_NAND_SPL */ 1065 #endif /* CONFIG_NAND_SPL */
1066 1066
1067 #endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */ 1067 #endif /* CONFIG_405GP || CONFIG_405 || CONFIG_405EP */
1068 /*----------------------------------------------------------------------- */ 1068 /*----------------------------------------------------------------------- */
1069 1069
1070 1070
1071 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD) 1071 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
1072 /* 1072 /*
1073 * This code finishes saving the registers to the exception frame 1073 * This code finishes saving the registers to the exception frame
1074 * and jumps to the appropriate handler for the exception. 1074 * and jumps to the appropriate handler for the exception.
1075 * Register r21 is pointer into trap frame, r1 has new stack pointer. 1075 * Register r21 is pointer into trap frame, r1 has new stack pointer.
1076 */ 1076 */
1077 .globl transfer_to_handler 1077 .globl transfer_to_handler
1078 transfer_to_handler: 1078 transfer_to_handler:
1079 stw r22,_NIP(r21) 1079 stw r22,_NIP(r21)
1080 lis r22,MSR_POW@h 1080 lis r22,MSR_POW@h
1081 andc r23,r23,r22 1081 andc r23,r23,r22
1082 stw r23,_MSR(r21) 1082 stw r23,_MSR(r21)
1083 SAVE_GPR(7, r21) 1083 SAVE_GPR(7, r21)
1084 SAVE_4GPRS(8, r21) 1084 SAVE_4GPRS(8, r21)
1085 SAVE_8GPRS(12, r21) 1085 SAVE_8GPRS(12, r21)
1086 SAVE_8GPRS(24, r21) 1086 SAVE_8GPRS(24, r21)
1087 mflr r23 1087 mflr r23
1088 andi. r24,r23,0x3f00 /* get vector offset */ 1088 andi. r24,r23,0x3f00 /* get vector offset */
1089 stw r24,TRAP(r21) 1089 stw r24,TRAP(r21)
1090 li r22,0 1090 li r22,0
1091 stw r22,RESULT(r21) 1091 stw r22,RESULT(r21)
1092 mtspr SPRG2,r22 /* r1 is now kernel sp */ 1092 mtspr SPRG2,r22 /* r1 is now kernel sp */
1093 lwz r24,0(r23) /* virtual address of handler */ 1093 lwz r24,0(r23) /* virtual address of handler */
1094 lwz r23,4(r23) /* where to go when done */ 1094 lwz r23,4(r23) /* where to go when done */
1095 mtspr SRR0,r24 1095 mtspr SRR0,r24
1096 mtspr SRR1,r20 1096 mtspr SRR1,r20
1097 mtlr r23 1097 mtlr r23
1098 SYNC 1098 SYNC
1099 rfi /* jump to handler, enable MMU */ 1099 rfi /* jump to handler, enable MMU */
1100 1100
1101 int_return: 1101 int_return:
1102 mfmsr r28 /* Disable interrupts */ 1102 mfmsr r28 /* Disable interrupts */
1103 li r4,0 1103 li r4,0
1104 ori r4,r4,MSR_EE 1104 ori r4,r4,MSR_EE
1105 andc r28,r28,r4 1105 andc r28,r28,r4
1106 SYNC /* Some chip revs need this... */ 1106 SYNC /* Some chip revs need this... */
1107 mtmsr r28 1107 mtmsr r28
1108 SYNC 1108 SYNC
1109 lwz r2,_CTR(r1) 1109 lwz r2,_CTR(r1)
1110 lwz r0,_LINK(r1) 1110 lwz r0,_LINK(r1)
1111 mtctr r2 1111 mtctr r2
1112 mtlr r0 1112 mtlr r0
1113 lwz r2,_XER(r1) 1113 lwz r2,_XER(r1)
1114 lwz r0,_CCR(r1) 1114 lwz r0,_CCR(r1)
1115 mtspr XER,r2 1115 mtspr XER,r2
1116 mtcrf 0xFF,r0 1116 mtcrf 0xFF,r0
1117 REST_10GPRS(3, r1) 1117 REST_10GPRS(3, r1)
1118 REST_10GPRS(13, r1) 1118 REST_10GPRS(13, r1)
1119 REST_8GPRS(23, r1) 1119 REST_8GPRS(23, r1)
1120 REST_GPR(31, r1) 1120 REST_GPR(31, r1)
1121 lwz r2,_NIP(r1) /* Restore environment */ 1121 lwz r2,_NIP(r1) /* Restore environment */
1122 lwz r0,_MSR(r1) 1122 lwz r0,_MSR(r1)
1123 mtspr SRR0,r2 1123 mtspr SRR0,r2
1124 mtspr SRR1,r0 1124 mtspr SRR1,r0
1125 lwz r0,GPR0(r1) 1125 lwz r0,GPR0(r1)
1126 lwz r2,GPR2(r1) 1126 lwz r2,GPR2(r1)
1127 lwz r1,GPR1(r1) 1127 lwz r1,GPR1(r1)
1128 SYNC 1128 SYNC
1129 rfi 1129 rfi
1130 1130
1131 crit_return: 1131 crit_return:
1132 mfmsr r28 /* Disable interrupts */ 1132 mfmsr r28 /* Disable interrupts */
1133 li r4,0 1133 li r4,0
1134 ori r4,r4,MSR_EE 1134 ori r4,r4,MSR_EE
1135 andc r28,r28,r4 1135 andc r28,r28,r4
1136 SYNC /* Some chip revs need this... */ 1136 SYNC /* Some chip revs need this... */
1137 mtmsr r28 1137 mtmsr r28
1138 SYNC 1138 SYNC
1139 lwz r2,_CTR(r1) 1139 lwz r2,_CTR(r1)
1140 lwz r0,_LINK(r1) 1140 lwz r0,_LINK(r1)
1141 mtctr r2 1141 mtctr r2
1142 mtlr r0 1142 mtlr r0
1143 lwz r2,_XER(r1) 1143 lwz r2,_XER(r1)
1144 lwz r0,_CCR(r1) 1144 lwz r0,_CCR(r1)
1145 mtspr XER,r2 1145 mtspr XER,r2
1146 mtcrf 0xFF,r0 1146 mtcrf 0xFF,r0
1147 REST_10GPRS(3, r1) 1147 REST_10GPRS(3, r1)
1148 REST_10GPRS(13, r1) 1148 REST_10GPRS(13, r1)
1149 REST_8GPRS(23, r1) 1149 REST_8GPRS(23, r1)
1150 REST_GPR(31, r1) 1150 REST_GPR(31, r1)
1151 lwz r2,_NIP(r1) /* Restore environment */ 1151 lwz r2,_NIP(r1) /* Restore environment */
1152 lwz r0,_MSR(r1) 1152 lwz r0,_MSR(r1)
1153 mtspr SPRN_CSRR0,r2 1153 mtspr SPRN_CSRR0,r2
1154 mtspr SPRN_CSRR1,r0 1154 mtspr SPRN_CSRR1,r0
1155 lwz r0,GPR0(r1) 1155 lwz r0,GPR0(r1)
1156 lwz r2,GPR2(r1) 1156 lwz r2,GPR2(r1)
1157 lwz r1,GPR1(r1) 1157 lwz r1,GPR1(r1)
1158 SYNC 1158 SYNC
1159 rfci 1159 rfci
1160 1160
1161 #ifdef CONFIG_440 1161 #ifdef CONFIG_440
1162 mck_return: 1162 mck_return:
1163 mfmsr r28 /* Disable interrupts */ 1163 mfmsr r28 /* Disable interrupts */
1164 li r4,0 1164 li r4,0
1165 ori r4,r4,MSR_EE 1165 ori r4,r4,MSR_EE
1166 andc r28,r28,r4 1166 andc r28,r28,r4
1167 SYNC /* Some chip revs need this... */ 1167 SYNC /* Some chip revs need this... */
1168 mtmsr r28 1168 mtmsr r28
1169 SYNC 1169 SYNC
1170 lwz r2,_CTR(r1) 1170 lwz r2,_CTR(r1)
1171 lwz r0,_LINK(r1) 1171 lwz r0,_LINK(r1)
1172 mtctr r2 1172 mtctr r2
1173 mtlr r0 1173 mtlr r0
1174 lwz r2,_XER(r1) 1174 lwz r2,_XER(r1)
1175 lwz r0,_CCR(r1) 1175 lwz r0,_CCR(r1)
1176 mtspr XER,r2 1176 mtspr XER,r2
1177 mtcrf 0xFF,r0 1177 mtcrf 0xFF,r0
1178 REST_10GPRS(3, r1) 1178 REST_10GPRS(3, r1)
1179 REST_10GPRS(13, r1) 1179 REST_10GPRS(13, r1)
1180 REST_8GPRS(23, r1) 1180 REST_8GPRS(23, r1)
1181 REST_GPR(31, r1) 1181 REST_GPR(31, r1)
1182 lwz r2,_NIP(r1) /* Restore environment */ 1182 lwz r2,_NIP(r1) /* Restore environment */
1183 lwz r0,_MSR(r1) 1183 lwz r0,_MSR(r1)
1184 mtspr SPRN_MCSRR0,r2 1184 mtspr SPRN_MCSRR0,r2
1185 mtspr SPRN_MCSRR1,r0 1185 mtspr SPRN_MCSRR1,r0
1186 lwz r0,GPR0(r1) 1186 lwz r0,GPR0(r1)
1187 lwz r2,GPR2(r1) 1187 lwz r2,GPR2(r1)
1188 lwz r1,GPR1(r1) 1188 lwz r1,GPR1(r1)
1189 SYNC 1189 SYNC
1190 rfmci 1190 rfmci
1191 #endif /* CONFIG_440 */ 1191 #endif /* CONFIG_440 */
1192 1192
1193 1193
1194 .globl get_pvr 1194 .globl get_pvr
1195 get_pvr: 1195 get_pvr:
1196 mfspr r3, PVR 1196 mfspr r3, PVR
1197 blr 1197 blr
1198 1198
1199 /*------------------------------------------------------------------------------- */ 1199 /*------------------------------------------------------------------------------- */
1200 /* Function: out16 */ 1200 /* Function: out16 */
1201 /* Description: Output 16 bits */ 1201 /* Description: Output 16 bits */
1202 /*------------------------------------------------------------------------------- */ 1202 /*------------------------------------------------------------------------------- */
1203 .globl out16 1203 .globl out16
1204 out16: 1204 out16:
1205 sth r4,0x0000(r3) 1205 sth r4,0x0000(r3)
1206 blr 1206 blr
1207 1207
1208 /*------------------------------------------------------------------------------- */ 1208 /*------------------------------------------------------------------------------- */
1209 /* Function: out16r */ 1209 /* Function: out16r */
1210 /* Description: Byte reverse and output 16 bits */ 1210 /* Description: Byte reverse and output 16 bits */
1211 /*------------------------------------------------------------------------------- */ 1211 /*------------------------------------------------------------------------------- */
1212 .globl out16r 1212 .globl out16r
1213 out16r: 1213 out16r:
1214 sthbrx r4,r0,r3 1214 sthbrx r4,r0,r3
1215 blr 1215 blr
1216 1216
1217 /*------------------------------------------------------------------------------- */ 1217 /*------------------------------------------------------------------------------- */
1218 /* Function: out32r */ 1218 /* Function: out32r */
1219 /* Description: Byte reverse and output 32 bits */ 1219 /* Description: Byte reverse and output 32 bits */
1220 /*------------------------------------------------------------------------------- */ 1220 /*------------------------------------------------------------------------------- */
1221 .globl out32r 1221 .globl out32r
1222 out32r: 1222 out32r:
1223 stwbrx r4,r0,r3 1223 stwbrx r4,r0,r3
1224 blr 1224 blr
1225 1225
1226 /*------------------------------------------------------------------------------- */ 1226 /*------------------------------------------------------------------------------- */
1227 /* Function: in16 */ 1227 /* Function: in16 */
1228 /* Description: Input 16 bits */ 1228 /* Description: Input 16 bits */
1229 /*------------------------------------------------------------------------------- */ 1229 /*------------------------------------------------------------------------------- */
1230 .globl in16 1230 .globl in16
1231 in16: 1231 in16:
1232 lhz r3,0x0000(r3) 1232 lhz r3,0x0000(r3)
1233 blr 1233 blr
1234 1234
1235 /*------------------------------------------------------------------------------- */ 1235 /*------------------------------------------------------------------------------- */
1236 /* Function: in16r */ 1236 /* Function: in16r */
1237 /* Description: Input 16 bits and byte reverse */ 1237 /* Description: Input 16 bits and byte reverse */
1238 /*------------------------------------------------------------------------------- */ 1238 /*------------------------------------------------------------------------------- */
1239 .globl in16r 1239 .globl in16r
1240 in16r: 1240 in16r:
1241 lhbrx r3,r0,r3 1241 lhbrx r3,r0,r3
1242 blr 1242 blr
1243 1243
1244 /*------------------------------------------------------------------------------- */ 1244 /*------------------------------------------------------------------------------- */
1245 /* Function: in32r */ 1245 /* Function: in32r */
1246 /* Description: Input 32 bits and byte reverse */ 1246 /* Description: Input 32 bits and byte reverse */
1247 /*------------------------------------------------------------------------------- */ 1247 /*------------------------------------------------------------------------------- */
1248 .globl in32r 1248 .globl in32r
1249 in32r: 1249 in32r:
1250 lwbrx r3,r0,r3 1250 lwbrx r3,r0,r3
1251 blr 1251 blr
1252 1252
1253 #if !defined(CONFIG_SPL_BUILD) 1253 #if !defined(CONFIG_SPL_BUILD)
1254 /* 1254 /*
1255 * void relocate_code (addr_sp, gd, addr_moni) 1255 * void relocate_code (addr_sp, gd, addr_moni)
1256 * 1256 *
1257 * This "function" does not return, instead it continues in RAM 1257 * This "function" does not return, instead it continues in RAM
1258 * after relocating the monitor code. 1258 * after relocating the monitor code.
1259 * 1259 *
1260 * r3 = Relocated stack pointer 1260 * r3 = Relocated stack pointer
1261 * r4 = Relocated global data pointer 1261 * r4 = Relocated global data pointer
1262 * r5 = Relocated text pointer 1262 * r5 = Relocated text pointer
1263 */ 1263 */
1264 .globl relocate_code 1264 .globl relocate_code
1265 relocate_code: 1265 relocate_code:
1266 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) 1266 #if defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS)
1267 /* 1267 /*
1268 * We need to flush the initial global data (gd_t) and bd_info 1268 * We need to flush the initial global data (gd_t) and bd_info
1269 * before the dcache will be invalidated. 1269 * before the dcache will be invalidated.
1270 */ 1270 */
1271 1271
1272 /* Save registers */ 1272 /* Save registers */
1273 mr r9, r3 1273 mr r9, r3
1274 mr r10, r4 1274 mr r10, r4
1275 mr r11, r5 1275 mr r11, r5
1276 1276
1277 /* 1277 /*
1278 * Flush complete dcache, this is faster than flushing the 1278 * Flush complete dcache, this is faster than flushing the
1279 * ranges for global_data and bd_info instead. 1279 * ranges for global_data and bd_info instead.
1280 */ 1280 */
1281 bl flush_dcache 1281 bl flush_dcache
1282 1282
1283 #if defined(CONFIG_SYS_INIT_DCACHE_CS) 1283 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
1284 /* 1284 /*
1285 * Undo the earlier data cache set-up for the primordial stack and 1285 * Undo the earlier data cache set-up for the primordial stack and
1286 * data area. First, invalidate the data cache and then disable data 1286 * data area. First, invalidate the data cache and then disable data
1287 * cacheability for that area. Finally, restore the EBC values, if 1287 * cacheability for that area. Finally, restore the EBC values, if
1288 * any. 1288 * any.
1289 */ 1289 */
1290 1290
1291 /* Invalidate the primordial stack and data area in cache */ 1291 /* Invalidate the primordial stack and data area in cache */
1292 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h 1292 lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
1293 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l 1293 ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
1294 1294
1295 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h 1295 lis r4, CONFIG_SYS_INIT_RAM_SIZE@h
1296 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l 1296 ori r4, r4, CONFIG_SYS_INIT_RAM_SIZE@l
1297 add r4, r4, r3 1297 add r4, r4, r3
1298 1298
1299 bl invalidate_dcache_range 1299 bl invalidate_dcache_range
1300 1300
1301 /* Disable cacheability for the region */ 1301 /* Disable cacheability for the region */
1302 mfdccr r3 1302 mfdccr r3
1303 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h 1303 lis r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@h
1304 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l 1304 ori r4, r4, ~PPC_128MB_SACR_VALUE(CONFIG_SYS_INIT_RAM_ADDR)@l
1305 and r3, r3, r4 1305 and r3, r3, r4
1306 mtdccr r3 1306 mtdccr r3
1307 1307
1308 /* Restore the EBC parameters */ 1308 /* Restore the EBC parameters */
1309 li r3, PBxAP 1309 li r3, PBxAP
1310 mtdcr EBC0_CFGADDR, r3 1310 mtdcr EBC0_CFGADDR, r3
1311 lis r3, PBxAP_VAL@h 1311 lis r3, PBxAP_VAL@h
1312 ori r3, r3, PBxAP_VAL@l 1312 ori r3, r3, PBxAP_VAL@l
1313 mtdcr EBC0_CFGDATA, r3 1313 mtdcr EBC0_CFGDATA, r3
1314 1314
1315 li r3, PBxCR 1315 li r3, PBxCR
1316 mtdcr EBC0_CFGADDR, r3 1316 mtdcr EBC0_CFGADDR, r3
1317 lis r3, PBxCR_VAL@h 1317 lis r3, PBxCR_VAL@h
1318 ori r3, r3, PBxCR_VAL@l 1318 ori r3, r3, PBxCR_VAL@l
1319 mtdcr EBC0_CFGDATA, r3 1319 mtdcr EBC0_CFGDATA, r3
1320 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */ 1320 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
1321 1321
1322 /* Restore registers */ 1322 /* Restore registers */
1323 mr r3, r9 1323 mr r3, r9
1324 mr r4, r10 1324 mr r4, r10
1325 mr r5, r11 1325 mr r5, r11
1326 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */ 1326 #endif /* defined(CONFIG_4xx_DCACHE) || defined(CONFIG_SYS_INIT_DCACHE_CS) */
1327 1327
1328 #ifdef CONFIG_SYS_INIT_RAM_DCACHE 1328 #ifdef CONFIG_SYS_INIT_RAM_DCACHE
1329 /* 1329 /*
1330 * Unlock the previously locked d-cache 1330 * Unlock the previously locked d-cache
1331 */ 1331 */
1332 msync 1332 msync
1333 isync 1333 isync
1334 /* set TFLOOR/NFLOOR to 0 again */ 1334 /* set TFLOOR/NFLOOR to 0 again */
1335 lis r6,0x0001 1335 lis r6,0x0001
1336 ori r6,r6,0xf800 1336 ori r6,r6,0xf800
1337 mtspr SPRN_DVLIM,r6 1337 mtspr SPRN_DVLIM,r6
1338 lis r6,0x0000 1338 lis r6,0x0000
1339 ori r6,r6,0x0000 1339 ori r6,r6,0x0000
1340 mtspr SPRN_DNV0,r6 1340 mtspr SPRN_DNV0,r6
1341 mtspr SPRN_DNV1,r6 1341 mtspr SPRN_DNV1,r6
1342 mtspr SPRN_DNV2,r6 1342 mtspr SPRN_DNV2,r6
1343 mtspr SPRN_DNV3,r6 1343 mtspr SPRN_DNV3,r6
1344 mtspr SPRN_DTV0,r6 1344 mtspr SPRN_DTV0,r6
1345 mtspr SPRN_DTV1,r6 1345 mtspr SPRN_DTV1,r6
1346 mtspr SPRN_DTV2,r6 1346 mtspr SPRN_DTV2,r6
1347 mtspr SPRN_DTV3,r6 1347 mtspr SPRN_DTV3,r6
1348 msync 1348 msync
1349 isync 1349 isync
1350 1350
1351 /* Invalidate data cache, now no longer our stack */ 1351 /* Invalidate data cache, now no longer our stack */
1352 dccci 0,0 1352 dccci 0,0
1353 sync 1353 sync
1354 isync 1354 isync
1355 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */ 1355 #endif /* CONFIG_SYS_INIT_RAM_DCACHE */
1356 1356
1357 /* 1357 /*
1358 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS) 1358 * On some 440er platforms the cache is enabled in the first TLB (Boot-CS)
1359 * to speed up the boot process. Now this cache needs to be disabled. 1359 * to speed up the boot process. Now this cache needs to be disabled.
1360 */ 1360 */
1361 #if defined(CONFIG_440) 1361 #if defined(CONFIG_440)
1362 /* Clear all potential pending exceptions */ 1362 /* Clear all potential pending exceptions */
1363 mfspr r1,SPRN_MCSR 1363 mfspr r1,SPRN_MCSR
1364 mtspr SPRN_MCSR,r1 1364 mtspr SPRN_MCSR,r1
1365 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */ 1365 addi r1,r0,CONFIG_SYS_TLB_FOR_BOOT_FLASH /* Use defined TLB */
1366 tlbre r0,r1,0x0002 /* Read contents */ 1366 tlbre r0,r1,0x0002 /* Read contents */
1367 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */ 1367 ori r0,r0,0x0c00 /* Or in the inhibit, write through bit */
1368 tlbwe r0,r1,0x0002 /* Save it out */ 1368 tlbwe r0,r1,0x0002 /* Save it out */
1369 sync 1369 sync
1370 isync 1370 isync
1371 #endif /* defined(CONFIG_440) */ 1371 #endif /* defined(CONFIG_440) */
1372 mr r1, r3 /* Set new stack pointer */ 1372 mr r1, r3 /* Set new stack pointer */
1373 mr r9, r4 /* Save copy of Init Data pointer */ 1373 mr r9, r4 /* Save copy of Init Data pointer */
1374 mr r10, r5 /* Save copy of Destination Address */ 1374 mr r10, r5 /* Save copy of Destination Address */
1375 1375
1376 GET_GOT 1376 GET_GOT
1377 mr r3, r5 /* Destination Address */ 1377 mr r3, r5 /* Destination Address */
1378 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */ 1378 lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
1379 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l 1379 ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
1380 lwz r5, GOT(__init_end) 1380 lwz r5, GOT(__init_end)
1381 sub r5, r5, r4 1381 sub r5, r5, r4
1382 li r6, L1_CACHE_BYTES /* Cache Line Size */ 1382 li r6, L1_CACHE_BYTES /* Cache Line Size */
1383 1383
1384 /* 1384 /*
1385 * Fix GOT pointer: 1385 * Fix GOT pointer:
1386 * 1386 *
1387 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address 1387 * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
1388 * 1388 *
1389 * Offset: 1389 * Offset:
1390 */ 1390 */
1391 sub r15, r10, r4 1391 sub r15, r10, r4
1392 1392
1393 /* First our own GOT */ 1393 /* First our own GOT */
1394 add r12, r12, r15 1394 add r12, r12, r15
1395 /* then the one used by the C code */ 1395 /* then the one used by the C code */
1396 add r30, r30, r15 1396 add r30, r30, r15
1397 1397
1398 /* 1398 /*
1399 * Now relocate code 1399 * Now relocate code
1400 */ 1400 */
1401 1401
1402 cmplw cr1,r3,r4 1402 cmplw cr1,r3,r4
1403 addi r0,r5,3 1403 addi r0,r5,3
1404 srwi. r0,r0,2 1404 srwi. r0,r0,2
1405 beq cr1,4f /* In place copy is not necessary */ 1405 beq cr1,4f /* In place copy is not necessary */
1406 beq 7f /* Protect against 0 count */ 1406 beq 7f /* Protect against 0 count */
1407 mtctr r0 1407 mtctr r0
1408 bge cr1,2f 1408 bge cr1,2f
1409 1409
1410 la r8,-4(r4) 1410 la r8,-4(r4)
1411 la r7,-4(r3) 1411 la r7,-4(r3)
1412 1: lwzu r0,4(r8) 1412 1: lwzu r0,4(r8)
1413 stwu r0,4(r7) 1413 stwu r0,4(r7)
1414 bdnz 1b 1414 bdnz 1b
1415 b 4f 1415 b 4f
1416 1416
1417 2: slwi r0,r0,2 1417 2: slwi r0,r0,2
1418 add r8,r4,r0 1418 add r8,r4,r0
1419 add r7,r3,r0 1419 add r7,r3,r0
1420 3: lwzu r0,-4(r8) 1420 3: lwzu r0,-4(r8)
1421 stwu r0,-4(r7) 1421 stwu r0,-4(r7)
1422 bdnz 3b 1422 bdnz 3b
1423 1423
1424 /* 1424 /*
1425 * Now flush the cache: note that we must start from a cache aligned 1425 * Now flush the cache: note that we must start from a cache aligned
1426 * address. Otherwise we might miss one cache line. 1426 * address. Otherwise we might miss one cache line.
1427 */ 1427 */
1428 4: cmpwi r6,0 1428 4: cmpwi r6,0
1429 add r5,r3,r5 1429 add r5,r3,r5
1430 beq 7f /* Always flush prefetch queue in any case */ 1430 beq 7f /* Always flush prefetch queue in any case */
1431 subi r0,r6,1 1431 subi r0,r6,1
1432 andc r3,r3,r0 1432 andc r3,r3,r0
1433 mr r4,r3 1433 mr r4,r3
1434 5: dcbst 0,r4 1434 5: dcbst 0,r4
1435 add r4,r4,r6 1435 add r4,r4,r6
1436 cmplw r4,r5 1436 cmplw r4,r5
1437 blt 5b 1437 blt 5b
1438 sync /* Wait for all dcbst to complete on bus */ 1438 sync /* Wait for all dcbst to complete on bus */
1439 mr r4,r3 1439 mr r4,r3
1440 6: icbi 0,r4 1440 6: icbi 0,r4
1441 add r4,r4,r6 1441 add r4,r4,r6
1442 cmplw r4,r5 1442 cmplw r4,r5
1443 blt 6b 1443 blt 6b
1444 7: sync /* Wait for all icbi to complete on bus */ 1444 7: sync /* Wait for all icbi to complete on bus */
1445 isync 1445 isync
1446 1446
1447 /* 1447 /*
1448 * We are done. Do not return, instead branch to second part of board 1448 * We are done. Do not return, instead branch to second part of board
1449 * initialization, now running from RAM. 1449 * initialization, now running from RAM.
1450 */ 1450 */
1451 1451
1452 addi r0, r10, in_ram - _start + _START_OFFSET 1452 addi r0, r10, in_ram - _start + _START_OFFSET
1453 mtlr r0 1453 mtlr r0
1454 blr /* NEVER RETURNS! */ 1454 blr /* NEVER RETURNS! */
1455 1455
1456 in_ram: 1456 in_ram:
1457 1457
1458 /* 1458 /*
1459 * Relocation Function, r12 point to got2+0x8000 1459 * Relocation Function, r12 point to got2+0x8000
1460 * 1460 *
1461 * Adjust got2 pointers, no need to check for 0, this code 1461 * Adjust got2 pointers, no need to check for 0, this code
1462 * already puts a few entries in the table. 1462 * already puts a few entries in the table.
1463 */ 1463 */
1464 li r0,__got2_entries@sectoff@l 1464 li r0,__got2_entries@sectoff@l
1465 la r3,GOT(_GOT2_TABLE_) 1465 la r3,GOT(_GOT2_TABLE_)
1466 lwz r11,GOT(_GOT2_TABLE_) 1466 lwz r11,GOT(_GOT2_TABLE_)
1467 mtctr r0 1467 mtctr r0
1468 sub r11,r3,r11 1468 sub r11,r3,r11
1469 addi r3,r3,-4 1469 addi r3,r3,-4
1470 1: lwzu r0,4(r3) 1470 1: lwzu r0,4(r3)
1471 cmpwi r0,0 1471 cmpwi r0,0
1472 beq- 2f 1472 beq- 2f
1473 add r0,r0,r11 1473 add r0,r0,r11
1474 stw r0,0(r3) 1474 stw r0,0(r3)
1475 2: bdnz 1b 1475 2: bdnz 1b
1476 1476
1477 /* 1477 /*
1478 * Now adjust the fixups and the pointers to the fixups 1478 * Now adjust the fixups and the pointers to the fixups
1479 * in case we need to move ourselves again. 1479 * in case we need to move ourselves again.
1480 */ 1480 */
1481 li r0,__fixup_entries@sectoff@l 1481 li r0,__fixup_entries@sectoff@l
1482 lwz r3,GOT(_FIXUP_TABLE_) 1482 lwz r3,GOT(_FIXUP_TABLE_)
1483 cmpwi r0,0 1483 cmpwi r0,0
1484 mtctr r0 1484 mtctr r0
1485 addi r3,r3,-4 1485 addi r3,r3,-4
1486 beq 4f 1486 beq 4f
1487 3: lwzu r4,4(r3) 1487 3: lwzu r4,4(r3)
1488 lwzux r0,r4,r11 1488 lwzux r0,r4,r11
1489 cmpwi r0,0 1489 cmpwi r0,0
1490 add r0,r0,r11 1490 add r0,r0,r11
1491 stw r4,0(r3) 1491 stw r4,0(r3)
1492 beq- 5f 1492 beq- 5f
1493 stw r0,0(r4) 1493 stw r0,0(r4)
1494 5: bdnz 3b 1494 5: bdnz 3b
1495 4: 1495 4:
1496 clear_bss: 1496 clear_bss:
1497 /* 1497 /*
1498 * Now clear BSS segment 1498 * Now clear BSS segment
1499 */ 1499 */
1500 lwz r3,GOT(__bss_start) 1500 lwz r3,GOT(__bss_start)
1501 lwz r4,GOT(__bss_end) 1501 lwz r4,GOT(__bss_end)
1502 1502
1503 cmplw 0, r3, r4 1503 cmplw 0, r3, r4
1504 beq 7f 1504 beq 7f
1505 1505
1506 li r0, 0 1506 li r0, 0
1507 1507
1508 andi. r5, r4, 3 1508 andi. r5, r4, 3
1509 beq 6f 1509 beq 6f
1510 sub r4, r4, r5 1510 sub r4, r4, r5
1511 mtctr r5 1511 mtctr r5
1512 mr r5, r4 1512 mr r5, r4
1513 5: stb r0, 0(r5) 1513 5: stb r0, 0(r5)
1514 addi r5, r5, 1 1514 addi r5, r5, 1
1515 bdnz 5b 1515 bdnz 5b
1516 6: 1516 6:
1517 stw r0, 0(r3) 1517 stw r0, 0(r3)
1518 addi r3, r3, 4 1518 addi r3, r3, 4
1519 cmplw 0, r3, r4 1519 cmplw 0, r3, r4
1520 bne 6b 1520 bne 6b
1521 1521
1522 7: 1522 7:
1523 mr r3, r9 /* Init Data pointer */ 1523 mr r3, r9 /* Init Data pointer */
1524 mr r4, r10 /* Destination Address */ 1524 mr r4, r10 /* Destination Address */
1525 bl board_init_r 1525 bl board_init_r
1526 1526
1527 /* 1527 /*
1528 * Copy exception vector code to low memory 1528 * Copy exception vector code to low memory
1529 * 1529 *
1530 * r3: dest_addr 1530 * r3: dest_addr
1531 * r7: source address, r8: end address, r9: target address 1531 * r7: source address, r8: end address, r9: target address
1532 */ 1532 */
1533 .globl trap_init 1533 .globl trap_init
1534 trap_init: 1534 trap_init:
1535 mflr r4 /* save link register */ 1535 mflr r4 /* save link register */
1536 GET_GOT 1536 GET_GOT
1537 lwz r7, GOT(_start_of_vectors) 1537 lwz r7, GOT(_start_of_vectors)
1538 lwz r8, GOT(_end_of_vectors) 1538 lwz r8, GOT(_end_of_vectors)
1539 1539
1540 li r9, 0x100 /* reset vector always at 0x100 */ 1540 li r9, 0x100 /* reset vector always at 0x100 */
1541 1541
1542 cmplw 0, r7, r8 1542 cmplw 0, r7, r8
1543 bgelr /* return if r7>=r8 - just in case */ 1543 bgelr /* return if r7>=r8 - just in case */
1544 1: 1544 1:
1545 lwz r0, 0(r7) 1545 lwz r0, 0(r7)
1546 stw r0, 0(r9) 1546 stw r0, 0(r9)
1547 addi r7, r7, 4 1547 addi r7, r7, 4
1548 addi r9, r9, 4 1548 addi r9, r9, 4
1549 cmplw 0, r7, r8 1549 cmplw 0, r7, r8
1550 bne 1b 1550 bne 1b
1551 1551
1552 /* 1552 /*
1553 * relocate `hdlr' and `int_return' entries 1553 * relocate `hdlr' and `int_return' entries
1554 */ 1554 */
1555 li r7, .L_MachineCheck - _start + _START_OFFSET 1555 li r7, .L_MachineCheck - _start + _START_OFFSET
1556 li r8, Alignment - _start + _START_OFFSET 1556 li r8, Alignment - _start + _START_OFFSET
1557 2: 1557 2:
1558 bl trap_reloc 1558 bl trap_reloc
1559 addi r7, r7, 0x100 /* next exception vector */ 1559 addi r7, r7, 0x100 /* next exception vector */
1560 cmplw 0, r7, r8 1560 cmplw 0, r7, r8
1561 blt 2b 1561 blt 2b
1562 1562
1563 li r7, .L_Alignment - _start + _START_OFFSET 1563 li r7, .L_Alignment - _start + _START_OFFSET
1564 bl trap_reloc 1564 bl trap_reloc
1565 1565
1566 li r7, .L_ProgramCheck - _start + _START_OFFSET 1566 li r7, .L_ProgramCheck - _start + _START_OFFSET
1567 bl trap_reloc 1567 bl trap_reloc
1568 1568
1569 #ifdef CONFIG_440 1569 #ifdef CONFIG_440
1570 li r7, .L_FPUnavailable - _start + _START_OFFSET 1570 li r7, .L_FPUnavailable - _start + _START_OFFSET
1571 bl trap_reloc 1571 bl trap_reloc
1572 1572
1573 li r7, .L_Decrementer - _start + _START_OFFSET 1573 li r7, .L_Decrementer - _start + _START_OFFSET
1574 bl trap_reloc 1574 bl trap_reloc
1575 1575
1576 li r7, .L_APU - _start + _START_OFFSET 1576 li r7, .L_APU - _start + _START_OFFSET
1577 bl trap_reloc 1577 bl trap_reloc
1578 1578
1579 li r7, .L_InstructionTLBError - _start + _START_OFFSET 1579 li r7, .L_InstructionTLBError - _start + _START_OFFSET
1580 bl trap_reloc 1580 bl trap_reloc
1581 1581
1582 li r7, .L_DataTLBError - _start + _START_OFFSET 1582 li r7, .L_DataTLBError - _start + _START_OFFSET
1583 bl trap_reloc 1583 bl trap_reloc
1584 #else /* CONFIG_440 */ 1584 #else /* CONFIG_440 */
1585 li r7, .L_PIT - _start + _START_OFFSET 1585 li r7, .L_PIT - _start + _START_OFFSET
1586 bl trap_reloc 1586 bl trap_reloc
1587 1587
1588 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET 1588 li r7, .L_InstructionTLBMiss - _start + _START_OFFSET
1589 bl trap_reloc 1589 bl trap_reloc
1590 1590
1591 li r7, .L_DataTLBMiss - _start + _START_OFFSET 1591 li r7, .L_DataTLBMiss - _start + _START_OFFSET
1592 bl trap_reloc 1592 bl trap_reloc
1593 #endif /* CONFIG_440 */ 1593 #endif /* CONFIG_440 */
1594 1594
1595 li r7, .L_DebugBreakpoint - _start + _START_OFFSET 1595 li r7, .L_DebugBreakpoint - _start + _START_OFFSET
1596 bl trap_reloc 1596 bl trap_reloc
1597 1597
1598 #if !defined(CONFIG_440) 1598 #if !defined(CONFIG_440)
1599 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ 1599 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1600 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ 1600 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1601 mtmsr r7 /* change MSR */ 1601 mtmsr r7 /* change MSR */
1602 #else 1602 #else
1603 bl __440_msr_set 1603 bl __440_msr_set
1604 b __440_msr_continue 1604 b __440_msr_continue
1605 1605
1606 __440_msr_set: 1606 __440_msr_set:
1607 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */ 1607 addi r7,r0,0x1000 /* set ME bit (Machine Exceptions) */
1608 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */ 1608 oris r7,r7,0x0002 /* set CE bit (Critical Exceptions) */
1609 mtspr SPRN_SRR1,r7 1609 mtspr SPRN_SRR1,r7
1610 mflr r7 1610 mflr r7
1611 mtspr SPRN_SRR0,r7 1611 mtspr SPRN_SRR0,r7
1612 rfi 1612 rfi
1613 __440_msr_continue: 1613 __440_msr_continue:
1614 #endif 1614 #endif
1615 1615
1616 mtlr r4 /* restore link register */ 1616 mtlr r4 /* restore link register */
1617 blr 1617 blr
1618 #endif /* CONFIG_SPL_BUILD */ 1618 #endif /* CONFIG_SPL_BUILD */
1619 1619
1620 #if defined(CONFIG_440) 1620 #if defined(CONFIG_440)
1621 /*----------------------------------------------------------------------------+ 1621 /*----------------------------------------------------------------------------+
1622 | dcbz_area. 1622 | dcbz_area.
1623 +----------------------------------------------------------------------------*/ 1623 +----------------------------------------------------------------------------*/
1624 function_prolog(dcbz_area) 1624 function_prolog(dcbz_area)
1625 rlwinm. r5,r4,0,27,31 1625 rlwinm. r5,r4,0,27,31
1626 rlwinm r5,r4,27,5,31 1626 rlwinm r5,r4,27,5,31
1627 beq ..d_ra2 1627 beq ..d_ra2
1628 addi r5,r5,0x0001 1628 addi r5,r5,0x0001
1629 ..d_ra2:mtctr r5 1629 ..d_ra2:mtctr r5
1630 ..d_ag2:dcbz r0,r3 1630 ..d_ag2:dcbz r0,r3
1631 addi r3,r3,32 1631 addi r3,r3,32
1632 bdnz ..d_ag2 1632 bdnz ..d_ag2
1633 sync 1633 sync
1634 blr 1634 blr
1635 function_epilog(dcbz_area) 1635 function_epilog(dcbz_area)
1636 #endif /* CONFIG_440 */ 1636 #endif /* CONFIG_440 */
1637 #endif /* CONFIG_NAND_SPL */ 1637 #endif /* CONFIG_NAND_SPL */
1638 1638
1639 /*------------------------------------------------------------------------------- */ 1639 /*------------------------------------------------------------------------------- */
1640 /* Function: in8 */ 1640 /* Function: in8 */
1641 /* Description: Input 8 bits */ 1641 /* Description: Input 8 bits */
1642 /*------------------------------------------------------------------------------- */ 1642 /*------------------------------------------------------------------------------- */
1643 .globl in8 1643 .globl in8
1644 in8: 1644 in8:
1645 lbz r3,0x0000(r3) 1645 lbz r3,0x0000(r3)
1646 blr 1646 blr
1647 1647
1648 /*------------------------------------------------------------------------------- */ 1648 /*------------------------------------------------------------------------------- */
1649 /* Function: out8 */ 1649 /* Function: out8 */
1650 /* Description: Output 8 bits */ 1650 /* Description: Output 8 bits */
1651 /*------------------------------------------------------------------------------- */ 1651 /*------------------------------------------------------------------------------- */
1652 .globl out8 1652 .globl out8
1653 out8: 1653 out8:
1654 stb r4,0x0000(r3) 1654 stb r4,0x0000(r3)
1655 blr 1655 blr
1656 1656
1657 /*------------------------------------------------------------------------------- */ 1657 /*------------------------------------------------------------------------------- */
1658 /* Function: out32 */ 1658 /* Function: out32 */
1659 /* Description: Output 32 bits */ 1659 /* Description: Output 32 bits */
1660 /*------------------------------------------------------------------------------- */ 1660 /*------------------------------------------------------------------------------- */
1661 .globl out32 1661 .globl out32
1662 out32: 1662 out32:
1663 stw r4,0x0000(r3) 1663 stw r4,0x0000(r3)
1664 blr 1664 blr
1665 1665
1666 /*------------------------------------------------------------------------------- */ 1666 /*------------------------------------------------------------------------------- */
1667 /* Function: in32 */ 1667 /* Function: in32 */
1668 /* Description: Input 32 bits */ 1668 /* Description: Input 32 bits */
1669 /*------------------------------------------------------------------------------- */ 1669 /*------------------------------------------------------------------------------- */
1670 .globl in32 1670 .globl in32
1671 in32: 1671 in32:
1672 lwz 3,0x0000(3) 1672 lwz 3,0x0000(3)
1673 blr 1673 blr
1674 1674
1675 /**************************************************************************/ 1675 /**************************************************************************/
1676 /* PPC405EP specific stuff */ 1676 /* PPC405EP specific stuff */
1677 /**************************************************************************/ 1677 /**************************************************************************/
1678 #ifdef CONFIG_405EP 1678 #ifdef CONFIG_405EP
1679 ppc405ep_init: 1679 ppc405ep_init:
1680 1680
1681 #ifdef CONFIG_BUBINGA 1681 #ifdef CONFIG_BUBINGA
1682 /* 1682 /*
1683 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate 1683 * Initialize EBC chip selects 1 & 4 and GPIO pins (for alternate
1684 * function) to support FPGA and NVRAM accesses below. 1684 * function) to support FPGA and NVRAM accesses below.
1685 */ 1685 */
1686 1686
1687 lis r3,GPIO0_OSRH@h /* config GPIO output select */ 1687 lis r3,GPIO0_OSRH@h /* config GPIO output select */
1688 ori r3,r3,GPIO0_OSRH@l 1688 ori r3,r3,GPIO0_OSRH@l
1689 lis r4,CONFIG_SYS_GPIO0_OSRH@h 1689 lis r4,CONFIG_SYS_GPIO0_OSRH@h
1690 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l 1690 ori r4,r4,CONFIG_SYS_GPIO0_OSRH@l
1691 stw r4,0(r3) 1691 stw r4,0(r3)
1692 lis r3,GPIO0_OSRL@h 1692 lis r3,GPIO0_OSRL@h
1693 ori r3,r3,GPIO0_OSRL@l 1693 ori r3,r3,GPIO0_OSRL@l
1694 lis r4,CONFIG_SYS_GPIO0_OSRL@h 1694 lis r4,CONFIG_SYS_GPIO0_OSRL@h
1695 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l 1695 ori r4,r4,CONFIG_SYS_GPIO0_OSRL@l
1696 stw r4,0(r3) 1696 stw r4,0(r3)
1697 1697
1698 lis r3,GPIO0_ISR1H@h /* config GPIO input select */ 1698 lis r3,GPIO0_ISR1H@h /* config GPIO input select */
1699 ori r3,r3,GPIO0_ISR1H@l 1699 ori r3,r3,GPIO0_ISR1H@l
1700 lis r4,CONFIG_SYS_GPIO0_ISR1H@h 1700 lis r4,CONFIG_SYS_GPIO0_ISR1H@h
1701 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l 1701 ori r4,r4,CONFIG_SYS_GPIO0_ISR1H@l
1702 stw r4,0(r3) 1702 stw r4,0(r3)
1703 lis r3,GPIO0_ISR1L@h 1703 lis r3,GPIO0_ISR1L@h
1704 ori r3,r3,GPIO0_ISR1L@l 1704 ori r3,r3,GPIO0_ISR1L@l
1705 lis r4,CONFIG_SYS_GPIO0_ISR1L@h 1705 lis r4,CONFIG_SYS_GPIO0_ISR1L@h
1706 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l 1706 ori r4,r4,CONFIG_SYS_GPIO0_ISR1L@l
1707 stw r4,0(r3) 1707 stw r4,0(r3)
1708 1708
1709 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */ 1709 lis r3,GPIO0_TSRH@h /* config GPIO three-state select */
1710 ori r3,r3,GPIO0_TSRH@l 1710 ori r3,r3,GPIO0_TSRH@l
1711 lis r4,CONFIG_SYS_GPIO0_TSRH@h 1711 lis r4,CONFIG_SYS_GPIO0_TSRH@h
1712 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l 1712 ori r4,r4,CONFIG_SYS_GPIO0_TSRH@l
1713 stw r4,0(r3) 1713 stw r4,0(r3)
1714 lis r3,GPIO0_TSRL@h 1714 lis r3,GPIO0_TSRL@h
1715 ori r3,r3,GPIO0_TSRL@l 1715 ori r3,r3,GPIO0_TSRL@l
1716 lis r4,CONFIG_SYS_GPIO0_TSRL@h 1716 lis r4,CONFIG_SYS_GPIO0_TSRL@h
1717 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l 1717 ori r4,r4,CONFIG_SYS_GPIO0_TSRL@l
1718 stw r4,0(r3) 1718 stw r4,0(r3)
1719 1719
1720 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */ 1720 lis r3,GPIO0_TCR@h /* config GPIO driver output enables */
1721 ori r3,r3,GPIO0_TCR@l 1721 ori r3,r3,GPIO0_TCR@l
1722 lis r4,CONFIG_SYS_GPIO0_TCR@h 1722 lis r4,CONFIG_SYS_GPIO0_TCR@h
1723 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l 1723 ori r4,r4,CONFIG_SYS_GPIO0_TCR@l
1724 stw r4,0(r3) 1724 stw r4,0(r3)
1725 1725
1726 li r3,PB1AP /* program EBC bank 1 for RTC access */ 1726 li r3,PB1AP /* program EBC bank 1 for RTC access */
1727 mtdcr EBC0_CFGADDR,r3 1727 mtdcr EBC0_CFGADDR,r3
1728 lis r3,CONFIG_SYS_EBC_PB1AP@h 1728 lis r3,CONFIG_SYS_EBC_PB1AP@h
1729 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l 1729 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1730 mtdcr EBC0_CFGDATA,r3 1730 mtdcr EBC0_CFGDATA,r3
1731 li r3,PB1CR 1731 li r3,PB1CR
1732 mtdcr EBC0_CFGADDR,r3 1732 mtdcr EBC0_CFGADDR,r3
1733 lis r3,CONFIG_SYS_EBC_PB1CR@h 1733 lis r3,CONFIG_SYS_EBC_PB1CR@h
1734 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l 1734 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1735 mtdcr EBC0_CFGDATA,r3 1735 mtdcr EBC0_CFGDATA,r3
1736 1736
1737 li r3,PB1AP /* program EBC bank 1 for RTC access */ 1737 li r3,PB1AP /* program EBC bank 1 for RTC access */
1738 mtdcr EBC0_CFGADDR,r3 1738 mtdcr EBC0_CFGADDR,r3
1739 lis r3,CONFIG_SYS_EBC_PB1AP@h 1739 lis r3,CONFIG_SYS_EBC_PB1AP@h
1740 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l 1740 ori r3,r3,CONFIG_SYS_EBC_PB1AP@l
1741 mtdcr EBC0_CFGDATA,r3 1741 mtdcr EBC0_CFGDATA,r3
1742 li r3,PB1CR 1742 li r3,PB1CR
1743 mtdcr EBC0_CFGADDR,r3 1743 mtdcr EBC0_CFGADDR,r3
1744 lis r3,CONFIG_SYS_EBC_PB1CR@h 1744 lis r3,CONFIG_SYS_EBC_PB1CR@h
1745 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l 1745 ori r3,r3,CONFIG_SYS_EBC_PB1CR@l
1746 mtdcr EBC0_CFGDATA,r3 1746 mtdcr EBC0_CFGDATA,r3
1747 1747
1748 li r3,PB4AP /* program EBC bank 4 for FPGA access */ 1748 li r3,PB4AP /* program EBC bank 4 for FPGA access */
1749 mtdcr EBC0_CFGADDR,r3 1749 mtdcr EBC0_CFGADDR,r3
1750 lis r3,CONFIG_SYS_EBC_PB4AP@h 1750 lis r3,CONFIG_SYS_EBC_PB4AP@h
1751 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l 1751 ori r3,r3,CONFIG_SYS_EBC_PB4AP@l
1752 mtdcr EBC0_CFGDATA,r3 1752 mtdcr EBC0_CFGDATA,r3
1753 li r3,PB4CR 1753 li r3,PB4CR
1754 mtdcr EBC0_CFGADDR,r3 1754 mtdcr EBC0_CFGADDR,r3
1755 lis r3,CONFIG_SYS_EBC_PB4CR@h 1755 lis r3,CONFIG_SYS_EBC_PB4CR@h
1756 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l 1756 ori r3,r3,CONFIG_SYS_EBC_PB4CR@l
1757 mtdcr EBC0_CFGDATA,r3 1757 mtdcr EBC0_CFGDATA,r3
1758 #endif 1758 #endif
1759 1759
1760 /* 1760 /*
1761 !----------------------------------------------------------------------- 1761 !-----------------------------------------------------------------------
1762 ! Check to see if chip is in bypass mode. 1762 ! Check to see if chip is in bypass mode.
1763 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a 1763 ! If so, write stored CPC0_PLLMR0 and CPC0_PLLMR1 values and perform a
1764 ! CPU reset Otherwise, skip this step and keep going. 1764 ! CPU reset Otherwise, skip this step and keep going.
1765 ! Note: Running BIOS in bypass mode is not supported since PLB speed 1765 ! Note: Running BIOS in bypass mode is not supported since PLB speed
1766 ! will not be fast enough for the SDRAM (min 66MHz) 1766 ! will not be fast enough for the SDRAM (min 66MHz)
1767 !----------------------------------------------------------------------- 1767 !-----------------------------------------------------------------------
1768 */ 1768 */
1769 mfdcr r5, CPC0_PLLMR1 1769 mfdcr r5, CPC0_PLLMR1
1770 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */ 1770 rlwinm r4,r5,1,0x1 /* get system clock source (SSCS) */
1771 cmpi cr0,0,r4,0x1 1771 cmpi cr0,0,r4,0x1
1772 1772
1773 beq pll_done /* if SSCS =b'1' then PLL has */ 1773 beq pll_done /* if SSCS =b'1' then PLL has */
1774 /* already been set */ 1774 /* already been set */
1775 /* and CPU has been reset */ 1775 /* and CPU has been reset */
1776 /* so skip to next section */ 1776 /* so skip to next section */
1777 1777
1778 #ifdef CONFIG_BUBINGA 1778 #ifdef CONFIG_BUBINGA
1779 /* 1779 /*
1780 !----------------------------------------------------------------------- 1780 !-----------------------------------------------------------------------
1781 ! Read NVRAM to get value to write in PLLMR. 1781 ! Read NVRAM to get value to write in PLLMR.
1782 ! If value has not been correctly saved, write default value 1782 ! If value has not been correctly saved, write default value
1783 ! Default config values (assuming on-board 33MHz SYS_CLK) are above. 1783 ! Default config values (assuming on-board 33MHz SYS_CLK) are above.
1784 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above. 1784 ! See CPU_DEFAULT_200 and CPU_DEFAULT_266 above.
1785 ! 1785 !
1786 ! WARNING: This code assumes the first three words in the nvram_t 1786 ! WARNING: This code assumes the first three words in the nvram_t
1787 ! structure in openbios.h. Changing the beginning of 1787 ! structure in openbios.h. Changing the beginning of
1788 ! the structure will break this code. 1788 ! the structure will break this code.
1789 ! 1789 !
1790 !----------------------------------------------------------------------- 1790 !-----------------------------------------------------------------------
1791 */ 1791 */
1792 addis r3,0,NVRAM_BASE@h 1792 addis r3,0,NVRAM_BASE@h
1793 addi r3,r3,NVRAM_BASE@l 1793 addi r3,r3,NVRAM_BASE@l
1794 1794
1795 lwz r4, 0(r3) 1795 lwz r4, 0(r3)
1796 addis r5,0,NVRVFY1@h 1796 addis r5,0,NVRVFY1@h
1797 addi r5,r5,NVRVFY1@l 1797 addi r5,r5,NVRVFY1@l
1798 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/ 1798 cmp cr0,0,r4,r5 /* Compare 1st NVRAM Magic number*/
1799 bne ..no_pllset 1799 bne ..no_pllset
1800 addi r3,r3,4 1800 addi r3,r3,4
1801 lwz r4, 0(r3) 1801 lwz r4, 0(r3)
1802 addis r5,0,NVRVFY2@h 1802 addis r5,0,NVRVFY2@h
1803 addi r5,r5,NVRVFY2@l 1803 addi r5,r5,NVRVFY2@l
1804 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */ 1804 cmp cr0,0,r4,r5 /* Compare 2 NVRAM Magic number */
1805 bne ..no_pllset 1805 bne ..no_pllset
1806 addi r3,r3,8 /* Skip over conf_size */ 1806 addi r3,r3,8 /* Skip over conf_size */
1807 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */ 1807 lwz r4, 4(r3) /* Load PLLMR1 value from NVRAM */
1808 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */ 1808 lwz r3, 0(r3) /* Load PLLMR0 value from NVRAM */
1809 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */ 1809 rlwinm r5,r4,1,0x1 /* get system clock source (SSCS) */
1810 cmpi cr0,0,r5,1 /* See if PLL is locked */ 1810 cmpi cr0,0,r5,1 /* See if PLL is locked */
1811 beq pll_write 1811 beq pll_write
1812 ..no_pllset: 1812 ..no_pllset:
1813 #endif /* CONFIG_BUBINGA */ 1813 #endif /* CONFIG_BUBINGA */
1814 1814
1815 #ifdef CONFIG_TAIHU 1815 #ifdef CONFIG_TAIHU
1816 mfdcr r4, CPC0_BOOT 1816 mfdcr r4, CPC0_BOOT
1817 andi. r5, r4, CPC0_BOOT_SEP@l 1817 andi. r5, r4, CPC0_BOOT_SEP@l
1818 bne strap_1 /* serial eeprom present */ 1818 bne strap_1 /* serial eeprom present */
1819 addis r5,0,CPLD_REG0_ADDR@h 1819 addis r5,0,CPLD_REG0_ADDR@h
1820 ori r5,r5,CPLD_REG0_ADDR@l 1820 ori r5,r5,CPLD_REG0_ADDR@l
1821 andi. r5, r5, 0x10 1821 andi. r5, r5, 0x10
1822 bne _pci_66mhz 1822 bne _pci_66mhz
1823 #endif /* CONFIG_TAIHU */ 1823 #endif /* CONFIG_TAIHU */
1824 1824
1825 #if defined(CONFIG_ZEUS) 1825 #if defined(CONFIG_ZEUS)
1826 mfdcr r4, CPC0_BOOT 1826 mfdcr r4, CPC0_BOOT
1827 andi. r5, r4, CPC0_BOOT_SEP@l 1827 andi. r5, r4, CPC0_BOOT_SEP@l
1828 bne strap_1 /* serial eeprom present */ 1828 bne strap_1 /* serial eeprom present */
1829 lis r3,0x0000 1829 lis r3,0x0000
1830 addi r3,r3,0x3030 1830 addi r3,r3,0x3030
1831 lis r4,0x8042 1831 lis r4,0x8042
1832 addi r4,r4,0x223e 1832 addi r4,r4,0x223e
1833 b 1f 1833 b 1f
1834 strap_1: 1834 strap_1:
1835 mfdcr r3, CPC0_PLLMR0 1835 mfdcr r3, CPC0_PLLMR0
1836 mfdcr r4, CPC0_PLLMR1 1836 mfdcr r4, CPC0_PLLMR1
1837 b 1f 1837 b 1f
1838 #endif 1838 #endif
1839 1839
1840 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */ 1840 addis r3,0,PLLMR0_DEFAULT@h /* PLLMR0 default value */
1841 ori r3,r3,PLLMR0_DEFAULT@l /* */ 1841 ori r3,r3,PLLMR0_DEFAULT@l /* */
1842 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */ 1842 addis r4,0,PLLMR1_DEFAULT@h /* PLLMR1 default value */
1843 ori r4,r4,PLLMR1_DEFAULT@l /* */ 1843 ori r4,r4,PLLMR1_DEFAULT@l /* */
1844 1844
1845 #ifdef CONFIG_TAIHU 1845 #ifdef CONFIG_TAIHU
1846 b 1f 1846 b 1f
1847 _pci_66mhz: 1847 _pci_66mhz:
1848 addis r3,0,PLLMR0_DEFAULT_PCI66@h 1848 addis r3,0,PLLMR0_DEFAULT_PCI66@h
1849 ori r3,r3,PLLMR0_DEFAULT_PCI66@l 1849 ori r3,r3,PLLMR0_DEFAULT_PCI66@l
1850 addis r4,0,PLLMR1_DEFAULT_PCI66@h 1850 addis r4,0,PLLMR1_DEFAULT_PCI66@h
1851 ori r4,r4,PLLMR1_DEFAULT_PCI66@l 1851 ori r4,r4,PLLMR1_DEFAULT_PCI66@l
1852 b 1f 1852 b 1f
1853 strap_1: 1853 strap_1:
1854 mfdcr r3, CPC0_PLLMR0 1854 mfdcr r3, CPC0_PLLMR0
1855 mfdcr r4, CPC0_PLLMR1 1855 mfdcr r4, CPC0_PLLMR1
1856 #endif /* CONFIG_TAIHU */ 1856 #endif /* CONFIG_TAIHU */
1857 1857
1858 1: 1858 1:
1859 b pll_write /* Write the CPC0_PLLMR with new value */ 1859 b pll_write /* Write the CPC0_PLLMR with new value */
1860 1860
1861 pll_done: 1861 pll_done:
1862 /* 1862 /*
1863 !----------------------------------------------------------------------- 1863 !-----------------------------------------------------------------------
1864 ! Clear Soft Reset Register 1864 ! Clear Soft Reset Register
1865 ! This is needed to enable PCI if not booting from serial EPROM 1865 ! This is needed to enable PCI if not booting from serial EPROM
1866 !----------------------------------------------------------------------- 1866 !-----------------------------------------------------------------------
1867 */ 1867 */
1868 addi r3, 0, 0x0 1868 addi r3, 0, 0x0
1869 mtdcr CPC0_SRR, r3 1869 mtdcr CPC0_SRR, r3
1870 1870
1871 addis r3,0,0x0010 1871 addis r3,0,0x0010
1872 mtctr r3 1872 mtctr r3
1873 pci_wait: 1873 pci_wait:
1874 bdnz pci_wait 1874 bdnz pci_wait
1875 1875
1876 blr /* return to main code */ 1876 blr /* return to main code */
1877 1877
1878 /* 1878 /*
1879 !----------------------------------------------------------------------------- 1879 !-----------------------------------------------------------------------------
1880 ! Function: pll_write 1880 ! Function: pll_write
1881 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation 1881 ! Description: Updates the value of the CPC0_PLLMR according to CMOS27E documentation
1882 ! That is: 1882 ! That is:
1883 ! 1. Pll is first disabled (de-activated by putting in bypass mode) 1883 ! 1. Pll is first disabled (de-activated by putting in bypass mode)
1884 ! 2. PLL is reset 1884 ! 2. PLL is reset
1885 ! 3. Clock dividers are set while PLL is held in reset and bypassed 1885 ! 3. Clock dividers are set while PLL is held in reset and bypassed
1886 ! 4. PLL Reset is cleared 1886 ! 4. PLL Reset is cleared
1887 ! 5. Wait 100us for PLL to lock 1887 ! 5. Wait 100us for PLL to lock
1888 ! 6. A core reset is performed 1888 ! 6. A core reset is performed
1889 ! Input: r3 = Value to write to CPC0_PLLMR0 1889 ! Input: r3 = Value to write to CPC0_PLLMR0
1890 ! Input: r4 = Value to write to CPC0_PLLMR1 1890 ! Input: r4 = Value to write to CPC0_PLLMR1
1891 ! Output r3 = none 1891 ! Output r3 = none
1892 !----------------------------------------------------------------------------- 1892 !-----------------------------------------------------------------------------
1893 */ 1893 */
1894 .globl pll_write 1894 .globl pll_write
1895 pll_write: 1895 pll_write:
1896 mfdcr r5, CPC0_UCR 1896 mfdcr r5, CPC0_UCR
1897 andis. r5,r5,0xFFFF 1897 andis. r5,r5,0xFFFF
1898 ori r5,r5,0x0101 /* Stop the UART clocks */ 1898 ori r5,r5,0x0101 /* Stop the UART clocks */
1899 mtdcr CPC0_UCR,r5 /* Before changing PLL */ 1899 mtdcr CPC0_UCR,r5 /* Before changing PLL */
1900 1900
1901 mfdcr r5, CPC0_PLLMR1 1901 mfdcr r5, CPC0_PLLMR1
1902 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */ 1902 rlwinm r5,r5,0,0x7FFFFFFF /* Disable PLL */
1903 mtdcr CPC0_PLLMR1,r5 1903 mtdcr CPC0_PLLMR1,r5
1904 oris r5,r5,0x4000 /* Set PLL Reset */ 1904 oris r5,r5,0x4000 /* Set PLL Reset */
1905 mtdcr CPC0_PLLMR1,r5 1905 mtdcr CPC0_PLLMR1,r5
1906 1906
1907 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */ 1907 mtdcr CPC0_PLLMR0,r3 /* Set clock dividers */
1908 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */ 1908 rlwinm r5,r4,0,0x3FFFFFFF /* Reset & Bypass new PLL dividers */
1909 oris r5,r5,0x4000 /* Set PLL Reset */ 1909 oris r5,r5,0x4000 /* Set PLL Reset */
1910 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */ 1910 mtdcr CPC0_PLLMR1,r5 /* Set clock dividers */
1911 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */ 1911 rlwinm r5,r5,0,0xBFFFFFFF /* Clear PLL Reset */
1912 mtdcr CPC0_PLLMR1,r5 1912 mtdcr CPC0_PLLMR1,r5
1913 1913
1914 /* 1914 /*
1915 ! Wait min of 100us for PLL to lock. 1915 ! Wait min of 100us for PLL to lock.
1916 ! See CMOS 27E databook for more info. 1916 ! See CMOS 27E databook for more info.
1917 ! At 200MHz, that means waiting 20,000 instructions 1917 ! At 200MHz, that means waiting 20,000 instructions
1918 */ 1918 */
1919 addi r3,0,20000 /* 2000 = 0x4e20 */ 1919 addi r3,0,20000 /* 2000 = 0x4e20 */
1920 mtctr r3 1920 mtctr r3
1921 pll_wait: 1921 pll_wait:
1922 bdnz pll_wait 1922 bdnz pll_wait
1923 1923
1924 oris r5,r5,0x8000 /* Enable PLL */ 1924 oris r5,r5,0x8000 /* Enable PLL */
1925 mtdcr CPC0_PLLMR1,r5 /* Engage */ 1925 mtdcr CPC0_PLLMR1,r5 /* Engage */
1926 1926
1927 /* 1927 /*
1928 * Reset CPU to guarantee timings are OK 1928 * Reset CPU to guarantee timings are OK
1929 * Not sure if this is needed... 1929 * Not sure if this is needed...
1930 */ 1930 */
1931 addis r3,0,0x1000 1931 addis r3,0,0x1000
1932 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */ 1932 mtspr SPRN_DBCR0,r3 /* This will cause a CPU core reset, and */
1933 /* execution will continue from the poweron */ 1933 /* execution will continue from the poweron */
1934 /* vector of 0xfffffffc */ 1934 /* vector of 0xfffffffc */
1935 #endif /* CONFIG_405EP */ 1935 #endif /* CONFIG_405EP */
1936 1936
1937 #if defined(CONFIG_440) 1937 #if defined(CONFIG_440)
1938 /*----------------------------------------------------------------------------+ 1938 /*----------------------------------------------------------------------------+
1939 | mttlb3. 1939 | mttlb3.
1940 +----------------------------------------------------------------------------*/ 1940 +----------------------------------------------------------------------------*/
1941 function_prolog(mttlb3) 1941 function_prolog(mttlb3)
1942 TLBWE(4,3,2) 1942 TLBWE(4,3,2)
1943 blr 1943 blr
1944 function_epilog(mttlb3) 1944 function_epilog(mttlb3)
1945 1945
1946 /*----------------------------------------------------------------------------+ 1946 /*----------------------------------------------------------------------------+
1947 | mftlb3. 1947 | mftlb3.
1948 +----------------------------------------------------------------------------*/ 1948 +----------------------------------------------------------------------------*/
1949 function_prolog(mftlb3) 1949 function_prolog(mftlb3)
1950 TLBRE(3,3,2) 1950 TLBRE(3,3,2)
1951 blr 1951 blr
1952 function_epilog(mftlb3) 1952 function_epilog(mftlb3)
1953 1953
1954 /*----------------------------------------------------------------------------+ 1954 /*----------------------------------------------------------------------------+
1955 | mttlb2. 1955 | mttlb2.
1956 +----------------------------------------------------------------------------*/ 1956 +----------------------------------------------------------------------------*/
1957 function_prolog(mttlb2) 1957 function_prolog(mttlb2)
1958 TLBWE(4,3,1) 1958 TLBWE(4,3,1)
1959 blr 1959 blr
1960 function_epilog(mttlb2) 1960 function_epilog(mttlb2)
1961 1961
1962 /*----------------------------------------------------------------------------+ 1962 /*----------------------------------------------------------------------------+
1963 | mftlb2. 1963 | mftlb2.
1964 +----------------------------------------------------------------------------*/ 1964 +----------------------------------------------------------------------------*/
1965 function_prolog(mftlb2) 1965 function_prolog(mftlb2)
1966 TLBRE(3,3,1) 1966 TLBRE(3,3,1)
1967 blr 1967 blr
1968 function_epilog(mftlb2) 1968 function_epilog(mftlb2)
1969 1969
1970 /*----------------------------------------------------------------------------+ 1970 /*----------------------------------------------------------------------------+
1971 | mttlb1. 1971 | mttlb1.
1972 +----------------------------------------------------------------------------*/ 1972 +----------------------------------------------------------------------------*/
1973 function_prolog(mttlb1) 1973 function_prolog(mttlb1)
1974 TLBWE(4,3,0) 1974 TLBWE(4,3,0)
1975 blr 1975 blr
1976 function_epilog(mttlb1) 1976 function_epilog(mttlb1)
1977 1977
1978 /*----------------------------------------------------------------------------+ 1978 /*----------------------------------------------------------------------------+
1979 | mftlb1. 1979 | mftlb1.
1980 +----------------------------------------------------------------------------*/ 1980 +----------------------------------------------------------------------------*/
1981 function_prolog(mftlb1) 1981 function_prolog(mftlb1)
1982 TLBRE(3,3,0) 1982 TLBRE(3,3,0)
1983 blr 1983 blr
1984 function_epilog(mftlb1) 1984 function_epilog(mftlb1)
1985 #endif /* CONFIG_440 */ 1985 #endif /* CONFIG_440 */
1986 1986
1987 #if defined(CONFIG_NAND_SPL) 1987 #if defined(CONFIG_NAND_SPL)
1988 /* 1988 /*
1989 * void nand_boot_relocate(dst, src, bytes) 1989 * void nand_boot_relocate(dst, src, bytes)
1990 * 1990 *
1991 * r3 = Destination address to copy code to (in SDRAM) 1991 * r3 = Destination address to copy code to (in SDRAM)
1992 * r4 = Source address to copy code from 1992 * r4 = Source address to copy code from
1993 * r5 = size to copy in bytes 1993 * r5 = size to copy in bytes
1994 */ 1994 */
1995 nand_boot_relocate: 1995 nand_boot_relocate:
1996 mr r6,r3 1996 mr r6,r3
1997 mr r7,r4 1997 mr r7,r4
1998 mflr r8 1998 mflr r8
1999 1999
2000 /* 2000 /*
2001 * Copy SPL from icache into SDRAM 2001 * Copy SPL from icache into SDRAM
2002 */ 2002 */
2003 subi r3,r3,4 2003 subi r3,r3,4
2004 subi r4,r4,4 2004 subi r4,r4,4
2005 srwi r5,r5,2 2005 srwi r5,r5,2
2006 mtctr r5 2006 mtctr r5
2007 ..spl_loop: 2007 ..spl_loop:
2008 lwzu r0,4(r4) 2008 lwzu r0,4(r4)
2009 stwu r0,4(r3) 2009 stwu r0,4(r3)
2010 bdnz ..spl_loop 2010 bdnz ..spl_loop
2011 2011
2012 /* 2012 /*
2013 * Calculate "corrected" link register, so that we "continue" 2013 * Calculate "corrected" link register, so that we "continue"
2014 * in execution in destination range 2014 * in execution in destination range
2015 */ 2015 */
2016 sub r3,r7,r6 /* r3 = src - dst */ 2016 sub r3,r7,r6 /* r3 = src - dst */
2017 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */ 2017 sub r8,r8,r3 /* r8 = link-reg - (src - dst) */
2018 mtlr r8 2018 mtlr r8
2019 blr 2019 blr
2020 2020
2021 nand_boot_common: 2021 nand_boot_common:
2022 /* 2022 /*
2023 * First initialize SDRAM. It has to be available *before* calling 2023 * First initialize SDRAM. It has to be available *before* calling
2024 * nand_boot(). 2024 * nand_boot().
2025 */ 2025 */
2026 lis r3,CONFIG_SYS_SDRAM_BASE@h 2026 lis r3,CONFIG_SYS_SDRAM_BASE@h
2027 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l 2027 ori r3,r3,CONFIG_SYS_SDRAM_BASE@l
2028 bl initdram 2028 bl initdram
2029 2029
2030 /* 2030 /*
2031 * Now copy the 4k SPL code into SDRAM and continue execution 2031 * Now copy the 4k SPL code into SDRAM and continue execution
2032 * from there. 2032 * from there.
2033 */ 2033 */
2034 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h 2034 lis r3,CONFIG_SYS_NAND_BOOT_SPL_DST@h
2035 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l 2035 ori r3,r3,CONFIG_SYS_NAND_BOOT_SPL_DST@l
2036 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h 2036 lis r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@h
2037 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l 2037 ori r4,r4,CONFIG_SYS_NAND_BOOT_SPL_SRC@l
2038 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h 2038 lis r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@h
2039 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l 2039 ori r5,r5,CONFIG_SYS_NAND_BOOT_SPL_SIZE@l
2040 bl nand_boot_relocate 2040 bl nand_boot_relocate
2041 2041
2042 /* 2042 /*
2043 * We're running from SDRAM now!!! 2043 * We're running from SDRAM now!!!
2044 * 2044 *
2045 * It is necessary for 4xx systems to relocate from running at 2045 * It is necessary for 4xx systems to relocate from running at
2046 * the original location (0xfffffxxx) to somewhere else (SDRAM 2046 * the original location (0xfffffxxx) to somewhere else (SDRAM
2047 * preferably). This is because CS0 needs to be reconfigured for 2047 * preferably). This is because CS0 needs to be reconfigured for
2048 * NAND access. And we can't reconfigure this CS when currently 2048 * NAND access. And we can't reconfigure this CS when currently
2049 * "running" from it. 2049 * "running" from it.
2050 */ 2050 */
2051 2051
2052 /* 2052 /*
2053 * Finally call nand_boot() to load main NAND U-Boot image from 2053 * Finally call nand_boot() to load main NAND U-Boot image from
2054 * NAND and jump to it. 2054 * NAND and jump to it.
2055 */ 2055 */
2056 bl nand_boot /* will not return */ 2056 bl nand_boot /* will not return */
2057 #endif /* CONFIG_NAND_SPL */ 2057 #endif /* CONFIG_NAND_SPL */
2058 2058
arch/powerpc/include/asm/ppc405.h
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 4
5 #ifndef __PPC405_H__ 5 #ifndef __PPC405_H__
6 #define __PPC405_H__ 6 #define __PPC405_H__
7 7
8 /* Define bits and masks for real-mode storage attribute control registers */ 8 /* Define bits and masks for real-mode storage attribute control registers */
9 #define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) 9 #define PPC_128MB_SACR_BIT(addr) ((addr) >> 27)
10 #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) 10 #define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1)
11 11
12 #define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ 12 #define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */
13 13
14 /* DCR registers */ 14 /* DCR registers */
15 #define PLB0_ACR 0x0087 15 #define PLB0_ACR 0x0087
16 16
17 /* SDR registers */ 17 /* SDR registers */
18 #define SDR0_PINSTP 0x0040 18 #define SDR0_PINSTP 0x0040
19 19
20 /* CPR registers */ 20 /* CPR registers */
21 #define CPR0_CLKUPD 0x0020 21 #define CPR0_CLKUPD 0x0020
22 #define CPR0_PLLC 0x0040 22 #define CPR0_PLLC 0x0040
23 #define CPR0_PLLD 0x0060 23 #define CPR0_PLLD 0x0060
24 #define CPR0_CPUD 0x0080 24 #define CPR0_CPUD 0x0080
25 #define CPR0_PLBD 0x00a0 25 #define CPR0_PLBD 0x00a0
26 #define CPR0_OPBD0 0x00c0 26 #define CPR0_OPBD0 0x00c0
27 #define CPR0_PERD 0x00e0 27 #define CPR0_PERD 0x00e0
28 28
29 /* 29 /*
30 * DMA 30 * DMA
31 */ 31 */
32 #define DMA_DCR_BASE 0x0100 32 #define DMA_DCR_BASE 0x0100
33 #define DMACR0 (DMA_DCR_BASE + 0x00) /* DMA channel control reg 0 */ 33 #define DMACR0 (DMA_DCR_BASE + 0x00) /* DMA channel control reg 0 */
34 #define DMACT0 (DMA_DCR_BASE + 0x01) /* DMA count reg 0 */ 34 #define DMACT0 (DMA_DCR_BASE + 0x01) /* DMA count reg 0 */
35 #define DMADA0 (DMA_DCR_BASE + 0x02) /* DMA destination address reg 0 */ 35 #define DMADA0 (DMA_DCR_BASE + 0x02) /* DMA destination address reg 0 */
36 #define DMASA0 (DMA_DCR_BASE + 0x03) /* DMA source address reg 0 */ 36 #define DMASA0 (DMA_DCR_BASE + 0x03) /* DMA source address reg 0 */
37 #define DMASB0 (DMA_DCR_BASE + 0x04) /* DMA sg descriptor addr 0 */ 37 #define DMASB0 (DMA_DCR_BASE + 0x04) /* DMA sg descriptor addr 0 */
38 #define DMACR1 (DMA_DCR_BASE + 0x08) /* DMA channel control reg 1 */ 38 #define DMACR1 (DMA_DCR_BASE + 0x08) /* DMA channel control reg 1 */
39 #define DMACT1 (DMA_DCR_BASE + 0x09) /* DMA count reg 1 */ 39 #define DMACT1 (DMA_DCR_BASE + 0x09) /* DMA count reg 1 */
40 #define DMADA1 (DMA_DCR_BASE + 0x0a) /* DMA destination address reg 1 */ 40 #define DMADA1 (DMA_DCR_BASE + 0x0a) /* DMA destination address reg 1 */
41 #define DMASA1 (DMA_DCR_BASE + 0x0b) /* DMA source address reg 1 */ 41 #define DMASA1 (DMA_DCR_BASE + 0x0b) /* DMA source address reg 1 */
42 #define DMASB1 (DMA_DCR_BASE + 0x0c) /* DMA sg descriptor addr 1 */ 42 #define DMASB1 (DMA_DCR_BASE + 0x0c) /* DMA sg descriptor addr 1 */
43 #define DMACR2 (DMA_DCR_BASE + 0x10) /* DMA channel control reg 2 */ 43 #define DMACR2 (DMA_DCR_BASE + 0x10) /* DMA channel control reg 2 */
44 #define DMACT2 (DMA_DCR_BASE + 0x11) /* DMA count reg 2 */ 44 #define DMACT2 (DMA_DCR_BASE + 0x11) /* DMA count reg 2 */
45 #define DMADA2 (DMA_DCR_BASE + 0x12) /* DMA destination address reg 2 */ 45 #define DMADA2 (DMA_DCR_BASE + 0x12) /* DMA destination address reg 2 */
46 #define DMASA2 (DMA_DCR_BASE + 0x13) /* DMA source address reg 2 */ 46 #define DMASA2 (DMA_DCR_BASE + 0x13) /* DMA source address reg 2 */
47 #define DMASB2 (DMA_DCR_BASE + 0x14) /* DMA sg descriptor addr 2 */ 47 #define DMASB2 (DMA_DCR_BASE + 0x14) /* DMA sg descriptor addr 2 */
48 #define DMACR3 (DMA_DCR_BASE + 0x18) /* DMA channel control reg 3 */ 48 #define DMACR3 (DMA_DCR_BASE + 0x18) /* DMA channel control reg 3 */
49 #define DMACT3 (DMA_DCR_BASE + 0x19) /* DMA count reg 3 */ 49 #define DMACT3 (DMA_DCR_BASE + 0x19) /* DMA count reg 3 */
50 #define DMADA3 (DMA_DCR_BASE + 0x1a) /* DMA destination address reg 3 */ 50 #define DMADA3 (DMA_DCR_BASE + 0x1a) /* DMA destination address reg 3 */
51 #define DMASA3 (DMA_DCR_BASE + 0x1b) /* DMA source address reg 3 */ 51 #define DMASA3 (DMA_DCR_BASE + 0x1b) /* DMA source address reg 3 */
52 #define DMASB3 (DMA_DCR_BASE + 0x1c) /* DMA sg descriptor addr 3 */ 52 #define DMASB3 (DMA_DCR_BASE + 0x1c) /* DMA sg descriptor addr 3 */
53 #define DMASR (DMA_DCR_BASE + 0x20) /* DMA status reg */ 53 #define DMASR (DMA_DCR_BASE + 0x20) /* DMA status reg */
54 #define DMASGC (DMA_DCR_BASE + 0x23) /* DMA scatter/gather command reg*/ 54 #define DMASGC (DMA_DCR_BASE + 0x23) /* DMA scatter/gather command reg*/
55 #define DMAADR (DMA_DCR_BASE + 0x24) /* DMA address decode reg */ 55 #define DMAADR (DMA_DCR_BASE + 0x24) /* DMA address decode reg */
56 56
57 #endif /* __PPC405_H__ */ 57 #endif /* __PPC405_H__ */
58 58
arch/powerpc/include/asm/ppc440.h
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * (C) Copyright 2006 2 * (C) Copyright 2006
3 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com 3 * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com
4 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com 4 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
5 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com 5 * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com
6 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com 6 * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com
7 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com 7 * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com
8 * 8 *
9 * (C) Copyright 2010 9 * (C) Copyright 2010
10 * Stefan Roese, DENX Software Engineering, sr@denx.de. 10 * Stefan Roese, DENX Software Engineering, sr@denx.de.
11 * 11 *
12 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 12 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
13 */ 13 */
14 14
15 #ifndef __PPC440_H__ 15 #ifndef __PPC440_H__
16 #define __PPC440_H__ 16 #define __PPC440_H__
17 17
18 #define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ 18 #define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */
19 19
20 /* 20 /*
21 * DCRs & Related 21 * DCRs & Related
22 */ 22 */
23 23
24 /* Memory mapped registers */ 24 /* Memory mapped registers */
25 #define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000) 25 #define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000)
26 #define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004) 26 #define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004)
27 #define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000) 27 #define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000)
28 #define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000) 28 #define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000)
29 29
30 /* DCR registers */ 30 /* DCR registers */
31 31
32 /* CPR register declarations */ 32 /* CPR register declarations */
33 #define CPR0_PLLC 0x0040 33 #define CPR0_PLLC 0x0040
34 #define CPR0_PLLD 0x0060 34 #define CPR0_PLLD 0x0060
35 #define CPR0_PRIMAD0 0x0080 35 #define CPR0_PRIMAD0 0x0080
36 #define CPR0_PRIMBD0 0x00a0 36 #define CPR0_PRIMBD0 0x00a0
37 #define CPR0_OPBD0 0x00c0 37 #define CPR0_OPBD0 0x00c0
38 #define CPR0_PERD 0x00e0 38 #define CPR0_PERD 0x00e0
39 #define CPR0_MALD 0x0100 39 #define CPR0_MALD 0x0100
40 #define CPR0_SPCID 0x0120 40 #define CPR0_SPCID 0x0120
41 #define CPR0_ICFG 0x0140 41 #define CPR0_ICFG 0x0140
42 42
43 /* SDR register definations */ 43 /* SDR register definations */
44 #define SDR0_SDSTP0 0x0020 44 #define SDR0_SDSTP0 0x0020
45 #define SDR0_SDSTP1 0x0021 45 #define SDR0_SDSTP1 0x0021
46 #define SDR0_PINSTP 0x0040 46 #define SDR0_PINSTP 0x0040
47 #define SDR0_SDCS0 0x0060 47 #define SDR0_SDCS0 0x0060
48 #define SDR0_ECID0 0x0080 48 #define SDR0_ECID0 0x0080
49 #define SDR0_ECID1 0x0081 49 #define SDR0_ECID1 0x0081
50 #define SDR0_ECID2 0x0082 50 #define SDR0_ECID2 0x0082
51 #define SDR0_ECID3 0x0083 51 #define SDR0_ECID3 0x0083
52 #define SDR0_DDR0 0x00e1 52 #define SDR0_DDR0 0x00e1
53 #define SDR0_EBC 0x0100 53 #define SDR0_EBC 0x0100
54 #define SDR0_UART0 0x0120 54 #define SDR0_UART0 0x0120
55 #define SDR0_UART1 0x0121 55 #define SDR0_UART1 0x0121
56 #define SDR0_UART2 0x0122 56 #define SDR0_UART2 0x0122
57 #define SDR0_UART3 0x0123 57 #define SDR0_UART3 0x0123
58 #define SDR0_CP440 0x0180 58 #define SDR0_CP440 0x0180
59 #define SDR0_XCR 0x01c0 59 #define SDR0_XCR 0x01c0
60 #define SDR0_XCR0 0x01c0 60 #define SDR0_XCR0 0x01c0
61 #define SDR0_XPLLC 0x01c1 61 #define SDR0_XPLLC 0x01c1
62 #define SDR0_XPLLD 0x01c2 62 #define SDR0_XPLLD 0x01c2
63 #define SDR0_SRST 0x0200 63 #define SDR0_SRST 0x0200
64 #define SDR0_SRST0 SDR0_SRST 64 #define SDR0_SRST0 SDR0_SRST
65 #define SDR0_SRST1 0x0201 65 #define SDR0_SRST1 0x0201
66 #define SDR0_AMP0 0x0240 66 #define SDR0_AMP0 0x0240
67 #define SDR0_AMP1 0x0241 67 #define SDR0_AMP1 0x0241
68 #define SDR0_USB0 0x0320 68 #define SDR0_USB0 0x0320
69 #define SDR0_CUST0 0x4000 69 #define SDR0_CUST0 0x4000
70 #define SDR0_CUST1 0x4002 70 #define SDR0_CUST1 0x4002
71 #define SDR0_CUST2 0x4004 71 #define SDR0_CUST2 0x4004
72 #define SDR0_CUST3 0x4006 72 #define SDR0_CUST3 0x4006
73 #define SDR0_PFC0 0x4100 73 #define SDR0_PFC0 0x4100
74 #define SDR0_PFC1 0x4101 74 #define SDR0_PFC1 0x4101
75 #define SDR0_PFC2 0x4102 75 #define SDR0_PFC2 0x4102
76 #define SDR0_PFC4 0x4104 76 #define SDR0_PFC4 0x4104
77 #define SDR0_MFR 0x4300 77 #define SDR0_MFR 0x4300
78 78
79 #define SDR0_DDR0_DDRM_DECODE(n) ((((u32)(n)) >> 29) & 0x03) 79 #define SDR0_DDR0_DDRM_DECODE(n) ((((u32)(n)) >> 29) & 0x03)
80 80
81 #define SDR0_PCI0_PAE_MASK (0x80000000 >> 0) 81 #define SDR0_PCI0_PAE_MASK (0x80000000 >> 0)
82 #define SDR0_XCR0_PAE_MASK (0x80000000 >> 0) 82 #define SDR0_XCR0_PAE_MASK (0x80000000 >> 0)
83 83
84 #define SDR0_PFC0_GEIE_MASK 0x00003e00 84 #define SDR0_PFC0_GEIE_MASK 0x00003e00
85 #define SDR0_PFC0_GEIE_TRE 0x00003e00 85 #define SDR0_PFC0_GEIE_TRE 0x00003e00
86 #define SDR0_PFC0_GEIE_NOTRE 0x00000000 86 #define SDR0_PFC0_GEIE_NOTRE 0x00000000
87 #define SDR0_PFC0_TRE_MASK (0x80000000 >> 23) 87 #define SDR0_PFC0_TRE_MASK (0x80000000 >> 23)
88 #define SDR0_PFC0_TRE_DISABLE 0x00000000 88 #define SDR0_PFC0_TRE_DISABLE 0x00000000
89 #define SDR0_PFC0_TRE_ENABLE (0x80000000 >> 23) 89 #define SDR0_PFC0_TRE_ENABLE (0x80000000 >> 23)
90 90
91 /* 91 /*
92 * Core Configuration/MMU configuration for 440 92 * Core Configuration/MMU configuration for 440
93 */ 93 */
94 #define CCR0_DAPUIB 0x00100000 94 #define CCR0_DAPUIB 0x00100000
95 #define CCR0_DTB 0x00008000 95 #define CCR0_DTB 0x00008000
96 96
97 #define SDR0_SDCS_SDD (0x80000000 >> 31) 97 #define SDR0_SDCS_SDD (0x80000000 >> 31)
98 98
99 /* todo: move this code from macro offsets to struct */ 99 /* todo: move this code from macro offsets to struct */
100 #define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID ) 100 #define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID )
101 #define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID ) 101 #define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID )
102 #define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND ) 102 #define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND )
103 #define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS ) 103 #define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS )
104 #define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID ) 104 #define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID )
105 #define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE) 105 #define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE)
106 #define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE ) 106 #define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE )
107 #define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER ) 107 #define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER )
108 #define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE ) 108 #define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE )
109 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST ) 109 #define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST )
110 #define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 ) 110 #define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 )
111 #define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 ) 111 #define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 )
112 #define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 ) 112 #define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 )
113 #define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 ) 113 #define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 )
114 #define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 ) 114 #define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 )
115 #define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 ) 115 #define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 )
116 #define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS ) 116 #define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS )
117 #define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) 117 #define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID )
118 #define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID ) 118 #define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID )
119 #define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS ) 119 #define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS )
120 #define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST ) 120 #define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST )
121 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 ) 121 #define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 )
122 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 ) 122 #define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 )
123 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 ) 123 #define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 )
124 #define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE ) 124 #define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE )
125 #define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN ) 125 #define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN )
126 126
127 #define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT ) 127 #define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT )
128 #define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT ) 128 #define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT )
129 129
130 #define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068) 130 #define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068)
131 #define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c) 131 #define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c)
132 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070) 132 #define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070)
133 #define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074) 133 #define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074)
134 #define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078) 134 #define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078)
135 #define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c) 135 #define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c)
136 #define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080) 136 #define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080)
137 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084) 137 #define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084)
138 #define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088) 138 #define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088)
139 #define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c) 139 #define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c)
140 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090) 140 #define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090)
141 141
142 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098) 142 #define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098)
143 #define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c) 143 #define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c)
144 #define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0) 144 #define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0)
145 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4) 145 #define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4)
146 #define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8) 146 #define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8)
147 #define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac) 147 #define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac)
148 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0) 148 #define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0)
149 #define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4) 149 #define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4)
150 #define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8) 150 #define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8)
151 151
152 #define PCIL0_STS (PCIL0_CFGBASE + 0x00e0) 152 #define PCIL0_STS (PCIL0_CFGBASE + 0x00e0)
153 153
154 #endif /* __PPC440_H__ */ 154 #endif /* __PPC440_H__ */
155 155
arch/powerpc/include/asm/ppc4xx-emac.h
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 /*----------------------------------------------------------------------------+ 4 /*----------------------------------------------------------------------------+
5 | 5 |
6 | File Name: enetemac.h 6 | File Name: enetemac.h
7 | 7 |
8 | Function: Header file for the EMAC3 macro on the 405GP. 8 | Function: Header file for the EMAC3 macro on the 405GP.
9 | 9 |
10 | Author: Mark Wisner 10 | Author: Mark Wisner
11 | 11 |
12 | Change Activity- 12 | Change Activity-
13 | 13 |
14 | Date Description of Change BY 14 | Date Description of Change BY
15 | --------- --------------------- --- 15 | --------- --------------------- ---
16 | 29-Apr-99 Created MKW 16 | 29-Apr-99 Created MKW
17 | 17 |
18 +----------------------------------------------------------------------------*/ 18 +----------------------------------------------------------------------------*/
19 /*----------------------------------------------------------------------------+ 19 /*----------------------------------------------------------------------------+
20 | 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com 20 | 19-Nov-03 Travis Sawyer, Sandburst Corporation, tsawyer@sandburst.com
21 | ported to handle 440GP and 440GX multiple EMACs 21 | ported to handle 440GP and 440GX multiple EMACs
22 +----------------------------------------------------------------------------*/ 22 +----------------------------------------------------------------------------*/
23 23
24 #ifndef _PPC4XX_ENET_H_ 24 #ifndef _PPC4XX_ENET_H_
25 #define _PPC4XX_ENET_H_ 25 #define _PPC4XX_ENET_H_
26 26
27 #include <net.h> 27 #include <net.h>
28 #include "asm/ppc4xx-mal.h" 28 #include "asm/ppc4xx-mal.h"
29 29
30 30
31 /*-----------------------------------------------------------------------------+ 31 /*-----------------------------------------------------------------------------+
32 | General enternet defines. 802 frames are not supported. 32 | General enternet defines. 802 frames are not supported.
33 +-----------------------------------------------------------------------------*/ 33 +-----------------------------------------------------------------------------*/
34 #define ENET_ADDR_LENGTH 6 34 #define ENET_ADDR_LENGTH 6
35 #define ENET_ARPTYPE 0x806 35 #define ENET_ARPTYPE 0x806
36 #define ARP_REQUEST 1 36 #define ARP_REQUEST 1
37 #define ARP_REPLY 2 37 #define ARP_REPLY 2
38 #define ENET_IPTYPE 0x800 38 #define ENET_IPTYPE 0x800
39 #define ARP_CACHE_SIZE 5 39 #define ARP_CACHE_SIZE 5
40 40
41 #define NUM_TX_BUFF 1 41 #define NUM_TX_BUFF 1
42 #define NUM_RX_BUFF PKTBUFSRX 42 #define NUM_RX_BUFF PKTBUFSRX
43 43
44 struct enet_frame { 44 struct enet_frame {
45 unsigned char dest_addr[ENET_ADDR_LENGTH]; 45 unsigned char dest_addr[ENET_ADDR_LENGTH];
46 unsigned char source_addr[ENET_ADDR_LENGTH]; 46 unsigned char source_addr[ENET_ADDR_LENGTH];
47 unsigned short type; 47 unsigned short type;
48 unsigned char enet_data[1]; 48 unsigned char enet_data[1];
49 }; 49 };
50 50
51 struct arp_entry { 51 struct arp_entry {
52 unsigned long inet_address; 52 unsigned long inet_address;
53 unsigned char mac_address[ENET_ADDR_LENGTH]; 53 unsigned char mac_address[ENET_ADDR_LENGTH];
54 unsigned long valid; 54 unsigned long valid;
55 unsigned long sec; 55 unsigned long sec;
56 unsigned long nsec; 56 unsigned long nsec;
57 }; 57 };
58 58
59 59
60 /* Statistic Areas */ 60 /* Statistic Areas */
61 #define MAX_ERR_LOG 10 61 #define MAX_ERR_LOG 10
62 62
63 typedef struct emac_stats_st{ /* Statistic Block */ 63 typedef struct emac_stats_st{ /* Statistic Block */
64 int data_len_err; 64 int data_len_err;
65 int rx_frames; 65 int rx_frames;
66 int rx; 66 int rx;
67 int rx_prot_err; 67 int rx_prot_err;
68 int int_err; 68 int int_err;
69 int pkts_tx; 69 int pkts_tx;
70 int pkts_rx; 70 int pkts_rx;
71 int pkts_handled; 71 int pkts_handled;
72 short tx_err_log[MAX_ERR_LOG]; 72 short tx_err_log[MAX_ERR_LOG];
73 short rx_err_log[MAX_ERR_LOG]; 73 short rx_err_log[MAX_ERR_LOG];
74 } EMAC_STATS_ST, *EMAC_STATS_PST; 74 } EMAC_STATS_ST, *EMAC_STATS_PST;
75 75
76 /* Structure containing variables used by the shared code (4xx_enet.c) */ 76 /* Structure containing variables used by the shared code (4xx_enet.c) */
77 typedef struct emac_4xx_hw_st { 77 typedef struct emac_4xx_hw_st {
78 uint32_t hw_addr; /* EMAC offset */ 78 uint32_t hw_addr; /* EMAC offset */
79 uint32_t tah_addr; /* TAH offset */ 79 uint32_t tah_addr; /* TAH offset */
80 uint32_t phy_id; 80 uint32_t phy_id;
81 uint32_t phy_addr; 81 uint32_t phy_addr;
82 uint32_t original_fc; 82 uint32_t original_fc;
83 uint32_t txcw; 83 uint32_t txcw;
84 uint32_t autoneg_failed; 84 uint32_t autoneg_failed;
85 uint32_t emac_ier; 85 uint32_t emac_ier;
86 volatile mal_desc_t *tx; 86 volatile mal_desc_t *tx;
87 volatile mal_desc_t *rx; 87 volatile mal_desc_t *rx;
88 u32 tx_phys; 88 u32 tx_phys;
89 u32 rx_phys; 89 u32 rx_phys;
90 bd_t *bis; /* for eth_init upon mal error */ 90 bd_t *bis; /* for eth_init upon mal error */
91 mal_desc_t *alloc_tx_buf; 91 mal_desc_t *alloc_tx_buf;
92 mal_desc_t *alloc_rx_buf; 92 mal_desc_t *alloc_rx_buf;
93 char *txbuf_ptr; 93 char *txbuf_ptr;
94 uint16_t devnum; 94 uint16_t devnum;
95 int get_link_status; 95 int get_link_status;
96 int tbi_compatibility_en; 96 int tbi_compatibility_en;
97 int tbi_compatibility_on; 97 int tbi_compatibility_on;
98 int fc_send_xon; 98 int fc_send_xon;
99 int report_tx_early; 99 int report_tx_early;
100 int first_init; 100 int first_init;
101 int tx_err_index; 101 int tx_err_index;
102 int rx_err_index; 102 int rx_err_index;
103 int rx_slot; /* MAL Receive Slot */ 103 int rx_slot; /* MAL Receive Slot */
104 int rx_i_index; /* Receive Interrupt Queue Index */ 104 int rx_i_index; /* Receive Interrupt Queue Index */
105 int rx_u_index; /* Receive User Queue Index */ 105 int rx_u_index; /* Receive User Queue Index */
106 int tx_slot; /* MAL Transmit Slot */ 106 int tx_slot; /* MAL Transmit Slot */
107 int tx_i_index; /* Transmit Interrupt Queue Index */ 107 int tx_i_index; /* Transmit Interrupt Queue Index */
108 int tx_u_index; /* Transmit User Queue Index */ 108 int tx_u_index; /* Transmit User Queue Index */
109 int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */ 109 int rx_ready[NUM_RX_BUFF]; /* Receive Ready Queue */
110 int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */ 110 int tx_run[NUM_TX_BUFF]; /* Transmit Running Queue */
111 int is_receiving; /* sync with eth interrupt */ 111 int is_receiving; /* sync with eth interrupt */
112 int print_speed; /* print speed message upon start */ 112 int print_speed; /* print speed message upon start */
113 EMAC_STATS_ST stats; 113 EMAC_STATS_ST stats;
114 } EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST; 114 } EMAC_4XX_HW_ST, *EMAC_4XX_HW_PST;
115 115
116 116
117 #if defined(CONFIG_440GX) || defined(CONFIG_460GT) 117 #if defined(CONFIG_440GX) || defined(CONFIG_460GT)
118 #define EMAC_NUM_DEV 4 118 #define EMAC_NUM_DEV 4
119 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \ 119 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \
120 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) 120 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
121 #define EMAC_NUM_DEV 2 121 #define EMAC_NUM_DEV 2
122 #else 122 #else
123 #define EMAC_NUM_DEV 1 123 #define EMAC_NUM_DEV 1
124 #endif 124 #endif
125 125
126 #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ 126 #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
127 #define EMAC_STACR_OC_MASK (0x00008000) 127 #define EMAC_STACR_OC_MASK (0x00008000)
128 #else 128 #else
129 #define EMAC_STACR_OC_MASK (0x00000000) 129 #define EMAC_STACR_OC_MASK (0x00000000)
130 #endif 130 #endif
131 131
132 /* 132 /*
133 * XMII bridge configurations for those systems (e.g. 405EX(r)) that do 133 * XMII bridge configurations for those systems (e.g. 405EX(r)) that do
134 * not have a pin function control (PFC) register to otherwise determine 134 * not have a pin function control (PFC) register to otherwise determine
135 * the bridge configuration. 135 * the bridge configuration.
136 */ 136 */
137 #define EMAC_PHY_MODE_NONE 0 137 #define EMAC_PHY_MODE_NONE 0
138 #define EMAC_PHY_MODE_NONE_RGMII 1 138 #define EMAC_PHY_MODE_NONE_RGMII 1
139 #define EMAC_PHY_MODE_RGMII_NONE 2 139 #define EMAC_PHY_MODE_RGMII_NONE 2
140 #define EMAC_PHY_MODE_RGMII_RGMII 3 140 #define EMAC_PHY_MODE_RGMII_RGMII 3
141 #define EMAC_PHY_MODE_NONE_GMII 4 141 #define EMAC_PHY_MODE_NONE_GMII 4
142 #define EMAC_PHY_MODE_GMII_NONE 5 142 #define EMAC_PHY_MODE_GMII_NONE 5
143 #define EMAC_PHY_MODE_NONE_MII 6 143 #define EMAC_PHY_MODE_NONE_MII 6
144 #define EMAC_PHY_MODE_MII_NONE 7 144 #define EMAC_PHY_MODE_MII_NONE 7
145 145
146 /* ZMII Bridge Register addresses */ 146 /* ZMII Bridge Register addresses */
147 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ 147 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
148 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 148 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
149 defined(CONFIG_460EX) || defined(CONFIG_460GT) 149 defined(CONFIG_460EX) || defined(CONFIG_460GT)
150 #define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00) 150 #define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0D00)
151 #else 151 #else
152 #define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780) 152 #define ZMII0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0780)
153 #endif 153 #endif
154 #define ZMII0_FER (ZMII0_BASE) 154 #define ZMII0_FER (ZMII0_BASE)
155 #define ZMII0_SSR (ZMII0_BASE + 4) 155 #define ZMII0_SSR (ZMII0_BASE + 4)
156 #define ZMII0_SMIISR (ZMII0_BASE + 8) 156 #define ZMII0_SMIISR (ZMII0_BASE + 8)
157 157
158 /* ZMII FER Register Bit Definitions */ 158 /* ZMII FER Register Bit Definitions */
159 #define ZMII_FER_DIS (0x0) 159 #define ZMII_FER_DIS (0x0)
160 #define ZMII_FER_MDI (0x8) 160 #define ZMII_FER_MDI (0x8)
161 #define ZMII_FER_SMII (0x4) 161 #define ZMII_FER_SMII (0x4)
162 #define ZMII_FER_RMII (0x2) 162 #define ZMII_FER_RMII (0x2)
163 #define ZMII_FER_MII (0x1) 163 #define ZMII_FER_MII (0x1)
164 164
165 #define ZMII_FER_RSVD11 (0x00200000) 165 #define ZMII_FER_RSVD11 (0x00200000)
166 #define ZMII_FER_RSVD10 (0x00100000) 166 #define ZMII_FER_RSVD10 (0x00100000)
167 #define ZMII_FER_RSVD14_31 (0x0003FFFF) 167 #define ZMII_FER_RSVD14_31 (0x0003FFFF)
168 168
169 #define ZMII_FER_V(__x) (((3 - __x) * 4) + 16) 169 #define ZMII_FER_V(__x) (((3 - __x) * 4) + 16)
170 170
171 171
172 /* ZMII Speed Selection Register Bit Definitions */ 172 /* ZMII Speed Selection Register Bit Definitions */
173 #define ZMII0_SSR_SCI (0x4) 173 #define ZMII0_SSR_SCI (0x4)
174 #define ZMII0_SSR_FSS (0x2) 174 #define ZMII0_SSR_FSS (0x2)
175 #define ZMII0_SSR_SP (0x1) 175 #define ZMII0_SSR_SP (0x1)
176 #define ZMII0_SSR_RSVD16_31 (0x0000FFFF) 176 #define ZMII0_SSR_RSVD16_31 (0x0000FFFF)
177 177
178 #define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16) 178 #define ZMII0_SSR_V(__x) (((3 - __x) * 4) + 16)
179 179
180 180
181 /* ZMII SMII Status Register Bit Definitions */ 181 /* ZMII SMII Status Register Bit Definitions */
182 #define ZMII0_SMIISR_E1 (0x80) 182 #define ZMII0_SMIISR_E1 (0x80)
183 #define ZMII0_SMIISR_EC (0x40) 183 #define ZMII0_SMIISR_EC (0x40)
184 #define ZMII0_SMIISR_EN (0x20) 184 #define ZMII0_SMIISR_EN (0x20)
185 #define ZMII0_SMIISR_EJ (0x10) 185 #define ZMII0_SMIISR_EJ (0x10)
186 #define ZMII0_SMIISR_EL (0x08) 186 #define ZMII0_SMIISR_EL (0x08)
187 #define ZMII0_SMIISR_ED (0x04) 187 #define ZMII0_SMIISR_ED (0x04)
188 #define ZMII0_SMIISR_ES (0x02) 188 #define ZMII0_SMIISR_ES (0x02)
189 #define ZMII0_SMIISR_EF (0x01) 189 #define ZMII0_SMIISR_EF (0x01)
190 190
191 #define ZMII0_SMIISR_V(__x) ((3 - __x) * 8) 191 #define ZMII0_SMIISR_V(__x) ((3 - __x) * 8)
192 192
193 /* RGMII Register Addresses */ 193 /* RGMII Register Addresses */
194 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) 194 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
195 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1000) 195 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1000)
196 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) 196 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
197 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1500) 197 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x1500)
198 #elif defined(CONFIG_405EX) 198 #elif defined(CONFIG_405EX)
199 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0xB00) 199 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0xB00)
200 #else 200 #else
201 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0790) 201 #define RGMII_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0790)
202 #endif 202 #endif
203 #define RGMII_FER (RGMII_BASE + 0x00) 203 #define RGMII_FER (RGMII_BASE + 0x00)
204 #define RGMII_SSR (RGMII_BASE + 0x04) 204 #define RGMII_SSR (RGMII_BASE + 0x04)
205 205
206 #if defined(CONFIG_460GT) 206 #if defined(CONFIG_460GT)
207 #define RGMII1_BASE_OFFSET 0x100 207 #define RGMII1_BASE_OFFSET 0x100
208 #endif 208 #endif
209 209
210 /* RGMII Function Enable (FER) Register Bit Definitions */ 210 /* RGMII Function Enable (FER) Register Bit Definitions */
211 #define RGMII_FER_DIS (0x00) 211 #define RGMII_FER_DIS (0x00)
212 #define RGMII_FER_RTBI (0x04) 212 #define RGMII_FER_RTBI (0x04)
213 #define RGMII_FER_RGMII (0x05) 213 #define RGMII_FER_RGMII (0x05)
214 #define RGMII_FER_TBI (0x06) 214 #define RGMII_FER_TBI (0x06)
215 #define RGMII_FER_GMII (0x07) 215 #define RGMII_FER_GMII (0x07)
216 #define RGMII_FER_MII (RGMII_FER_GMII) 216 #define RGMII_FER_MII (RGMII_FER_GMII)
217 217
218 #define RGMII_FER_V(__x) ((__x - 2) * 4) 218 #define RGMII_FER_V(__x) ((__x - 2) * 4)
219 219
220 #define RGMII_FER_MDIO(__x) (1 << (19 - (__x))) 220 #define RGMII_FER_MDIO(__x) (1 << (19 - (__x)))
221 221
222 /* RGMII Speed Selection Register Bit Definitions */ 222 /* RGMII Speed Selection Register Bit Definitions */
223 #define RGMII_SSR_SP_10MBPS (0x00) 223 #define RGMII_SSR_SP_10MBPS (0x00)
224 #define RGMII_SSR_SP_100MBPS (0x02) 224 #define RGMII_SSR_SP_100MBPS (0x02)
225 #define RGMII_SSR_SP_1000MBPS (0x04) 225 #define RGMII_SSR_SP_1000MBPS (0x04)
226 226
227 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 227 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
228 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 228 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
229 defined(CONFIG_405EX) 229 defined(CONFIG_405EX)
230 #define RGMII_SSR_V(__x) ((__x) * 8) 230 #define RGMII_SSR_V(__x) ((__x) * 8)
231 #else 231 #else
232 #define RGMII_SSR_V(__x) ((__x -2) * 8) 232 #define RGMII_SSR_V(__x) ((__x -2) * 8)
233 #endif 233 #endif
234 234
235 /*---------------------------------------------------------------------------+ 235 /*---------------------------------------------------------------------------+
236 | TCP/IP Acceleration Hardware (TAH) 440GX Only 236 | TCP/IP Acceleration Hardware (TAH) 440GX Only
237 +---------------------------------------------------------------------------*/ 237 +---------------------------------------------------------------------------*/
238 #if defined(CONFIG_440GX) 238 #if defined(CONFIG_440GX)
239 #define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50) 239 #define TAH_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0B50)
240 #define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/ 240 #define TAH_REVID (TAH_BASE + 0x0) /* Revision ID (RO)*/
241 #define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */ 241 #define TAH_MR (TAH_BASE + 0x10) /* Mode Register (R/W) */
242 #define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */ 242 #define TAH_SSR0 (TAH_BASE + 0x14) /* Segment Size Reg 0 (R/W) */
243 #define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */ 243 #define TAH_SSR1 (TAH_BASE + 0x18) /* Segment Size Reg 1 (R/W) */
244 #define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */ 244 #define TAH_SSR2 (TAH_BASE + 0x1C) /* Segment Size Reg 2 (R/W) */
245 #define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */ 245 #define TAH_SSR3 (TAH_BASE + 0x20) /* Segment Size Reg 3 (R/W) */
246 #define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */ 246 #define TAH_SSR4 (TAH_BASE + 0x24) /* Segment Size Reg 4 (R/W) */
247 #define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */ 247 #define TAH_SSR5 (TAH_BASE + 0x28) /* Segment Size Reg 5 (R/W) */
248 #define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */ 248 #define TAH_TSR (TAH_BASE + 0x2C) /* Transmit Status Register (RO) */
249 249
250 /* TAH Revision */ 250 /* TAH Revision */
251 #define TAH_REV_RN_M (0x000FFF00) /* Revision Number */ 251 #define TAH_REV_RN_M (0x000FFF00) /* Revision Number */
252 #define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */ 252 #define TAH_REV_BN_M (0x000000FF) /* Branch Revision Number */
253 253
254 #define TAH_REV_RN_V (8) 254 #define TAH_REV_RN_V (8)
255 #define TAH_REV_BN_V (0) 255 #define TAH_REV_BN_V (0)
256 256
257 /* TAH Mode Register */ 257 /* TAH Mode Register */
258 #define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */ 258 #define TAH_MR_CVR (0x80000000) /* Checksum verification on RX */
259 #define TAH_MR_SR (0x40000000) /* Software reset */ 259 #define TAH_MR_SR (0x40000000) /* Software reset */
260 #define TAH_MR_ST (0x3F000000) /* Send Threshold */ 260 #define TAH_MR_ST (0x3F000000) /* Send Threshold */
261 #define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */ 261 #define TAH_MR_TFS (0x00E00000) /* Transmit FIFO size */
262 #define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */ 262 #define TAH_MR_DTFP (0x00100000) /* Disable TX FIFO parity */
263 #define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */ 263 #define TAH_MR_DIG (0x00080000) /* Disable interrupt generation */
264 #define TAH_MR_RSVD (0x0007FFFF) /* Reserved */ 264 #define TAH_MR_RSVD (0x0007FFFF) /* Reserved */
265 265
266 #define TAH_MR_ST_V (20) 266 #define TAH_MR_ST_V (20)
267 #define TAH_MR_TFS_V (17) 267 #define TAH_MR_TFS_V (17)
268 268
269 #define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */ 269 #define TAH_MR_TFS_2K (0x1) /* Transmit FIFO size 2Kbyte */
270 #define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */ 270 #define TAH_MR_TFS_4K (0x2) /* Transmit FIFO size 4Kbyte */
271 #define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */ 271 #define TAH_MR_TFS_6K (0x3) /* Transmit FIFO size 6Kbyte */
272 #define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */ 272 #define TAH_MR_TFS_8K (0x4) /* Transmit FIFO size 8Kbyte */
273 #define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/ 273 #define TAH_MR_TFS_10K (0x5) /* Transmit FIFO size 10Kbyte (max)*/
274 274
275 275
276 /* TAH Segment Size Registers 0:5 */ 276 /* TAH Segment Size Registers 0:5 */
277 #define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */ 277 #define TAH_SSR_RSVD0 (0xC0000000) /* Reserved */
278 #define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */ 278 #define TAH_SSR_SS (0x3FFE0000) /* Segment size in multiples of 2 */
279 #define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */ 279 #define TAH_SSR_RSVD1 (0x0001FFFF) /* Reserved */
280 280
281 /* TAH Transmit Status Register */ 281 /* TAH Transmit Status Register */
282 #define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */ 282 #define TAH_TSR_TFTS (0x80000000) /* Transmit FIFO too small */
283 #define TAH_TSR_UH (0x40000000) /* Unrecognized header */ 283 #define TAH_TSR_UH (0x40000000) /* Unrecognized header */
284 #define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */ 284 #define TAH_TSR_NIPF (0x20000000) /* Not IPv4 */
285 #define TAH_TSR_IPOP (0x10000000) /* IP option present */ 285 #define TAH_TSR_IPOP (0x10000000) /* IP option present */
286 #define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */ 286 #define TAH_TSR_NISF (0x08000000) /* No IEEE SNAP format */
287 #define TAH_TSR_ILTS (0x04000000) /* IP length too short */ 287 #define TAH_TSR_ILTS (0x04000000) /* IP length too short */
288 #define TAH_TSR_IPFP (0x02000000) /* IP fragment present */ 288 #define TAH_TSR_IPFP (0x02000000) /* IP fragment present */
289 #define TAH_TSR_UP (0x01000000) /* Unsupported protocol */ 289 #define TAH_TSR_UP (0x01000000) /* Unsupported protocol */
290 #define TAH_TSR_TFP (0x00800000) /* TCP flags present */ 290 #define TAH_TSR_TFP (0x00800000) /* TCP flags present */
291 #define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */ 291 #define TAH_TSR_SUDP (0x00400000) /* Segmentation for UDP */
292 #define TAH_TSR_DLM (0x00200000) /* Data length mismatch */ 292 #define TAH_TSR_DLM (0x00200000) /* Data length mismatch */
293 #define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */ 293 #define TAH_TSR_SIEEE (0x00100000) /* Segmentation for IEEE */
294 #define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */ 294 #define TAH_TSR_TFPE (0x00080000) /* Transmit FIFO parity error */
295 #define TAH_TSR_SSTS (0x00040000) /* Segment size too small */ 295 #define TAH_TSR_SSTS (0x00040000) /* Segment size too small */
296 #define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */ 296 #define TAH_TSR_RSVD (0x0003FFFF) /* Reserved */
297 #endif /* CONFIG_440GX */ 297 #endif /* CONFIG_440GX */
298 298
299 299
300 /* Ethernet MAC Regsiter Addresses */ 300 /* Ethernet MAC Regsiter Addresses */
301 #if defined(CONFIG_440) 301 #if defined(CONFIG_440)
302 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ 302 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \
303 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 303 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
304 defined(CONFIG_460EX) || defined(CONFIG_460GT) 304 defined(CONFIG_460EX) || defined(CONFIG_460GT)
305 #define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00) 305 #define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0E00)
306 #else 306 #else
307 #define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800) 307 #define EMAC0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800)
308 #endif 308 #endif
309 #else 309 #else
310 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX) 310 #if defined(CONFIG_405EZ) || defined(CONFIG_405EX)
311 #define EMAC0_BASE 0xEF600900 311 #define EMAC0_BASE 0xEF600900
312 #else 312 #else
313 #define EMAC0_BASE 0xEF600800 313 #define EMAC0_BASE 0xEF600800
314 #endif 314 #endif
315 #endif 315 #endif
316 316
317 #if defined(CONFIG_440EPX) 317 #if defined(CONFIG_440EPX)
318 #define EMAC1_BASE 0xEF600F00 318 #define EMAC1_BASE 0xEF600F00
319 #define EMAC1_MR1 (EMAC1_BASE + 0x04) 319 #define EMAC1_MR1 (EMAC1_BASE + 0x04)
320 #endif 320 #endif
321 321
322 #define EMAC0_MR0 (EMAC0_BASE) 322 #define EMAC0_MR0 (EMAC0_BASE)
323 #define EMAC0_MR1 (EMAC0_BASE + 0x04) 323 #define EMAC0_MR1 (EMAC0_BASE + 0x04)
324 #define EMAC0_TMR0 (EMAC0_BASE + 0x08) 324 #define EMAC0_TMR0 (EMAC0_BASE + 0x08)
325 #define EMAC0_TMR1 (EMAC0_BASE + 0x0c) 325 #define EMAC0_TMR1 (EMAC0_BASE + 0x0c)
326 #define EMAC0_RXM (EMAC0_BASE + 0x10) 326 #define EMAC0_RXM (EMAC0_BASE + 0x10)
327 #define EMAC0_ISR (EMAC0_BASE + 0x14) 327 #define EMAC0_ISR (EMAC0_BASE + 0x14)
328 #define EMAC0_IER (EMAC0_BASE + 0x18) 328 #define EMAC0_IER (EMAC0_BASE + 0x18)
329 #define EMAC0_IAH (EMAC0_BASE + 0x1c) 329 #define EMAC0_IAH (EMAC0_BASE + 0x1c)
330 #define EMAC0_IAL (EMAC0_BASE + 0x20) 330 #define EMAC0_IAL (EMAC0_BASE + 0x20)
331 #define EMAC0_PTR (EMAC0_BASE + 0x2c) 331 #define EMAC0_PTR (EMAC0_BASE + 0x2c)
332 #define EMAC0_PAUSE_TIME_REG EMAC0_PTR 332 #define EMAC0_PAUSE_TIME_REG EMAC0_PTR
333 #define EMAC0_IPGVR (EMAC0_BASE + 0x58) 333 #define EMAC0_IPGVR (EMAC0_BASE + 0x58)
334 #define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR 334 #define EMAC0_I_FRAME_GAP_REG EMAC0_IPGVR
335 #define EMAC0_STACR (EMAC0_BASE + 0x5c) 335 #define EMAC0_STACR (EMAC0_BASE + 0x5c)
336 #define EMAC0_TRTR (EMAC0_BASE + 0x60) 336 #define EMAC0_TRTR (EMAC0_BASE + 0x60)
337 #define EMAC0_RWMR (EMAC0_BASE + 0x64) 337 #define EMAC0_RWMR (EMAC0_BASE + 0x64)
338 #define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR 338 #define EMAC0_RX_HI_LO_WMARK EMAC0_RWMR
339 339
340 /* bit definitions */ 340 /* bit definitions */
341 /* MODE REG 0 */ 341 /* MODE REG 0 */
342 #define EMAC_MR0_RXI (0x80000000) 342 #define EMAC_MR0_RXI (0x80000000)
343 #define EMAC_MR0_TXI (0x40000000) 343 #define EMAC_MR0_TXI (0x40000000)
344 #define EMAC_MR0_SRST (0x20000000) 344 #define EMAC_MR0_SRST (0x20000000)
345 #define EMAC_MR0_TXE (0x10000000) 345 #define EMAC_MR0_TXE (0x10000000)
346 #define EMAC_MR0_RXE (0x08000000) 346 #define EMAC_MR0_RXE (0x08000000)
347 #define EMAC_MR0_WKE (0x04000000) 347 #define EMAC_MR0_WKE (0x04000000)
348 348
349 /* on 440GX EMAC_MR1 has a different layout! */ 349 /* on 440GX EMAC_MR1 has a different layout! */
350 #if defined(CONFIG_440GX) || \ 350 #if defined(CONFIG_440GX) || \
351 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 351 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
352 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ 352 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
353 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 353 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
354 defined(CONFIG_405EX) 354 defined(CONFIG_405EX)
355 /* MODE Reg 1 */ 355 /* MODE Reg 1 */
356 #define EMAC_MR1_FDE (0x80000000) 356 #define EMAC_MR1_FDE (0x80000000)
357 #define EMAC_MR1_ILE (0x40000000) 357 #define EMAC_MR1_ILE (0x40000000)
358 #define EMAC_MR1_VLE (0x20000000) 358 #define EMAC_MR1_VLE (0x20000000)
359 #define EMAC_MR1_EIFC (0x10000000) 359 #define EMAC_MR1_EIFC (0x10000000)
360 #define EMAC_MR1_APP (0x08000000) 360 #define EMAC_MR1_APP (0x08000000)
361 #define EMAC_MR1_RSVD (0x06000000) 361 #define EMAC_MR1_RSVD (0x06000000)
362 #define EMAC_MR1_IST (0x01000000) 362 #define EMAC_MR1_IST (0x01000000)
363 #define EMAC_MR1_MF_1000GPCS (0x00C00000) 363 #define EMAC_MR1_MF_1000GPCS (0x00C00000)
364 #define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ 364 #define EMAC_MR1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */
365 #define EMAC_MR1_MF_100MBPS (0x00400000) 365 #define EMAC_MR1_MF_100MBPS (0x00400000)
366 #define EMAC_MR1_RFS_MASK (0x00380000) 366 #define EMAC_MR1_RFS_MASK (0x00380000)
367 #define EMAC_MR1_RFS_16K (0x00280000) 367 #define EMAC_MR1_RFS_16K (0x00280000)
368 #define EMAC_MR1_RFS_8K (0x00200000) 368 #define EMAC_MR1_RFS_8K (0x00200000)
369 #define EMAC_MR1_RFS_4K (0x00180000) 369 #define EMAC_MR1_RFS_4K (0x00180000)
370 #define EMAC_MR1_RFS_2K (0x00100000) 370 #define EMAC_MR1_RFS_2K (0x00100000)
371 #define EMAC_MR1_RFS_1K (0x00080000) 371 #define EMAC_MR1_RFS_1K (0x00080000)
372 #define EMAC_MR1_TX_FIFO_MASK (0x00070000) 372 #define EMAC_MR1_TX_FIFO_MASK (0x00070000)
373 #define EMAC_MR1_TX_FIFO_16K (0x00050000) 373 #define EMAC_MR1_TX_FIFO_16K (0x00050000)
374 #define EMAC_MR1_TX_FIFO_8K (0x00040000) 374 #define EMAC_MR1_TX_FIFO_8K (0x00040000)
375 #define EMAC_MR1_TX_FIFO_4K (0x00030000) 375 #define EMAC_MR1_TX_FIFO_4K (0x00030000)
376 #define EMAC_MR1_TX_FIFO_2K (0x00020000) 376 #define EMAC_MR1_TX_FIFO_2K (0x00020000)
377 #define EMAC_MR1_TX_FIFO_1K (0x00010000) 377 #define EMAC_MR1_TX_FIFO_1K (0x00010000)
378 #define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */ 378 #define EMAC_MR1_TR_MULTI (0x00008000) /* 0'x for single packet */
379 #define EMAC_MR1_MWSW (0x00007000) 379 #define EMAC_MR1_MWSW (0x00007000)
380 #define EMAC_MR1_JUMBO_ENABLE (0x00000800) 380 #define EMAC_MR1_JUMBO_ENABLE (0x00000800)
381 #define EMAC_MR1_IPPA (0x000007c0) 381 #define EMAC_MR1_IPPA (0x000007c0)
382 #define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6) 382 #define EMAC_MR1_IPPA_SET(id) (((id) & 0x1f) << 6)
383 #define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f) 383 #define EMAC_MR1_IPPA_GET(id) (((id) >> 6) & 0x1f)
384 #define EMAC_MR1_OBCI_GT100 (0x00000020) 384 #define EMAC_MR1_OBCI_GT100 (0x00000020)
385 #define EMAC_MR1_OBCI_100 (0x00000018) 385 #define EMAC_MR1_OBCI_100 (0x00000018)
386 #define EMAC_MR1_OBCI_83 (0x00000010) 386 #define EMAC_MR1_OBCI_83 (0x00000010)
387 #define EMAC_MR1_OBCI_66 (0x00000008) 387 #define EMAC_MR1_OBCI_66 (0x00000008)
388 #define EMAC_MR1_RSVD1 (0x00000007) 388 #define EMAC_MR1_RSVD1 (0x00000007)
389 #else /* defined(CONFIG_440GX) */ 389 #else /* defined(CONFIG_440GX) */
390 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */ 390 /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */
391 #define EMAC_MR1_FDE 0x80000000 391 #define EMAC_MR1_FDE 0x80000000
392 #define EMAC_MR1_ILE 0x40000000 392 #define EMAC_MR1_ILE 0x40000000
393 #define EMAC_MR1_VLE 0x20000000 393 #define EMAC_MR1_VLE 0x20000000
394 #define EMAC_MR1_EIFC 0x10000000 394 #define EMAC_MR1_EIFC 0x10000000
395 #define EMAC_MR1_APP 0x08000000 395 #define EMAC_MR1_APP 0x08000000
396 #define EMAC_MR1_AEMI 0x02000000 396 #define EMAC_MR1_AEMI 0x02000000
397 #define EMAC_MR1_IST 0x01000000 397 #define EMAC_MR1_IST 0x01000000
398 #define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ 398 #define EMAC_MR1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */
399 #define EMAC_MR1_MF_100MBPS 0x00400000 399 #define EMAC_MR1_MF_100MBPS 0x00400000
400 #define EMAC_MR1_RFS_MASK 0x00300000 400 #define EMAC_MR1_RFS_MASK 0x00300000
401 #define EMAC_MR1_RFS_4K 0x00300000 401 #define EMAC_MR1_RFS_4K 0x00300000
402 #define EMAC_MR1_RFS_2K 0x00200000 402 #define EMAC_MR1_RFS_2K 0x00200000
403 #define EMAC_MR1_RFS_1K 0x00100000 403 #define EMAC_MR1_RFS_1K 0x00100000
404 #define EMAC_MR1_RFS_512 0x00000000 404 #define EMAC_MR1_RFS_512 0x00000000
405 #define EMAC_MR1_TX_FIFO_MASK 0x000c0000 405 #define EMAC_MR1_TX_FIFO_MASK 0x000c0000
406 #define EMAC_MR1_TX_FIFO_2K 0x00080000 406 #define EMAC_MR1_TX_FIFO_2K 0x00080000
407 #define EMAC_MR1_TX_FIFO_1K 0x00040000 407 #define EMAC_MR1_TX_FIFO_1K 0x00040000
408 #define EMAC_MR1_TX_FIFO_512 0x00000000 408 #define EMAC_MR1_TX_FIFO_512 0x00000000
409 #define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ 409 #define EMAC_MR1_TR0_DEPEND 0x00010000 /* 0'x for single packet */
410 #define EMAC_MR1_TR0_MULTI 0x00008000 410 #define EMAC_MR1_TR0_MULTI 0x00008000
411 #define EMAC_MR1_TR1_DEPEND 0x00004000 411 #define EMAC_MR1_TR1_DEPEND 0x00004000
412 #define EMAC_MR1_TR1_MULTI 0x00002000 412 #define EMAC_MR1_TR1_MULTI 0x00002000
413 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) 413 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
414 #define EMAC_MR1_JUMBO_ENABLE 0x00001000 414 #define EMAC_MR1_JUMBO_ENABLE 0x00001000
415 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ 415 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */
416 #endif /* defined(CONFIG_440GX) */ 416 #endif /* defined(CONFIG_440GX) */
417 417
418 #define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK) 418 #define EMAC_MR1_FIFO_MASK (EMAC_MR1_RFS_MASK | EMAC_MR1_TX_FIFO_MASK)
419 #if defined(CONFIG_405EZ) 419 #if defined(CONFIG_405EZ)
420 /* 405EZ only supports 512 bytes fifos */ 420 /* 405EZ only supports 512 bytes fifos */
421 #define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512) 421 #define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_512 | EMAC_MR1_TX_FIFO_512)
422 #else 422 #else
423 /* Set receive fifo to 4k and tx fifo to 2k */ 423 /* Set receive fifo to 4k and tx fifo to 2k */
424 #define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K) 424 #define EMAC_MR1_FIFO_SIZE (EMAC_MR1_RFS_4K | EMAC_MR1_TX_FIFO_2K)
425 #endif 425 #endif
426 426
427 /* Transmit Mode Register 0 */ 427 /* Transmit Mode Register 0 */
428 #define EMAC_TMR0_GNP0 (0x80000000) 428 #define EMAC_TMR0_GNP0 (0x80000000)
429 #define EMAC_TMR0_GNP1 (0x40000000) 429 #define EMAC_TMR0_GNP1 (0x40000000)
430 #define EMAC_TMR0_GNPD (0x20000000) 430 #define EMAC_TMR0_GNPD (0x20000000)
431 #define EMAC_TMR0_FC (0x10000000) 431 #define EMAC_TMR0_FC (0x10000000)
432 432
433 /* Receive Mode Register */ 433 /* Receive Mode Register */
434 #define EMAC_RMR_SP (0x80000000) 434 #define EMAC_RMR_SP (0x80000000)
435 #define EMAC_RMR_SFCS (0x40000000) 435 #define EMAC_RMR_SFCS (0x40000000)
436 #define EMAC_RMR_ARRP (0x20000000) 436 #define EMAC_RMR_ARRP (0x20000000)
437 #define EMAC_RMR_ARP (0x10000000) 437 #define EMAC_RMR_ARP (0x10000000)
438 #define EMAC_RMR_AROP (0x08000000) 438 #define EMAC_RMR_AROP (0x08000000)
439 #define EMAC_RMR_ARPI (0x04000000) 439 #define EMAC_RMR_ARPI (0x04000000)
440 #define EMAC_RMR_PPP (0x02000000) 440 #define EMAC_RMR_PPP (0x02000000)
441 #define EMAC_RMR_PME (0x01000000) 441 #define EMAC_RMR_PME (0x01000000)
442 #define EMAC_RMR_PMME (0x00800000) 442 #define EMAC_RMR_PMME (0x00800000)
443 #define EMAC_RMR_IAE (0x00400000) 443 #define EMAC_RMR_IAE (0x00400000)
444 #define EMAC_RMR_MIAE (0x00200000) 444 #define EMAC_RMR_MIAE (0x00200000)
445 #define EMAC_RMR_BAE (0x00100000) 445 #define EMAC_RMR_BAE (0x00100000)
446 #define EMAC_RMR_MAE (0x00080000) 446 #define EMAC_RMR_MAE (0x00080000)
447 447
448 /* Interrupt Status & enable Regs */ 448 /* Interrupt Status & enable Regs */
449 #define EMAC_ISR_OVR (0x02000000) 449 #define EMAC_ISR_OVR (0x02000000)
450 #define EMAC_ISR_PP (0x01000000) 450 #define EMAC_ISR_PP (0x01000000)
451 #define EMAC_ISR_BP (0x00800000) 451 #define EMAC_ISR_BP (0x00800000)
452 #define EMAC_ISR_RP (0x00400000) 452 #define EMAC_ISR_RP (0x00400000)
453 #define EMAC_ISR_SE (0x00200000) 453 #define EMAC_ISR_SE (0x00200000)
454 #define EMAC_ISR_SYE (0x00100000) 454 #define EMAC_ISR_SYE (0x00100000)
455 #define EMAC_ISR_BFCS (0x00080000) 455 #define EMAC_ISR_BFCS (0x00080000)
456 #define EMAC_ISR_PTLE (0x00040000) 456 #define EMAC_ISR_PTLE (0x00040000)
457 #define EMAC_ISR_ORE (0x00020000) 457 #define EMAC_ISR_ORE (0x00020000)
458 #define EMAC_ISR_IRE (0x00010000) 458 #define EMAC_ISR_IRE (0x00010000)
459 #define EMAC_ISR_DBDM (0x00000200) 459 #define EMAC_ISR_DBDM (0x00000200)
460 #define EMAC_ISR_DB0 (0x00000100) 460 #define EMAC_ISR_DB0 (0x00000100)
461 #define EMAC_ISR_SE0 (0x00000080) 461 #define EMAC_ISR_SE0 (0x00000080)
462 #define EMAC_ISR_TE0 (0x00000040) 462 #define EMAC_ISR_TE0 (0x00000040)
463 #define EMAC_ISR_DB1 (0x00000020) 463 #define EMAC_ISR_DB1 (0x00000020)
464 #define EMAC_ISR_SE1 (0x00000010) 464 #define EMAC_ISR_SE1 (0x00000010)
465 #define EMAC_ISR_TE1 (0x00000008) 465 #define EMAC_ISR_TE1 (0x00000008)
466 #define EMAC_ISR_MOS (0x00000002) 466 #define EMAC_ISR_MOS (0x00000002)
467 #define EMAC_ISR_MOF (0x00000001) 467 #define EMAC_ISR_MOF (0x00000001)
468 468
469 /* STA CONTROL REG */ 469 /* STA CONTROL REG */
470 #define EMAC_STACR_OC (0x00008000) 470 #define EMAC_STACR_OC (0x00008000)
471 #define EMAC_STACR_PHYE (0x00004000) 471 #define EMAC_STACR_PHYE (0x00004000)
472 472
473 #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ 473 #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */
474 #define EMAC_STACR_INDIRECT_MODE (0x00002000) 474 #define EMAC_STACR_INDIRECT_MODE (0x00002000)
475 #define EMAC_STACR_WRITE (0x00000800) /* $BUC */ 475 #define EMAC_STACR_WRITE (0x00000800) /* $BUC */
476 #define EMAC_STACR_READ (0x00001000) /* $BUC */ 476 #define EMAC_STACR_READ (0x00001000) /* $BUC */
477 #define EMAC_STACR_OP_MASK (0x00001800) 477 #define EMAC_STACR_OP_MASK (0x00001800)
478 #define EMAC_STACR_MDIO_ADDR (0x00000000) 478 #define EMAC_STACR_MDIO_ADDR (0x00000000)
479 #define EMAC_STACR_MDIO_WRITE (0x00000800) 479 #define EMAC_STACR_MDIO_WRITE (0x00000800)
480 #define EMAC_STACR_MDIO_READ (0x00001800) 480 #define EMAC_STACR_MDIO_READ (0x00001800)
481 #define EMAC_STACR_MDIO_READ_INC (0x00001000) 481 #define EMAC_STACR_MDIO_READ_INC (0x00001000)
482 #else 482 #else
483 #define EMAC_STACR_WRITE (0x00002000) 483 #define EMAC_STACR_WRITE (0x00002000)
484 #define EMAC_STACR_READ (0x00001000) 484 #define EMAC_STACR_READ (0x00001000)
485 #endif 485 #endif
486 486
487 #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */ 487 #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */
488 #define EMAC_STACR_CLK_66MHZ (0x00000400) 488 #define EMAC_STACR_CLK_66MHZ (0x00000400)
489 #define EMAC_STACR_CLK_100MHZ (0x00000C00) 489 #define EMAC_STACR_CLK_100MHZ (0x00000C00)
490 490
491 /* Transmit Request Threshold Register */ 491 /* Transmit Request Threshold Register */
492 #define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */ 492 #define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */
493 #define EMAC_TRTR_192 (0x10000000) 493 #define EMAC_TRTR_192 (0x10000000)
494 #define EMAC_TRTR_128 (0x01000000) 494 #define EMAC_TRTR_128 (0x01000000)
495 495
496 /* the follwing defines are for the MadMAL status and control registers. */ 496 /* the follwing defines are for the MadMAL status and control registers. */
497 /* For bits 0..5 look at the mal.h file */ 497 /* For bits 0..5 look at the mal.h file */
498 #define EMAC_TX_CTRL_GFCS (0x0200) 498 #define EMAC_TX_CTRL_GFCS (0x0200)
499 #define EMAC_TX_CTRL_GP (0x0100) 499 #define EMAC_TX_CTRL_GP (0x0100)
500 #define EMAC_TX_CTRL_ISA (0x0080) 500 #define EMAC_TX_CTRL_ISA (0x0080)
501 #define EMAC_TX_CTRL_RSA (0x0040) 501 #define EMAC_TX_CTRL_RSA (0x0040)
502 #define EMAC_TX_CTRL_IVT (0x0020) 502 #define EMAC_TX_CTRL_IVT (0x0020)
503 #define EMAC_TX_CTRL_RVT (0x0010) 503 #define EMAC_TX_CTRL_RVT (0x0010)
504 504
505 #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP) 505 #define EMAC_TX_CTRL_DEFAULT (EMAC_TX_CTRL_GFCS |EMAC_TX_CTRL_GP)
506 506
507 #define EMAC_TX_ST_BFCS (0x0200) 507 #define EMAC_TX_ST_BFCS (0x0200)
508 #define EMAC_TX_ST_BPP (0x0100) 508 #define EMAC_TX_ST_BPP (0x0100)
509 #define EMAC_TX_ST_LCS (0x0080) 509 #define EMAC_TX_ST_LCS (0x0080)
510 #define EMAC_TX_ST_ED (0x0040) 510 #define EMAC_TX_ST_ED (0x0040)
511 #define EMAC_TX_ST_EC (0x0020) 511 #define EMAC_TX_ST_EC (0x0020)
512 #define EMAC_TX_ST_LC (0x0010) 512 #define EMAC_TX_ST_LC (0x0010)
513 #define EMAC_TX_ST_MC (0x0008) 513 #define EMAC_TX_ST_MC (0x0008)
514 #define EMAC_TX_ST_SC (0x0004) 514 #define EMAC_TX_ST_SC (0x0004)
515 #define EMAC_TX_ST_UR (0x0002) 515 #define EMAC_TX_ST_UR (0x0002)
516 #define EMAC_TX_ST_SQE (0x0001) 516 #define EMAC_TX_ST_SQE (0x0001)
517 517
518 #define EMAC_TX_ST_DEFAULT (0x03F3) 518 #define EMAC_TX_ST_DEFAULT (0x03F3)
519 519
520 520
521 /* madmal receive status / Control bits */ 521 /* madmal receive status / Control bits */
522 522
523 #define EMAC_RX_ST_OE (0x0200) 523 #define EMAC_RX_ST_OE (0x0200)
524 #define EMAC_RX_ST_PP (0x0100) 524 #define EMAC_RX_ST_PP (0x0100)
525 #define EMAC_RX_ST_BP (0x0080) 525 #define EMAC_RX_ST_BP (0x0080)
526 #define EMAC_RX_ST_RP (0x0040) 526 #define EMAC_RX_ST_RP (0x0040)
527 #define EMAC_RX_ST_SE (0x0020) 527 #define EMAC_RX_ST_SE (0x0020)
528 #define EMAC_RX_ST_AE (0x0010) 528 #define EMAC_RX_ST_AE (0x0010)
529 #define EMAC_RX_ST_BFCS (0x0008) 529 #define EMAC_RX_ST_BFCS (0x0008)
530 #define EMAC_RX_ST_PTL (0x0004) 530 #define EMAC_RX_ST_PTL (0x0004)
531 #define EMAC_RX_ST_ORE (0x0002) 531 #define EMAC_RX_ST_ORE (0x0002)
532 #define EMAC_RX_ST_IRE (0x0001) 532 #define EMAC_RX_ST_IRE (0x0001)
533 /* all the errors we care about */ 533 /* all the errors we care about */
534 #define EMAC_RX_ERRORS (0x03FF) 534 #define EMAC_RX_ERRORS (0x03FF)
535 535
536 #endif /* _PPC4XX_ENET_H_ */ 536 #endif /* _PPC4XX_ENET_H_ */
537 537
arch/powerpc/include/asm/ppc4xx-mal.h
Diff comments   View file @ 1b387ef
1 /* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */ 1 /* include/mal.h, openbios_walnut, walnut_bios 8/6/99 08:48:40 */
2 /* 2 /*
3 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 3 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
4 */ 4 */
5 /*----------------------------------------------------------------------------+ 5 /*----------------------------------------------------------------------------+
6 | 6 |
7 | File Name: mal.h 7 | File Name: mal.h
8 | 8 |
9 | Function: Header file for the MAL (MADMAL) macro on the 405GP. 9 | Function: Header file for the MAL (MADMAL) macro on the 405GP.
10 | 10 |
11 | Author: Mark Wisner 11 | Author: Mark Wisner
12 | 12 |
13 | Change Activity- 13 | Change Activity-
14 | 14 |
15 | Date Description of Change BY 15 | Date Description of Change BY
16 | --------- --------------------- --- 16 | --------- --------------------- ---
17 | 29-Apr-99 Created MKW 17 | 29-Apr-99 Created MKW
18 | 18 |
19 +----------------------------------------------------------------------------*/ 19 +----------------------------------------------------------------------------*/
20 /*----------------------------------------------------------------------------+ 20 /*----------------------------------------------------------------------------+
21 | 17-Nov-03 Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com 21 | 17-Nov-03 Travis B. Sawyer, Sandburst Corporation, tsawyer@sandburst.com
22 | Added register bit definitions to support multiple channels 22 | Added register bit definitions to support multiple channels
23 +----------------------------------------------------------------------------*/ 23 +----------------------------------------------------------------------------*/
24 #ifndef _mal_h_ 24 #ifndef _mal_h_
25 #define _mal_h_ 25 #define _mal_h_
26 26
27 #if !defined(MAL_DCR_BASE) 27 #if !defined(MAL_DCR_BASE)
28 #define MAL_DCR_BASE 0x180 28 #define MAL_DCR_BASE 0x180
29 #endif 29 #endif
30 #define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ 30 #define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */
31 #define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */ 31 #define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */
32 #define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ 32 #define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */
33 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ 33 #define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */
34 #define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ 34 #define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */
35 #define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/ 35 #define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/
36 #define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ 36 #define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */
37 #define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/ 37 #define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/
38 #define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ 38 #define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */
39 #define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ 39 #define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */
40 #define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/ 40 #define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/
41 #define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ 41 #define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */
42 #define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ 42 #define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */
43 #define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ 43 #define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */
44 #define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */ 44 #define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */
45 #define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */ 45 #define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */
46 #define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */ 46 #define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */
47 #define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */ 47 #define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */
48 #define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */ 48 #define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */
49 #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ 49 #define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */
50 #define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ 50 #define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */
51 #if defined(CONFIG_440GX) || \ 51 #if defined(CONFIG_440GX) || \
52 defined(CONFIG_460EX) || defined(CONFIG_460GT) 52 defined(CONFIG_460EX) || defined(CONFIG_460GT)
53 #define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */ 53 #define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */
54 #define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */ 54 #define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */
55 #define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */ 55 #define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */
56 #define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/ 56 #define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/
57 #define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/ 57 #define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/
58 #define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ 58 #define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */
59 #define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ 59 #define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */
60 #define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ 60 #define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */
61 #define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ 61 #define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */
62 #define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ 62 #define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */
63 #endif /* CONFIG_440GX */ 63 #endif /* CONFIG_440GX */
64 64
65 /* MADMAL transmit and receive status/control bits */ 65 /* MADMAL transmit and receive status/control bits */
66 /* for COMMAC bits, refer to the COMMAC header file */ 66 /* for COMMAC bits, refer to the COMMAC header file */
67 67
68 #define MAL_TX_CTRL_READY 0x8000 68 #define MAL_TX_CTRL_READY 0x8000
69 #define MAL_TX_CTRL_WRAP 0x4000 69 #define MAL_TX_CTRL_WRAP 0x4000
70 #define MAL_TX_CTRL_CM 0x2000 70 #define MAL_TX_CTRL_CM 0x2000
71 #define MAL_TX_CTRL_LAST 0x1000 71 #define MAL_TX_CTRL_LAST 0x1000
72 #define MAL_TX_CTRL_INTR 0x0400 72 #define MAL_TX_CTRL_INTR 0x0400
73 73
74 #define MAL_RX_CTRL_EMPTY 0x8000 74 #define MAL_RX_CTRL_EMPTY 0x8000
75 #define MAL_RX_CTRL_WRAP 0x4000 75 #define MAL_RX_CTRL_WRAP 0x4000
76 #define MAL_RX_CTRL_CM 0x2000 76 #define MAL_RX_CTRL_CM 0x2000
77 #define MAL_RX_CTRL_LAST 0x1000 77 #define MAL_RX_CTRL_LAST 0x1000
78 #define MAL_RX_CTRL_FIRST 0x0800 78 #define MAL_RX_CTRL_FIRST 0x0800
79 #define MAL_RX_CTRL_INTR 0x0400 79 #define MAL_RX_CTRL_INTR 0x0400
80 80
81 /* Configuration Reg */ 81 /* Configuration Reg */
82 #define MAL_CR_MMSR 0x80000000 82 #define MAL_CR_MMSR 0x80000000
83 #define MAL_CR_PLBP_1 0x00400000 /* lowsest is 00 */ 83 #define MAL_CR_PLBP_1 0x00400000 /* lowsest is 00 */
84 #define MAL_CR_PLBP_2 0x00800000 84 #define MAL_CR_PLBP_2 0x00800000
85 #define MAL_CR_PLBP_3 0x00C00000 /* highest */ 85 #define MAL_CR_PLBP_3 0x00C00000 /* highest */
86 #define MAL_CR_GA 0x00200000 86 #define MAL_CR_GA 0x00200000
87 #define MAL_CR_OA 0x00100000 87 #define MAL_CR_OA 0x00100000
88 #define MAL_CR_PLBLE 0x00080000 88 #define MAL_CR_PLBLE 0x00080000
89 #define MAL_CR_PLBLT_1 0x00040000 89 #define MAL_CR_PLBLT_1 0x00040000
90 #define MAL_CR_PLBLT_2 0x00020000 90 #define MAL_CR_PLBLT_2 0x00020000
91 #define MAL_CR_PLBLT_3 0x00010000 91 #define MAL_CR_PLBLT_3 0x00010000
92 #define MAL_CR_PLBLT_4 0x00008000 92 #define MAL_CR_PLBLT_4 0x00008000
93 #define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */ 93 #define MAL_CR_PLBLT_DEFAULT 0x00078000 /* ????? */
94 #define MAL_CR_PLBB 0x00004000 94 #define MAL_CR_PLBB 0x00004000
95 #define MAL_CR_OPBBL 0x00000080 95 #define MAL_CR_OPBBL 0x00000080
96 #define MAL_CR_EOPIE 0x00000004 96 #define MAL_CR_EOPIE 0x00000004
97 #define MAL_CR_LEA 0x00000002 97 #define MAL_CR_LEA 0x00000002
98 #define MAL_CR_MSD 0x00000001 98 #define MAL_CR_MSD 0x00000001
99 99
100 /* Error Status Reg */ 100 /* Error Status Reg */
101 #define MAL_ESR_EVB 0x80000000 101 #define MAL_ESR_EVB 0x80000000
102 #define MAL_ESR_CID 0x40000000 102 #define MAL_ESR_CID 0x40000000
103 #define MAL_ESR_DE 0x00100000 103 #define MAL_ESR_DE 0x00100000
104 #define MAL_ESR_ONE 0x00080000 104 #define MAL_ESR_ONE 0x00080000
105 #define MAL_ESR_OTE 0x00040000 105 #define MAL_ESR_OTE 0x00040000
106 #define MAL_ESR_OSE 0x00020000 106 #define MAL_ESR_OSE 0x00020000
107 #define MAL_ESR_PEIN 0x00010000 107 #define MAL_ESR_PEIN 0x00010000
108 /* same bit position as the IER */ 108 /* same bit position as the IER */
109 /* VV VV */ 109 /* VV VV */
110 #define MAL_ESR_DEI 0x00000010 110 #define MAL_ESR_DEI 0x00000010
111 #define MAL_ESR_ONEI 0x00000008 111 #define MAL_ESR_ONEI 0x00000008
112 #define MAL_ESR_OTEI 0x00000004 112 #define MAL_ESR_OTEI 0x00000004
113 #define MAL_ESR_OSEI 0x00000002 113 #define MAL_ESR_OSEI 0x00000002
114 #define MAL_ESR_PBEI 0x00000001 114 #define MAL_ESR_PBEI 0x00000001
115 /* ^^ ^^ */ 115 /* ^^ ^^ */
116 /* Mal IER */ 116 /* Mal IER */
117 #if defined(CONFIG_440SPE) || \ 117 #if defined(CONFIG_440SPE) || \
118 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 118 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
119 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 119 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
120 defined(CONFIG_405EX) 120 defined(CONFIG_405EX)
121 #define MAL_IER_PT 0x00000080 121 #define MAL_IER_PT 0x00000080
122 #define MAL_IER_PRE 0x00000040 122 #define MAL_IER_PRE 0x00000040
123 #define MAL_IER_PWE 0x00000020 123 #define MAL_IER_PWE 0x00000020
124 #define MAL_IER_DE 0x00000010 124 #define MAL_IER_DE 0x00000010
125 #define MAL_IER_OTE 0x00000004 125 #define MAL_IER_OTE 0x00000004
126 #define MAL_IER_OE 0x00000002 126 #define MAL_IER_OE 0x00000002
127 #define MAL_IER_PE 0x00000001 127 #define MAL_IER_PE 0x00000001
128 #else 128 #else
129 #define MAL_IER_DE 0x00000010 129 #define MAL_IER_DE 0x00000010
130 #define MAL_IER_NE 0x00000008 130 #define MAL_IER_NE 0x00000008
131 #define MAL_IER_TE 0x00000004 131 #define MAL_IER_TE 0x00000004
132 #define MAL_IER_OPBE 0x00000002 132 #define MAL_IER_OPBE 0x00000002
133 #define MAL_IER_PLBE 0x00000001 133 #define MAL_IER_PLBE 0x00000001
134 #endif 134 #endif
135 135
136 /* MAL Channel Active Set and Reset Registers */ 136 /* MAL Channel Active Set and Reset Registers */
137 #define MAL_TXRX_CASR (0x80000000) 137 #define MAL_TXRX_CASR (0x80000000)
138 138
139 #define MAL_TXRX_CASR_V(__x) (__x) /* Channel 0 shifts 0, channel 1 shifts 1, etc */ 139 #define MAL_TXRX_CASR_V(__x) (__x) /* Channel 0 shifts 0, channel 1 shifts 1, etc */
140 140
141 141
142 /* MAL Buffer Descriptor structure */ 142 /* MAL Buffer Descriptor structure */
143 typedef struct { 143 typedef struct {
144 short ctrl; /* MAL / Commac status control bits */ 144 short ctrl; /* MAL / Commac status control bits */
145 short data_len; /* Max length is 4K-1 (12 bits) */ 145 short data_len; /* Max length is 4K-1 (12 bits) */
146 char *data_ptr; /* pointer to actual data buffer */ 146 char *data_ptr; /* pointer to actual data buffer */
147 } mal_desc_t; 147 } mal_desc_t;
148 148
149 #endif 149 #endif
150 150
arch/powerpc/include/asm/ppc4xx.h
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 4
5 #ifndef __PPC4XX_H__ 5 #ifndef __PPC4XX_H__
6 #define __PPC4XX_H__ 6 #define __PPC4XX_H__
7 7
8 /* 8 /*
9 * Include SoC specific headers 9 * Include SoC specific headers
10 */ 10 */
11 #if defined(CONFIG_405EP) 11 #if defined(CONFIG_405EP)
12 #include <asm/ppc405ep.h> 12 #include <asm/ppc405ep.h>
13 #endif 13 #endif
14 14
15 #if defined(CONFIG_405EX) 15 #if defined(CONFIG_405EX)
16 #include <asm/ppc405ex.h> 16 #include <asm/ppc405ex.h>
17 #endif 17 #endif
18 18
19 #if defined(CONFIG_405EZ) 19 #if defined(CONFIG_405EZ)
20 #include <asm/ppc405ez.h> 20 #include <asm/ppc405ez.h>
21 #endif 21 #endif
22 22
23 #if defined(CONFIG_405GP) 23 #if defined(CONFIG_405GP)
24 #include <asm/ppc405gp.h> 24 #include <asm/ppc405gp.h>
25 #endif 25 #endif
26 26
27 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) 27 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
28 #include <asm/ppc440ep_gr.h> 28 #include <asm/ppc440ep_gr.h>
29 #endif 29 #endif
30 30
31 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) 31 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
32 #include <asm/ppc440epx_grx.h> 32 #include <asm/ppc440epx_grx.h>
33 #endif 33 #endif
34 34
35 #if defined(CONFIG_440GP) 35 #if defined(CONFIG_440GP)
36 #include <asm/ppc440gp.h> 36 #include <asm/ppc440gp.h>
37 #endif 37 #endif
38 38
39 #if defined(CONFIG_440GX) 39 #if defined(CONFIG_440GX)
40 #include <asm/ppc440gx.h> 40 #include <asm/ppc440gx.h>
41 #endif 41 #endif
42 42
43 #if defined(CONFIG_440SP) 43 #if defined(CONFIG_440SP)
44 #include <asm/ppc440sp.h> 44 #include <asm/ppc440sp.h>
45 #endif 45 #endif
46 46
47 #if defined(CONFIG_440SPE) 47 #if defined(CONFIG_440SPE)
48 #include <asm/ppc440spe.h> 48 #include <asm/ppc440spe.h>
49 #endif 49 #endif
50 50
51 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 51 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
52 #include <asm/ppc460ex_gt.h> 52 #include <asm/ppc460ex_gt.h>
53 #endif 53 #endif
54 54
55 #if defined(CONFIG_460SX) 55 #if defined(CONFIG_460SX)
56 #include <asm/ppc460sx.h> 56 #include <asm/ppc460sx.h>
57 #endif 57 #endif
58 58
59 #if defined(CONFIG_APM821XX) 59 #if defined(CONFIG_APM821XX)
60 #include <asm/apm821xx.h> 60 #include <asm/apm821xx.h>
61 #endif 61 #endif
62 62
63 /* 63 /*
64 * Common registers for all SoC's 64 * Common registers for all SoC's
65 */ 65 */
66 /* DCR registers */ 66 /* DCR registers */
67 #define PLB3A0_ACR 0x0077 67 #define PLB3A0_ACR 0x0077
68 #define PLB4A0_ACR 0x0081 68 #define PLB4A0_ACR 0x0081
69 #define PLB4A1_ACR 0x0089 69 #define PLB4A1_ACR 0x0089
70 70
71 /* CPR register declarations */ 71 /* CPR register declarations */
72 72
73 #define PLB4Ax_ACR_PPM_MASK 0xf0000000 73 #define PLB4Ax_ACR_PPM_MASK 0xf0000000
74 #define PLB4Ax_ACR_PPM_FIXED 0x00000000 74 #define PLB4Ax_ACR_PPM_FIXED 0x00000000
75 #define PLB4Ax_ACR_PPM_FAIR 0xd0000000 75 #define PLB4Ax_ACR_PPM_FAIR 0xd0000000
76 #define PLB4Ax_ACR_HBU_MASK 0x08000000 76 #define PLB4Ax_ACR_HBU_MASK 0x08000000
77 #define PLB4Ax_ACR_HBU_DISABLED 0x00000000 77 #define PLB4Ax_ACR_HBU_DISABLED 0x00000000
78 #define PLB4Ax_ACR_HBU_ENABLED 0x08000000 78 #define PLB4Ax_ACR_HBU_ENABLED 0x08000000
79 #define PLB4Ax_ACR_RDP_MASK 0x06000000 79 #define PLB4Ax_ACR_RDP_MASK 0x06000000
80 #define PLB4Ax_ACR_RDP_DISABLED 0x00000000 80 #define PLB4Ax_ACR_RDP_DISABLED 0x00000000
81 #define PLB4Ax_ACR_RDP_2DEEP 0x02000000 81 #define PLB4Ax_ACR_RDP_2DEEP 0x02000000
82 #define PLB4Ax_ACR_RDP_3DEEP 0x04000000 82 #define PLB4Ax_ACR_RDP_3DEEP 0x04000000
83 #define PLB4Ax_ACR_RDP_4DEEP 0x06000000 83 #define PLB4Ax_ACR_RDP_4DEEP 0x06000000
84 #define PLB4Ax_ACR_WRP_MASK 0x01000000 84 #define PLB4Ax_ACR_WRP_MASK 0x01000000
85 #define PLB4Ax_ACR_WRP_DISABLED 0x00000000 85 #define PLB4Ax_ACR_WRP_DISABLED 0x00000000
86 #define PLB4Ax_ACR_WRP_2DEEP 0x01000000 86 #define PLB4Ax_ACR_WRP_2DEEP 0x01000000
87 87
88 /* 88 /*
89 * External Bus Controller 89 * External Bus Controller
90 */ 90 */
91 /* Values for EBC0_CFGADDR register - indirect addressing of these regs */ 91 /* Values for EBC0_CFGADDR register - indirect addressing of these regs */
92 #define PB0CR 0x00 /* periph bank 0 config reg */ 92 #define PB0CR 0x00 /* periph bank 0 config reg */
93 #define PB1CR 0x01 /* periph bank 1 config reg */ 93 #define PB1CR 0x01 /* periph bank 1 config reg */
94 #define PB2CR 0x02 /* periph bank 2 config reg */ 94 #define PB2CR 0x02 /* periph bank 2 config reg */
95 #define PB3CR 0x03 /* periph bank 3 config reg */ 95 #define PB3CR 0x03 /* periph bank 3 config reg */
96 #define PB4CR 0x04 /* periph bank 4 config reg */ 96 #define PB4CR 0x04 /* periph bank 4 config reg */
97 #define PB5CR 0x05 /* periph bank 5 config reg */ 97 #define PB5CR 0x05 /* periph bank 5 config reg */
98 #define PB6CR 0x06 /* periph bank 6 config reg */ 98 #define PB6CR 0x06 /* periph bank 6 config reg */
99 #define PB7CR 0x07 /* periph bank 7 config reg */ 99 #define PB7CR 0x07 /* periph bank 7 config reg */
100 #define PB0AP 0x10 /* periph bank 0 access parameters */ 100 #define PB0AP 0x10 /* periph bank 0 access parameters */
101 #define PB1AP 0x11 /* periph bank 1 access parameters */ 101 #define PB1AP 0x11 /* periph bank 1 access parameters */
102 #define PB2AP 0x12 /* periph bank 2 access parameters */ 102 #define PB2AP 0x12 /* periph bank 2 access parameters */
103 #define PB3AP 0x13 /* periph bank 3 access parameters */ 103 #define PB3AP 0x13 /* periph bank 3 access parameters */
104 #define PB4AP 0x14 /* periph bank 4 access parameters */ 104 #define PB4AP 0x14 /* periph bank 4 access parameters */
105 #define PB5AP 0x15 /* periph bank 5 access parameters */ 105 #define PB5AP 0x15 /* periph bank 5 access parameters */
106 #define PB6AP 0x16 /* periph bank 6 access parameters */ 106 #define PB6AP 0x16 /* periph bank 6 access parameters */
107 #define PB7AP 0x17 /* periph bank 7 access parameters */ 107 #define PB7AP 0x17 /* periph bank 7 access parameters */
108 #define PBEAR 0x20 /* periph bus error addr reg */ 108 #define PBEAR 0x20 /* periph bus error addr reg */
109 #define PBESR0 0x21 /* periph bus error status reg 0 */ 109 #define PBESR0 0x21 /* periph bus error status reg 0 */
110 #define PBESR1 0x22 /* periph bus error status reg 1 */ 110 #define PBESR1 0x22 /* periph bus error status reg 1 */
111 #define EBC0_CFG 0x23 /* external bus configuration reg */ 111 #define EBC0_CFG 0x23 /* external bus configuration reg */
112 112
113 /* 113 /*
114 * GPIO macro register defines 114 * GPIO macro register defines
115 */ 115 */
116 /* todo: merge with gpio.h header */ 116 /* todo: merge with gpio.h header */
117 #define GPIO_BASE GPIO0_BASE 117 #define GPIO_BASE GPIO0_BASE
118 118
119 #define GPIO0_OR (GPIO0_BASE + 0x0) 119 #define GPIO0_OR (GPIO0_BASE + 0x0)
120 #define GPIO0_TCR (GPIO0_BASE + 0x4) 120 #define GPIO0_TCR (GPIO0_BASE + 0x4)
121 #define GPIO0_OSRL (GPIO0_BASE + 0x8) 121 #define GPIO0_OSRL (GPIO0_BASE + 0x8)
122 #define GPIO0_OSRH (GPIO0_BASE + 0xC) 122 #define GPIO0_OSRH (GPIO0_BASE + 0xC)
123 #define GPIO0_TSRL (GPIO0_BASE + 0x10) 123 #define GPIO0_TSRL (GPIO0_BASE + 0x10)
124 #define GPIO0_TSRH (GPIO0_BASE + 0x14) 124 #define GPIO0_TSRH (GPIO0_BASE + 0x14)
125 #define GPIO0_ODR (GPIO0_BASE + 0x18) 125 #define GPIO0_ODR (GPIO0_BASE + 0x18)
126 #define GPIO0_IR (GPIO0_BASE + 0x1C) 126 #define GPIO0_IR (GPIO0_BASE + 0x1C)
127 #define GPIO0_RR1 (GPIO0_BASE + 0x20) 127 #define GPIO0_RR1 (GPIO0_BASE + 0x20)
128 #define GPIO0_RR2 (GPIO0_BASE + 0x24) 128 #define GPIO0_RR2 (GPIO0_BASE + 0x24)
129 #define GPIO0_RR3 (GPIO0_BASE + 0x28) 129 #define GPIO0_RR3 (GPIO0_BASE + 0x28)
130 #define GPIO0_ISR1L (GPIO0_BASE + 0x30) 130 #define GPIO0_ISR1L (GPIO0_BASE + 0x30)
131 #define GPIO0_ISR1H (GPIO0_BASE + 0x34) 131 #define GPIO0_ISR1H (GPIO0_BASE + 0x34)
132 #define GPIO0_ISR2L (GPIO0_BASE + 0x38) 132 #define GPIO0_ISR2L (GPIO0_BASE + 0x38)
133 #define GPIO0_ISR2H (GPIO0_BASE + 0x3C) 133 #define GPIO0_ISR2H (GPIO0_BASE + 0x3C)
134 #define GPIO0_ISR3L (GPIO0_BASE + 0x40) 134 #define GPIO0_ISR3L (GPIO0_BASE + 0x40)
135 #define GPIO0_ISR3H (GPIO0_BASE + 0x44) 135 #define GPIO0_ISR3H (GPIO0_BASE + 0x44)
136 136
137 #define GPIO1_OR (GPIO1_BASE + 0x0) 137 #define GPIO1_OR (GPIO1_BASE + 0x0)
138 #define GPIO1_TCR (GPIO1_BASE + 0x4) 138 #define GPIO1_TCR (GPIO1_BASE + 0x4)
139 #define GPIO1_OSRL (GPIO1_BASE + 0x8) 139 #define GPIO1_OSRL (GPIO1_BASE + 0x8)
140 #define GPIO1_OSRH (GPIO1_BASE + 0xC) 140 #define GPIO1_OSRH (GPIO1_BASE + 0xC)
141 #define GPIO1_TSRL (GPIO1_BASE + 0x10) 141 #define GPIO1_TSRL (GPIO1_BASE + 0x10)
142 #define GPIO1_TSRH (GPIO1_BASE + 0x14) 142 #define GPIO1_TSRH (GPIO1_BASE + 0x14)
143 #define GPIO1_ODR (GPIO1_BASE + 0x18) 143 #define GPIO1_ODR (GPIO1_BASE + 0x18)
144 #define GPIO1_IR (GPIO1_BASE + 0x1C) 144 #define GPIO1_IR (GPIO1_BASE + 0x1C)
145 #define GPIO1_RR1 (GPIO1_BASE + 0x20) 145 #define GPIO1_RR1 (GPIO1_BASE + 0x20)
146 #define GPIO1_RR2 (GPIO1_BASE + 0x24) 146 #define GPIO1_RR2 (GPIO1_BASE + 0x24)
147 #define GPIO1_RR3 (GPIO1_BASE + 0x28) 147 #define GPIO1_RR3 (GPIO1_BASE + 0x28)
148 #define GPIO1_ISR1L (GPIO1_BASE + 0x30) 148 #define GPIO1_ISR1L (GPIO1_BASE + 0x30)
149 #define GPIO1_ISR1H (GPIO1_BASE + 0x34) 149 #define GPIO1_ISR1H (GPIO1_BASE + 0x34)
150 #define GPIO1_ISR2L (GPIO1_BASE + 0x38) 150 #define GPIO1_ISR2L (GPIO1_BASE + 0x38)
151 #define GPIO1_ISR2H (GPIO1_BASE + 0x3C) 151 #define GPIO1_ISR2H (GPIO1_BASE + 0x3C)
152 #define GPIO1_ISR3L (GPIO1_BASE + 0x40) 152 #define GPIO1_ISR3L (GPIO1_BASE + 0x40)
153 #define GPIO1_ISR3H (GPIO1_BASE + 0x44) 153 #define GPIO1_ISR3H (GPIO1_BASE + 0x44)
154 154
155 /* General Purpose Timer (GPT) Register Offsets */ 155 /* General Purpose Timer (GPT) Register Offsets */
156 #define GPT0_TBC 0x00000000 156 #define GPT0_TBC 0x00000000
157 #define GPT0_IM 0x00000018 157 #define GPT0_IM 0x00000018
158 #define GPT0_ISS 0x0000001C 158 #define GPT0_ISS 0x0000001C
159 #define GPT0_ISC 0x00000020 159 #define GPT0_ISC 0x00000020
160 #define GPT0_IE 0x00000024 160 #define GPT0_IE 0x00000024
161 #define GPT0_COMP0 0x00000080 161 #define GPT0_COMP0 0x00000080
162 #define GPT0_COMP1 0x00000084 162 #define GPT0_COMP1 0x00000084
163 #define GPT0_COMP2 0x00000088 163 #define GPT0_COMP2 0x00000088
164 #define GPT0_COMP3 0x0000008C 164 #define GPT0_COMP3 0x0000008C
165 #define GPT0_COMP4 0x00000090 165 #define GPT0_COMP4 0x00000090
166 #define GPT0_COMP5 0x00000094 166 #define GPT0_COMP5 0x00000094
167 #define GPT0_COMP6 0x00000098 167 #define GPT0_COMP6 0x00000098
168 #define GPT0_MASK0 0x000000C0 168 #define GPT0_MASK0 0x000000C0
169 #define GPT0_MASK1 0x000000C4 169 #define GPT0_MASK1 0x000000C4
170 #define GPT0_MASK2 0x000000C8 170 #define GPT0_MASK2 0x000000C8
171 #define GPT0_MASK3 0x000000CC 171 #define GPT0_MASK3 0x000000CC
172 #define GPT0_MASK4 0x000000D0 172 #define GPT0_MASK4 0x000000D0
173 #define GPT0_MASK5 0x000000D4 173 #define GPT0_MASK5 0x000000D4
174 #define GPT0_MASK6 0x000000D8 174 #define GPT0_MASK6 0x000000D8
175 #define GPT0_DCT0 0x00000110 175 #define GPT0_DCT0 0x00000110
176 #define GPT0_DCIS 0x0000011C 176 #define GPT0_DCIS 0x0000011C
177 177
178 #if defined(CONFIG_440) 178 #if defined(CONFIG_440)
179 #include <asm/ppc440.h> 179 #include <asm/ppc440.h>
180 #else 180 #else
181 #include <asm/ppc405.h> 181 #include <asm/ppc405.h>
182 #endif 182 #endif
183 183
184 #include <asm/ppc4xx-sdram.h> 184 #include <asm/ppc4xx-sdram.h>
185 #include <asm/ppc4xx-ebc.h> 185 #include <asm/ppc4xx-ebc.h>
186 #if !defined(CONFIG_XILINX_440) 186 #if !defined(CONFIG_XILINX_440)
187 #include <asm/ppc4xx-uic.h> 187 #include <asm/ppc4xx-uic.h>
188 #endif 188 #endif
189 189
190 /* 190 /*
191 * Macro for generating register field mnemonics 191 * Macro for generating register field mnemonics
192 */ 192 */
193 #define PPC_REG_BITS 32 193 #define PPC_REG_BITS 32
194 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) 194 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit)))
195 195
196 /* 196 /*
197 * Elide casts when assembling register mnemonics 197 * Elide casts when assembling register mnemonics
198 */ 198 */
199 #ifndef __ASSEMBLY__ 199 #ifndef __ASSEMBLY__
200 #define static_cast(type, val) (type)(val) 200 #define static_cast(type, val) (type)(val)
201 #else 201 #else
202 #define static_cast(type, val) (val) 202 #define static_cast(type, val) (val)
203 #endif 203 #endif
204 204
205 /* 205 /*
206 * Common stuff for 4xx (405 and 440) 206 * Common stuff for 4xx (405 and 440)
207 */ 207 */
208 208
209 #define EXC_OFF_SYS_RESET 0x0100 /* System reset */ 209 #define EXC_OFF_SYS_RESET 0x0100 /* System reset */
210 #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) 210 #define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000)
211 211
212 #define RESET_VECTOR 0xfffffffc 212 #define RESET_VECTOR 0xfffffffc
213 #define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for 213 #define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for
214 cache line aligned data. */ 214 cache line aligned data. */
215 215
216 #define CPR0_DCR_BASE 0x0C 216 #define CPR0_DCR_BASE 0x0C
217 #define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0) 217 #define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0)
218 #define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1) 218 #define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1)
219 219
220 #define SDR_DCR_BASE 0x0E 220 #define SDR_DCR_BASE 0x0E
221 #define SDR0_CFGADDR (SDR_DCR_BASE + 0x0) 221 #define SDR0_CFGADDR (SDR_DCR_BASE + 0x0)
222 #define SDR0_CFGDATA (SDR_DCR_BASE + 0x1) 222 #define SDR0_CFGDATA (SDR_DCR_BASE + 0x1)
223 223
224 #define SDRAM_DCR_BASE 0x10 224 #define SDRAM_DCR_BASE 0x10
225 #define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0) 225 #define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0)
226 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) 226 #define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1)
227 227
228 #define EBC_DCR_BASE 0x12 228 #define EBC_DCR_BASE 0x12
229 #define EBC0_CFGADDR (EBC_DCR_BASE + 0x0) 229 #define EBC0_CFGADDR (EBC_DCR_BASE + 0x0)
230 #define EBC0_CFGDATA (EBC_DCR_BASE + 0x1) 230 #define EBC0_CFGDATA (EBC_DCR_BASE + 0x1)
231 231
232 /* 232 /*
233 * Macros for indirect DCR access 233 * Macros for indirect DCR access
234 */ 234 */
235 #define mtcpr(reg, d) \ 235 #define mtcpr(reg, d) \
236 do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0) 236 do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0)
237 #define mfcpr(reg, d) \ 237 #define mfcpr(reg, d) \
238 do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0) 238 do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0)
239 239
240 #define mtebc(reg, d) \ 240 #define mtebc(reg, d) \
241 do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0) 241 do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0)
242 #define mfebc(reg, d) \ 242 #define mfebc(reg, d) \
243 do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0) 243 do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0)
244 244
245 #define mtsdram(reg, d) \ 245 #define mtsdram(reg, d) \
246 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0) 246 do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0)
247 #define mfsdram(reg, d) \ 247 #define mfsdram(reg, d) \
248 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0) 248 do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0)
249 249
250 #define mtsdr(reg, d) \ 250 #define mtsdr(reg, d) \
251 do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0) 251 do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0)
252 #define mfsdr(reg, d) \ 252 #define mfsdr(reg, d) \
253 do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0) 253 do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0)
254 254
255 #ifndef __ASSEMBLY__ 255 #ifndef __ASSEMBLY__
256 256
257 typedef struct 257 typedef struct
258 { 258 {
259 unsigned long freqDDR; 259 unsigned long freqDDR;
260 unsigned long freqEBC; 260 unsigned long freqEBC;
261 unsigned long freqOPB; 261 unsigned long freqOPB;
262 unsigned long freqPCI; 262 unsigned long freqPCI;
263 unsigned long freqPLB; 263 unsigned long freqPLB;
264 unsigned long freqTmrClk; 264 unsigned long freqTmrClk;
265 unsigned long freqUART; 265 unsigned long freqUART;
266 unsigned long freqProcessor; 266 unsigned long freqProcessor;
267 unsigned long freqVCOHz; 267 unsigned long freqVCOHz;
268 unsigned long freqVCOMhz; /* in MHz */ 268 unsigned long freqVCOMhz; /* in MHz */
269 unsigned long pciClkSync; /* PCI clock is synchronous */ 269 unsigned long pciClkSync; /* PCI clock is synchronous */
270 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ 270 unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */
271 unsigned long pllExtBusDiv; 271 unsigned long pllExtBusDiv;
272 unsigned long pllFbkDiv; 272 unsigned long pllFbkDiv;
273 unsigned long pllFwdDiv; 273 unsigned long pllFwdDiv;
274 unsigned long pllFwdDivA; 274 unsigned long pllFwdDivA;
275 unsigned long pllFwdDivB; 275 unsigned long pllFwdDivB;
276 unsigned long pllOpbDiv; 276 unsigned long pllOpbDiv;
277 unsigned long pllPciDiv; 277 unsigned long pllPciDiv;
278 unsigned long pllPlbDiv; 278 unsigned long pllPlbDiv;
279 } PPC4xx_SYS_INFO; 279 } PPC4xx_SYS_INFO;
280 280
281 static inline u32 get_mcsr(void) 281 static inline u32 get_mcsr(void)
282 { 282 {
283 u32 val; 283 u32 val;
284 284
285 asm volatile("mfspr %0, 0x23c" : "=r" (val) :); 285 asm volatile("mfspr %0, 0x23c" : "=r" (val) :);
286 return val; 286 return val;
287 } 287 }
288 288
289 static inline void set_mcsr(u32 val) 289 static inline void set_mcsr(u32 val)
290 { 290 {
291 asm volatile("mtspr 0x23c, %0" : "=r" (val) :); 291 asm volatile("mtspr 0x23c, %0" : "=r" (val) :);
292 } 292 }
293 293
294 int ppc4xx_pci_sync_clock_config(u32 async); 294 int ppc4xx_pci_sync_clock_config(u32 async);
295 295
296 #endif /* __ASSEMBLY__ */ 296 #endif /* __ASSEMBLY__ */
297 297
298 /* for multi-cpu support */ 298 /* for multi-cpu support */
299 #define NA_OR_UNKNOWN_CPU -1 299 #define NA_OR_UNKNOWN_CPU -1
300 300
301 #endif /* __PPC4XX_H__ */ 301 #endif /* __PPC4XX_H__ */
302 302
board/cray/L1/init.S
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 4
5 /*----------------------------------------------------------------------------- */ 5 /*----------------------------------------------------------------------------- */
6 /* Function: ext_bus_cntlr_init */ 6 /* Function: ext_bus_cntlr_init */
7 /* Description: Initializes the External Bus Controller for the external */ 7 /* Description: Initializes the External Bus Controller for the external */
8 /* peripherals. IMPORTANT: For pass1 this code must run from */ 8 /* peripherals. IMPORTANT: For pass1 this code must run from */
9 /* cache since you can not reliably change a peripheral banks */ 9 /* cache since you can not reliably change a peripheral banks */
10 /* timing register (pbxap) while running code from that bank. */ 10 /* timing register (pbxap) while running code from that bank. */
11 /* For ex., since we are running from ROM on bank 0, we can NOT */ 11 /* For ex., since we are running from ROM on bank 0, we can NOT */
12 /* execute the code that modifies bank 0 timings from ROM, so */ 12 /* execute the code that modifies bank 0 timings from ROM, so */
13 /* we run it from cache. */ 13 /* we run it from cache. */
14 /* Bank 0 - Flash and SRAM */ 14 /* Bank 0 - Flash and SRAM */
15 /* Bank 1 - NVRAM/RTC */ 15 /* Bank 1 - NVRAM/RTC */
16 /* Bank 2 - Keyboard/Mouse controller */ 16 /* Bank 2 - Keyboard/Mouse controller */
17 /* Bank 3 - IR controller */ 17 /* Bank 3 - IR controller */
18 /* Bank 4 - not used */ 18 /* Bank 4 - not used */
19 /* Bank 5 - not used */ 19 /* Bank 5 - not used */
20 /* Bank 6 - not used */ 20 /* Bank 6 - not used */
21 /* Bank 7 - FPGA registers */ 21 /* Bank 7 - FPGA registers */
22 /*-----------------------------------------------------------------------------#include <config.h> */ 22 /*-----------------------------------------------------------------------------#include <config.h> */
23 #include <asm/ppc4xx.h> 23 #include <asm/ppc4xx.h>
24 24
25 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 25 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
26 26
27 #include <ppc_asm.tmpl> 27 #include <ppc_asm.tmpl>
28 #include <ppc_defs.h> 28 #include <ppc_defs.h>
29 29
30 #include <asm/cache.h> 30 #include <asm/cache.h>
31 #include <asm/mmu.h> 31 #include <asm/mmu.h>
32 32
33 /* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */ 33 /* CRAY - L1: only nominally a 'walnut', since ext.Bus.Cntlr is all empty */
34 /* except for #1 which we use for DMA'ing to IOCA-like things, so the */ 34 /* except for #1 which we use for DMA'ing to IOCA-like things, so the */
35 /* control registers to set that up are determined by what we've */ 35 /* control registers to set that up are determined by what we've */
36 /* empirically discovered work there. */ 36 /* empirically discovered work there. */
37 37
38 .globl ext_bus_cntlr_init 38 .globl ext_bus_cntlr_init
39 ext_bus_cntlr_init: 39 ext_bus_cntlr_init:
40 mflr r4 /* save link register */ 40 mflr r4 /* save link register */
41 bl ..getAddr 41 bl ..getAddr
42 ..getAddr: 42 ..getAddr:
43 mflr r3 /* get address of ..getAddr */ 43 mflr r3 /* get address of ..getAddr */
44 mtlr r4 /* restore link register */ 44 mtlr r4 /* restore link register */
45 addi r4,0,14 /* set ctr to 10; used to prefetch */ 45 addi r4,0,14 /* set ctr to 10; used to prefetch */
46 mtctr r4 /* 10 cache lines to fit this function */ 46 mtctr r4 /* 10 cache lines to fit this function */
47 /* in cache (gives us 8x10=80 instrctns) */ 47 /* in cache (gives us 8x10=80 instrctns) */
48 ..ebcloop: 48 ..ebcloop:
49 icbt r0,r3 /* prefetch cache line for addr in r3 */ 49 icbt r0,r3 /* prefetch cache line for addr in r3 */
50 addi r3,r3,32 /* move to next cache line */ 50 addi r3,r3,32 /* move to next cache line */
51 bdnz ..ebcloop /* continue for 10 cache lines */ 51 bdnz ..ebcloop /* continue for 10 cache lines */
52 52
53 /*------------------------------------------------------------------- */ 53 /*------------------------------------------------------------------- */
54 /* Delay to ensure all accesses to ROM are complete before changing */ 54 /* Delay to ensure all accesses to ROM are complete before changing */
55 /* bank 0 timings. 200usec should be enough. */ 55 /* bank 0 timings. 200usec should be enough. */
56 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ 56 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
57 /*------------------------------------------------------------------- */ 57 /*------------------------------------------------------------------- */
58 addis r3,0,0x0 58 addis r3,0,0x0
59 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ 59 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
60 mtctr r3 60 mtctr r3
61 ..spinlp: 61 ..spinlp:
62 bdnz ..spinlp /* spin loop */ 62 bdnz ..spinlp /* spin loop */
63 63
64 64
65 /*---------------------------------------------------------------------- */ 65 /*---------------------------------------------------------------------- */
66 /* Peripheral Bank 0 (Flash) initialization */ 66 /* Peripheral Bank 0 (Flash) initialization */
67 /*---------------------------------------------------------------------- */ 67 /*---------------------------------------------------------------------- */
68 /* 0x7F8FFE80 slowest boot */ 68 /* 0x7F8FFE80 slowest boot */
69 addi r4,0,PB1AP 69 addi r4,0,PB1AP
70 mtdcr EBC0_CFGADDR,r4 70 mtdcr EBC0_CFGADDR,r4
71 addis r4,0,0x9B01 71 addis r4,0,0x9B01
72 ori r4,r4,0x5480 72 ori r4,r4,0x5480
73 mtdcr EBC0_CFGDATA,r4 73 mtdcr EBC0_CFGDATA,r4
74 74
75 addi r4,0,PB0CR 75 addi r4,0,PB0CR
76 mtdcr EBC0_CFGADDR,r4 76 mtdcr EBC0_CFGADDR,r4
77 addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */ 77 addis r4,0,0xFFC5 /* BAS=0xFFC,BS=0x4(4MB),BU=0x3(R/W), */
78 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ 78 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
79 mtdcr EBC0_CFGDATA,r4 79 mtdcr EBC0_CFGDATA,r4
80 80
81 blr 81 blr
82 82
83 /*---------------------------------------------------------------------- */ 83 /*---------------------------------------------------------------------- */
84 /* Peripheral Bank 1 (NVRAM/RTC) initialization */ 84 /* Peripheral Bank 1 (NVRAM/RTC) initialization */
85 /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */ 85 /* CRAY:the L1 has NOT this bank, it is tied to SV2/IOCA/etc/ instead */
86 /* and we do DMA on it. The ConfigurationRegister part is threfore */ 86 /* and we do DMA on it. The ConfigurationRegister part is threfore */
87 /* almost arbitrary, except that our linux driver needs to know the */ 87 /* almost arbitrary, except that our linux driver needs to know the */
88 /* address, but it can query, it.. */ 88 /* address, but it can query, it.. */
89 /* */ 89 /* */
90 /* The AccessParameter is CRITICAL, */ 90 /* The AccessParameter is CRITICAL, */
91 /* thouch, since it needs to agree with the electrical timings on the */ 91 /* thouch, since it needs to agree with the electrical timings on the */
92 /* IOCA parallel interface. That value is: 0x0185,4380 */ 92 /* IOCA parallel interface. That value is: 0x0185,4380 */
93 /* BurstModeEnable BME=0 */ 93 /* BurstModeEnable BME=0 */
94 /* TransferWait TWT=3 */ 94 /* TransferWait TWT=3 */
95 /* ChipSelectOnTiming CSN=1 */ 95 /* ChipSelectOnTiming CSN=1 */
96 /* OutputEnableOnTimimg OEN=1 */ 96 /* OutputEnableOnTimimg OEN=1 */
97 /* WriteByteEnableOnTiming WBN=1 */ 97 /* WriteByteEnableOnTiming WBN=1 */
98 /* WriteByteEnableOffTiming WBF=0 */ 98 /* WriteByteEnableOffTiming WBF=0 */
99 /* TransferHold TH=1 */ 99 /* TransferHold TH=1 */
100 /* ReadyEnable RE=1 */ 100 /* ReadyEnable RE=1 */
101 /* SampleOnReady SOR=1 */ 101 /* SampleOnReady SOR=1 */
102 /* ByteEnableMode BEM=0 */ 102 /* ByteEnableMode BEM=0 */
103 /* ParityEnable PEN=0 */ 103 /* ParityEnable PEN=0 */
104 /* all reserved bits=0 */ 104 /* all reserved bits=0 */
105 /*---------------------------------------------------------------------- */ 105 /*---------------------------------------------------------------------- */
106 /*---------------------------------------------------------------------- */ 106 /*---------------------------------------------------------------------- */
107 addi r4,0,PB1AP 107 addi r4,0,PB1AP
108 mtdcr EBC0_CFGADDR,r4 108 mtdcr EBC0_CFGADDR,r4
109 addis r4,0,0x0185 /* hiword */ 109 addis r4,0,0x0185 /* hiword */
110 ori r4,r4,0x4380 /* loword */ 110 ori r4,r4,0x4380 /* loword */
111 mtdcr EBC0_CFGDATA,r4 111 mtdcr EBC0_CFGDATA,r4
112 112
113 addi r4,0,PB1CR 113 addi r4,0,PB1CR
114 mtdcr EBC0_CFGADDR,r4 114 mtdcr EBC0_CFGADDR,r4
115 addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */ 115 addis r4,0,0xF001 /* BAS=0xF00,BS=0x0(1MB),BU=0x3(R/W), */
116 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ 116 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
117 mtdcr EBC0_CFGDATA,r4 117 mtdcr EBC0_CFGDATA,r4
118 118
119 blr 119 blr
120 120
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 #include <config.h> 4 #include <config.h>
5 #include <asm/ppc4xx.h> 5 #include <asm/ppc4xx.h>
6 6
7 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 7 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
8 8
9 #include <ppc_asm.tmpl> 9 #include <ppc_asm.tmpl>
10 #include <ppc_defs.h> 10 #include <ppc_defs.h>
11 11
12 #include <asm/cache.h> 12 #include <asm/cache.h>
13 #include <asm/mmu.h> 13 #include <asm/mmu.h>
14 14
15 #define LI32(reg,val) \ 15 #define LI32(reg,val) \
16 addis reg,0,val@h;\ 16 addis reg,0,val@h;\
17 ori reg,reg,val@l 17 ori reg,reg,val@l
18 18
19 #define WDCR_EBC(reg,val) \ 19 #define WDCR_EBC(reg,val) \
20 addi r4,0,reg;\ 20 addi r4,0,reg;\
21 mtdcr EBC0_CFGADDR,r4;\ 21 mtdcr EBC0_CFGADDR,r4;\
22 addis r4,0,val@h;\ 22 addis r4,0,val@h;\
23 ori r4,r4,val@l;\ 23 ori r4,r4,val@l;\
24 mtdcr EBC0_CFGDATA,r4 24 mtdcr EBC0_CFGDATA,r4
25 25
26 #define WDCR_SDRAM(reg,val) \ 26 #define WDCR_SDRAM(reg,val) \
27 addi r4,0,reg;\ 27 addi r4,0,reg;\
28 mtdcr SDRAM0_CFGADDR,r4;\ 28 mtdcr SDRAM0_CFGADDR,r4;\
29 addis r4,0,val@h;\ 29 addis r4,0,val@h;\
30 ori r4,r4,val@l;\ 30 ori r4,r4,val@l;\
31 mtdcr SDRAM0_CFGDATA,r4 31 mtdcr SDRAM0_CFGDATA,r4
32 32
33 /****************************************************************************** 33 /******************************************************************************
34 * Function: ext_bus_cntlr_init 34 * Function: ext_bus_cntlr_init
35 * 35 *
36 * Description: Configures EBC Controller and a few basic chip selects. 36 * Description: Configures EBC Controller and a few basic chip selects.
37 * 37 *
38 * CS0 is setup to get the Boot Flash out of the addresss range 38 * CS0 is setup to get the Boot Flash out of the addresss range
39 * so that we may setup a stack. CS7 is setup so that we can 39 * so that we may setup a stack. CS7 is setup so that we can
40 * access and reset the hardware watchdog. 40 * access and reset the hardware watchdog.
41 * 41 *
42 * IMPORTANT: For pass1 this code must run from 42 * IMPORTANT: For pass1 this code must run from
43 * cache since you can not reliably change a peripheral banks 43 * cache since you can not reliably change a peripheral banks
44 * timing register (pbxap) while running code from that bank. 44 * timing register (pbxap) while running code from that bank.
45 * For ex., since we are running from ROM on bank 0, we can NOT 45 * For ex., since we are running from ROM on bank 0, we can NOT
46 * execute the code that modifies bank 0 timings from ROM, so 46 * execute the code that modifies bank 0 timings from ROM, so
47 * we run it from cache. 47 * we run it from cache.
48 * 48 *
49 * Notes: Does NOT use the stack. 49 * Notes: Does NOT use the stack.
50 *****************************************************************************/ 50 *****************************************************************************/
51 .section ".text" 51 .section ".text"
52 .align 2 52 .align 2
53 .globl ext_bus_cntlr_init 53 .globl ext_bus_cntlr_init
54 .type ext_bus_cntlr_init, @function 54 .type ext_bus_cntlr_init, @function
55 ext_bus_cntlr_init: 55 ext_bus_cntlr_init:
56 mflr r0 56 mflr r0
57 /******************************************************************** 57 /********************************************************************
58 * Prefetch entire ext_bus_cntrl_init function into the icache. 58 * Prefetch entire ext_bus_cntrl_init function into the icache.
59 * This is necessary because we are going to change the same CS we 59 * This is necessary because we are going to change the same CS we
60 * are executing from. Otherwise a CPU lockup may occur. 60 * are executing from. Otherwise a CPU lockup may occur.
61 *******************************************************************/ 61 *******************************************************************/
62 bl ..getAddr 62 bl ..getAddr
63 ..getAddr: 63 ..getAddr:
64 mflr r3 /* get address of ..getAddr */ 64 mflr r3 /* get address of ..getAddr */
65 65
66 /* Calculate number of cache lines for this function */ 66 /* Calculate number of cache lines for this function */
67 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) 67 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
68 mtctr r4 68 mtctr r4
69 ..ebcloop: 69 ..ebcloop:
70 icbt r0, r3 /* prefetch cache line for addr in r3*/ 70 icbt r0, r3 /* prefetch cache line for addr in r3*/
71 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ 71 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
72 bdnz ..ebcloop /* continue for $CTR cache lines */ 72 bdnz ..ebcloop /* continue for $CTR cache lines */
73 73
74 /******************************************************************** 74 /********************************************************************
75 * Delay to ensure all accesses to ROM are complete before changing 75 * Delay to ensure all accesses to ROM are complete before changing
76 * bank 0 timings. 200usec should be enough. 76 * bank 0 timings. 200usec should be enough.
77 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. 77 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
78 *******************************************************************/ 78 *******************************************************************/
79 addis r3, 0, 0x0 79 addis r3, 0, 0x0
80 ori r3, r3, 0xA000 /* wait 200us from reset */ 80 ori r3, r3, 0xA000 /* wait 200us from reset */
81 mtctr r3 81 mtctr r3
82 ..spinlp: 82 ..spinlp:
83 bdnz ..spinlp /* spin loop */ 83 bdnz ..spinlp /* spin loop */
84 84
85 /******************************************************************** 85 /********************************************************************
86 * SETUP CPC0_CR0 86 * SETUP CPC0_CR0
87 *******************************************************************/ 87 *******************************************************************/
88 LI32(r4, 0x007000c0) 88 LI32(r4, 0x007000c0)
89 mtdcr CPC0_CR0, r4 89 mtdcr CPC0_CR0, r4
90 90
91 /******************************************************************** 91 /********************************************************************
92 * Setup CPC0_CR1: Change PCIINT signal to PerWE 92 * Setup CPC0_CR1: Change PCIINT signal to PerWE
93 *******************************************************************/ 93 *******************************************************************/
94 mfdcr r4, CPC0_CR1 94 mfdcr r4, CPC0_CR1
95 ori r4, r4, 0x4000 95 ori r4, r4, 0x4000
96 mtdcr CPC0_CR1, r4 96 mtdcr CPC0_CR1, r4
97 97
98 /******************************************************************** 98 /********************************************************************
99 * Setup External Bus Controller (EBC). 99 * Setup External Bus Controller (EBC).
100 *******************************************************************/ 100 *******************************************************************/
101 WDCR_EBC(EBC0_CFG, 0xd84c0000) 101 WDCR_EBC(EBC0_CFG, 0xd84c0000)
102 /******************************************************************** 102 /********************************************************************
103 * Memory Bank 0 (Intel 28F128J3 Flash) initialization 103 * Memory Bank 0 (Intel 28F128J3 Flash) initialization
104 *******************************************************************/ 104 *******************************************************************/
105 /*WDCR_EBC(PB1AP, 0x02869200)*/ 105 /*WDCR_EBC(PB1AP, 0x02869200)*/
106 WDCR_EBC(PB1AP, 0x07869200) 106 WDCR_EBC(PB1AP, 0x07869200)
107 WDCR_EBC(PB0CR, 0xfe0bc000) 107 WDCR_EBC(PB0CR, 0xfe0bc000)
108 /******************************************************************** 108 /********************************************************************
109 * Memory Bank 1 (Holtek HT6542B PS/2) initialization 109 * Memory Bank 1 (Holtek HT6542B PS/2) initialization
110 *******************************************************************/ 110 *******************************************************************/
111 WDCR_EBC(PB1AP, 0x1f869200) 111 WDCR_EBC(PB1AP, 0x1f869200)
112 WDCR_EBC(PB1CR, 0xf0818000) 112 WDCR_EBC(PB1CR, 0xf0818000)
113 /******************************************************************** 113 /********************************************************************
114 * Memory Bank 2 (Epson S1D13506) initialization 114 * Memory Bank 2 (Epson S1D13506) initialization
115 *******************************************************************/ 115 *******************************************************************/
116 WDCR_EBC(PB2AP, 0x05860300) 116 WDCR_EBC(PB2AP, 0x05860300)
117 WDCR_EBC(PB2CR, 0xf045a000) 117 WDCR_EBC(PB2CR, 0xf045a000)
118 /******************************************************************** 118 /********************************************************************
119 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization 119 * Memory Bank 3 (Philips SJA1000 CAN Controllers) initialization
120 *******************************************************************/ 120 *******************************************************************/
121 WDCR_EBC(PB3AP, 0x0387d200) 121 WDCR_EBC(PB3AP, 0x0387d200)
122 WDCR_EBC(PB3CR, 0xf021c000) 122 WDCR_EBC(PB3CR, 0xf021c000)
123 /******************************************************************** 123 /********************************************************************
124 * Memory Bank 4-7 (Unused) initialization 124 * Memory Bank 4-7 (Unused) initialization
125 *******************************************************************/ 125 *******************************************************************/
126 WDCR_EBC(PB4AP, 0) 126 WDCR_EBC(PB4AP, 0)
127 WDCR_EBC(PB4CR, 0) 127 WDCR_EBC(PB4CR, 0)
128 WDCR_EBC(PB5AP, 0) 128 WDCR_EBC(PB5AP, 0)
129 WDCR_EBC(PB5CR, 0) 129 WDCR_EBC(PB5CR, 0)
130 WDCR_EBC(PB6AP, 0) 130 WDCR_EBC(PB6AP, 0)
131 WDCR_EBC(PB6CR, 0) 131 WDCR_EBC(PB6CR, 0)
132 WDCR_EBC(PB7AP, 0) 132 WDCR_EBC(PB7AP, 0)
133 WDCR_EBC(PB7CR, 0) 133 WDCR_EBC(PB7CR, 0)
134 134
135 /* We are all done */ 135 /* We are all done */
136 mtlr r0 /* Restore link register */ 136 mtlr r0 /* Restore link register */
137 blr /* Return to calling function */ 137 blr /* Return to calling function */
138 .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init 138 .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
139 /* end ext_bus_cntlr_init() */ 139 /* end ext_bus_cntlr_init() */
140 140
141 /****************************************************************************** 141 /******************************************************************************
142 * Function: sdram_init 142 * Function: sdram_init
143 * 143 *
144 * Description: Configures SDRAM memory banks. 144 * Description: Configures SDRAM memory banks.
145 * 145 *
146 * Notes: Does NOT use the stack. 146 * Notes: Does NOT use the stack.
147 *****************************************************************************/ 147 *****************************************************************************/
148 .section ".text" 148 .section ".text"
149 .align 2 149 .align 2
150 .globl sdram_init 150 .globl sdram_init
151 .type sdram_init, @function 151 .type sdram_init, @function
152 sdram_init: 152 sdram_init:
153 153
154 /* 154 /*
155 * Disable memory controller to allow 155 * Disable memory controller to allow
156 * values to be changed. 156 * values to be changed.
157 */ 157 */
158 WDCR_SDRAM(SDRAM0_CFG, 0x00000000) 158 WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
159 159
160 /* 160 /*
161 * Configure Memory Banks 161 * Configure Memory Banks
162 */ 162 */
163 WDCR_SDRAM(SDRAM0_B0CR, 0x00084001) 163 WDCR_SDRAM(SDRAM0_B0CR, 0x00084001)
164 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) 164 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
165 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) 165 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
166 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) 166 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
167 167
168 /* 168 /*
169 * Set up SDTR1 (SDRAM Timing Register) 169 * Set up SDTR1 (SDRAM Timing Register)
170 */ 170 */
171 WDCR_SDRAM(SDRAM0_TR, 0x00854009) 171 WDCR_SDRAM(SDRAM0_TR, 0x00854009)
172 172
173 /* 173 /*
174 * Set RTR (Refresh Timing Register) 174 * Set RTR (Refresh Timing Register)
175 */ 175 */
176 WDCR_SDRAM(SDRAM0_RTR, 0x10000000) 176 WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
177 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ 177 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
178 178
179 /******************************************************************** 179 /********************************************************************
180 * Delay to ensure 200usec have elapsed since reset. Assume worst 180 * Delay to ensure 200usec have elapsed since reset. Assume worst
181 * case that the core is running 200Mhz: 181 * case that the core is running 200Mhz:
182 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles 182 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
183 *******************************************************************/ 183 *******************************************************************/
184 addis r3, 0, 0x0000 184 addis r3, 0, 0x0000
185 ori r3, r3, 0xA000 /* Wait >200us from reset */ 185 ori r3, r3, 0xA000 /* Wait >200us from reset */
186 mtctr r3 186 mtctr r3
187 ..spinlp2: 187 ..spinlp2:
188 bdnz ..spinlp2 /* spin loop */ 188 bdnz ..spinlp2 /* spin loop */
189 189
190 /******************************************************************** 190 /********************************************************************
191 * Set memory controller options reg, MCOPT1. 191 * Set memory controller options reg, MCOPT1.
192 *******************************************************************/ 192 *******************************************************************/
193 WDCR_SDRAM(SDRAM0_CFG,0x80800000) 193 WDCR_SDRAM(SDRAM0_CFG,0x80800000)
194 194
195 ..sdri_done: 195 ..sdri_done:
196 blr /* Return to calling function */ 196 blr /* Return to calling function */
197 .Lfe1: .size sdram_init,.Lfe1-sdram_init 197 .Lfe1: .size sdram_init,.Lfe1-sdram_init
198 /* end sdram_init() */ 198 /* end sdram_init() */
199 199
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 #include <config.h> 4 #include <config.h>
5 #include <asm/ppc4xx.h> 5 #include <asm/ppc4xx.h>
6 6
7 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 7 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
8 8
9 #include <ppc_asm.tmpl> 9 #include <ppc_asm.tmpl>
10 #include <ppc_defs.h> 10 #include <ppc_defs.h>
11 11
12 #include <asm/cache.h> 12 #include <asm/cache.h>
13 #include <asm/mmu.h> 13 #include <asm/mmu.h>
14 14
15 #define LI32(reg,val) \ 15 #define LI32(reg,val) \
16 addis reg,0,val@h;\ 16 addis reg,0,val@h;\
17 ori reg,reg,val@l 17 ori reg,reg,val@l
18 18
19 #define WDCR_EBC(reg,val) \ 19 #define WDCR_EBC(reg,val) \
20 addi r4,0,reg;\ 20 addi r4,0,reg;\
21 mtdcr EBC0_CFGADDR,r4;\ 21 mtdcr EBC0_CFGADDR,r4;\
22 addis r4,0,val@h;\ 22 addis r4,0,val@h;\
23 ori r4,r4,val@l;\ 23 ori r4,r4,val@l;\
24 mtdcr EBC0_CFGDATA,r4 24 mtdcr EBC0_CFGDATA,r4
25 25
26 #define WDCR_SDRAM(reg,val) \ 26 #define WDCR_SDRAM(reg,val) \
27 addi r4,0,reg;\ 27 addi r4,0,reg;\
28 mtdcr SDRAM0_CFGADDR,r4;\ 28 mtdcr SDRAM0_CFGADDR,r4;\
29 addis r4,0,val@h;\ 29 addis r4,0,val@h;\
30 ori r4,r4,val@l;\ 30 ori r4,r4,val@l;\
31 mtdcr SDRAM0_CFGDATA,r4 31 mtdcr SDRAM0_CFGDATA,r4
32 32
33 /****************************************************************************** 33 /******************************************************************************
34 * Function: ext_bus_cntlr_init 34 * Function: ext_bus_cntlr_init
35 * 35 *
36 * Description: Configures EBC Controller and a few basic chip selects. 36 * Description: Configures EBC Controller and a few basic chip selects.
37 * 37 *
38 * CS0 is setup to get the Boot Flash out of the addresss range 38 * CS0 is setup to get the Boot Flash out of the addresss range
39 * so that we may setup a stack. CS7 is setup so that we can 39 * so that we may setup a stack. CS7 is setup so that we can
40 * access and reset the hardware watchdog. 40 * access and reset the hardware watchdog.
41 * 41 *
42 * IMPORTANT: For pass1 this code must run from 42 * IMPORTANT: For pass1 this code must run from
43 * cache since you can not reliably change a peripheral banks 43 * cache since you can not reliably change a peripheral banks
44 * timing register (pbxap) while running code from that bank. 44 * timing register (pbxap) while running code from that bank.
45 * For ex., since we are running from ROM on bank 0, we can NOT 45 * For ex., since we are running from ROM on bank 0, we can NOT
46 * execute the code that modifies bank 0 timings from ROM, so 46 * execute the code that modifies bank 0 timings from ROM, so
47 * we run it from cache. 47 * we run it from cache.
48 * 48 *
49 * Notes: Does NOT use the stack. 49 * Notes: Does NOT use the stack.
50 *****************************************************************************/ 50 *****************************************************************************/
51 .section ".text" 51 .section ".text"
52 .align 2 52 .align 2
53 .globl ext_bus_cntlr_init 53 .globl ext_bus_cntlr_init
54 .type ext_bus_cntlr_init, @function 54 .type ext_bus_cntlr_init, @function
55 ext_bus_cntlr_init: 55 ext_bus_cntlr_init:
56 mflr r0 56 mflr r0
57 /******************************************************************** 57 /********************************************************************
58 * Prefetch entire ext_bus_cntrl_init function into the icache. 58 * Prefetch entire ext_bus_cntrl_init function into the icache.
59 * This is necessary because we are going to change the same CS we 59 * This is necessary because we are going to change the same CS we
60 * are executing from. Otherwise a CPU lockup may occur. 60 * are executing from. Otherwise a CPU lockup may occur.
61 *******************************************************************/ 61 *******************************************************************/
62 bl ..getAddr 62 bl ..getAddr
63 ..getAddr: 63 ..getAddr:
64 mflr r3 /* get address of ..getAddr */ 64 mflr r3 /* get address of ..getAddr */
65 65
66 /* Calculate number of cache lines for this function */ 66 /* Calculate number of cache lines for this function */
67 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) 67 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
68 mtctr r4 68 mtctr r4
69 ..ebcloop: 69 ..ebcloop:
70 icbt r0, r3 /* prefetch cache line for addr in r3*/ 70 icbt r0, r3 /* prefetch cache line for addr in r3*/
71 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ 71 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
72 bdnz ..ebcloop /* continue for $CTR cache lines */ 72 bdnz ..ebcloop /* continue for $CTR cache lines */
73 73
74 /******************************************************************** 74 /********************************************************************
75 * Delay to ensure all accesses to ROM are complete before changing 75 * Delay to ensure all accesses to ROM are complete before changing
76 * bank 0 timings. 200usec should be enough. 76 * bank 0 timings. 200usec should be enough.
77 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. 77 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
78 *******************************************************************/ 78 *******************************************************************/
79 addis r3, 0, 0x0 79 addis r3, 0, 0x0
80 ori r3, r3, 0xA000 /* wait 200us from reset */ 80 ori r3, r3, 0xA000 /* wait 200us from reset */
81 mtctr r3 81 mtctr r3
82 ..spinlp: 82 ..spinlp:
83 bdnz ..spinlp /* spin loop */ 83 bdnz ..spinlp /* spin loop */
84 84
85 /******************************************************************** 85 /********************************************************************
86 * SETUP CPC0_CR0 86 * SETUP CPC0_CR0
87 *******************************************************************/ 87 *******************************************************************/
88 LI32(r4, 0x00c01030) 88 LI32(r4, 0x00c01030)
89 mtdcr CPC0_CR0, r4 89 mtdcr CPC0_CR0, r4
90 90
91 /******************************************************************** 91 /********************************************************************
92 * Setup CPC0_CR1: Change PCIINT signal to PerWE 92 * Setup CPC0_CR1: Change PCIINT signal to PerWE
93 *******************************************************************/ 93 *******************************************************************/
94 mfdcr r4, CPC0_CR1 94 mfdcr r4, CPC0_CR1
95 ori r4, r4, 0x4000 95 ori r4, r4, 0x4000
96 mtdcr CPC0_CR1, r4 96 mtdcr CPC0_CR1, r4
97 97
98 /******************************************************************** 98 /********************************************************************
99 * Setup External Bus Controller (EBC). 99 * Setup External Bus Controller (EBC).
100 *******************************************************************/ 100 *******************************************************************/
101 WDCR_EBC(EBC0_CFG, 0xd84c0000) 101 WDCR_EBC(EBC0_CFG, 0xd84c0000)
102 /******************************************************************** 102 /********************************************************************
103 * Memory Bank 0 (Intel 28F640J3 Flash) initialization 103 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
104 *******************************************************************/ 104 *******************************************************************/
105 /*WDCR_EBC(PB1AP, 0x03055200)*/ 105 /*WDCR_EBC(PB1AP, 0x03055200)*/
106 /*WDCR_EBC(PB1AP, 0x04055200)*/ 106 /*WDCR_EBC(PB1AP, 0x04055200)*/
107 WDCR_EBC(PB1AP, 0x08055200) 107 WDCR_EBC(PB1AP, 0x08055200)
108 WDCR_EBC(PB0CR, 0xff87a000) 108 WDCR_EBC(PB0CR, 0xff87a000)
109 /******************************************************************** 109 /********************************************************************
110 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization 110 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
111 *******************************************************************/ 111 *******************************************************************/
112 /*WDCR_EBC(PB3AP, 0x07869200)*/ 112 /*WDCR_EBC(PB3AP, 0x07869200)*/
113 WDCR_EBC(PB3AP, 0x04055200) 113 WDCR_EBC(PB3AP, 0x04055200)
114 WDCR_EBC(PB3CR, 0xf081c000) 114 WDCR_EBC(PB3CR, 0xf081c000)
115 /******************************************************************** 115 /********************************************************************
116 * Memory Bank 1,2,4-7 (Unused) initialization 116 * Memory Bank 1,2,4-7 (Unused) initialization
117 *******************************************************************/ 117 *******************************************************************/
118 WDCR_EBC(PB1AP, 0) 118 WDCR_EBC(PB1AP, 0)
119 WDCR_EBC(PB1CR, 0) 119 WDCR_EBC(PB1CR, 0)
120 WDCR_EBC(PB2AP, 0) 120 WDCR_EBC(PB2AP, 0)
121 WDCR_EBC(PB2CR, 0) 121 WDCR_EBC(PB2CR, 0)
122 WDCR_EBC(PB4AP, 0) 122 WDCR_EBC(PB4AP, 0)
123 WDCR_EBC(PB4CR, 0) 123 WDCR_EBC(PB4CR, 0)
124 WDCR_EBC(PB5AP, 0) 124 WDCR_EBC(PB5AP, 0)
125 WDCR_EBC(PB5CR, 0) 125 WDCR_EBC(PB5CR, 0)
126 WDCR_EBC(PB6AP, 0) 126 WDCR_EBC(PB6AP, 0)
127 WDCR_EBC(PB6CR, 0) 127 WDCR_EBC(PB6CR, 0)
128 WDCR_EBC(PB7AP, 0) 128 WDCR_EBC(PB7AP, 0)
129 WDCR_EBC(PB7CR, 0) 129 WDCR_EBC(PB7CR, 0)
130 130
131 /* We are all done */ 131 /* We are all done */
132 mtlr r0 /* Restore link register */ 132 mtlr r0 /* Restore link register */
133 blr /* Return to calling function */ 133 blr /* Return to calling function */
134 .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init 134 .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
135 /* end ext_bus_cntlr_init() */ 135 /* end ext_bus_cntlr_init() */
136 136
137 /****************************************************************************** 137 /******************************************************************************
138 * Function: sdram_init 138 * Function: sdram_init
139 * 139 *
140 * Description: Configures SDRAM memory banks. 140 * Description: Configures SDRAM memory banks.
141 * 141 *
142 * Notes: Does NOT use the stack. 142 * Notes: Does NOT use the stack.
143 *****************************************************************************/ 143 *****************************************************************************/
144 .section ".text" 144 .section ".text"
145 .align 2 145 .align 2
146 .globl sdram_init 146 .globl sdram_init
147 .type sdram_init, @function 147 .type sdram_init, @function
148 sdram_init: 148 sdram_init:
149 149
150 /* 150 /*
151 * Disable memory controller to allow 151 * Disable memory controller to allow
152 * values to be changed. 152 * values to be changed.
153 */ 153 */
154 WDCR_SDRAM(SDRAM0_CFG, 0x00000000) 154 WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
155 155
156 /* 156 /*
157 * Configure Memory Banks 157 * Configure Memory Banks
158 */ 158 */
159 WDCR_SDRAM(SDRAM0_B0CR, 0x00062001) 159 WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
160 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) 160 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
161 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) 161 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
162 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) 162 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
163 163
164 /* 164 /*
165 * Set up SDTR1 (SDRAM Timing Register) 165 * Set up SDTR1 (SDRAM Timing Register)
166 */ 166 */
167 WDCR_SDRAM(SDRAM0_TR, 0x00854009) 167 WDCR_SDRAM(SDRAM0_TR, 0x00854009)
168 168
169 /* 169 /*
170 * Set RTR (Refresh Timing Register) 170 * Set RTR (Refresh Timing Register)
171 */ 171 */
172 WDCR_SDRAM(SDRAM0_RTR, 0x10000000) 172 WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
173 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ 173 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
174 174
175 /******************************************************************** 175 /********************************************************************
176 * Delay to ensure 200usec have elapsed since reset. Assume worst 176 * Delay to ensure 200usec have elapsed since reset. Assume worst
177 * case that the core is running 200Mhz: 177 * case that the core is running 200Mhz:
178 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles 178 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
179 *******************************************************************/ 179 *******************************************************************/
180 addis r3, 0, 0x0000 180 addis r3, 0, 0x0000
181 ori r3, r3, 0xA000 /* Wait >200us from reset */ 181 ori r3, r3, 0xA000 /* Wait >200us from reset */
182 mtctr r3 182 mtctr r3
183 ..spinlp2: 183 ..spinlp2:
184 bdnz ..spinlp2 /* spin loop */ 184 bdnz ..spinlp2 /* spin loop */
185 185
186 /******************************************************************** 186 /********************************************************************
187 * Set memory controller options reg, MCOPT1. 187 * Set memory controller options reg, MCOPT1.
188 *******************************************************************/ 188 *******************************************************************/
189 WDCR_SDRAM(SDRAM0_CFG,0x80800000) 189 WDCR_SDRAM(SDRAM0_CFG,0x80800000)
190 190
191 ..sdri_done: 191 ..sdri_done:
192 blr /* Return to calling function */ 192 blr /* Return to calling function */
193 .Lfe1: .size sdram_init,.Lfe1-sdram_init 193 .Lfe1: .size sdram_init,.Lfe1-sdram_init
194 /* end sdram_init() */ 194 /* end sdram_init() */
195 195
board/esd/pci405/writeibm.S
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 /*----------------------------------------------------------------------------- */ 4 /*----------------------------------------------------------------------------- */
5 /* Function: ext_bus_cntlr_init */ 5 /* Function: ext_bus_cntlr_init */
6 /* Description: Initializes the External Bus Controller for the external */ 6 /* Description: Initializes the External Bus Controller for the external */
7 /* peripherals. IMPORTANT: For pass1 this code must run from */ 7 /* peripherals. IMPORTANT: For pass1 this code must run from */
8 /* cache since you can not reliably change a peripheral banks */ 8 /* cache since you can not reliably change a peripheral banks */
9 /* timing register (pbxap) while running code from that bank. */ 9 /* timing register (pbxap) while running code from that bank. */
10 /* For ex., since we are running from ROM on bank 0, we can NOT */ 10 /* For ex., since we are running from ROM on bank 0, we can NOT */
11 /* execute the code that modifies bank 0 timings from ROM, so */ 11 /* execute the code that modifies bank 0 timings from ROM, so */
12 /* we run it from cache. */ 12 /* we run it from cache. */
13 /* Bank 0 - Flash and SRAM */ 13 /* Bank 0 - Flash and SRAM */
14 /* Bank 1 - NVRAM/RTC */ 14 /* Bank 1 - NVRAM/RTC */
15 /* Bank 2 - Keyboard/Mouse controller */ 15 /* Bank 2 - Keyboard/Mouse controller */
16 /* Bank 3 - IR controller */ 16 /* Bank 3 - IR controller */
17 /* Bank 4 - not used */ 17 /* Bank 4 - not used */
18 /* Bank 5 - not used */ 18 /* Bank 5 - not used */
19 /* Bank 6 - not used */ 19 /* Bank 6 - not used */
20 /* Bank 7 - FPGA registers */ 20 /* Bank 7 - FPGA registers */
21 /*----------------------------------------------------------------------------- */ 21 /*----------------------------------------------------------------------------- */
22 #include <asm/ppc4xx.h> 22 #include <asm/ppc4xx.h>
23 23
24 #include <ppc_asm.tmpl> 24 #include <ppc_asm.tmpl>
25 #include <ppc_defs.h> 25 #include <ppc_defs.h>
26 26
27 #include <asm/cache.h> 27 #include <asm/cache.h>
28 #include <asm/mmu.h> 28 #include <asm/mmu.h>
29 29
30 30
31 .globl write_without_sync 31 .globl write_without_sync
32 write_without_sync: 32 write_without_sync:
33 /* 33 /*
34 * Write one values to host via pci busmastering 34 * Write one values to host via pci busmastering
35 * ptr = 0xc0000000 -> 0x01000000 (PCI) 35 * ptr = 0xc0000000 -> 0x01000000 (PCI)
36 * *ptr = 0x01234567; 36 * *ptr = 0x01234567;
37 */ 37 */
38 addi r31,0,0 38 addi r31,0,0
39 lis r31,0xc000 39 lis r31,0xc000
40 40
41 start1: 41 start1:
42 lis r0,0x0123 42 lis r0,0x0123
43 ori r0,r0,0x4567 43 ori r0,r0,0x4567
44 stw r0,0(r31) 44 stw r0,0(r31)
45 45
46 /* 46 /*
47 * Read one value back 47 * Read one value back
48 * ptr = (volatile unsigned long *)addr; 48 * ptr = (volatile unsigned long *)addr;
49 * val = *ptr; 49 * val = *ptr;
50 */ 50 */
51 51
52 lwz r0,0(r31) 52 lwz r0,0(r31)
53 53
54 /* 54 /*
55 * One pci config write 55 * One pci config write
56 * ibmPciConfigWrite(0x2e, 2, 0x1234); 56 * ibmPciConfigWrite(0x2e, 2, 0x1234);
57 */ 57 */
58 /* subsystem id */ 58 /* subsystem id */
59 59
60 li r4,0x002C 60 li r4,0x002C
61 oris r4,r4,0x8000 61 oris r4,r4,0x8000
62 lis r3,0xEEC0 62 lis r3,0xEEC0
63 stwbrx r4,0,r3 63 stwbrx r4,0,r3
64 64
65 li r5,0x1234 65 li r5,0x1234
66 ori r3,r3,0x4 66 ori r3,r3,0x4
67 stwbrx r5,0,r3 67 stwbrx r5,0,r3
68 68
69 b start1 69 b start1
70 70
71 blr /* never reached !!!! */ 71 blr /* never reached !!!! */
72 72
73 .globl write_with_sync 73 .globl write_with_sync
74 write_with_sync: 74 write_with_sync:
75 /* 75 /*
76 * Write one values to host via pci busmastering 76 * Write one values to host via pci busmastering
77 * ptr = 0xc0000000 -> 0x01000000 (PCI) 77 * ptr = 0xc0000000 -> 0x01000000 (PCI)
78 * *ptr = 0x01234567; 78 * *ptr = 0x01234567;
79 */ 79 */
80 addi r31,0,0 80 addi r31,0,0
81 lis r31,0xc000 81 lis r31,0xc000
82 82
83 start2: 83 start2:
84 lis r0,0x0123 84 lis r0,0x0123
85 ori r0,r0,0x4567 85 ori r0,r0,0x4567
86 stw r0,0(r31) 86 stw r0,0(r31)
87 87
88 /* 88 /*
89 * Read one value back 89 * Read one value back
90 * ptr = (volatile unsigned long *)addr; 90 * ptr = (volatile unsigned long *)addr;
91 * val = *ptr; 91 * val = *ptr;
92 */ 92 */
93 93
94 lwz r0,0(r31) 94 lwz r0,0(r31)
95 95
96 /* 96 /*
97 * One pci config write 97 * One pci config write
98 * ibmPciConfigWrite(0x2e, 2, 0x1234); 98 * ibmPciConfigWrite(0x2e, 2, 0x1234);
99 */ 99 */
100 /* subsystem id */ 100 /* subsystem id */
101 101
102 li r4,0x002C 102 li r4,0x002C
103 oris r4,r4,0x8000 103 oris r4,r4,0x8000
104 lis r3,0xEEC0 104 lis r3,0xEEC0
105 stwbrx r4,0,r3 105 stwbrx r4,0,r3
106 sync 106 sync
107 107
108 li r5,0x1234 108 li r5,0x1234
109 ori r3,r3,0x4 109 ori r3,r3,0x4
110 stwbrx r5,0,r3 110 stwbrx r5,0,r3
111 sync 111 sync
112 112
113 b start2 113 b start2
114 114
115 blr /* never reached !!!! */ 115 blr /* never reached !!!! */
116 116
117 .globl write_with_less_sync 117 .globl write_with_less_sync
118 write_with_less_sync: 118 write_with_less_sync:
119 /* 119 /*
120 * Write one values to host via pci busmastering 120 * Write one values to host via pci busmastering
121 * ptr = 0xc0000000 -> 0x01000000 (PCI) 121 * ptr = 0xc0000000 -> 0x01000000 (PCI)
122 * *ptr = 0x01234567; 122 * *ptr = 0x01234567;
123 */ 123 */
124 addi r31,0,0 124 addi r31,0,0
125 lis r31,0xc000 125 lis r31,0xc000
126 126
127 start2b: 127 start2b:
128 lis r0,0x0123 128 lis r0,0x0123
129 ori r0,r0,0x4567 129 ori r0,r0,0x4567
130 stw r0,0(r31) 130 stw r0,0(r31)
131 131
132 /* 132 /*
133 * Read one value back 133 * Read one value back
134 * ptr = (volatile unsigned long *)addr; 134 * ptr = (volatile unsigned long *)addr;
135 * val = *ptr; 135 * val = *ptr;
136 */ 136 */
137 137
138 lwz r0,0(r31) 138 lwz r0,0(r31)
139 139
140 /* 140 /*
141 * One pci config write 141 * One pci config write
142 * ibmPciConfigWrite(0x2e, 2, 0x1234); 142 * ibmPciConfigWrite(0x2e, 2, 0x1234);
143 */ 143 */
144 /* subsystem id */ 144 /* subsystem id */
145 145
146 li r4,0x002C 146 li r4,0x002C
147 oris r4,r4,0x8000 147 oris r4,r4,0x8000
148 lis r3,0xEEC0 148 lis r3,0xEEC0
149 stwbrx r4,0,r3 149 stwbrx r4,0,r3
150 sync 150 sync
151 151
152 li r5,0x1234 152 li r5,0x1234
153 ori r3,r3,0x4 153 ori r3,r3,0x4
154 stwbrx r5,0,r3 154 stwbrx r5,0,r3
155 /* sync */ 155 /* sync */
156 156
157 b start2b 157 b start2b
158 158
159 blr /* never reached !!!! */ 159 blr /* never reached !!!! */
160 160
161 .globl write_with_more_sync 161 .globl write_with_more_sync
162 write_with_more_sync: 162 write_with_more_sync:
163 /* 163 /*
164 * Write one values to host via pci busmastering 164 * Write one values to host via pci busmastering
165 * ptr = 0xc0000000 -> 0x01000000 (PCI) 165 * ptr = 0xc0000000 -> 0x01000000 (PCI)
166 * *ptr = 0x01234567; 166 * *ptr = 0x01234567;
167 */ 167 */
168 addi r31,0,0 168 addi r31,0,0
169 lis r31,0xc000 169 lis r31,0xc000
170 170
171 start3: 171 start3:
172 lis r0,0x0123 172 lis r0,0x0123
173 ori r0,r0,0x4567 173 ori r0,r0,0x4567
174 stw r0,0(r31) 174 stw r0,0(r31)
175 sync 175 sync
176 176
177 /* 177 /*
178 * Read one value back 178 * Read one value back
179 * ptr = (volatile unsigned long *)addr; 179 * ptr = (volatile unsigned long *)addr;
180 * val = *ptr; 180 * val = *ptr;
181 */ 181 */
182 182
183 lwz r0,0(r31) 183 lwz r0,0(r31)
184 sync 184 sync
185 185
186 /* 186 /*
187 * One pci config write 187 * One pci config write
188 * ibmPciConfigWrite(0x2e, 2, 0x1234); 188 * ibmPciConfigWrite(0x2e, 2, 0x1234);
189 */ 189 */
190 /* subsystem id (PCIC0_SBSYSVID)*/ 190 /* subsystem id (PCIC0_SBSYSVID)*/
191 191
192 li r4,0x002C 192 li r4,0x002C
193 oris r4,r4,0x8000 193 oris r4,r4,0x8000
194 lis r3,0xEEC0 194 lis r3,0xEEC0
195 stwbrx r4,0,r3 195 stwbrx r4,0,r3
196 sync 196 sync
197 197
198 li r5,0x1234 198 li r5,0x1234
199 ori r3,r3,0x4 199 ori r3,r3,0x4
200 stwbrx r5,0,r3 200 stwbrx r5,0,r3
201 sync 201 sync
202 202
203 b start3 203 b start3
204 204
205 blr /* never reached !!!! */ 205 blr /* never reached !!!! */
206 206
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 /*------------------------------------------------------------------------- */ 4 /*------------------------------------------------------------------------- */
5 /* Function: ext_bus_cntlr_init */ 5 /* Function: ext_bus_cntlr_init */
6 /* Description: Initializes the External Bus Controller for the external */ 6 /* Description: Initializes the External Bus Controller for the external */
7 /* peripherals. IMPORTANT: For pass1 this code must run from */ 7 /* peripherals. IMPORTANT: For pass1 this code must run from */
8 /* cache since you can not reliably change a peripheral banks */ 8 /* cache since you can not reliably change a peripheral banks */
9 /* timing register (pbxap) while running code from that bank. */ 9 /* timing register (pbxap) while running code from that bank. */
10 /* For ex., since we are running from ROM on bank 0, we can NOT */ 10 /* For ex., since we are running from ROM on bank 0, we can NOT */
11 /* execute the code that modifies bank 0 timings from ROM, so */ 11 /* execute the code that modifies bank 0 timings from ROM, so */
12 /* we run it from cache. */ 12 /* we run it from cache. */
13 /* */ 13 /* */
14 /* */ 14 /* */
15 /* The layout for the PEI JSE board: */ 15 /* The layout for the PEI JSE board: */
16 /* Bank 0 - Flash and SRAM */ 16 /* Bank 0 - Flash and SRAM */
17 /* Bank 1 - SystemACE */ 17 /* Bank 1 - SystemACE */
18 /* Bank 2 - not used */ 18 /* Bank 2 - not used */
19 /* Bank 3 - not used */ 19 /* Bank 3 - not used */
20 /* Bank 4 - not used */ 20 /* Bank 4 - not used */
21 /* Bank 5 - not used */ 21 /* Bank 5 - not used */
22 /* Bank 6 - not used */ 22 /* Bank 6 - not used */
23 /* Bank 7 - not used */ 23 /* Bank 7 - not used */
24 /*------------------------------------------------------------------------- */ 24 /*------------------------------------------------------------------------- */
25 #include <asm/ppc4xx.h> 25 #include <asm/ppc4xx.h>
26 26
27 #include <ppc_asm.tmpl> 27 #include <ppc_asm.tmpl>
28 #include <ppc_defs.h> 28 #include <ppc_defs.h>
29 29
30 #include <asm/cache.h> 30 #include <asm/cache.h>
31 #include <asm/mmu.h> 31 #include <asm/mmu.h>
32 32
33 .globl ext_bus_cntlr_init 33 .globl ext_bus_cntlr_init
34 ext_bus_cntlr_init: 34 ext_bus_cntlr_init:
35 mflr r4 /* save link register */ 35 mflr r4 /* save link register */
36 bl ..getAddr 36 bl ..getAddr
37 ..getAddr: 37 ..getAddr:
38 mflr r3 /* get address of ..getAddr */ 38 mflr r3 /* get address of ..getAddr */
39 mtlr r4 /* restore link register */ 39 mtlr r4 /* restore link register */
40 addi r4,0,14 /* set ctr to 10; used to prefetch */ 40 addi r4,0,14 /* set ctr to 10; used to prefetch */
41 mtctr r4 /* 10 cache lines to fit this function */ 41 mtctr r4 /* 10 cache lines to fit this function */
42 /* in cache (gives us 8x10=80 instrctns) */ 42 /* in cache (gives us 8x10=80 instrctns) */
43 ..ebcloop: 43 ..ebcloop:
44 icbt r0,r3 /* prefetch cache line for addr in r3 */ 44 icbt r0,r3 /* prefetch cache line for addr in r3 */
45 addi r3,r3,32 /* move to next cache line */ 45 addi r3,r3,32 /* move to next cache line */
46 bdnz ..ebcloop /* continue for 10 cache lines */ 46 bdnz ..ebcloop /* continue for 10 cache lines */
47 47
48 /*----------------------------------------------------------------- */ 48 /*----------------------------------------------------------------- */
49 /* Delay to ensure all accesses to ROM are complete before changing */ 49 /* Delay to ensure all accesses to ROM are complete before changing */
50 /* bank 0 timings. 200usec should be enough. */ 50 /* bank 0 timings. 200usec should be enough. */
51 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */ 51 /* 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles */
52 /*----------------------------------------------------------------- */ 52 /*----------------------------------------------------------------- */
53 addis r3,0,0x0 53 addis r3,0,0x0
54 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ 54 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
55 mtctr r3 55 mtctr r3
56 ..spinlp: 56 ..spinlp:
57 bdnz ..spinlp /* spin loop */ 57 bdnz ..spinlp /* spin loop */
58 58
59 /*----------------------------------------------------------------- */ 59 /*----------------------------------------------------------------- */
60 /* Memory Bank 0 (Flash) initialization */ 60 /* Memory Bank 0 (Flash) initialization */
61 /*----------------------------------------------------------------- */ 61 /*----------------------------------------------------------------- */
62 62
63 addi r4,0,PB1AP 63 addi r4,0,PB1AP
64 mtdcr EBC0_CFGADDR,r4 64 mtdcr EBC0_CFGADDR,r4
65 addis r4,0,0x9B01 65 addis r4,0,0x9B01
66 ori r4,r4,0x5480 66 ori r4,r4,0x5480
67 mtdcr EBC0_CFGDATA,r4 67 mtdcr EBC0_CFGDATA,r4
68 68
69 addi r4,0,PB0CR 69 addi r4,0,PB0CR
70 mtdcr EBC0_CFGADDR,r4 70 mtdcr EBC0_CFGADDR,r4
71 addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */ 71 addis r4,0,0xFFF1 /* BAS=0xFFF,BS=0x0(1MB),BU=0x3(R/W), */
72 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */ 72 ori r4,r4,0x8000 /* BW=0x0( 8 bits) */
73 mtdcr EBC0_CFGDATA,r4 73 mtdcr EBC0_CFGDATA,r4
74 74
75 blr 75 blr
76 76
board/mpl/common/pci.c
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 /* 4 /*
5 * Adapted for PIP405 03.07.01 5 * Adapted for PIP405 03.07.01
6 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch 6 * Denis Peter, MPL AG Switzerland, d.peter@mpl.ch
7 * 7 *
8 * TODO: Clean-up 8 * TODO: Clean-up
9 */ 9 */
10 10
11 #include <common.h> 11 #include <common.h>
12 #include <pci.h> 12 #include <pci.h>
13 #include "isa.h" 13 #include "isa.h"
14 14
15 #ifdef CONFIG_405GP 15 #ifdef CONFIG_405GP
16 #ifdef CONFIG_PCI 16 #ifdef CONFIG_PCI
17 17
18 DECLARE_GLOBAL_DATA_PTR; 18 DECLARE_GLOBAL_DATA_PTR;
19 19
20 #include "piix4_pci.h" 20 #include "piix4_pci.h"
21 #include "pci_parts.h" 21 #include "pci_parts.h"
22 22
23 void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev, 23 void pci_pip405_write_regs(struct pci_controller *hose, pci_dev_t dev,
24 struct pci_config_table *entry) 24 struct pci_config_table *entry)
25 { 25 {
26 struct pci_pip405_config_entry *table; 26 struct pci_pip405_config_entry *table;
27 int i; 27 int i;
28 28
29 table = (struct pci_pip405_config_entry*) entry->priv[0]; 29 table = (struct pci_pip405_config_entry*) entry->priv[0];
30 30
31 for (i=0; table[i].width; i++) 31 for (i=0; table[i].width; i++)
32 { 32 {
33 #ifdef DEBUG 33 #ifdef DEBUG
34 printf("Reg 0x%02X Value 0x%08lX Width %02d written\n", 34 printf("Reg 0x%02X Value 0x%08lX Width %02d written\n",
35 table[i].index, table[i].val, table[i].width); 35 table[i].index, table[i].val, table[i].width);
36 #endif 36 #endif
37 37
38 switch(table[i].width) 38 switch(table[i].width)
39 { 39 {
40 case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break; 40 case 1: pci_hose_write_config_byte(hose, dev, table[i].index, table[i].val); break;
41 case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break; 41 case 2: pci_hose_write_config_word(hose, dev, table[i].index, table[i].val); break;
42 case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break; 42 case 4: pci_hose_write_config_dword(hose, dev, table[i].index, table[i].val); break;
43 } 43 }
44 } 44 }
45 } 45 }
46 46
47 47
48 static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev) 48 static void pci_pip405_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
49 { 49 {
50 unsigned char int_line = 0xff; 50 unsigned char int_line = 0xff;
51 unsigned char pin; 51 unsigned char pin;
52 /* 52 /*
53 * Write pci interrupt line register 53 * Write pci interrupt line register
54 */ 54 */
55 if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */ 55 if(PCI_DEV(dev)==0) /* Device0 = PPC405 -> skip */
56 return; 56 return;
57 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin); 57 pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &pin);
58 if ((pin == 0) || (pin > 4)) 58 if ((pin == 0) || (pin > 4))
59 return; 59 return;
60 60
61 int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28; 61 int_line = ((PCI_DEV(dev) + (pin-1) + 10) % 4) + 28;
62 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line); 62 pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, int_line);
63 #ifdef DEBUG 63 #ifdef DEBUG
64 printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n", 64 printf("Fixup IRQ: dev %d (%x) int line %d 0x%x\n",
65 PCI_DEV(dev),dev,int_line,int_line); 65 PCI_DEV(dev),dev,int_line,int_line);
66 #endif 66 #endif
67 } 67 }
68 68
69 extern void pci_405gp_init(struct pci_controller *hose); 69 extern void pci_405gp_init(struct pci_controller *hose);
70 70
71 71
72 static struct pci_controller hose = { 72 static struct pci_controller hose = {
73 config_table: pci_pip405_config_table, 73 config_table: pci_pip405_config_table,
74 fixup_irq: pci_pip405_fixup_irq, 74 fixup_irq: pci_pip405_fixup_irq,
75 }; 75 };
76 76
77 77
78 void pci_init_board(void) 78 void pci_init_board(void)
79 { 79 {
80 /*we want the ptrs to RAM not flash (ie don't use init list)*/ 80 /*we want the ptrs to RAM not flash (ie don't use init list)*/
81 hose.fixup_irq = pci_pip405_fixup_irq; 81 hose.fixup_irq = pci_pip405_fixup_irq;
82 hose.config_table = pci_pip405_config_table; 82 hose.config_table = pci_pip405_config_table;
83 #ifdef DEBUG 83 #ifdef DEBUG
84 printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose); 84 printf("Init PCI: fixup_irq=%p config_table=%p hose=%p\n",pci_pip405_fixup_irq,pci_pip405_config_table,hose);
85 #endif 85 #endif
86 pci_405gp_init(&hose); 86 pci_405gp_init(&hose);
87 } 87 }
88 88
89 #endif /* CONFIG_PCI */ 89 #endif /* CONFIG_PCI */
90 #endif /* CONFIG_405GP */ 90 #endif /* CONFIG_405GP */
91 91
board/mpl/mip405/init.S
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 /*----------------------------------------------------------------------------- 4 /*-----------------------------------------------------------------------------
5 * Function: ext_bus_cntlr_init 5 * Function: ext_bus_cntlr_init
6 * Description: Initializes the External Bus Controller for the external 6 * Description: Initializes the External Bus Controller for the external
7 * peripherals. IMPORTANT: For pass1 this code must run from 7 * peripherals. IMPORTANT: For pass1 this code must run from
8 * cache since you can not reliably change a peripheral banks 8 * cache since you can not reliably change a peripheral banks
9 * timing register (pbxap) while running code from that bank. 9 * timing register (pbxap) while running code from that bank.
10 * For ex., since we are running from ROM on bank 0, we can NOT 10 * For ex., since we are running from ROM on bank 0, we can NOT
11 * execute the code that modifies bank 0 timings from ROM, so 11 * execute the code that modifies bank 0 timings from ROM, so
12 * we run it from cache. 12 * we run it from cache.
13 * Bank 0 - Flash or Multi Purpose Socket 13 * Bank 0 - Flash or Multi Purpose Socket
14 * Bank 1 - Multi Purpose Socket or Flash (set in C-Code) 14 * Bank 1 - Multi Purpose Socket or Flash (set in C-Code)
15 * Bank 2 - UART 1 (set in C-Code) 15 * Bank 2 - UART 1 (set in C-Code)
16 * Bank 3 - UART 2 (set in C-Code) 16 * Bank 3 - UART 2 (set in C-Code)
17 * Bank 4 - not used 17 * Bank 4 - not used
18 * Bank 5 - not used 18 * Bank 5 - not used
19 * Bank 6 - not used 19 * Bank 6 - not used
20 * Bank 7 - PLD Register 20 * Bank 7 - PLD Register
21 *-----------------------------------------------------------------------------*/ 21 *-----------------------------------------------------------------------------*/
22 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 22 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
23 23
24 #include <configs/MIP405.h> 24 #include <configs/MIP405.h>
25 #include <ppc_asm.tmpl> 25 #include <ppc_asm.tmpl>
26 #include <ppc_defs.h> 26 #include <ppc_defs.h>
27 27
28 #include <asm/cache.h> 28 #include <asm/cache.h>
29 #include <asm/mmu.h> 29 #include <asm/mmu.h>
30 #include <asm/ppc4xx.h> 30 #include <asm/ppc4xx.h>
31 #include "mip405.h" 31 #include "mip405.h"
32 32
33 33
34 .globl ext_bus_cntlr_init 34 .globl ext_bus_cntlr_init
35 ext_bus_cntlr_init: 35 ext_bus_cntlr_init:
36 mflr r4 /* save link register */ 36 mflr r4 /* save link register */
37 mfdcr r3,CPC0_PSR /* get strapping reg */ 37 mfdcr r3,CPC0_PSR /* get strapping reg */
38 andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ 38 andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
39 bnelr /* jump back if PCI boot */ 39 bnelr /* jump back if PCI boot */
40 40
41 bl ..getAddr 41 bl ..getAddr
42 ..getAddr: 42 ..getAddr:
43 mflr r3 /* get address of ..getAddr */ 43 mflr r3 /* get address of ..getAddr */
44 mtlr r4 /* restore link register */ 44 mtlr r4 /* restore link register */
45 addi r4,0,14 /* set ctr to 14; used to prefetch */ 45 addi r4,0,14 /* set ctr to 14; used to prefetch */
46 mtctr r4 /* 14 cache lines to fit this function */ 46 mtctr r4 /* 14 cache lines to fit this function */
47 /* in cache (gives us 8x14=112 instrctns) */ 47 /* in cache (gives us 8x14=112 instrctns) */
48 ..ebcloop: 48 ..ebcloop:
49 icbt r0,r3 /* prefetch cache line for addr in r3 */ 49 icbt r0,r3 /* prefetch cache line for addr in r3 */
50 addi r3,r3,32 /* move to next cache line */ 50 addi r3,r3,32 /* move to next cache line */
51 bdnz ..ebcloop /* continue for 14 cache lines */ 51 bdnz ..ebcloop /* continue for 14 cache lines */
52 52
53 /*------------------------------------------------------------------- 53 /*-------------------------------------------------------------------
54 * Delay to ensure all accesses to ROM are complete before changing 54 * Delay to ensure all accesses to ROM are complete before changing
55 * bank 0 timings. 55 * bank 0 timings.
56 *------------------------------------------------------------------- */ 56 *------------------------------------------------------------------- */
57 addis r3,0,0x0 57 addis r3,0,0x0
58 ori r3,r3,0xA000 58 ori r3,r3,0xA000
59 mtctr r3 59 mtctr r3
60 ..spinlp: 60 ..spinlp:
61 bdnz ..spinlp /* spin loop */ 61 bdnz ..spinlp /* spin loop */
62 62
63 /*----------------------------------------------------------------------- 63 /*-----------------------------------------------------------------------
64 * decide boot up mode 64 * decide boot up mode
65 *----------------------------------------------------------------------- */ 65 *----------------------------------------------------------------------- */
66 addi r4,0,PB0CR 66 addi r4,0,PB0CR
67 mtdcr EBC0_CFGADDR,r4 67 mtdcr EBC0_CFGADDR,r4
68 mfdcr r4,EBC0_CFGDATA 68 mfdcr r4,EBC0_CFGDATA
69 69
70 andi. r0, r4, 0x2000 /* mask out irrelevant bits */ 70 andi. r0, r4, 0x2000 /* mask out irrelevant bits */
71 beq 0f /* jump if 8 bit bus width */ 71 beq 0f /* jump if 8 bit bus width */
72 72
73 /* setup 16 bit things 73 /* setup 16 bit things
74 *----------------------------------------------------------------------- 74 *-----------------------------------------------------------------------
75 * Memory Bank 0 (16 Bit Flash) initialization 75 * Memory Bank 0 (16 Bit Flash) initialization
76 *---------------------------------------------------------------------- */ 76 *---------------------------------------------------------------------- */
77 77
78 addi r4,0,PB1AP 78 addi r4,0,PB1AP
79 mtdcr EBC0_CFGADDR,r4 79 mtdcr EBC0_CFGADDR,r4
80 addis r4,0,(FLASH_AP_B)@h 80 addis r4,0,(FLASH_AP_B)@h
81 ori r4,r4,(FLASH_AP_B)@l 81 ori r4,r4,(FLASH_AP_B)@l
82 mtdcr EBC0_CFGDATA,r4 82 mtdcr EBC0_CFGDATA,r4
83 83
84 addi r4,0,PB0CR 84 addi r4,0,PB0CR
85 mtdcr EBC0_CFGADDR,r4 85 mtdcr EBC0_CFGADDR,r4
86 /* BS=0x010(4MB),BU=0x3(R/W), */ 86 /* BS=0x010(4MB),BU=0x3(R/W), */
87 addis r4,0,(FLASH_CR_B)@h 87 addis r4,0,(FLASH_CR_B)@h
88 ori r4,r4,(FLASH_CR_B)@l 88 ori r4,r4,(FLASH_CR_B)@l
89 mtdcr EBC0_CFGDATA,r4 89 mtdcr EBC0_CFGDATA,r4
90 b 1f 90 b 1f
91 91
92 0: 92 0:
93 93
94 /* 8Bit boot mode: */ 94 /* 8Bit boot mode: */
95 /*----------------------------------------------------------------------- 95 /*-----------------------------------------------------------------------
96 * Memory Bank 0 Multi Purpose Socket initialization 96 * Memory Bank 0 Multi Purpose Socket initialization
97 *----------------------------------------------------------------------- */ 97 *----------------------------------------------------------------------- */
98 /* 0x7F8FFE80 slowest boot */ 98 /* 0x7F8FFE80 slowest boot */
99 addi r4,0,PB1AP 99 addi r4,0,PB1AP
100 mtdcr EBC0_CFGADDR,r4 100 mtdcr EBC0_CFGADDR,r4
101 addis r4,0,(MPS_AP_B)@h 101 addis r4,0,(MPS_AP_B)@h
102 ori r4,r4,(MPS_AP_B)@l 102 ori r4,r4,(MPS_AP_B)@l
103 mtdcr EBC0_CFGDATA,r4 103 mtdcr EBC0_CFGDATA,r4
104 104
105 addi r4,0,PB0CR 105 addi r4,0,PB0CR
106 mtdcr EBC0_CFGADDR,r4 106 mtdcr EBC0_CFGADDR,r4
107 /* BS=0x010(4MB),BU=0x3(R/W), */ 107 /* BS=0x010(4MB),BU=0x3(R/W), */
108 addis r4,0,(MPS_CR_B)@h 108 addis r4,0,(MPS_CR_B)@h
109 ori r4,r4,(MPS_CR_B)@l 109 ori r4,r4,(MPS_CR_B)@l
110 110
111 mtdcr EBC0_CFGDATA,r4 111 mtdcr EBC0_CFGDATA,r4
112 112
113 113
114 1: 114 1:
115 /*----------------------------------------------------------------------- 115 /*-----------------------------------------------------------------------
116 * Memory Bank 2-3-4-5-6 (not used) initialization 116 * Memory Bank 2-3-4-5-6 (not used) initialization
117 *-----------------------------------------------------------------------*/ 117 *-----------------------------------------------------------------------*/
118 addi r4,0,PB1CR 118 addi r4,0,PB1CR
119 mtdcr EBC0_CFGADDR,r4 119 mtdcr EBC0_CFGADDR,r4
120 addis r4,0,0x0000 120 addis r4,0,0x0000
121 ori r4,r4,0x0000 121 ori r4,r4,0x0000
122 mtdcr EBC0_CFGDATA,r4 122 mtdcr EBC0_CFGDATA,r4
123 123
124 addi r4,0,PB2CR 124 addi r4,0,PB2CR
125 mtdcr EBC0_CFGADDR,r4 125 mtdcr EBC0_CFGADDR,r4
126 addis r4,0,0x0000 126 addis r4,0,0x0000
127 ori r4,r4,0x0000 127 ori r4,r4,0x0000
128 mtdcr EBC0_CFGDATA,r4 128 mtdcr EBC0_CFGDATA,r4
129 129
130 addi r4,0,PB3CR 130 addi r4,0,PB3CR
131 mtdcr EBC0_CFGADDR,r4 131 mtdcr EBC0_CFGADDR,r4
132 addis r4,0,0x0000 132 addis r4,0,0x0000
133 ori r4,r4,0x0000 133 ori r4,r4,0x0000
134 mtdcr EBC0_CFGDATA,r4 134 mtdcr EBC0_CFGDATA,r4
135 135
136 addi r4,0,PB4CR 136 addi r4,0,PB4CR
137 mtdcr EBC0_CFGADDR,r4 137 mtdcr EBC0_CFGADDR,r4
138 addis r4,0,0x0000 138 addis r4,0,0x0000
139 ori r4,r4,0x0000 139 ori r4,r4,0x0000
140 mtdcr EBC0_CFGDATA,r4 140 mtdcr EBC0_CFGDATA,r4
141 141
142 addi r4,0,PB5CR 142 addi r4,0,PB5CR
143 mtdcr EBC0_CFGADDR,r4 143 mtdcr EBC0_CFGADDR,r4
144 addis r4,0,0x0000 144 addis r4,0,0x0000
145 ori r4,r4,0x0000 145 ori r4,r4,0x0000
146 mtdcr EBC0_CFGDATA,r4 146 mtdcr EBC0_CFGDATA,r4
147 147
148 addi r4,0,PB6CR 148 addi r4,0,PB6CR
149 mtdcr EBC0_CFGADDR,r4 149 mtdcr EBC0_CFGADDR,r4
150 addis r4,0,0x0000 150 addis r4,0,0x0000
151 ori r4,r4,0x0000 151 ori r4,r4,0x0000
152 mtdcr EBC0_CFGDATA,r4 152 mtdcr EBC0_CFGDATA,r4
153 153
154 addi r4,0,PB7CR 154 addi r4,0,PB7CR
155 mtdcr EBC0_CFGADDR,r4 155 mtdcr EBC0_CFGADDR,r4
156 addis r4,0,0x0000 156 addis r4,0,0x0000
157 ori r4,r4,0x0000 157 ori r4,r4,0x0000
158 mtdcr EBC0_CFGDATA,r4 158 mtdcr EBC0_CFGDATA,r4
159 nop /* pass2 DCR errata #8 */ 159 nop /* pass2 DCR errata #8 */
160 blr 160 blr
161 161
162 #if defined(CONFIG_BOOT_PCI) 162 #if defined(CONFIG_BOOT_PCI)
163 .section .bootpg,"ax" 163 .section .bootpg,"ax"
164 .globl _start_pci 164 .globl _start_pci
165 /******************************************* 165 /*******************************************
166 */ 166 */
167 167
168 _start_pci: 168 _start_pci:
169 /* first handle errata #68 / PCI_18 */ 169 /* first handle errata #68 / PCI_18 */
170 iccci r0, r0 /* invalidate I-cache */ 170 iccci r0, r0 /* invalidate I-cache */
171 lis r31, 0 171 lis r31, 0
172 mticcr r31 /* ICCR = 0 (all uncachable) */ 172 mticcr r31 /* ICCR = 0 (all uncachable) */
173 isync 173 isync
174 174
175 mfccr0 r28 /* set CCR0[24] = 1 */ 175 mfccr0 r28 /* set CCR0[24] = 1 */
176 ori r28, r28, 0x0080 176 ori r28, r28, 0x0080
177 mtccr0 r28 177 mtccr0 r28
178 178
179 /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ 179 /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
180 lis r28, 0xEF40 180 lis r28, 0xEF40
181 addi r28, r28, 0x0004 181 addi r28, r28, 0x0004
182 stw r31, 0x0C(r28) /* clear PMM0PCIHA */ 182 stw r31, 0x0C(r28) /* clear PMM0PCIHA */
183 lis r29, 0xFFF8 /* open 512 kByte */ 183 lis r29, 0xFFF8 /* open 512 kByte */
184 addi r29, r29, 0x0001/* and enable this region */ 184 addi r29, r29, 0x0001/* and enable this region */
185 stwbrx r29, r0, r28 /* write PMM0MA */ 185 stwbrx r29, r0, r28 /* write PMM0MA */
186 186
187 lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ 187 lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
188 addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ 188 addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
189 189
190 lis r31, 0x8000 /* set en bit bus 0 */ 190 lis r31, 0x8000 /* set en bit bus 0 */
191 ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ 191 ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
192 stwbrx r31, r0, r28 /* write it */ 192 stwbrx r31, r0, r28 /* write it */
193 193
194 lwbrx r31, r0, r29 /* load XBCS register */ 194 lwbrx r31, r0, r29 /* load XBCS register */
195 oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ 195 oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
196 stwbrx r31, r0, r29 /* write back XBCS register */ 196 stwbrx r31, r0, r29 /* write back XBCS register */
197 197
198 nop 198 nop
199 nop 199 nop
200 b _start /* normal start */ 200 b _start /* normal start */
201 #endif 201 #endif
202 202
board/mpl/pip405/init.S
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 /*----------------------------------------------------------------------------- 4 /*-----------------------------------------------------------------------------
5 * Function: ext_bus_cntlr_init 5 * Function: ext_bus_cntlr_init
6 * Description: Initializes the External Bus Controller for the external 6 * Description: Initializes the External Bus Controller for the external
7 * peripherals. IMPORTANT: For pass1 this code must run from 7 * peripherals. IMPORTANT: For pass1 this code must run from
8 * cache since you can not reliably change a peripheral banks 8 * cache since you can not reliably change a peripheral banks
9 * timing register (pbxap) while running code from that bank. 9 * timing register (pbxap) while running code from that bank.
10 * For ex., since we are running from ROM on bank 0, we can NOT 10 * For ex., since we are running from ROM on bank 0, we can NOT
11 * execute the code that modifies bank 0 timings from ROM, so 11 * execute the code that modifies bank 0 timings from ROM, so
12 * we run it from cache. 12 * we run it from cache.
13 * Bank 0 - Flash or Multi Purpose Socket 13 * Bank 0 - Flash or Multi Purpose Socket
14 * Bank 1 - Multi Purpose Socket or Flash 14 * Bank 1 - Multi Purpose Socket or Flash
15 * Bank 2 - not used 15 * Bank 2 - not used
16 * Bank 3 - not used 16 * Bank 3 - not used
17 * Bank 4 - not used 17 * Bank 4 - not used
18 * Bank 5 - not used 18 * Bank 5 - not used
19 * Bank 6 - used to switch on the 12V for the Multipurpose socket 19 * Bank 6 - used to switch on the 12V for the Multipurpose socket
20 * Bank 7 - Config Register 20 * Bank 7 - Config Register
21 *-----------------------------------------------------------------------------*/ 21 *-----------------------------------------------------------------------------*/
22 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 22 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
23 23
24 #include <configs/PIP405.h> 24 #include <configs/PIP405.h>
25 #include <ppc_asm.tmpl> 25 #include <ppc_asm.tmpl>
26 #include <ppc_defs.h> 26 #include <ppc_defs.h>
27 27
28 #include <asm/cache.h> 28 #include <asm/cache.h>
29 #include <asm/mmu.h> 29 #include <asm/mmu.h>
30 #include <asm/ppc4xx.h> 30 #include <asm/ppc4xx.h>
31 #include "pip405.h" 31 #include "pip405.h"
32 32
33 .globl ext_bus_cntlr_init 33 .globl ext_bus_cntlr_init
34 ext_bus_cntlr_init: 34 ext_bus_cntlr_init:
35 mflr r4 /* save link register */ 35 mflr r4 /* save link register */
36 mfdcr r3,CPC0_PSR /* get strapping reg */ 36 mfdcr r3,CPC0_PSR /* get strapping reg */
37 andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */ 37 andi. r0, r3, PSR_ROM_LOC /* mask out irrelevant bits */
38 bnelr /* jump back if PCI boot */ 38 bnelr /* jump back if PCI boot */
39 39
40 bl ..getAddr 40 bl ..getAddr
41 ..getAddr: 41 ..getAddr:
42 mflr r3 /* get address of ..getAddr */ 42 mflr r3 /* get address of ..getAddr */
43 mtlr r4 /* restore link register */ 43 mtlr r4 /* restore link register */
44 addi r4,0,14 /* set ctr to 14; used to prefetch */ 44 addi r4,0,14 /* set ctr to 14; used to prefetch */
45 mtctr r4 /* 14 cache lines to fit this function */ 45 mtctr r4 /* 14 cache lines to fit this function */
46 /* in cache (gives us 8x14=112 instrctns) */ 46 /* in cache (gives us 8x14=112 instrctns) */
47 ..ebcloop: 47 ..ebcloop:
48 icbt r0,r3 /* prefetch cache line for addr in r3 */ 48 icbt r0,r3 /* prefetch cache line for addr in r3 */
49 addi r3,r3,32 /* move to next cache line */ 49 addi r3,r3,32 /* move to next cache line */
50 bdnz ..ebcloop /* continue for 14 cache lines */ 50 bdnz ..ebcloop /* continue for 14 cache lines */
51 51
52 /*------------------------------------------------------------------- 52 /*-------------------------------------------------------------------
53 * Delay to ensure all accesses to ROM are complete before changing 53 * Delay to ensure all accesses to ROM are complete before changing
54 * bank 0 timings. 54 * bank 0 timings.
55 *------------------------------------------------------------------- */ 55 *------------------------------------------------------------------- */
56 addis r3,0,0x0 56 addis r3,0,0x0
57 ori r3,r3,0xA000 57 ori r3,r3,0xA000
58 mtctr r3 58 mtctr r3
59 ..spinlp: 59 ..spinlp:
60 bdnz ..spinlp /* spin loop */ 60 bdnz ..spinlp /* spin loop */
61 61
62 /*----------------------------------------------------------------------- 62 /*-----------------------------------------------------------------------
63 * decide boot up mode 63 * decide boot up mode
64 *----------------------------------------------------------------------- */ 64 *----------------------------------------------------------------------- */
65 addi r4,0,PB0CR 65 addi r4,0,PB0CR
66 mtdcr EBC0_CFGADDR,r4 66 mtdcr EBC0_CFGADDR,r4
67 mfdcr r4,EBC0_CFGDATA 67 mfdcr r4,EBC0_CFGDATA
68 68
69 andi. r0, r4, 0x2000 /* mask out irrelevant bits */ 69 andi. r0, r4, 0x2000 /* mask out irrelevant bits */
70 beq 0f /* jump if 8 bit bus width */ 70 beq 0f /* jump if 8 bit bus width */
71 71
72 /* setup 16 bit things 72 /* setup 16 bit things
73 *----------------------------------------------------------------------- 73 *-----------------------------------------------------------------------
74 * Memory Bank 0 (16 Bit Flash) initialization 74 * Memory Bank 0 (16 Bit Flash) initialization
75 *---------------------------------------------------------------------- */ 75 *---------------------------------------------------------------------- */
76 76
77 addi r4,0,PB1AP 77 addi r4,0,PB1AP
78 mtdcr EBC0_CFGADDR,r4 78 mtdcr EBC0_CFGADDR,r4
79 addis r4,0,(FLASH_AP_B)@h 79 addis r4,0,(FLASH_AP_B)@h
80 ori r4,r4,(FLASH_AP_B)@l 80 ori r4,r4,(FLASH_AP_B)@l
81 mtdcr EBC0_CFGDATA,r4 81 mtdcr EBC0_CFGDATA,r4
82 82
83 addi r4,0,PB0CR 83 addi r4,0,PB0CR
84 mtdcr EBC0_CFGADDR,r4 84 mtdcr EBC0_CFGADDR,r4
85 /* BS=0x010(4MB),BU=0x3(R/W), */ 85 /* BS=0x010(4MB),BU=0x3(R/W), */
86 addis r4,0,(FLASH_CR_B)@h 86 addis r4,0,(FLASH_CR_B)@h
87 ori r4,r4,(FLASH_CR_B)@l 87 ori r4,r4,(FLASH_CR_B)@l
88 mtdcr EBC0_CFGDATA,r4 88 mtdcr EBC0_CFGDATA,r4
89 b 1f 89 b 1f
90 90
91 0: 91 0:
92 /* 8Bit boot mode: */ 92 /* 8Bit boot mode: */
93 /*----------------------------------------------------------------------- 93 /*-----------------------------------------------------------------------
94 * Memory Bank 0 Multi Purpose Socket initialization 94 * Memory Bank 0 Multi Purpose Socket initialization
95 *----------------------------------------------------------------------- */ 95 *----------------------------------------------------------------------- */
96 /* 0x7F8FFE80 slowest boot */ 96 /* 0x7F8FFE80 slowest boot */
97 addi r4,0,PB1AP 97 addi r4,0,PB1AP
98 mtdcr EBC0_CFGADDR,r4 98 mtdcr EBC0_CFGADDR,r4
99 addis r4,0,(MPS_AP_B)@h 99 addis r4,0,(MPS_AP_B)@h
100 ori r4,r4,(MPS_AP_B)@l 100 ori r4,r4,(MPS_AP_B)@l
101 mtdcr EBC0_CFGDATA,r4 101 mtdcr EBC0_CFGDATA,r4
102 102
103 addi r4,0,PB0CR 103 addi r4,0,PB0CR
104 mtdcr EBC0_CFGADDR,r4 104 mtdcr EBC0_CFGADDR,r4
105 /* BS=0x010(4MB),BU=0x3(R/W), */ 105 /* BS=0x010(4MB),BU=0x3(R/W), */
106 addis r4,0,(MPS_CR_B)@h 106 addis r4,0,(MPS_CR_B)@h
107 ori r4,r4,(MPS_CR_B)@l 107 ori r4,r4,(MPS_CR_B)@l
108 mtdcr EBC0_CFGDATA,r4 108 mtdcr EBC0_CFGDATA,r4
109 109
110 110
111 1: 111 1:
112 /*----------------------------------------------------------------------- 112 /*-----------------------------------------------------------------------
113 * Memory Bank 2-3-4-5-6 (not used) initialization 113 * Memory Bank 2-3-4-5-6 (not used) initialization
114 *-----------------------------------------------------------------------*/ 114 *-----------------------------------------------------------------------*/
115 addi r4,0,PB1CR 115 addi r4,0,PB1CR
116 mtdcr EBC0_CFGADDR,r4 116 mtdcr EBC0_CFGADDR,r4
117 addis r4,0,0x0000 117 addis r4,0,0x0000
118 ori r4,r4,0x0000 118 ori r4,r4,0x0000
119 mtdcr EBC0_CFGDATA,r4 119 mtdcr EBC0_CFGDATA,r4
120 120
121 addi r4,0,PB2CR 121 addi r4,0,PB2CR
122 mtdcr EBC0_CFGADDR,r4 122 mtdcr EBC0_CFGADDR,r4
123 addis r4,0,0x0000 123 addis r4,0,0x0000
124 ori r4,r4,0x0000 124 ori r4,r4,0x0000
125 mtdcr EBC0_CFGDATA,r4 125 mtdcr EBC0_CFGDATA,r4
126 126
127 addi r4,0,PB3CR 127 addi r4,0,PB3CR
128 mtdcr EBC0_CFGADDR,r4 128 mtdcr EBC0_CFGADDR,r4
129 addis r4,0,0x0000 129 addis r4,0,0x0000
130 ori r4,r4,0x0000 130 ori r4,r4,0x0000
131 mtdcr EBC0_CFGDATA,r4 131 mtdcr EBC0_CFGDATA,r4
132 132
133 addi r4,0,PB4CR 133 addi r4,0,PB4CR
134 mtdcr EBC0_CFGADDR,r4 134 mtdcr EBC0_CFGADDR,r4
135 addis r4,0,0x0000 135 addis r4,0,0x0000
136 ori r4,r4,0x0000 136 ori r4,r4,0x0000
137 mtdcr EBC0_CFGDATA,r4 137 mtdcr EBC0_CFGDATA,r4
138 138
139 addi r4,0,PB5CR 139 addi r4,0,PB5CR
140 mtdcr EBC0_CFGADDR,r4 140 mtdcr EBC0_CFGADDR,r4
141 addis r4,0,0x0000 141 addis r4,0,0x0000
142 ori r4,r4,0x0000 142 ori r4,r4,0x0000
143 mtdcr EBC0_CFGDATA,r4 143 mtdcr EBC0_CFGDATA,r4
144 144
145 addi r4,0,PB6CR 145 addi r4,0,PB6CR
146 mtdcr EBC0_CFGADDR,r4 146 mtdcr EBC0_CFGADDR,r4
147 addis r4,0,0x0000 147 addis r4,0,0x0000
148 ori r4,r4,0x0000 148 ori r4,r4,0x0000
149 mtdcr EBC0_CFGDATA,r4 149 mtdcr EBC0_CFGDATA,r4
150 150
151 addi r4,0,PB7CR 151 addi r4,0,PB7CR
152 mtdcr EBC0_CFGADDR,r4 152 mtdcr EBC0_CFGADDR,r4
153 addis r4,0,0x0000 153 addis r4,0,0x0000
154 ori r4,r4,0x0000 154 ori r4,r4,0x0000
155 mtdcr EBC0_CFGDATA,r4 155 mtdcr EBC0_CFGDATA,r4
156 nop /* pass2 DCR errata #8 */ 156 nop /* pass2 DCR errata #8 */
157 blr 157 blr
158 158
159 #if defined(CONFIG_BOOT_PCI) 159 #if defined(CONFIG_BOOT_PCI)
160 .section .bootpg,"ax" 160 .section .bootpg,"ax"
161 .globl _start_pci 161 .globl _start_pci
162 /******************************************* 162 /*******************************************
163 */ 163 */
164 164
165 _start_pci: 165 _start_pci:
166 /* first handle errata #68 / PCI_18 */ 166 /* first handle errata #68 / PCI_18 */
167 iccci r0, r0 /* invalidate I-cache */ 167 iccci r0, r0 /* invalidate I-cache */
168 lis r31, 0 168 lis r31, 0
169 mticcr r31 /* ICCR = 0 (all uncachable) */ 169 mticcr r31 /* ICCR = 0 (all uncachable) */
170 isync 170 isync
171 171
172 mfccr0 r28 /* set CCR0[24] = 1 */ 172 mfccr0 r28 /* set CCR0[24] = 1 */
173 ori r28, r28, 0x0080 173 ori r28, r28, 0x0080
174 mtccr0 r28 174 mtccr0 r28
175 175
176 /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */ 176 /* setup PMM0MA (0xEF400004) and PMM0PCIHA (0xEF40000C) */
177 lis r28, 0xEF40 177 lis r28, 0xEF40
178 addi r28, r28, 0x0004 178 addi r28, r28, 0x0004
179 stw r31, 0x0C(r28) /* clear PMM0PCIHA */ 179 stw r31, 0x0C(r28) /* clear PMM0PCIHA */
180 lis r29, 0xFFF8 /* open 512 kByte */ 180 lis r29, 0xFFF8 /* open 512 kByte */
181 addi r29, r29, 0x0001/* and enable this region */ 181 addi r29, r29, 0x0001/* and enable this region */
182 stwbrx r29, r0, r28 /* write PMM0MA */ 182 stwbrx r29, r0, r28 /* write PMM0MA */
183 183
184 lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */ 184 lis r28, 0xEEC0 /* address of PCIC0_CFGADDR */
185 addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */ 185 addi r29, r28, 4 /* add 4 to r29 -> PCIC0_CFGDATA */
186 186
187 lis r31, 0x8000 /* set en bit bus 0 */ 187 lis r31, 0x8000 /* set en bit bus 0 */
188 ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */ 188 ori r31, r31, 0x304C/* device 6 func 0 reg 4C (XBCS register) */
189 stwbrx r31, r0, r28 /* write it */ 189 stwbrx r31, r0, r28 /* write it */
190 190
191 lwbrx r31, r0, r29 /* load XBCS register */ 191 lwbrx r31, r0, r29 /* load XBCS register */
192 oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */ 192 oris r31, r31, 0x02C4/* clear BIOSCS WPE, set lower, extended and 1M extended BIOS enable */
193 stwbrx r31, r0, r29 /* write back XBCS register */ 193 stwbrx r31, r0, r29 /* write back XBCS register */
194 194
195 nop 195 nop
196 nop 196 nop
197 b _start /* normal start */ 197 b _start /* normal start */
198 #endif 198 #endif
199 199
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 #include <config.h> 4 #include <config.h>
5 #include <asm/ppc4xx.h> 5 #include <asm/ppc4xx.h>
6 6
7 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 7 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
8 8
9 #include <ppc_asm.tmpl> 9 #include <ppc_asm.tmpl>
10 #include <ppc_defs.h> 10 #include <ppc_defs.h>
11 11
12 #include <asm/cache.h> 12 #include <asm/cache.h>
13 #include <asm/mmu.h> 13 #include <asm/mmu.h>
14 14
15 /** 15 /**
16 * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals 16 * ext_bus_cntlr_init - Initializes the External Bus Controller for the external peripherals
17 * 17 *
18 * IMPORTANT: For pass1 this code must run from cache since you can not 18 * IMPORTANT: For pass1 this code must run from cache since you can not
19 * reliably change a peripheral banks timing register (pbxap) while running 19 * reliably change a peripheral banks timing register (pbxap) while running
20 * code from that bank. For ex., since we are running from ROM on bank 0, we 20 * code from that bank. For ex., since we are running from ROM on bank 0, we
21 * can NOT execute the code that modifies bank 0 timings from ROM, so 21 * can NOT execute the code that modifies bank 0 timings from ROM, so
22 * we run it from cache. 22 * we run it from cache.
23 * 23 *
24 * Bank 0 - Boot-Flash 24 * Bank 0 - Boot-Flash
25 * Bank 1 - NAND-Flash 25 * Bank 1 - NAND-Flash
26 * Bank 2 - ISA bus 26 * Bank 2 - ISA bus
27 * Bank 3 - Second Flash 27 * Bank 3 - Second Flash
28 * Bank 4 - USB controller 28 * Bank 4 - USB controller
29 */ 29 */
30 .globl ext_bus_cntlr_init 30 .globl ext_bus_cntlr_init
31 ext_bus_cntlr_init: 31 ext_bus_cntlr_init:
32 /* 32 /*
33 * We need the current boot up configuration to set correct 33 * We need the current boot up configuration to set correct
34 * timings into internal flash and external flash 34 * timings into internal flash and external flash
35 */ 35 */
36 mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx 36 mfdcr r24,CPC0_PSR /* xxxx xxxx xxxx xxx? ?xxx xxxx xxxx xxxx
37 0 0 -> 8 bit external ROM 37 0 0 -> 8 bit external ROM
38 0 1 -> 16 bit internal ROM */ 38 0 1 -> 16 bit internal ROM */
39 addi r4,0,2 39 addi r4,0,2
40 srw r24,r24,r4 /* shift right r24 two positions */ 40 srw r24,r24,r4 /* shift right r24 two positions */
41 andi. r24,r24,0x06000 41 andi. r24,r24,0x06000
42 /* 42 /*
43 * All calculations are based on 33MHz EBC clock. 43 * All calculations are based on 33MHz EBC clock.
44 * 44 *
45 * First, create a "very slow" timing (~250ns) with burst mode enabled 45 * First, create a "very slow" timing (~250ns) with burst mode enabled
46 * This is need for the external flash access 46 * This is need for the external flash access
47 */ 47 */
48 lis r25,0x0800 48 lis r25,0x0800
49 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */ 49 /* 0000 1000 0xxx 0000 0000 0010 100x xxxx = 0x03800280 */
50 ori r25,r25,0x0280 50 ori r25,r25,0x0280
51 /* 51 /*
52 * Second, create a fast timing: 52 * Second, create a fast timing:
53 * 90ns first cycle - 3 clock access 53 * 90ns first cycle - 3 clock access
54 * and 90ns burst cycle, plus 1 clock after the last access 54 * and 90ns burst cycle, plus 1 clock after the last access
55 * This is used for the internal access 55 * This is used for the internal access
56 */ 56 */
57 lis r26,0x8900 57 lis r26,0x8900
58 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */ 58 /* 1000 1001 0xxx 0000 0000 0010 100x xxxx */
59 ori r26,r26,0x0280 59 ori r26,r26,0x0280
60 /* 60 /*
61 * We can't change settings on CS# if we currently use them. 61 * We can't change settings on CS# if we currently use them.
62 * -> load a few instructions into cache and run this code from cache 62 * -> load a few instructions into cache and run this code from cache
63 */ 63 */
64 mflr r4 /* save link register */ 64 mflr r4 /* save link register */
65 bl ..getAddr 65 bl ..getAddr
66 ..getAddr: 66 ..getAddr:
67 mflr r3 /* get address of ..getAddr */ 67 mflr r3 /* get address of ..getAddr */
68 mtlr r4 /* restore link register */ 68 mtlr r4 /* restore link register */
69 addi r4,0,14 /* set ctr to 10; used to prefetch */ 69 addi r4,0,14 /* set ctr to 10; used to prefetch */
70 mtctr r4 /* 10 cache lines to fit this function 70 mtctr r4 /* 10 cache lines to fit this function
71 in cache (gives us 8x10=80 instructions) */ 71 in cache (gives us 8x10=80 instructions) */
72 ..ebcloop: 72 ..ebcloop:
73 icbt r0,r3 /* prefetch cache line for addr in r3 */ 73 icbt r0,r3 /* prefetch cache line for addr in r3 */
74 addi r3,r3,32 /* move to next cache line */ 74 addi r3,r3,32 /* move to next cache line */
75 bdnz ..ebcloop /* continue for 10 cache lines */ 75 bdnz ..ebcloop /* continue for 10 cache lines */
76 /* 76 /*
77 * Delay to ensure all accesses to ROM are complete before changing 77 * Delay to ensure all accesses to ROM are complete before changing
78 * bank 0 timings. 200usec should be enough. 78 * bank 0 timings. 200usec should be enough.
79 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles 79 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
80 */ 80 */
81 lis r3,0x0 81 lis r3,0x0
82 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */ 82 ori r3,r3,0xA000 /* ensure 200usec have passed since reset */
83 mtctr r3 83 mtctr r3
84 ..spinlp: 84 ..spinlp:
85 bdnz ..spinlp /* spin loop */ 85 bdnz ..spinlp /* spin loop */
86 86
87 /*----------------------------------------------------------------------- 87 /*-----------------------------------------------------------------------
88 * Memory Bank 0 (BOOT-ROM) initialization 88 * Memory Bank 0 (BOOT-ROM) initialization
89 * 0xFFEF00000....0xFFFFFFF 89 * 0xFFEF00000....0xFFFFFFF
90 * We only have to change the timing. Mapping is ok by boot-strapping 90 * We only have to change the timing. Mapping is ok by boot-strapping
91 *----------------------------------------------------------------------- */ 91 *----------------------------------------------------------------------- */
92 92
93 li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */ 93 li r4,PB1AP /* PB0AP=Peripheral Bank 0 Access Parameters */
94 mtdcr EBC0_CFGADDR,r4 94 mtdcr EBC0_CFGADDR,r4
95 95
96 mr r4,r26 /* assume internal fast flash is boot flash */ 96 mr r4,r26 /* assume internal fast flash is boot flash */
97 cmpwi r24,0x2000 /* assumption true? ... */ 97 cmpwi r24,0x2000 /* assumption true? ... */
98 beq 1f /* ...yes! */ 98 beq 1f /* ...yes! */
99 mr r4,r25 /* ...no, use the slow variant */ 99 mr r4,r25 /* ...no, use the slow variant */
100 mr r25,r26 /* use this for the other flash */ 100 mr r25,r26 /* use this for the other flash */
101 1: 101 1:
102 mtdcr EBC0_CFGDATA,r4 /* change timing now */ 102 mtdcr EBC0_CFGDATA,r4 /* change timing now */
103 103
104 li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */ 104 li r4,PB0CR /* PB0CR=Peripheral Bank 0 Control Register */
105 mtdcr EBC0_CFGADDR,r4 105 mtdcr EBC0_CFGADDR,r4
106 mfdcr r4,EBC0_CFGDATA 106 mfdcr r4,EBC0_CFGDATA
107 lis r3,0x0001 107 lis r3,0x0001
108 ori r3,r3,0x8000 /* allow reads and writes */ 108 ori r3,r3,0x8000 /* allow reads and writes */
109 or r4,r4,r3 109 or r4,r4,r3
110 mtdcr EBC0_CFGDATA,r4 110 mtdcr EBC0_CFGDATA,r4
111 111
112 /*----------------------------------------------------------------------- 112 /*-----------------------------------------------------------------------
113 * Memory Bank 3 (Second-Flash) initialization 113 * Memory Bank 3 (Second-Flash) initialization
114 * 0xF0000000...0xF01FFFFF -> 2MB 114 * 0xF0000000...0xF01FFFFF -> 2MB
115 *----------------------------------------------------------------------- */ 115 *----------------------------------------------------------------------- */
116 116
117 li r4,PB3AP /* Peripheral Bank 1 Access Parameter */ 117 li r4,PB3AP /* Peripheral Bank 1 Access Parameter */
118 mtdcr EBC0_CFGADDR,r4 118 mtdcr EBC0_CFGADDR,r4
119 mtdcr EBC0_CFGDATA,r2 /* change timing */ 119 mtdcr EBC0_CFGDATA,r2 /* change timing */
120 120
121 li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */ 121 li r4,PB3CR /* Peripheral Bank 1 Configuration Registers */
122 mtdcr EBC0_CFGADDR,r4 122 mtdcr EBC0_CFGADDR,r4
123 123
124 lis r4,0xF003 124 lis r4,0xF003
125 ori r4,r4,0x8000 125 ori r4,r4,0x8000
126 /* 126 /*
127 * Consider boot configuration 127 * Consider boot configuration
128 */ 128 */
129 xori r24,r24,0x2000 /* invert current bus width */ 129 xori r24,r24,0x2000 /* invert current bus width */
130 or r4,r4,r24 130 or r4,r4,r24
131 mtdcr EBC0_CFGDATA,r4 131 mtdcr EBC0_CFGDATA,r4
132 132
133 /*----------------------------------------------------------------------- 133 /*-----------------------------------------------------------------------
134 * Memory Bank 1 (NAND-Flash) initialization 134 * Memory Bank 1 (NAND-Flash) initialization
135 * 0x77D00000...0x77DFFFFF -> 1MB 135 * 0x77D00000...0x77DFFFFF -> 1MB
136 * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns 136 * - the write/read pulse to the NAND can be as short as 25ns, bus the cycle time is always 50ns
137 * - the setup time is 0ns 137 * - the setup time is 0ns
138 * - the hold time is 15ns 138 * - the hold time is 15ns
139 * -> 139 * ->
140 * - TWT = 0 140 * - TWT = 0
141 * - CSN = 0 141 * - CSN = 0
142 * - OEN = 0 142 * - OEN = 0
143 * - WBN = 0 143 * - WBN = 0
144 * - WBF = 0 144 * - WBF = 0
145 * - TH = 1 145 * - TH = 1
146 * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold) 146 * ----> 2 clocks per cycle = 60ns cycle (30ns active, 30ns hold)
147 *----------------------------------------------------------------------- */ 147 *----------------------------------------------------------------------- */
148 148
149 li r4,PB1AP /* Peripheral Bank 1 Access Parameter */ 149 li r4,PB1AP /* Peripheral Bank 1 Access Parameter */
150 mtdcr EBC0_CFGADDR,r4 150 mtdcr EBC0_CFGADDR,r4
151 151
152 lis r4,0x0000 152 lis r4,0x0000
153 ori r4,r4,0x0200 153 ori r4,r4,0x0200
154 mtdcr EBC0_CFGDATA,r4 154 mtdcr EBC0_CFGDATA,r4
155 155
156 li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */ 156 li r4,PB1CR /* Peripheral Bank 1 Configuration Registers */
157 mtdcr EBC0_CFGADDR,r4 157 mtdcr EBC0_CFGADDR,r4
158 158
159 lis r4,0x77D1 159 lis r4,0x77D1
160 ori r4,r4,0x8000 160 ori r4,r4,0x8000
161 mtdcr EBC0_CFGDATA,r4 161 mtdcr EBC0_CFGDATA,r4
162 162
163 163
164 /* USB init (without acceleration) */ 164 /* USB init (without acceleration) */
165 #ifndef CONFIG_ISP1161_PRESENT 165 #ifndef CONFIG_ISP1161_PRESENT
166 li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */ 166 li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
167 mtdcr EBC0_CFGADDR,r4 167 mtdcr EBC0_CFGADDR,r4
168 lis r4,0x0180 168 lis r4,0x0180
169 ori r4,r4,0x5940 169 ori r4,r4,0x5940
170 mtdcr EBC0_CFGDATA,r4 170 mtdcr EBC0_CFGDATA,r4
171 #endif 171 #endif
172 172
173 /*----------------------------------------------------------------------- 173 /*-----------------------------------------------------------------------
174 * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7) 174 * Memory Bank 2 (ISA Access) initialization (plus memory bank 6 and 7)
175 * 0x78000000...0x7BFFFFFF -> 64 MB 175 * 0x78000000...0x7BFFFFFF -> 64 MB
176 * Wir arbeiten bei 33 MHz -> 30ns 176 * Wir arbeiten bei 33 MHz -> 30ns
177 *----------------------------------------------------------------------- 177 *-----------------------------------------------------------------------
178 178
179 A7 (ppc notation) or A24 (standard notation) decides about 179 A7 (ppc notation) or A24 (standard notation) decides about
180 the type of access: 180 the type of access:
181 A7/A24=0 -> memory cycle 181 A7/A24=0 -> memory cycle
182 A7/ /A24=1 -> I/O cycle 182 A7/ /A24=1 -> I/O cycle
183 */ 183 */
184 li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */ 184 li r4,PB2AP /* PB2AP=Peripheral Bank 2 Access Parameters */
185 mtdcr EBC0_CFGADDR,r4 185 mtdcr EBC0_CFGADDR,r4
186 /* 186 /*
187 We emulate an ISA access 187 We emulate an ISA access
188 188
189 1. Address active 189 1. Address active
190 2. wait 0 EBC clocks -> CSN=0 190 2. wait 0 EBC clocks -> CSN=0
191 3. set CS# 191 3. set CS#
192 4. wait 0 EBC clock -> OEN/WBN=0 192 4. wait 0 EBC clock -> OEN/WBN=0
193 5. set OE#/WE# 193 5. set OE#/WE#
194 6. wait 4 clocks (ca. 90ns) and for Ready signal 194 6. wait 4 clocks (ca. 90ns) and for Ready signal
195 7. hold for 4 clocks -> TH=4 195 7. hold for 4 clocks -> TH=4
196 */ 196 */
197 197
198 #if 1 198 #if 1
199 /* faster access to isa-bus */ 199 /* faster access to isa-bus */
200 lis r4,0x0180 200 lis r4,0x0180
201 ori r4,r4,0x5940 201 ori r4,r4,0x5940
202 #else 202 #else
203 lis r4,0x0100 203 lis r4,0x0100
204 ori r4,r4,0x0340 204 ori r4,r4,0x0340
205 #endif 205 #endif
206 mtdcr EBC0_CFGDATA,r4 206 mtdcr EBC0_CFGDATA,r4
207 207
208 #ifdef IDE_USES_ISA_EMULATION 208 #ifdef IDE_USES_ISA_EMULATION
209 li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */ 209 li r25,PB5AP /* PB5AP=Peripheral Bank 5 Access Parameters */
210 mtdcr EBC0_CFGADDR,r25 210 mtdcr EBC0_CFGADDR,r25
211 mtdcr EBC0_CFGDATA,r4 211 mtdcr EBC0_CFGDATA,r4
212 #endif 212 #endif
213 213
214 li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */ 214 li r25,PB6AP /* PB6AP=Peripheral Bank 6 Access Parameters */
215 mtdcr EBC0_CFGADDR,r25 215 mtdcr EBC0_CFGADDR,r25
216 mtdcr EBC0_CFGDATA,r4 216 mtdcr EBC0_CFGDATA,r4
217 li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */ 217 li r25,PB7AP /* PB7AP=Peripheral Bank 7 Access Parameters */
218 mtdcr EBC0_CFGADDR,r25 218 mtdcr EBC0_CFGADDR,r25
219 mtdcr EBC0_CFGDATA,r4 219 mtdcr EBC0_CFGDATA,r4
220 220
221 li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */ 221 li r25,PB2CR /* PB2CR=Peripheral Bank 2 Configuration Register */
222 mtdcr EBC0_CFGADDR,r25 222 mtdcr EBC0_CFGADDR,r25
223 223
224 lis r4,0x780B 224 lis r4,0x780B
225 ori r4,r4,0xA000 225 ori r4,r4,0xA000
226 mtdcr EBC0_CFGDATA,r4 226 mtdcr EBC0_CFGDATA,r4
227 /* 227 /*
228 * the other areas are only 1MiB in size 228 * the other areas are only 1MiB in size
229 */ 229 */
230 lis r4,0x7401 230 lis r4,0x7401
231 ori r4,r4,0xA000 231 ori r4,r4,0xA000
232 232
233 li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */ 233 li r25,PB6CR /* PB6CR=Peripheral Bank 6 Configuration Register */
234 mtdcr EBC0_CFGADDR,r25 234 mtdcr EBC0_CFGADDR,r25
235 lis r4,0x7401 235 lis r4,0x7401
236 ori r4,r4,0xA000 236 ori r4,r4,0xA000
237 mtdcr EBC0_CFGDATA,r4 237 mtdcr EBC0_CFGDATA,r4
238 238
239 li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */ 239 li r25,PB7CR /* PB7CR=Peripheral Bank 7 Configuration Register */
240 mtdcr EBC0_CFGADDR,r25 240 mtdcr EBC0_CFGADDR,r25
241 lis r4,0x7411 241 lis r4,0x7411
242 ori r4,r4,0xA000 242 ori r4,r4,0xA000
243 mtdcr EBC0_CFGDATA,r4 243 mtdcr EBC0_CFGDATA,r4
244 244
245 #ifndef CONFIG_ISP1161_PRESENT 245 #ifndef CONFIG_ISP1161_PRESENT
246 li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */ 246 li r25,PB4CR /* PB4CR=Peripheral Bank 4 Configuration Register */
247 mtdcr EBC0_CFGADDR,r25 247 mtdcr EBC0_CFGADDR,r25
248 lis r4,0x7421 248 lis r4,0x7421
249 ori r4,r4,0xA000 249 ori r4,r4,0xA000
250 mtdcr EBC0_CFGDATA,r4 250 mtdcr EBC0_CFGDATA,r4
251 #endif 251 #endif
252 #ifdef IDE_USES_ISA_EMULATION 252 #ifdef IDE_USES_ISA_EMULATION
253 li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */ 253 li r25,PB5CR /* PB5CR=Peripheral Bank 5 Configuration Register */
254 mtdcr EBC0_CFGADDR,r25 254 mtdcr EBC0_CFGADDR,r25
255 lis r4,0x0000 255 lis r4,0x0000
256 ori r4,r4,0x0000 256 ori r4,r4,0x0000
257 mtdcr EBC0_CFGDATA,r4 257 mtdcr EBC0_CFGDATA,r4
258 #endif 258 #endif
259 259
260 /*----------------------------------------------------------------------- 260 /*-----------------------------------------------------------------------
261 * Memory bank 4: USB controller Philips ISP6111 261 * Memory bank 4: USB controller Philips ISP6111
262 * 0x77C00000 ... 0x77CFFFFF 262 * 0x77C00000 ... 0x77CFFFFF
263 * 263 *
264 * The chip is connected to: 264 * The chip is connected to:
265 * - CPU CS#4 265 * - CPU CS#4
266 * - CPU IRQ#2 266 * - CPU IRQ#2
267 * - CPU DMA 3 267 * - CPU DMA 3
268 * 268 *
269 * Timing: 269 * Timing:
270 * - command to first data: 300ns. Software must ensure this timing! 270 * - command to first data: 300ns. Software must ensure this timing!
271 * - Write pulse: 26ns 271 * - Write pulse: 26ns
272 * - Read pulse: 33ns 272 * - Read pulse: 33ns
273 * - read cycle time: 150ns 273 * - read cycle time: 150ns
274 * - write cycle time: 140ns 274 * - write cycle time: 140ns
275 * 275 *
276 * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns 276 * Note: All calculations are based on 33MHz EBC clock. One '#' or '_' is 30ns
277 * 277 *
278 * |- 300ns --| 278 * |- 300ns --|
279 * |---- 420ns ---|---- 420ns ---| cycle 279 * |---- 420ns ---|---- 420ns ---| cycle
280 * CS ############:###____#######:###____####### 280 * CS ############:###____#######:###____#######
281 * OE ############:####___#######:####___####### 281 * OE ############:####___#######:####___#######
282 * WE ############:####__########:####__######## 282 * WE ############:####__########:####__########
283 * 283 *
284 * ----> 2 clocks RD/WR pulses: 60ns 284 * ----> 2 clocks RD/WR pulses: 60ns
285 * ----> CSN: 3 clock, 90ns 285 * ----> CSN: 3 clock, 90ns
286 * ----> OEN: 1 clocks (read cycle) 286 * ----> OEN: 1 clocks (read cycle)
287 * ----> WBN: 1 clocks (write cycle) 287 * ----> WBN: 1 clocks (write cycle)
288 * ----> WBE: 2 clocks 288 * ----> WBE: 2 clocks
289 * ----> TH: 7 clock, 210ns 289 * ----> TH: 7 clock, 210ns
290 * ----> TWT: 7 clocks 290 * ----> TWT: 7 clocks
291 *----------------------------------------------------------------------- */ 291 *----------------------------------------------------------------------- */
292 292
293 #ifdef CONFIG_ISP1161_PRESENT 293 #ifdef CONFIG_ISP1161_PRESENT
294 294
295 li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */ 295 li r4,PB4AP /* PB4AP=Peripheral Bank 4 Access Parameters */
296 mtdcr EBC0_CFGADDR,r4 296 mtdcr EBC0_CFGADDR,r4
297 297
298 lis r4,0x030D 298 lis r4,0x030D
299 ori r4,r4,0x5E80 299 ori r4,r4,0x5E80
300 mtdcr EBC0_CFGDATA,r4 300 mtdcr EBC0_CFGDATA,r4
301 301
302 li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */ 302 li r4,PB4CR /* PB2CR=Peripheral Bank 4 Configuration Register */
303 mtdcr EBC0_CFGADDR,r4 303 mtdcr EBC0_CFGADDR,r4
304 304
305 lis r4,0x77C1 305 lis r4,0x77C1
306 ori r4,r4,0xA000 306 ori r4,r4,0xA000
307 mtdcr EBC0_CFGDATA,r4 307 mtdcr EBC0_CFGDATA,r4
308 308
309 #endif 309 #endif
310 310
311 #ifndef IDE_USES_ISA_EMULATION 311 #ifndef IDE_USES_ISA_EMULATION
312 312
313 /*----------------------------------------------------------------------- 313 /*-----------------------------------------------------------------------
314 * Memory Bank 5 used for IDE access 314 * Memory Bank 5 used for IDE access
315 * 315 *
316 * Timings for IDE Interface 316 * Timings for IDE Interface
317 * 317 *
318 * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time 318 * SETUP / LENGTH / HOLD - cycles valid for 33.3 MHz clk -> 30ns cycle time
319 * 70 165 30 PIO-Mode 0, [ns] 319 * 70 165 30 PIO-Mode 0, [ns]
320 * 3 6 1 [Cycles] ----> AP=0x040C0200 320 * 3 6 1 [Cycles] ----> AP=0x040C0200
321 * 50 125 20 PIO-Mode 1, [ns] 321 * 50 125 20 PIO-Mode 1, [ns]
322 * 2 5 1 [Cycles] ----> AP=0x03080200 322 * 2 5 1 [Cycles] ----> AP=0x03080200
323 * 30 100 15 PIO-Mode 2, [ns] 323 * 30 100 15 PIO-Mode 2, [ns]
324 * 1 4 1 [Cycles] ----> AP=0x02040200 324 * 1 4 1 [Cycles] ----> AP=0x02040200
325 * 30 80 10 PIO-Mode 3, [ns] 325 * 30 80 10 PIO-Mode 3, [ns]
326 * 1 3 1 [Cycles] ----> AP=0x01840200 326 * 1 3 1 [Cycles] ----> AP=0x01840200
327 * 25 70 10 PIO-Mode 4, [ns] 327 * 25 70 10 PIO-Mode 4, [ns]
328 * 1 3 1 [Cycles] ----> AP=0x01840200 328 * 1 3 1 [Cycles] ----> AP=0x01840200
329 * 329 *
330 *----------------------------------------------------------------------- */ 330 *----------------------------------------------------------------------- */
331 331
332 li r4,PB5AP 332 li r4,PB5AP
333 mtdcr EBC0_CFGADDR,r4 333 mtdcr EBC0_CFGADDR,r4
334 lis r4,0x040C 334 lis r4,0x040C
335 ori r4,r4,0x0200 335 ori r4,r4,0x0200
336 mtdcr EBC0_CFGDATA,r4 336 mtdcr EBC0_CFGDATA,r4
337 337
338 li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */ 338 li r4,PB5CR /* PB2CR=Peripheral Bank 2 Configuration Register */
339 mtdcr EBC0_CFGADDR,r4 339 mtdcr EBC0_CFGADDR,r4
340 340
341 lis r4,0x7A01 341 lis r4,0x7A01
342 ori r4,r4,0xA000 342 ori r4,r4,0xA000
343 mtdcr EBC0_CFGDATA,r4 343 mtdcr EBC0_CFGDATA,r4
344 #endif 344 #endif
345 /* 345 /*
346 * External Peripheral Control Register 346 * External Peripheral Control Register
347 */ 347 */
348 li r4,EBC0_CFG 348 li r4,EBC0_CFG
349 mtdcr EBC0_CFGADDR,r4 349 mtdcr EBC0_CFGADDR,r4
350 350
351 lis r4,0xB84E 351 lis r4,0xB84E
352 ori r4,r4,0xF000 352 ori r4,r4,0xF000
353 mtdcr EBC0_CFGDATA,r4 353 mtdcr EBC0_CFGDATA,r4
354 /* 354 /*
355 * drive POST code 355 * drive POST code
356 */ 356 */
357 lis r4,0x7900 357 lis r4,0x7900
358 ori r4,r4,0x0080 358 ori r4,r4,0x0080
359 li r3,0x0001 359 li r3,0x0001
360 stb r3,0(r4) /* 01 -> external bus controller is initialized */ 360 stb r3,0(r4) /* 01 -> external bus controller is initialized */
361 nop /* pass2 DCR errata #8 */ 361 nop /* pass2 DCR errata #8 */
362 blr 362 blr
363 363
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 #include <config.h> 4 #include <config.h>
5 #include <asm/ppc4xx.h> 5 #include <asm/ppc4xx.h>
6 6
7 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ 7 #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
8 8
9 #include <ppc_asm.tmpl> 9 #include <ppc_asm.tmpl>
10 #include <ppc_defs.h> 10 #include <ppc_defs.h>
11 11
12 #include <asm/cache.h> 12 #include <asm/cache.h>
13 #include <asm/mmu.h> 13 #include <asm/mmu.h>
14 14
15 /****************************************************************************** 15 /******************************************************************************
16 * Function: ext_bus_cntlr_init 16 * Function: ext_bus_cntlr_init
17 * 17 *
18 * Description: Configures EBC Controller and a few basic chip selects. 18 * Description: Configures EBC Controller and a few basic chip selects.
19 * 19 *
20 * CS0 is setup to get the Boot Flash out of the addresss range 20 * CS0 is setup to get the Boot Flash out of the addresss range
21 * so that we may setup a stack. CS7 is setup so that we can 21 * so that we may setup a stack. CS7 is setup so that we can
22 * access and reset the hardware watchdog. 22 * access and reset the hardware watchdog.
23 * 23 *
24 * IMPORTANT: For pass1 this code must run from 24 * IMPORTANT: For pass1 this code must run from
25 * cache since you can not reliably change a peripheral banks 25 * cache since you can not reliably change a peripheral banks
26 * timing register (pbxap) while running code from that bank. 26 * timing register (pbxap) while running code from that bank.
27 * For ex., since we are running from ROM on bank 0, we can NOT 27 * For ex., since we are running from ROM on bank 0, we can NOT
28 * execute the code that modifies bank 0 timings from ROM, so 28 * execute the code that modifies bank 0 timings from ROM, so
29 * we run it from cache. 29 * we run it from cache.
30 * 30 *
31 * Notes: Does NOT use the stack. 31 * Notes: Does NOT use the stack.
32 *****************************************************************************/ 32 *****************************************************************************/
33 .section ".text" 33 .section ".text"
34 .align 2 34 .align 2
35 .globl ext_bus_cntlr_init 35 .globl ext_bus_cntlr_init
36 .type ext_bus_cntlr_init, @function 36 .type ext_bus_cntlr_init, @function
37 ext_bus_cntlr_init: 37 ext_bus_cntlr_init:
38 mflr r0 38 mflr r0
39 /******************************************************************** 39 /********************************************************************
40 * Prefetch entire ext_bus_cntrl_init function into the icache. 40 * Prefetch entire ext_bus_cntrl_init function into the icache.
41 * This is necessary because we are going to change the same CS we 41 * This is necessary because we are going to change the same CS we
42 * are executing from. Otherwise a CPU lockup may occur. 42 * are executing from. Otherwise a CPU lockup may occur.
43 *******************************************************************/ 43 *******************************************************************/
44 bl ..getAddr 44 bl ..getAddr
45 ..getAddr: 45 ..getAddr:
46 mflr r3 /* get address of ..getAddr */ 46 mflr r3 /* get address of ..getAddr */
47 47
48 /* Calculate number of cache lines for this function */ 48 /* Calculate number of cache lines for this function */
49 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) 49 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
50 mtctr r4 50 mtctr r4
51 ..ebcloop: 51 ..ebcloop:
52 icbt r0, r3 /* prefetch cache line for addr in r3*/ 52 icbt r0, r3 /* prefetch cache line for addr in r3*/
53 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ 53 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
54 bdnz ..ebcloop /* continue for $CTR cache lines */ 54 bdnz ..ebcloop /* continue for $CTR cache lines */
55 55
56 /******************************************************************** 56 /********************************************************************
57 * Delay to ensure all accesses to ROM are complete before changing 57 * Delay to ensure all accesses to ROM are complete before changing
58 * bank 0 timings. 200usec should be enough. 58 * bank 0 timings. 200usec should be enough.
59 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. 59 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
60 *******************************************************************/ 60 *******************************************************************/
61 addis r3, 0, 0x0 61 addis r3, 0, 0x0
62 ori r3, r3, 0xA000 /* wait 200us from reset */ 62 ori r3, r3, 0xA000 /* wait 200us from reset */
63 mtctr r3 63 mtctr r3
64 ..spinlp: 64 ..spinlp:
65 bdnz ..spinlp /* spin loop */ 65 bdnz ..spinlp /* spin loop */
66 66
67 /******************************************************************** 67 /********************************************************************
68 * Setup External Bus Controller (EBC). 68 * Setup External Bus Controller (EBC).
69 *******************************************************************/ 69 *******************************************************************/
70 addi r3, 0, EBC0_CFG 70 addi r3, 0, EBC0_CFG
71 mtdcr EBC0_CFGADDR, r3 71 mtdcr EBC0_CFGADDR, r3
72 addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */ 72 addis r4, 0, 0xb040 /* Device base timeout = 1024 cycles */
73 ori r4, r4, 0x0 /* Drive CS with external master */ 73 ori r4, r4, 0x0 /* Drive CS with external master */
74 mtdcr EBC0_CFGDATA, r4 74 mtdcr EBC0_CFGDATA, r4
75 75
76 /******************************************************************** 76 /********************************************************************
77 * Change PCIINT signal to PerWE 77 * Change PCIINT signal to PerWE
78 *******************************************************************/ 78 *******************************************************************/
79 mfdcr r4, CPC0_CR1 79 mfdcr r4, CPC0_CR1
80 ori r4, r4, 0x4000 80 ori r4, r4, 0x4000
81 mtdcr CPC0_CR1, r4 81 mtdcr CPC0_CR1, r4
82 82
83 /******************************************************************** 83 /********************************************************************
84 * Memory Bank 0 (Flash Bank 0) initialization 84 * Memory Bank 0 (Flash Bank 0) initialization
85 *******************************************************************/ 85 *******************************************************************/
86 addi r3, 0, PB1AP 86 addi r3, 0, PB1AP
87 mtdcr EBC0_CFGADDR, r3 87 mtdcr EBC0_CFGADDR, r3
88 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h 88 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
89 ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l 89 ori r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
90 mtdcr EBC0_CFGDATA, r4 90 mtdcr EBC0_CFGDATA, r4
91 91
92 addi r3, 0, PB0CR 92 addi r3, 0, PB0CR
93 mtdcr EBC0_CFGADDR, r3 93 mtdcr EBC0_CFGADDR, r3
94 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h 94 addis r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
95 ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l 95 ori r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
96 mtdcr EBC0_CFGDATA, r4 96 mtdcr EBC0_CFGDATA, r4
97 97
98 /******************************************************************** 98 /********************************************************************
99 * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs. 99 * Memory Bank 7 LEDs - NEEDED BECAUSE OF HW WATCHDOG AND LEDs.
100 *******************************************************************/ 100 *******************************************************************/
101 addi r3, 0, PB7AP 101 addi r3, 0, PB7AP
102 mtdcr EBC0_CFGADDR, r3 102 mtdcr EBC0_CFGADDR, r3
103 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h 103 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
104 ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l 104 ori r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
105 mtdcr EBC0_CFGDATA, r4 105 mtdcr EBC0_CFGDATA, r4
106 106
107 addi r3, 0, PB7CR 107 addi r3, 0, PB7CR
108 mtdcr EBC0_CFGADDR, r3 108 mtdcr EBC0_CFGADDR, r3
109 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h 109 addis r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
110 ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l 110 ori r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
111 mtdcr EBC0_CFGDATA, r4 111 mtdcr EBC0_CFGDATA, r4
112 112
113 /* We are all done */ 113 /* We are all done */
114 mtlr r0 /* Restore link register */ 114 mtlr r0 /* Restore link register */
115 blr /* Return to calling function */ 115 blr /* Return to calling function */
116 .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init 116 .Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
117 /* end ext_bus_cntlr_init() */ 117 /* end ext_bus_cntlr_init() */
118 118
119 /****************************************************************************** 119 /******************************************************************************
120 * Function: sdram_init 120 * Function: sdram_init
121 * 121 *
122 * Description: Configures SDRAM memory banks. 122 * Description: Configures SDRAM memory banks.
123 * 123 *
124 * Serial Presence Detect, "SPD," reads the SDRAM EEPROM 124 * Serial Presence Detect, "SPD," reads the SDRAM EEPROM
125 * via the IIC bus and then configures the SDRAM memory 125 * via the IIC bus and then configures the SDRAM memory
126 * banks appropriately. If Auto Memory Configuration is 126 * banks appropriately. If Auto Memory Configuration is
127 * is not used, it is assumed that a 4MB 11x8x2, non-ECC, 127 * is not used, it is assumed that a 4MB 11x8x2, non-ECC,
128 * SDRAM is soldered down. 128 * SDRAM is soldered down.
129 * 129 *
130 * Notes: Expects that the stack is already setup. 130 * Notes: Expects that the stack is already setup.
131 *****************************************************************************/ 131 *****************************************************************************/
132 .section ".text" 132 .section ".text"
133 .align 2 133 .align 2
134 .globl sdram_init 134 .globl sdram_init
135 .type sdram_init, @function 135 .type sdram_init, @function
136 sdram_init: 136 sdram_init:
137 /* save the return info on stack */ 137 /* save the return info on stack */
138 mflr r0 /* Get link register */ 138 mflr r0 /* Get link register */
139 stwu r1, -8(r1) /* Save back chain and move SP */ 139 stwu r1, -8(r1) /* Save back chain and move SP */
140 stw r0, +12(r1) /* Save link register */ 140 stw r0, +12(r1) /* Save link register */
141 141
142 /* 142 /*
143 * First call spd_sdram to try to init SDRAM according to the 143 * First call spd_sdram to try to init SDRAM according to the
144 * contents of the SPD EEPROM. If the SPD EEPROM is blank or 144 * contents of the SPD EEPROM. If the SPD EEPROM is blank or
145 * erronious, spd_sdram returns 0 in R3. 145 * erronious, spd_sdram returns 0 in R3.
146 */ 146 */
147 li r3,0 147 li r3,0
148 bl spd_sdram 148 bl spd_sdram
149 addic. r3, r3, 0 /* Check for error, save dram size */ 149 addic. r3, r3, 0 /* Check for error, save dram size */
150 bne ..sdri_done /* If it worked, we're done... */ 150 bne ..sdri_done /* If it worked, we're done... */
151 151
152 /******************************************************************** 152 /********************************************************************
153 * If SPD detection fails, we'll default to 4MB, 11x8x2, as this 153 * If SPD detection fails, we'll default to 4MB, 11x8x2, as this
154 * is the SMALLEST SDRAM size the 405 supports. We can do this 154 * is the SMALLEST SDRAM size the 405 supports. We can do this
155 * because W7O boards have soldered on RAM, and there will always 155 * because W7O boards have soldered on RAM, and there will always
156 * be some amount present. If we were using DIMMs, we should hang 156 * be some amount present. If we were using DIMMs, we should hang
157 * the board instead, since it doesn't have any RAM to continue 157 * the board instead, since it doesn't have any RAM to continue
158 * running with. 158 * running with.
159 *******************************************************************/ 159 *******************************************************************/
160 160
161 /* 161 /*
162 * Disable memory controller to allow 162 * Disable memory controller to allow
163 * values to be changed. 163 * values to be changed.
164 */ 164 */
165 addi r3, 0, SDRAM0_CFG 165 addi r3, 0, SDRAM0_CFG
166 mtdcr SDRAM0_CFGADDR, r3 166 mtdcr SDRAM0_CFGADDR, r3
167 addis r4, 0, 0x0 167 addis r4, 0, 0x0
168 ori r4, r4, 0x0 168 ori r4, r4, 0x0
169 mtdcr SDRAM0_CFGDATA, r4 169 mtdcr SDRAM0_CFGDATA, r4
170 170
171 /* 171 /*
172 * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2 172 * Set MB0CF for ext bank 0. (0-4MB) Address Mode 5 since 11x8x2
173 * All other banks are disabled. 173 * All other banks are disabled.
174 */ 174 */
175 addi r3, 0, SDRAM0_B0CR 175 addi r3, 0, SDRAM0_B0CR
176 mtdcr SDRAM0_CFGADDR, r3 176 mtdcr SDRAM0_CFGADDR, r3
177 addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */ 177 addis r4, 0, 0x0000 /* BA=0x0, SZ=4MB */
178 ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */ 178 ori r4, r4, 0x8001 /* Mode is 5, 11x8x2or4, BE=Enabled */
179 mtdcr SDRAM0_CFGDATA, r4 179 mtdcr SDRAM0_CFGDATA, r4
180 180
181 /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */ 181 /* Clear MB1CR,MB2CR,MB3CR to turn other banks off */
182 addi r4, 0, 0 /* Zero the data reg */ 182 addi r4, 0, 0 /* Zero the data reg */
183 183
184 addi r3, r3, 4 /* Point to MB1CF reg */ 184 addi r3, r3, 4 /* Point to MB1CF reg */
185 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ 185 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
186 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ 186 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
187 187
188 addi r3, r3, 4 /* Point to MB2CF reg */ 188 addi r3, r3, 4 /* Point to MB2CF reg */
189 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ 189 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
190 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ 190 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
191 191
192 addi r3, r3, 4 /* Point to MB3CF reg */ 192 addi r3, r3, 4 /* Point to MB3CF reg */
193 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */ 193 mtdcr SDRAM0_CFGADDR, r3 /* Set the address */
194 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */ 194 mtdcr SDRAM0_CFGDATA, r4 /* Zero the reg */
195 195
196 /******************************************************************** 196 /********************************************************************
197 * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR. 197 * Set the SDRAM Timing reg, SDTR1 and the refresh timer reg, RTR.
198 * To set the appropriate timings, we assume sdram is 198 * To set the appropriate timings, we assume sdram is
199 * 100MHz (pc100 compliant). 199 * 100MHz (pc100 compliant).
200 *******************************************************************/ 200 *******************************************************************/
201 201
202 /* 202 /*
203 * Set up SDTR1 203 * Set up SDTR1
204 */ 204 */
205 addi r3, 0, SDRAM0_TR 205 addi r3, 0, SDRAM0_TR
206 mtdcr SDRAM0_CFGADDR, r3 206 mtdcr SDRAM0_CFGADDR, r3
207 addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */ 207 addis r4, 0, 0x0086 /* SDTR1 value for 100Mhz */
208 ori r4, r4, 0x400D 208 ori r4, r4, 0x400D
209 mtdcr SDRAM0_CFGDATA, r4 209 mtdcr SDRAM0_CFGDATA, r4
210 210
211 /* 211 /*
212 * Set RTR 212 * Set RTR
213 */ 213 */
214 addi r3, 0, SDRAM0_RTR 214 addi r3, 0, SDRAM0_RTR
215 mtdcr SDRAM0_CFGADDR, r3 215 mtdcr SDRAM0_CFGADDR, r3
216 addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */ 216 addis r4, 0, 0x05F0 /* RTR refresh val = 15.625ms@100Mhz */
217 mtdcr SDRAM0_CFGDATA, r4 217 mtdcr SDRAM0_CFGDATA, r4
218 218
219 /******************************************************************** 219 /********************************************************************
220 * Delay to ensure 200usec have elapsed since reset. Assume worst 220 * Delay to ensure 200usec have elapsed since reset. Assume worst
221 * case that the core is running 200Mhz: 221 * case that the core is running 200Mhz:
222 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles 222 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
223 *******************************************************************/ 223 *******************************************************************/
224 addis r3, 0, 0x0000 224 addis r3, 0, 0x0000
225 ori r3, r3, 0xA000 /* Wait 200us from reset */ 225 ori r3, r3, 0xA000 /* Wait 200us from reset */
226 mtctr r3 226 mtctr r3
227 ..spinlp2: 227 ..spinlp2:
228 bdnz ..spinlp2 /* spin loop */ 228 bdnz ..spinlp2 /* spin loop */
229 229
230 /******************************************************************** 230 /********************************************************************
231 * Set memory controller options reg, MCOPT1. 231 * Set memory controller options reg, MCOPT1.
232 *******************************************************************/ 232 *******************************************************************/
233 addi r3, 0, SDRAM0_CFG 233 addi r3, 0, SDRAM0_CFG
234 mtdcr SDRAM0_CFGADDR, r3 234 mtdcr SDRAM0_CFGADDR, r3
235 addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */ 235 addis r4, 0, 0x80E0 /* DC_EN=1,SRE=0,PME=0,MEMCHK=0 */
236 ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */ 236 ori r4, r4, 0x0000 /* REGEN=0,DRW=00,BRPF=01,ECCDD=1 */
237 mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */ 237 mtdcr SDRAM0_CFGDATA, r4 /* EMDULR=1 */
238 238
239 ..sdri_done: 239 ..sdri_done:
240 /* restore and return */ 240 /* restore and return */
241 lwz r0, +12(r1) /* Get saved link register */ 241 lwz r0, +12(r1) /* Get saved link register */
242 addi r1, r1, +8 /* Remove frame from stack */ 242 addi r1, r1, +8 /* Remove frame from stack */
243 mtlr r0 /* Restore link register */ 243 mtlr r0 /* Restore link register */
244 blr /* Return to calling function */ 244 blr /* Return to calling function */
245 .Lfe1: .size sdram_init,.Lfe1-sdram_init 245 .Lfe1: .size sdram_init,.Lfe1-sdram_init
246 /* end sdram_init() */ 246 /* end sdram_init() */
247 247
drivers/net/4xx_enet.c
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 /*-----------------------------------------------------------------------------+ 4 /*-----------------------------------------------------------------------------+
5 * 5 *
6 * File Name: enetemac.c 6 * File Name: enetemac.c
7 * 7 *
8 * Function: Device driver for the ethernet EMAC3 macro on the 405GP. 8 * Function: Device driver for the ethernet EMAC3 macro on the 405GP.
9 * 9 *
10 * Author: Mark Wisner 10 * Author: Mark Wisner
11 * 11 *
12 * Change Activity- 12 * Change Activity-
13 * 13 *
14 * Date Description of Change BY 14 * Date Description of Change BY
15 * --------- --------------------- --- 15 * --------- --------------------- ---
16 * 05-May-99 Created MKW 16 * 05-May-99 Created MKW
17 * 27-Jun-99 Clean up JWB 17 * 27-Jun-99 Clean up JWB
18 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW 18 * 16-Jul-99 Added MAL error recovery and better IP packet handling MKW
19 * 29-Jul-99 Added Full duplex support MKW 19 * 29-Jul-99 Added Full duplex support MKW
20 * 06-Aug-99 Changed names for Mal CR reg MKW 20 * 06-Aug-99 Changed names for Mal CR reg MKW
21 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW 21 * 23-Aug-99 Turned off SYE when running at 10Mbs MKW
22 * 24-Aug-99 Marked descriptor empty after call_xlc MKW 22 * 24-Aug-99 Marked descriptor empty after call_xlc MKW
23 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG 23 * 07-Sep-99 Set MAL RX buffer size reg to ENET_MAX_MTU_ALIGNED / 16 MCG
24 * to avoid chaining maximum sized packets. Push starting 24 * to avoid chaining maximum sized packets. Push starting
25 * RX descriptor address up to the next cache line boundary. 25 * RX descriptor address up to the next cache line boundary.
26 * 16-Jan-00 Added support for booting with IP of 0x0 MKW 26 * 16-Jan-00 Added support for booting with IP of 0x0 MKW
27 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the 27 * 15-Mar-00 Updated enetInit() to enable broadcast addresses in the
28 * EMAC0_RXM register. JWB 28 * EMAC0_RXM register. JWB
29 * 12-Mar-01 anne-sophie.harnois@nextream.fr 29 * 12-Mar-01 anne-sophie.harnois@nextream.fr
30 * - Variables are compatible with those already defined in 30 * - Variables are compatible with those already defined in
31 * include/net.h 31 * include/net.h
32 * - Receive buffer descriptor ring is used to send buffers 32 * - Receive buffer descriptor ring is used to send buffers
33 * to the user 33 * to the user
34 * - Info print about send/received/handled packet number if 34 * - Info print about send/received/handled packet number if
35 * INFO_405_ENET is set 35 * INFO_405_ENET is set
36 * 17-Apr-01 stefan.roese@esd-electronics.com 36 * 17-Apr-01 stefan.roese@esd-electronics.com
37 * - MAL reset in "eth_halt" included 37 * - MAL reset in "eth_halt" included
38 * - Enet speed and duplex output now in one line 38 * - Enet speed and duplex output now in one line
39 * 08-May-01 stefan.roese@esd-electronics.com 39 * 08-May-01 stefan.roese@esd-electronics.com
40 * - MAL error handling added (eth_init called again) 40 * - MAL error handling added (eth_init called again)
41 * 13-Nov-01 stefan.roese@esd-electronics.com 41 * 13-Nov-01 stefan.roese@esd-electronics.com
42 * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex 42 * - Set IST bit in EMAC0_MR1 reg upon 100MBit or full duplex
43 * 04-Jan-02 stefan.roese@esd-electronics.com 43 * 04-Jan-02 stefan.roese@esd-electronics.com
44 * - Wait for PHY auto negotiation to complete added 44 * - Wait for PHY auto negotiation to complete added
45 * 06-Feb-02 stefan.roese@esd-electronics.com 45 * 06-Feb-02 stefan.roese@esd-electronics.com
46 * - Bug fixed in waiting for auto negotiation to complete 46 * - Bug fixed in waiting for auto negotiation to complete
47 * 26-Feb-02 stefan.roese@esd-electronics.com 47 * 26-Feb-02 stefan.roese@esd-electronics.com
48 * - rx and tx buffer descriptors now allocated (no fixed address 48 * - rx and tx buffer descriptors now allocated (no fixed address
49 * used anymore) 49 * used anymore)
50 * 17-Jun-02 stefan.roese@esd-electronics.com 50 * 17-Jun-02 stefan.roese@esd-electronics.com
51 * - MAL error debug printf 'M' removed (rx de interrupt may 51 * - MAL error debug printf 'M' removed (rx de interrupt may
52 * occur upon many incoming packets with only 4 rx buffers). 52 * occur upon many incoming packets with only 4 rx buffers).
53 *-----------------------------------------------------------------------------* 53 *-----------------------------------------------------------------------------*
54 * 17-Nov-03 travis.sawyer@sandburst.com 54 * 17-Nov-03 travis.sawyer@sandburst.com
55 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports 55 * - ported from 405gp_enet.c to utilized upto 4 EMAC ports
56 * in the 440GX. This port should work with the 440GP 56 * in the 440GX. This port should work with the 440GP
57 * (2 EMACs) also 57 * (2 EMACs) also
58 * 15-Aug-05 sr@denx.de 58 * 15-Aug-05 sr@denx.de
59 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c 59 * - merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.c
60 now handling all 4xx cpu's. 60 now handling all 4xx cpu's.
61 *-----------------------------------------------------------------------------*/ 61 *-----------------------------------------------------------------------------*/
62 62
63 #include <config.h> 63 #include <config.h>
64 #include <common.h> 64 #include <common.h>
65 #include <net.h> 65 #include <net.h>
66 #include <asm/processor.h> 66 #include <asm/processor.h>
67 #include <asm/io.h> 67 #include <asm/io.h>
68 #include <asm/cache.h> 68 #include <asm/cache.h>
69 #include <asm/mmu.h> 69 #include <asm/mmu.h>
70 #include <commproc.h> 70 #include <commproc.h>
71 #include <asm/ppc4xx.h> 71 #include <asm/ppc4xx.h>
72 #include <asm/ppc4xx-emac.h> 72 #include <asm/ppc4xx-emac.h>
73 #include <asm/ppc4xx-mal.h> 73 #include <asm/ppc4xx-mal.h>
74 #include <miiphy.h> 74 #include <miiphy.h>
75 #include <malloc.h> 75 #include <malloc.h>
76 #include <linux/compiler.h> 76 #include <linux/compiler.h>
77 77
78 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII)) 78 #if !(defined(CONFIG_MII) || defined(CONFIG_CMD_MII))
79 #error "CONFIG_MII has to be defined!" 79 #error "CONFIG_MII has to be defined!"
80 #endif 80 #endif
81 81
82 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */ 82 #define EMAC_RESET_TIMEOUT 1000 /* 1000 ms reset timeout */
83 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */ 83 #define PHY_AUTONEGOTIATE_TIMEOUT 5000 /* 5000 ms autonegotiate timeout */
84 84
85 /* Ethernet Transmit and Receive Buffers */ 85 /* Ethernet Transmit and Receive Buffers */
86 /* AS.HARNOIS 86 /* AS.HARNOIS
87 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from 87 * In the same way ENET_MAX_MTU and ENET_MAX_MTU_ALIGNED are set from
88 * PKTSIZE and PKTSIZE_ALIGN (include/net.h) 88 * PKTSIZE and PKTSIZE_ALIGN (include/net.h)
89 */ 89 */
90 #define ENET_MAX_MTU PKTSIZE 90 #define ENET_MAX_MTU PKTSIZE
91 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN 91 #define ENET_MAX_MTU_ALIGNED PKTSIZE_ALIGN
92 92
93 /*-----------------------------------------------------------------------------+ 93 /*-----------------------------------------------------------------------------+
94 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal 94 * Defines for MAL/EMAC interrupt conditions as reported in the UIC (Universal
95 * Interrupt Controller). 95 * Interrupt Controller).
96 *-----------------------------------------------------------------------------*/ 96 *-----------------------------------------------------------------------------*/
97 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS)) 97 #define ETH_IRQ_NUM(dev) (VECNUM_ETH0 + ((dev) * VECNUM_ETH1_OFFS))
98 98
99 #if defined(CONFIG_HAS_ETH3) 99 #if defined(CONFIG_HAS_ETH3)
100 #if !defined(CONFIG_440GX) 100 #if !defined(CONFIG_440GX)
101 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ 101 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
102 UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) 102 UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
103 #else 103 #else
104 /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */ 104 /* Unfortunately 440GX spreads EMAC interrupts on multiple UIC's */
105 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) 105 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
106 #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3))) 106 #define UIC_ETHxB (UIC_MASK(ETH_IRQ_NUM(2)) || UIC_MASK(ETH_IRQ_NUM(3)))
107 #endif /* !defined(CONFIG_440GX) */ 107 #endif /* !defined(CONFIG_440GX) */
108 #elif defined(CONFIG_HAS_ETH2) 108 #elif defined(CONFIG_HAS_ETH2)
109 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \ 109 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)) || \
110 UIC_MASK(ETH_IRQ_NUM(2))) 110 UIC_MASK(ETH_IRQ_NUM(2)))
111 #elif defined(CONFIG_HAS_ETH1) 111 #elif defined(CONFIG_HAS_ETH1)
112 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1))) 112 #define UIC_ETHx (UIC_MASK(ETH_IRQ_NUM(0)) || UIC_MASK(ETH_IRQ_NUM(1)))
113 #else 113 #else
114 #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0)) 114 #define UIC_ETHx UIC_MASK(ETH_IRQ_NUM(0))
115 #endif 115 #endif
116 116
117 /* 117 /*
118 * Define a default version for UIC_ETHxB for non 440GX so that we can 118 * Define a default version for UIC_ETHxB for non 440GX so that we can
119 * use common code for all 4xx variants 119 * use common code for all 4xx variants
120 */ 120 */
121 #if !defined(UIC_ETHxB) 121 #if !defined(UIC_ETHxB)
122 #define UIC_ETHxB 0 122 #define UIC_ETHxB 0
123 #endif 123 #endif
124 124
125 #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR) 125 #define UIC_MAL_SERR UIC_MASK(VECNUM_MAL_SERR)
126 #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE) 126 #define UIC_MAL_TXDE UIC_MASK(VECNUM_MAL_TXDE)
127 #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE) 127 #define UIC_MAL_RXDE UIC_MASK(VECNUM_MAL_RXDE)
128 #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB) 128 #define UIC_MAL_TXEOB UIC_MASK(VECNUM_MAL_TXEOB)
129 #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB) 129 #define UIC_MAL_RXEOB UIC_MASK(VECNUM_MAL_RXEOB)
130 130
131 #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE) 131 #define MAL_UIC_ERR (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)
132 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR) 132 #define MAL_UIC_DEF (UIC_MAL_RXEOB | MAL_UIC_ERR)
133 133
134 /* 134 /*
135 * We have 3 different interrupt types: 135 * We have 3 different interrupt types:
136 * - MAL interrupts indicating successful transfer 136 * - MAL interrupts indicating successful transfer
137 * - MAL error interrupts indicating MAL related errors 137 * - MAL error interrupts indicating MAL related errors
138 * - EMAC interrupts indicating EMAC related errors 138 * - EMAC interrupts indicating EMAC related errors
139 * 139 *
140 * All those interrupts can be on different UIC's, but since 140 * All those interrupts can be on different UIC's, but since
141 * now at least all interrupts from one type are on the same 141 * now at least all interrupts from one type are on the same
142 * UIC. Only exception is 440GX where the EMAC interrupts are 142 * UIC. Only exception is 440GX where the EMAC interrupts are
143 * spread over two UIC's! 143 * spread over two UIC's!
144 */ 144 */
145 #if defined(CONFIG_440GX) 145 #if defined(CONFIG_440GX)
146 #define UIC_BASE_MAL UIC1_DCR_BASE 146 #define UIC_BASE_MAL UIC1_DCR_BASE
147 #define UIC_BASE_MAL_ERR UIC2_DCR_BASE 147 #define UIC_BASE_MAL_ERR UIC2_DCR_BASE
148 #define UIC_BASE_EMAC UIC2_DCR_BASE 148 #define UIC_BASE_EMAC UIC2_DCR_BASE
149 #define UIC_BASE_EMAC_B UIC3_DCR_BASE 149 #define UIC_BASE_EMAC_B UIC3_DCR_BASE
150 #else 150 #else
151 #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10)) 151 #define UIC_BASE_MAL (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_TXEOB) * 0x10))
152 #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10)) 152 #define UIC_BASE_MAL_ERR (UIC0_DCR_BASE + (UIC_NR(VECNUM_MAL_SERR) * 0x10))
153 #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) 153 #define UIC_BASE_EMAC (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
154 #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10)) 154 #define UIC_BASE_EMAC_B (UIC0_DCR_BASE + (UIC_NR(ETH_IRQ_NUM(0)) * 0x10))
155 #endif 155 #endif
156 156
157 #undef INFO_4XX_ENET 157 #undef INFO_4XX_ENET
158 158
159 #define BI_PHYMODE_NONE 0 159 #define BI_PHYMODE_NONE 0
160 #define BI_PHYMODE_ZMII 1 160 #define BI_PHYMODE_ZMII 1
161 #define BI_PHYMODE_RGMII 2 161 #define BI_PHYMODE_RGMII 2
162 #define BI_PHYMODE_GMII 3 162 #define BI_PHYMODE_GMII 3
163 #define BI_PHYMODE_RTBI 4 163 #define BI_PHYMODE_RTBI 4
164 #define BI_PHYMODE_TBI 5 164 #define BI_PHYMODE_TBI 5
165 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 165 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
166 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 166 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
167 defined(CONFIG_405EX) 167 defined(CONFIG_405EX)
168 #define BI_PHYMODE_SMII 6 168 #define BI_PHYMODE_SMII 6
169 #define BI_PHYMODE_MII 7 169 #define BI_PHYMODE_MII 7
170 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 170 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
171 #define BI_PHYMODE_RMII 8 171 #define BI_PHYMODE_RMII 8
172 #endif 172 #endif
173 #endif 173 #endif
174 #define BI_PHYMODE_SGMII 9 174 #define BI_PHYMODE_SGMII 9
175 175
176 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ 176 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
177 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 177 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
178 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 178 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
179 defined(CONFIG_405EX) 179 defined(CONFIG_405EX)
180 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1)) 180 #define SDR0_MFR_ETH_CLK_SEL_V(n) ((0x01<<27) / (n+1))
181 #endif 181 #endif
182 182
183 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 183 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
184 #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n)) 184 #define SDR0_ETH_CFG_CLK_SEL_V(n) (0x01 << (8 + n))
185 #endif 185 #endif
186 186
187 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 187 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
188 #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */ 188 #define MAL_RX_CHAN_MUL 8 /* 460EX/GT uses MAL channel 8 for EMAC1 */
189 #else 189 #else
190 #define MAL_RX_CHAN_MUL 1 190 #define MAL_RX_CHAN_MUL 1
191 #endif 191 #endif
192 192
193 /*--------------------------------------------------------------------+ 193 /*--------------------------------------------------------------------+
194 * Fixed PHY (PHY-less) support for Ethernet Ports. 194 * Fixed PHY (PHY-less) support for Ethernet Ports.
195 *--------------------------------------------------------------------*/ 195 *--------------------------------------------------------------------*/
196 196
197 /* 197 /*
198 * Some boards do not have a PHY for each ethernet port. These ports 198 * Some boards do not have a PHY for each ethernet port. These ports
199 * are known as Fixed PHY (or PHY-less) ports. For such ports, set 199 * are known as Fixed PHY (or PHY-less) ports. For such ports, set
200 * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and 200 * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and
201 * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and 201 * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and
202 * duplex should be for these ports in the board configuration 202 * duplex should be for these ports in the board configuration
203 * file. 203 * file.
204 * 204 *
205 * For Example: 205 * For Example:
206 * #define CONFIG_FIXED_PHY 0xFFFFFFFF 206 * #define CONFIG_FIXED_PHY 0xFFFFFFFF
207 * 207 *
208 * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY 208 * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
209 * #define CONFIG_PHY1_ADDR 1 209 * #define CONFIG_PHY1_ADDR 1
210 * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY 210 * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY
211 * #define CONFIG_PHY3_ADDR 3 211 * #define CONFIG_PHY3_ADDR 3
212 * 212 *
213 * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \ 213 * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \
214 * {devnum, speed, duplex}, 214 * {devnum, speed, duplex},
215 * 215 *
216 * #define CONFIG_SYS_FIXED_PHY_PORTS \ 216 * #define CONFIG_SYS_FIXED_PHY_PORTS \
217 * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \ 217 * CONFIG_SYS_FIXED_PHY_PORT(0,1000,FULL) \
218 * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF) 218 * CONFIG_SYS_FIXED_PHY_PORT(2,100,HALF)
219 */ 219 */
220 220
221 #ifndef CONFIG_FIXED_PHY 221 #ifndef CONFIG_FIXED_PHY
222 #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ 222 #define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */
223 #endif 223 #endif
224 224
225 #ifndef CONFIG_SYS_FIXED_PHY_PORTS 225 #ifndef CONFIG_SYS_FIXED_PHY_PORTS
226 #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */ 226 #define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */
227 #endif 227 #endif
228 228
229 struct fixed_phy_port { 229 struct fixed_phy_port {
230 unsigned int devnum; /* ethernet port */ 230 unsigned int devnum; /* ethernet port */
231 unsigned int speed; /* specified speed 10,100 or 1000 */ 231 unsigned int speed; /* specified speed 10,100 or 1000 */
232 unsigned int duplex; /* specified duplex FULL or HALF */ 232 unsigned int duplex; /* specified duplex FULL or HALF */
233 }; 233 };
234 234
235 static const struct fixed_phy_port fixed_phy_port[] = { 235 static const struct fixed_phy_port fixed_phy_port[] = {
236 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ 236 CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */
237 }; 237 };
238 238
239 /*-----------------------------------------------------------------------------+ 239 /*-----------------------------------------------------------------------------+
240 * Global variables. TX and RX descriptors and buffers. 240 * Global variables. TX and RX descriptors and buffers.
241 *-----------------------------------------------------------------------------*/ 241 *-----------------------------------------------------------------------------*/
242 242
243 /* 243 /*
244 * Get count of EMAC devices (doesn't have to be the max. possible number 244 * Get count of EMAC devices (doesn't have to be the max. possible number
245 * supported by the cpu) 245 * supported by the cpu)
246 * 246 *
247 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the 247 * CONFIG_BOARD_EMAC_COUNT added so now a "dynamic" way to configure the
248 * EMAC count is possible. As it is needed for the Kilauea/Haleakala 248 * EMAC count is possible. As it is needed for the Kilauea/Haleakala
249 * 405EX/405EXr eval board, using the same binary. 249 * 405EX/405EXr eval board, using the same binary.
250 */ 250 */
251 #if defined(CONFIG_BOARD_EMAC_COUNT) 251 #if defined(CONFIG_BOARD_EMAC_COUNT)
252 #define LAST_EMAC_NUM board_emac_count() 252 #define LAST_EMAC_NUM board_emac_count()
253 #else /* CONFIG_BOARD_EMAC_COUNT */ 253 #else /* CONFIG_BOARD_EMAC_COUNT */
254 #if defined(CONFIG_HAS_ETH3) 254 #if defined(CONFIG_HAS_ETH3)
255 #define LAST_EMAC_NUM 4 255 #define LAST_EMAC_NUM 4
256 #elif defined(CONFIG_HAS_ETH2) 256 #elif defined(CONFIG_HAS_ETH2)
257 #define LAST_EMAC_NUM 3 257 #define LAST_EMAC_NUM 3
258 #elif defined(CONFIG_HAS_ETH1) 258 #elif defined(CONFIG_HAS_ETH1)
259 #define LAST_EMAC_NUM 2 259 #define LAST_EMAC_NUM 2
260 #else 260 #else
261 #define LAST_EMAC_NUM 1 261 #define LAST_EMAC_NUM 1
262 #endif 262 #endif
263 #endif /* CONFIG_BOARD_EMAC_COUNT */ 263 #endif /* CONFIG_BOARD_EMAC_COUNT */
264 264
265 /* normal boards start with EMAC0 */ 265 /* normal boards start with EMAC0 */
266 #if !defined(CONFIG_EMAC_NR_START) 266 #if !defined(CONFIG_EMAC_NR_START)
267 #define CONFIG_EMAC_NR_START 0 267 #define CONFIG_EMAC_NR_START 0
268 #endif 268 #endif
269 269
270 #define MAL_RX_DESC_SIZE 2048 270 #define MAL_RX_DESC_SIZE 2048
271 #define MAL_TX_DESC_SIZE 2048 271 #define MAL_TX_DESC_SIZE 2048
272 #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE) 272 #define MAL_ALLOC_SIZE (MAL_TX_DESC_SIZE + MAL_RX_DESC_SIZE)
273 273
274 /*-----------------------------------------------------------------------------+ 274 /*-----------------------------------------------------------------------------+
275 * Prototypes and externals. 275 * Prototypes and externals.
276 *-----------------------------------------------------------------------------*/ 276 *-----------------------------------------------------------------------------*/
277 static void enet_rcv (struct eth_device *dev, unsigned long malisr); 277 static void enet_rcv (struct eth_device *dev, unsigned long malisr);
278 278
279 int enetInt (struct eth_device *dev); 279 int enetInt (struct eth_device *dev);
280 static void mal_err (struct eth_device *dev, unsigned long isr, 280 static void mal_err (struct eth_device *dev, unsigned long isr,
281 unsigned long uic, unsigned long maldef, 281 unsigned long uic, unsigned long maldef,
282 unsigned long mal_errr); 282 unsigned long mal_errr);
283 static void emac_err (struct eth_device *dev, unsigned long isr); 283 static void emac_err (struct eth_device *dev, unsigned long isr);
284 284
285 extern int phy_setup_aneg (char *devname, unsigned char addr); 285 extern int phy_setup_aneg (char *devname, unsigned char addr);
286 extern int emac4xx_miiphy_read (const char *devname, unsigned char addr, 286 extern int emac4xx_miiphy_read (const char *devname, unsigned char addr,
287 unsigned char reg, unsigned short *value); 287 unsigned char reg, unsigned short *value);
288 extern int emac4xx_miiphy_write (const char *devname, unsigned char addr, 288 extern int emac4xx_miiphy_write (const char *devname, unsigned char addr,
289 unsigned char reg, unsigned short value); 289 unsigned char reg, unsigned short value);
290 290
291 int board_emac_count(void); 291 int board_emac_count(void);
292 292
293 static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p) 293 static void emac_loopback_enable(EMAC_4XX_HW_PST hw_p)
294 { 294 {
295 #if defined(CONFIG_440SPE) || \ 295 #if defined(CONFIG_440SPE) || \
296 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 296 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
297 defined(CONFIG_405EX) 297 defined(CONFIG_405EX)
298 u32 val; 298 u32 val;
299 299
300 mfsdr(SDR0_MFR, val); 300 mfsdr(SDR0_MFR, val);
301 val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); 301 val |= SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
302 mtsdr(SDR0_MFR, val); 302 mtsdr(SDR0_MFR, val);
303 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) 303 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
304 u32 val; 304 u32 val;
305 305
306 mfsdr(SDR0_ETH_CFG, val); 306 mfsdr(SDR0_ETH_CFG, val);
307 val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); 307 val |= SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
308 mtsdr(SDR0_ETH_CFG, val); 308 mtsdr(SDR0_ETH_CFG, val);
309 #endif 309 #endif
310 } 310 }
311 311
312 static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p) 312 static void emac_loopback_disable(EMAC_4XX_HW_PST hw_p)
313 { 313 {
314 #if defined(CONFIG_440SPE) || \ 314 #if defined(CONFIG_440SPE) || \
315 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 315 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
316 defined(CONFIG_405EX) 316 defined(CONFIG_405EX)
317 u32 val; 317 u32 val;
318 318
319 mfsdr(SDR0_MFR, val); 319 mfsdr(SDR0_MFR, val);
320 val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum); 320 val &= ~SDR0_MFR_ETH_CLK_SEL_V(hw_p->devnum);
321 mtsdr(SDR0_MFR, val); 321 mtsdr(SDR0_MFR, val);
322 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT) 322 #elif defined(CONFIG_460EX) || defined(CONFIG_460GT)
323 u32 val; 323 u32 val;
324 324
325 mfsdr(SDR0_ETH_CFG, val); 325 mfsdr(SDR0_ETH_CFG, val);
326 val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum); 326 val &= ~SDR0_ETH_CFG_CLK_SEL_V(hw_p->devnum);
327 mtsdr(SDR0_ETH_CFG, val); 327 mtsdr(SDR0_ETH_CFG, val);
328 #endif 328 #endif
329 } 329 }
330 330
331 /*-----------------------------------------------------------------------------+ 331 /*-----------------------------------------------------------------------------+
332 | ppc_4xx_eth_halt 332 | ppc_4xx_eth_halt
333 | Disable MAL channel, and EMACn 333 | Disable MAL channel, and EMACn
334 +-----------------------------------------------------------------------------*/ 334 +-----------------------------------------------------------------------------*/
335 static void ppc_4xx_eth_halt (struct eth_device *dev) 335 static void ppc_4xx_eth_halt (struct eth_device *dev)
336 { 336 {
337 EMAC_4XX_HW_PST hw_p = dev->priv; 337 EMAC_4XX_HW_PST hw_p = dev->priv;
338 u32 val = 10000; 338 u32 val = 10000;
339 339
340 out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */ 340 out_be32((void *)EMAC0_IER + hw_p->hw_addr, 0x00000000); /* disable emac interrupts */
341 341
342 /* 1st reset MAL channel */ 342 /* 1st reset MAL channel */
343 /* Note: writing a 0 to a channel has no effect */ 343 /* Note: writing a 0 to a channel has no effect */
344 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) 344 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
345 mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2))); 345 mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> (hw_p->devnum * 2)));
346 #else 346 #else
347 mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum)); 347 mtdcr (MAL0_TXCARR, (MAL_CR_MMSR >> hw_p->devnum));
348 #endif 348 #endif
349 mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum)); 349 mtdcr (MAL0_RXCARR, (MAL_CR_MMSR >> hw_p->devnum));
350 350
351 /* wait for reset */ 351 /* wait for reset */
352 while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) { 352 while (mfdcr (MAL0_RXCASR) & (MAL_CR_MMSR >> hw_p->devnum)) {
353 udelay (1000); /* Delay 1 MS so as not to hammer the register */ 353 udelay (1000); /* Delay 1 MS so as not to hammer the register */
354 val--; 354 val--;
355 if (val == 0) 355 if (val == 0)
356 break; 356 break;
357 } 357 }
358 358
359 /* provide clocks for EMAC internal loopback */ 359 /* provide clocks for EMAC internal loopback */
360 emac_loopback_enable(hw_p); 360 emac_loopback_enable(hw_p);
361 361
362 /* EMAC RESET */ 362 /* EMAC RESET */
363 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); 363 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
364 364
365 /* remove clocks for EMAC internal loopback */ 365 /* remove clocks for EMAC internal loopback */
366 emac_loopback_disable(hw_p); 366 emac_loopback_disable(hw_p);
367 367
368 #ifndef CONFIG_NETCONSOLE 368 #ifndef CONFIG_NETCONSOLE
369 hw_p->print_speed = 1; /* print speed message again next time */ 369 hw_p->print_speed = 1; /* print speed message again next time */
370 #endif 370 #endif
371 371
372 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 372 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
373 /* don't bypass the TAHOE0/TAHOE1 cores for Linux */ 373 /* don't bypass the TAHOE0/TAHOE1 cores for Linux */
374 mfsdr(SDR0_ETH_CFG, val); 374 mfsdr(SDR0_ETH_CFG, val);
375 val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); 375 val &= ~(SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
376 mtsdr(SDR0_ETH_CFG, val); 376 mtsdr(SDR0_ETH_CFG, val);
377 #endif 377 #endif
378 378
379 return; 379 return;
380 } 380 }
381 381
382 #if defined (CONFIG_440GX) 382 #if defined (CONFIG_440GX)
383 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) 383 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
384 { 384 {
385 unsigned long pfc1; 385 unsigned long pfc1;
386 unsigned long zmiifer; 386 unsigned long zmiifer;
387 unsigned long rmiifer; 387 unsigned long rmiifer;
388 388
389 mfsdr(SDR0_PFC1, pfc1); 389 mfsdr(SDR0_PFC1, pfc1);
390 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1); 390 pfc1 = SDR0_PFC1_EPS_DECODE(pfc1);
391 391
392 zmiifer = 0; 392 zmiifer = 0;
393 rmiifer = 0; 393 rmiifer = 0;
394 394
395 switch (pfc1) { 395 switch (pfc1) {
396 case 1: 396 case 1:
397 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); 397 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
398 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); 398 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
399 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); 399 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
400 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); 400 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
401 bis->bi_phymode[0] = BI_PHYMODE_ZMII; 401 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
402 bis->bi_phymode[1] = BI_PHYMODE_ZMII; 402 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
403 bis->bi_phymode[2] = BI_PHYMODE_ZMII; 403 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
404 bis->bi_phymode[3] = BI_PHYMODE_ZMII; 404 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
405 break; 405 break;
406 case 2: 406 case 2:
407 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); 407 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
408 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); 408 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
409 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); 409 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
410 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); 410 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
411 bis->bi_phymode[0] = BI_PHYMODE_ZMII; 411 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
412 bis->bi_phymode[1] = BI_PHYMODE_ZMII; 412 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
413 bis->bi_phymode[2] = BI_PHYMODE_ZMII; 413 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
414 bis->bi_phymode[3] = BI_PHYMODE_ZMII; 414 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
415 break; 415 break;
416 case 3: 416 case 3:
417 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); 417 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
418 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); 418 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
419 bis->bi_phymode[0] = BI_PHYMODE_ZMII; 419 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
420 bis->bi_phymode[1] = BI_PHYMODE_NONE; 420 bis->bi_phymode[1] = BI_PHYMODE_NONE;
421 bis->bi_phymode[2] = BI_PHYMODE_RGMII; 421 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
422 bis->bi_phymode[3] = BI_PHYMODE_NONE; 422 bis->bi_phymode[3] = BI_PHYMODE_NONE;
423 break; 423 break;
424 case 4: 424 case 4:
425 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); 425 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
426 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); 426 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
427 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2); 427 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (2);
428 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3); 428 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V (3);
429 bis->bi_phymode[0] = BI_PHYMODE_ZMII; 429 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
430 bis->bi_phymode[1] = BI_PHYMODE_ZMII; 430 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
431 bis->bi_phymode[2] = BI_PHYMODE_RGMII; 431 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
432 bis->bi_phymode[3] = BI_PHYMODE_RGMII; 432 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
433 break; 433 break;
434 case 5: 434 case 5:
435 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); 435 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
436 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); 436 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
437 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2); 437 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (2);
438 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); 438 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
439 bis->bi_phymode[0] = BI_PHYMODE_ZMII; 439 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
440 bis->bi_phymode[1] = BI_PHYMODE_ZMII; 440 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
441 bis->bi_phymode[2] = BI_PHYMODE_ZMII; 441 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
442 bis->bi_phymode[3] = BI_PHYMODE_RGMII; 442 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
443 break; 443 break;
444 case 6: 444 case 6:
445 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0); 445 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (0);
446 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1); 446 zmiifer |= ZMII_FER_SMII << ZMII_FER_V (1);
447 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); 447 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
448 bis->bi_phymode[0] = BI_PHYMODE_ZMII; 448 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
449 bis->bi_phymode[1] = BI_PHYMODE_ZMII; 449 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
450 bis->bi_phymode[2] = BI_PHYMODE_RGMII; 450 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
451 break; 451 break;
452 case 0: 452 case 0:
453 default: 453 default:
454 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum); 454 zmiifer = ZMII_FER_MII << ZMII_FER_V(devnum);
455 rmiifer = 0x0; 455 rmiifer = 0x0;
456 bis->bi_phymode[0] = BI_PHYMODE_ZMII; 456 bis->bi_phymode[0] = BI_PHYMODE_ZMII;
457 bis->bi_phymode[1] = BI_PHYMODE_ZMII; 457 bis->bi_phymode[1] = BI_PHYMODE_ZMII;
458 bis->bi_phymode[2] = BI_PHYMODE_ZMII; 458 bis->bi_phymode[2] = BI_PHYMODE_ZMII;
459 bis->bi_phymode[3] = BI_PHYMODE_ZMII; 459 bis->bi_phymode[3] = BI_PHYMODE_ZMII;
460 break; 460 break;
461 } 461 }
462 462
463 /* Ensure we setup mdio for this devnum and ONLY this devnum */ 463 /* Ensure we setup mdio for this devnum and ONLY this devnum */
464 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); 464 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
465 465
466 out_be32((void *)ZMII0_FER, zmiifer); 466 out_be32((void *)ZMII0_FER, zmiifer);
467 out_be32((void *)RGMII_FER, rmiifer); 467 out_be32((void *)RGMII_FER, rmiifer);
468 468
469 return ((int)pfc1); 469 return ((int)pfc1);
470 } 470 }
471 #endif /* CONFIG_440_GX */ 471 #endif /* CONFIG_440_GX */
472 472
473 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) 473 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX)
474 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) 474 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
475 { 475 {
476 unsigned long zmiifer=0x0; 476 unsigned long zmiifer=0x0;
477 unsigned long pfc1; 477 unsigned long pfc1;
478 478
479 mfsdr(SDR0_PFC1, pfc1); 479 mfsdr(SDR0_PFC1, pfc1);
480 pfc1 &= SDR0_PFC1_SELECT_MASK; 480 pfc1 &= SDR0_PFC1_SELECT_MASK;
481 481
482 switch (pfc1) { 482 switch (pfc1) {
483 case SDR0_PFC1_SELECT_CONFIG_2: 483 case SDR0_PFC1_SELECT_CONFIG_2:
484 /* 1 x GMII port */ 484 /* 1 x GMII port */
485 out_be32((void *)ZMII0_FER, 0x00); 485 out_be32((void *)ZMII0_FER, 0x00);
486 out_be32((void *)RGMII_FER, 0x00000037); 486 out_be32((void *)RGMII_FER, 0x00000037);
487 bis->bi_phymode[0] = BI_PHYMODE_GMII; 487 bis->bi_phymode[0] = BI_PHYMODE_GMII;
488 bis->bi_phymode[1] = BI_PHYMODE_NONE; 488 bis->bi_phymode[1] = BI_PHYMODE_NONE;
489 break; 489 break;
490 case SDR0_PFC1_SELECT_CONFIG_4: 490 case SDR0_PFC1_SELECT_CONFIG_4:
491 /* 2 x RGMII ports */ 491 /* 2 x RGMII ports */
492 out_be32((void *)ZMII0_FER, 0x00); 492 out_be32((void *)ZMII0_FER, 0x00);
493 out_be32((void *)RGMII_FER, 0x00000055); 493 out_be32((void *)RGMII_FER, 0x00000055);
494 bis->bi_phymode[0] = BI_PHYMODE_RGMII; 494 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
495 bis->bi_phymode[1] = BI_PHYMODE_RGMII; 495 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
496 break; 496 break;
497 case SDR0_PFC1_SELECT_CONFIG_6: 497 case SDR0_PFC1_SELECT_CONFIG_6:
498 /* 2 x SMII ports */ 498 /* 2 x SMII ports */
499 out_be32((void *)ZMII0_FER, 499 out_be32((void *)ZMII0_FER,
500 ((ZMII_FER_SMII) << ZMII_FER_V(0)) | 500 ((ZMII_FER_SMII) << ZMII_FER_V(0)) |
501 ((ZMII_FER_SMII) << ZMII_FER_V(1))); 501 ((ZMII_FER_SMII) << ZMII_FER_V(1)));
502 out_be32((void *)RGMII_FER, 0x00000000); 502 out_be32((void *)RGMII_FER, 0x00000000);
503 bis->bi_phymode[0] = BI_PHYMODE_SMII; 503 bis->bi_phymode[0] = BI_PHYMODE_SMII;
504 bis->bi_phymode[1] = BI_PHYMODE_SMII; 504 bis->bi_phymode[1] = BI_PHYMODE_SMII;
505 break; 505 break;
506 case SDR0_PFC1_SELECT_CONFIG_1_2: 506 case SDR0_PFC1_SELECT_CONFIG_1_2:
507 /* only 1 x MII supported */ 507 /* only 1 x MII supported */
508 out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0)); 508 out_be32((void *)ZMII0_FER, (ZMII_FER_MII) << ZMII_FER_V(0));
509 out_be32((void *)RGMII_FER, 0x00000000); 509 out_be32((void *)RGMII_FER, 0x00000000);
510 bis->bi_phymode[0] = BI_PHYMODE_MII; 510 bis->bi_phymode[0] = BI_PHYMODE_MII;
511 bis->bi_phymode[1] = BI_PHYMODE_NONE; 511 bis->bi_phymode[1] = BI_PHYMODE_NONE;
512 break; 512 break;
513 default: 513 default:
514 break; 514 break;
515 } 515 }
516 516
517 /* Ensure we setup mdio for this devnum and ONLY this devnum */ 517 /* Ensure we setup mdio for this devnum and ONLY this devnum */
518 zmiifer = in_be32((void *)ZMII0_FER); 518 zmiifer = in_be32((void *)ZMII0_FER);
519 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum); 519 zmiifer |= (ZMII_FER_MDI) << ZMII_FER_V(devnum);
520 out_be32((void *)ZMII0_FER, zmiifer); 520 out_be32((void *)ZMII0_FER, zmiifer);
521 521
522 return ((int)0x0); 522 return ((int)0x0);
523 } 523 }
524 #endif /* CONFIG_440EPX */ 524 #endif /* CONFIG_440EPX */
525 525
526 #if defined(CONFIG_405EX) 526 #if defined(CONFIG_405EX)
527 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) 527 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
528 { 528 {
529 u32 rgmiifer = 0; 529 u32 rgmiifer = 0;
530 530
531 /* 531 /*
532 * The 405EX(r)'s RGMII bridge can operate in one of several 532 * The 405EX(r)'s RGMII bridge can operate in one of several
533 * modes, only one of which (2 x RGMII) allows the 533 * modes, only one of which (2 x RGMII) allows the
534 * simultaneous use of both EMACs on the 405EX. 534 * simultaneous use of both EMACs on the 405EX.
535 */ 535 */
536 536
537 switch (CONFIG_EMAC_PHY_MODE) { 537 switch (CONFIG_EMAC_PHY_MODE) {
538 538
539 case EMAC_PHY_MODE_NONE: 539 case EMAC_PHY_MODE_NONE:
540 /* No ports */ 540 /* No ports */
541 rgmiifer |= RGMII_FER_DIS << 0; 541 rgmiifer |= RGMII_FER_DIS << 0;
542 rgmiifer |= RGMII_FER_DIS << 4; 542 rgmiifer |= RGMII_FER_DIS << 4;
543 out_be32((void *)RGMII_FER, rgmiifer); 543 out_be32((void *)RGMII_FER, rgmiifer);
544 bis->bi_phymode[0] = BI_PHYMODE_NONE; 544 bis->bi_phymode[0] = BI_PHYMODE_NONE;
545 bis->bi_phymode[1] = BI_PHYMODE_NONE; 545 bis->bi_phymode[1] = BI_PHYMODE_NONE;
546 break; 546 break;
547 case EMAC_PHY_MODE_NONE_RGMII: 547 case EMAC_PHY_MODE_NONE_RGMII:
548 /* 1 x RGMII port on channel 0 */ 548 /* 1 x RGMII port on channel 0 */
549 rgmiifer |= RGMII_FER_RGMII << 0; 549 rgmiifer |= RGMII_FER_RGMII << 0;
550 rgmiifer |= RGMII_FER_DIS << 4; 550 rgmiifer |= RGMII_FER_DIS << 4;
551 out_be32((void *)RGMII_FER, rgmiifer); 551 out_be32((void *)RGMII_FER, rgmiifer);
552 bis->bi_phymode[0] = BI_PHYMODE_RGMII; 552 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
553 bis->bi_phymode[1] = BI_PHYMODE_NONE; 553 bis->bi_phymode[1] = BI_PHYMODE_NONE;
554 break; 554 break;
555 case EMAC_PHY_MODE_RGMII_NONE: 555 case EMAC_PHY_MODE_RGMII_NONE:
556 /* 1 x RGMII port on channel 1 */ 556 /* 1 x RGMII port on channel 1 */
557 rgmiifer |= RGMII_FER_DIS << 0; 557 rgmiifer |= RGMII_FER_DIS << 0;
558 rgmiifer |= RGMII_FER_RGMII << 4; 558 rgmiifer |= RGMII_FER_RGMII << 4;
559 out_be32((void *)RGMII_FER, rgmiifer); 559 out_be32((void *)RGMII_FER, rgmiifer);
560 bis->bi_phymode[0] = BI_PHYMODE_NONE; 560 bis->bi_phymode[0] = BI_PHYMODE_NONE;
561 bis->bi_phymode[1] = BI_PHYMODE_RGMII; 561 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
562 break; 562 break;
563 case EMAC_PHY_MODE_RGMII_RGMII: 563 case EMAC_PHY_MODE_RGMII_RGMII:
564 /* 2 x RGMII ports */ 564 /* 2 x RGMII ports */
565 rgmiifer |= RGMII_FER_RGMII << 0; 565 rgmiifer |= RGMII_FER_RGMII << 0;
566 rgmiifer |= RGMII_FER_RGMII << 4; 566 rgmiifer |= RGMII_FER_RGMII << 4;
567 out_be32((void *)RGMII_FER, rgmiifer); 567 out_be32((void *)RGMII_FER, rgmiifer);
568 bis->bi_phymode[0] = BI_PHYMODE_RGMII; 568 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
569 bis->bi_phymode[1] = BI_PHYMODE_RGMII; 569 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
570 break; 570 break;
571 case EMAC_PHY_MODE_NONE_GMII: 571 case EMAC_PHY_MODE_NONE_GMII:
572 /* 1 x GMII port on channel 0 */ 572 /* 1 x GMII port on channel 0 */
573 rgmiifer |= RGMII_FER_GMII << 0; 573 rgmiifer |= RGMII_FER_GMII << 0;
574 rgmiifer |= RGMII_FER_DIS << 4; 574 rgmiifer |= RGMII_FER_DIS << 4;
575 out_be32((void *)RGMII_FER, rgmiifer); 575 out_be32((void *)RGMII_FER, rgmiifer);
576 bis->bi_phymode[0] = BI_PHYMODE_GMII; 576 bis->bi_phymode[0] = BI_PHYMODE_GMII;
577 bis->bi_phymode[1] = BI_PHYMODE_NONE; 577 bis->bi_phymode[1] = BI_PHYMODE_NONE;
578 break; 578 break;
579 case EMAC_PHY_MODE_NONE_MII: 579 case EMAC_PHY_MODE_NONE_MII:
580 /* 1 x MII port on channel 0 */ 580 /* 1 x MII port on channel 0 */
581 rgmiifer |= RGMII_FER_MII << 0; 581 rgmiifer |= RGMII_FER_MII << 0;
582 rgmiifer |= RGMII_FER_DIS << 4; 582 rgmiifer |= RGMII_FER_DIS << 4;
583 out_be32((void *)RGMII_FER, rgmiifer); 583 out_be32((void *)RGMII_FER, rgmiifer);
584 bis->bi_phymode[0] = BI_PHYMODE_MII; 584 bis->bi_phymode[0] = BI_PHYMODE_MII;
585 bis->bi_phymode[1] = BI_PHYMODE_NONE; 585 bis->bi_phymode[1] = BI_PHYMODE_NONE;
586 break; 586 break;
587 case EMAC_PHY_MODE_GMII_NONE: 587 case EMAC_PHY_MODE_GMII_NONE:
588 /* 1 x GMII port on channel 1 */ 588 /* 1 x GMII port on channel 1 */
589 rgmiifer |= RGMII_FER_DIS << 0; 589 rgmiifer |= RGMII_FER_DIS << 0;
590 rgmiifer |= RGMII_FER_GMII << 4; 590 rgmiifer |= RGMII_FER_GMII << 4;
591 out_be32((void *)RGMII_FER, rgmiifer); 591 out_be32((void *)RGMII_FER, rgmiifer);
592 bis->bi_phymode[0] = BI_PHYMODE_NONE; 592 bis->bi_phymode[0] = BI_PHYMODE_NONE;
593 bis->bi_phymode[1] = BI_PHYMODE_GMII; 593 bis->bi_phymode[1] = BI_PHYMODE_GMII;
594 break; 594 break;
595 case EMAC_PHY_MODE_MII_NONE: 595 case EMAC_PHY_MODE_MII_NONE:
596 /* 1 x MII port on channel 1 */ 596 /* 1 x MII port on channel 1 */
597 rgmiifer |= RGMII_FER_DIS << 0; 597 rgmiifer |= RGMII_FER_DIS << 0;
598 rgmiifer |= RGMII_FER_MII << 4; 598 rgmiifer |= RGMII_FER_MII << 4;
599 out_be32((void *)RGMII_FER, rgmiifer); 599 out_be32((void *)RGMII_FER, rgmiifer);
600 bis->bi_phymode[0] = BI_PHYMODE_NONE; 600 bis->bi_phymode[0] = BI_PHYMODE_NONE;
601 bis->bi_phymode[1] = BI_PHYMODE_MII; 601 bis->bi_phymode[1] = BI_PHYMODE_MII;
602 break; 602 break;
603 default: 603 default:
604 break; 604 break;
605 } 605 }
606 606
607 /* Ensure we setup mdio for this devnum and ONLY this devnum */ 607 /* Ensure we setup mdio for this devnum and ONLY this devnum */
608 rgmiifer = in_be32((void *)RGMII_FER); 608 rgmiifer = in_be32((void *)RGMII_FER);
609 rgmiifer |= (1 << (19-devnum)); 609 rgmiifer |= (1 << (19-devnum));
610 out_be32((void *)RGMII_FER, rgmiifer); 610 out_be32((void *)RGMII_FER, rgmiifer);
611 611
612 return ((int)0x0); 612 return ((int)0x0);
613 } 613 }
614 #endif /* CONFIG_405EX */ 614 #endif /* CONFIG_405EX */
615 615
616 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 616 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
617 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis) 617 int ppc_4xx_eth_setup_bridge(int devnum, bd_t * bis)
618 { 618 {
619 u32 eth_cfg; 619 u32 eth_cfg;
620 u32 zmiifer; /* ZMII0_FER reg. */ 620 u32 zmiifer; /* ZMII0_FER reg. */
621 u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */ 621 u32 rmiifer; /* RGMII0_FER reg. Bridge 0 */
622 u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */ 622 u32 rmiifer1; /* RGMII0_FER reg. Bridge 1 */
623 int mode; 623 int mode;
624 624
625 zmiifer = 0; 625 zmiifer = 0;
626 rmiifer = 0; 626 rmiifer = 0;
627 rmiifer1 = 0; 627 rmiifer1 = 0;
628 628
629 #if defined(CONFIG_460EX) 629 #if defined(CONFIG_460EX)
630 mode = 9; 630 mode = 9;
631 mfsdr(SDR0_ETH_CFG, eth_cfg); 631 mfsdr(SDR0_ETH_CFG, eth_cfg);
632 if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && 632 if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
633 ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0)) 633 ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0))
634 mode = 11; /* config SGMII */ 634 mode = 11; /* config SGMII */
635 #else 635 #else
636 mode = 10; 636 mode = 10;
637 mfsdr(SDR0_ETH_CFG, eth_cfg); 637 mfsdr(SDR0_ETH_CFG, eth_cfg);
638 if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) && 638 if (((eth_cfg & SDR0_ETH_CFG_SGMII0_ENABLE) > 0) &&
639 ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) && 639 ((eth_cfg & SDR0_ETH_CFG_SGMII1_ENABLE) > 0) &&
640 ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0)) 640 ((eth_cfg & SDR0_ETH_CFG_SGMII2_ENABLE) > 0))
641 mode = 12; /* config SGMII */ 641 mode = 12; /* config SGMII */
642 #endif 642 #endif
643 643
644 /* TODO: 644 /* TODO:
645 * NOTE: 460GT has 2 RGMII bridge cores: 645 * NOTE: 460GT has 2 RGMII bridge cores:
646 * emac0 ------ RGMII0_BASE 646 * emac0 ------ RGMII0_BASE
647 * | 647 * |
648 * emac1 -----+ 648 * emac1 -----+
649 * 649 *
650 * emac2 ------ RGMII1_BASE 650 * emac2 ------ RGMII1_BASE
651 * | 651 * |
652 * emac3 -----+ 652 * emac3 -----+
653 * 653 *
654 * 460EX has 1 RGMII bridge core: 654 * 460EX has 1 RGMII bridge core:
655 * and RGMII1_BASE is disabled 655 * and RGMII1_BASE is disabled
656 * emac0 ------ RGMII0_BASE 656 * emac0 ------ RGMII0_BASE
657 * | 657 * |
658 * emac1 -----+ 658 * emac1 -----+
659 */ 659 */
660 660
661 /* 661 /*
662 * Right now only 2*RGMII is supported. Please extend when needed. 662 * Right now only 2*RGMII is supported. Please extend when needed.
663 * sr - 2008-02-19 663 * sr - 2008-02-19
664 * Add SGMII support. 664 * Add SGMII support.
665 * vg - 2008-07-28 665 * vg - 2008-07-28
666 */ 666 */
667 switch (mode) { 667 switch (mode) {
668 case 1: 668 case 1:
669 /* 1 MII - 460EX */ 669 /* 1 MII - 460EX */
670 /* GMC0 EMAC4_0, ZMII Bridge */ 670 /* GMC0 EMAC4_0, ZMII Bridge */
671 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); 671 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
672 bis->bi_phymode[0] = BI_PHYMODE_MII; 672 bis->bi_phymode[0] = BI_PHYMODE_MII;
673 bis->bi_phymode[1] = BI_PHYMODE_NONE; 673 bis->bi_phymode[1] = BI_PHYMODE_NONE;
674 bis->bi_phymode[2] = BI_PHYMODE_NONE; 674 bis->bi_phymode[2] = BI_PHYMODE_NONE;
675 bis->bi_phymode[3] = BI_PHYMODE_NONE; 675 bis->bi_phymode[3] = BI_PHYMODE_NONE;
676 break; 676 break;
677 case 2: 677 case 2:
678 /* 2 MII - 460GT */ 678 /* 2 MII - 460GT */
679 /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */ 679 /* GMC0 EMAC4_0, GMC1 EMAC4_2, ZMII Bridge */
680 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0); 680 zmiifer |= ZMII_FER_MII << ZMII_FER_V(0);
681 zmiifer |= ZMII_FER_MII << ZMII_FER_V(2); 681 zmiifer |= ZMII_FER_MII << ZMII_FER_V(2);
682 bis->bi_phymode[0] = BI_PHYMODE_MII; 682 bis->bi_phymode[0] = BI_PHYMODE_MII;
683 bis->bi_phymode[1] = BI_PHYMODE_NONE; 683 bis->bi_phymode[1] = BI_PHYMODE_NONE;
684 bis->bi_phymode[2] = BI_PHYMODE_MII; 684 bis->bi_phymode[2] = BI_PHYMODE_MII;
685 bis->bi_phymode[3] = BI_PHYMODE_NONE; 685 bis->bi_phymode[3] = BI_PHYMODE_NONE;
686 break; 686 break;
687 case 3: 687 case 3:
688 /* 2 RMII - 460EX */ 688 /* 2 RMII - 460EX */
689 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ 689 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
690 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); 690 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
691 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); 691 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
692 bis->bi_phymode[0] = BI_PHYMODE_RMII; 692 bis->bi_phymode[0] = BI_PHYMODE_RMII;
693 bis->bi_phymode[1] = BI_PHYMODE_RMII; 693 bis->bi_phymode[1] = BI_PHYMODE_RMII;
694 bis->bi_phymode[2] = BI_PHYMODE_NONE; 694 bis->bi_phymode[2] = BI_PHYMODE_NONE;
695 bis->bi_phymode[3] = BI_PHYMODE_NONE; 695 bis->bi_phymode[3] = BI_PHYMODE_NONE;
696 break; 696 break;
697 case 4: 697 case 4:
698 /* 4 RMII - 460GT */ 698 /* 4 RMII - 460GT */
699 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */ 699 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC1 EMAC4_2, GMC1, EMAC4_3 */
700 /* ZMII Bridge */ 700 /* ZMII Bridge */
701 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0); 701 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(0);
702 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1); 702 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(1);
703 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2); 703 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(2);
704 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3); 704 zmiifer |= ZMII_FER_RMII << ZMII_FER_V(3);
705 bis->bi_phymode[0] = BI_PHYMODE_RMII; 705 bis->bi_phymode[0] = BI_PHYMODE_RMII;
706 bis->bi_phymode[1] = BI_PHYMODE_RMII; 706 bis->bi_phymode[1] = BI_PHYMODE_RMII;
707 bis->bi_phymode[2] = BI_PHYMODE_RMII; 707 bis->bi_phymode[2] = BI_PHYMODE_RMII;
708 bis->bi_phymode[3] = BI_PHYMODE_RMII; 708 bis->bi_phymode[3] = BI_PHYMODE_RMII;
709 break; 709 break;
710 case 5: 710 case 5:
711 /* 2 SMII - 460EX */ 711 /* 2 SMII - 460EX */
712 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */ 712 /* GMC0 EMAC4_0, GMC0 EMAC4_1, ZMII Bridge */
713 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); 713 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
714 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); 714 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
715 bis->bi_phymode[0] = BI_PHYMODE_SMII; 715 bis->bi_phymode[0] = BI_PHYMODE_SMII;
716 bis->bi_phymode[1] = BI_PHYMODE_SMII; 716 bis->bi_phymode[1] = BI_PHYMODE_SMII;
717 bis->bi_phymode[2] = BI_PHYMODE_NONE; 717 bis->bi_phymode[2] = BI_PHYMODE_NONE;
718 bis->bi_phymode[3] = BI_PHYMODE_NONE; 718 bis->bi_phymode[3] = BI_PHYMODE_NONE;
719 break; 719 break;
720 case 6: 720 case 6:
721 /* 4 SMII - 460GT */ 721 /* 4 SMII - 460GT */
722 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */ 722 /* GMC0 EMAC4_0, GMC0 EMAC4_1, GMC0 EMAC4_3, GMC0 EMAC4_3 */
723 /* ZMII Bridge */ 723 /* ZMII Bridge */
724 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0); 724 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(0);
725 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1); 725 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(1);
726 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2); 726 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(2);
727 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3); 727 zmiifer |= ZMII_FER_SMII << ZMII_FER_V(3);
728 bis->bi_phymode[0] = BI_PHYMODE_SMII; 728 bis->bi_phymode[0] = BI_PHYMODE_SMII;
729 bis->bi_phymode[1] = BI_PHYMODE_SMII; 729 bis->bi_phymode[1] = BI_PHYMODE_SMII;
730 bis->bi_phymode[2] = BI_PHYMODE_SMII; 730 bis->bi_phymode[2] = BI_PHYMODE_SMII;
731 bis->bi_phymode[3] = BI_PHYMODE_SMII; 731 bis->bi_phymode[3] = BI_PHYMODE_SMII;
732 break; 732 break;
733 case 7: 733 case 7:
734 /* This is the default mode that we want for board bringup - Maple */ 734 /* This is the default mode that we want for board bringup - Maple */
735 /* 1 GMII - 460EX */ 735 /* 1 GMII - 460EX */
736 /* GMC0 EMAC4_0, RGMII Bridge 0 */ 736 /* GMC0 EMAC4_0, RGMII Bridge 0 */
737 rmiifer |= RGMII_FER_MDIO(0); 737 rmiifer |= RGMII_FER_MDIO(0);
738 738
739 if (devnum == 0) { 739 if (devnum == 0) {
740 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ 740 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
741 bis->bi_phymode[0] = BI_PHYMODE_GMII; 741 bis->bi_phymode[0] = BI_PHYMODE_GMII;
742 bis->bi_phymode[1] = BI_PHYMODE_NONE; 742 bis->bi_phymode[1] = BI_PHYMODE_NONE;
743 bis->bi_phymode[2] = BI_PHYMODE_NONE; 743 bis->bi_phymode[2] = BI_PHYMODE_NONE;
744 bis->bi_phymode[3] = BI_PHYMODE_NONE; 744 bis->bi_phymode[3] = BI_PHYMODE_NONE;
745 } else { 745 } else {
746 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */ 746 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(3); /* CH1CFG - EMAC1 */
747 bis->bi_phymode[0] = BI_PHYMODE_NONE; 747 bis->bi_phymode[0] = BI_PHYMODE_NONE;
748 bis->bi_phymode[1] = BI_PHYMODE_GMII; 748 bis->bi_phymode[1] = BI_PHYMODE_GMII;
749 bis->bi_phymode[2] = BI_PHYMODE_NONE; 749 bis->bi_phymode[2] = BI_PHYMODE_NONE;
750 bis->bi_phymode[3] = BI_PHYMODE_NONE; 750 bis->bi_phymode[3] = BI_PHYMODE_NONE;
751 } 751 }
752 break; 752 break;
753 case 8: 753 case 8:
754 /* 2 GMII - 460GT */ 754 /* 2 GMII - 460GT */
755 /* GMC0 EMAC4_0, RGMII Bridge 0 */ 755 /* GMC0 EMAC4_0, RGMII Bridge 0 */
756 /* GMC1 EMAC4_2, RGMII Bridge 1 */ 756 /* GMC1 EMAC4_2, RGMII Bridge 1 */
757 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */ 757 rmiifer |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC0 */
758 rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */ 758 rmiifer1 |= RGMII_FER_GMII << RGMII_FER_V(2); /* CH0CFG - EMAC2 */
759 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ 759 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
760 rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */ 760 rmiifer1 |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC2 */
761 761
762 bis->bi_phymode[0] = BI_PHYMODE_GMII; 762 bis->bi_phymode[0] = BI_PHYMODE_GMII;
763 bis->bi_phymode[1] = BI_PHYMODE_NONE; 763 bis->bi_phymode[1] = BI_PHYMODE_NONE;
764 bis->bi_phymode[2] = BI_PHYMODE_GMII; 764 bis->bi_phymode[2] = BI_PHYMODE_GMII;
765 bis->bi_phymode[3] = BI_PHYMODE_NONE; 765 bis->bi_phymode[3] = BI_PHYMODE_NONE;
766 break; 766 break;
767 case 9: 767 case 9:
768 /* 2 RGMII - 460EX */ 768 /* 2 RGMII - 460EX */
769 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ 769 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
770 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); 770 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
771 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); 771 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
772 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */ 772 rmiifer |= RGMII_FER_MDIO(0); /* enable MDIO - EMAC0 */
773 773
774 bis->bi_phymode[0] = BI_PHYMODE_RGMII; 774 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
775 bis->bi_phymode[1] = BI_PHYMODE_RGMII; 775 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
776 bis->bi_phymode[2] = BI_PHYMODE_NONE; 776 bis->bi_phymode[2] = BI_PHYMODE_NONE;
777 bis->bi_phymode[3] = BI_PHYMODE_NONE; 777 bis->bi_phymode[3] = BI_PHYMODE_NONE;
778 break; 778 break;
779 case 10: 779 case 10:
780 /* 4 RGMII - 460GT */ 780 /* 4 RGMII - 460GT */
781 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */ 781 /* GMC0 EMAC4_0, GMC0 EMAC4_1, RGMII Bridge 0 */
782 /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */ 782 /* GMC1 EMAC4_2, GMC1 EMAC4_3, RGMII Bridge 1 */
783 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2); 783 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(2);
784 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3); 784 rmiifer |= RGMII_FER_RGMII << RGMII_FER_V(3);
785 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2); 785 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(2);
786 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3); 786 rmiifer1 |= RGMII_FER_RGMII << RGMII_FER_V(3);
787 bis->bi_phymode[0] = BI_PHYMODE_RGMII; 787 bis->bi_phymode[0] = BI_PHYMODE_RGMII;
788 bis->bi_phymode[1] = BI_PHYMODE_RGMII; 788 bis->bi_phymode[1] = BI_PHYMODE_RGMII;
789 bis->bi_phymode[2] = BI_PHYMODE_RGMII; 789 bis->bi_phymode[2] = BI_PHYMODE_RGMII;
790 bis->bi_phymode[3] = BI_PHYMODE_RGMII; 790 bis->bi_phymode[3] = BI_PHYMODE_RGMII;
791 break; 791 break;
792 case 11: 792 case 11:
793 /* 2 SGMII - 460EX */ 793 /* 2 SGMII - 460EX */
794 bis->bi_phymode[0] = BI_PHYMODE_SGMII; 794 bis->bi_phymode[0] = BI_PHYMODE_SGMII;
795 bis->bi_phymode[1] = BI_PHYMODE_SGMII; 795 bis->bi_phymode[1] = BI_PHYMODE_SGMII;
796 bis->bi_phymode[2] = BI_PHYMODE_NONE; 796 bis->bi_phymode[2] = BI_PHYMODE_NONE;
797 bis->bi_phymode[3] = BI_PHYMODE_NONE; 797 bis->bi_phymode[3] = BI_PHYMODE_NONE;
798 break; 798 break;
799 case 12: 799 case 12:
800 /* 3 SGMII - 460GT */ 800 /* 3 SGMII - 460GT */
801 bis->bi_phymode[0] = BI_PHYMODE_SGMII; 801 bis->bi_phymode[0] = BI_PHYMODE_SGMII;
802 bis->bi_phymode[1] = BI_PHYMODE_SGMII; 802 bis->bi_phymode[1] = BI_PHYMODE_SGMII;
803 bis->bi_phymode[2] = BI_PHYMODE_SGMII; 803 bis->bi_phymode[2] = BI_PHYMODE_SGMII;
804 bis->bi_phymode[3] = BI_PHYMODE_NONE; 804 bis->bi_phymode[3] = BI_PHYMODE_NONE;
805 break; 805 break;
806 default: 806 default:
807 break; 807 break;
808 } 808 }
809 809
810 /* Set EMAC for MDIO */ 810 /* Set EMAC for MDIO */
811 mfsdr(SDR0_ETH_CFG, eth_cfg); 811 mfsdr(SDR0_ETH_CFG, eth_cfg);
812 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0; 812 eth_cfg |= SDR0_ETH_CFG_MDIO_SEL_EMAC0;
813 mtsdr(SDR0_ETH_CFG, eth_cfg); 813 mtsdr(SDR0_ETH_CFG, eth_cfg);
814 814
815 out_be32((void *)RGMII_FER, rmiifer); 815 out_be32((void *)RGMII_FER, rmiifer);
816 #if defined(CONFIG_460GT) 816 #if defined(CONFIG_460GT)
817 out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1); 817 out_be32((void *)RGMII_FER + RGMII1_BASE_OFFSET, rmiifer1);
818 #endif 818 #endif
819 819
820 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */ 820 /* bypass the TAHOE0/TAHOE1 cores for U-Boot */
821 mfsdr(SDR0_ETH_CFG, eth_cfg); 821 mfsdr(SDR0_ETH_CFG, eth_cfg);
822 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS); 822 eth_cfg |= (SDR0_ETH_CFG_TAHOE0_BYPASS | SDR0_ETH_CFG_TAHOE1_BYPASS);
823 mtsdr(SDR0_ETH_CFG, eth_cfg); 823 mtsdr(SDR0_ETH_CFG, eth_cfg);
824 824
825 return 0; 825 return 0;
826 } 826 }
827 #endif /* CONFIG_460EX || CONFIG_460GT */ 827 #endif /* CONFIG_460EX || CONFIG_460GT */
828 828
829 static inline void *malloc_aligned(u32 size, u32 align) 829 static inline void *malloc_aligned(u32 size, u32 align)
830 { 830 {
831 return (void *)(((u32)malloc(size + align) + align - 1) & 831 return (void *)(((u32)malloc(size + align) + align - 1) &
832 ~(align - 1)); 832 ~(align - 1));
833 } 833 }
834 834
835 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis) 835 static int ppc_4xx_eth_init (struct eth_device *dev, bd_t * bis)
836 { 836 {
837 int i; 837 int i;
838 unsigned long reg = 0; 838 unsigned long reg = 0;
839 unsigned long msr; 839 unsigned long msr;
840 unsigned long speed; 840 unsigned long speed;
841 unsigned long duplex; 841 unsigned long duplex;
842 unsigned long failsafe; 842 unsigned long failsafe;
843 unsigned mode_reg; 843 unsigned mode_reg;
844 unsigned short devnum; 844 unsigned short devnum;
845 unsigned short reg_short; 845 unsigned short reg_short;
846 #if defined(CONFIG_440GX) || \ 846 #if defined(CONFIG_440GX) || \
847 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 847 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
848 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ 848 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
849 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 849 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
850 defined(CONFIG_405EX) 850 defined(CONFIG_405EX)
851 u32 opbfreq; 851 u32 opbfreq;
852 sys_info_t sysinfo; 852 sys_info_t sysinfo;
853 #if defined(CONFIG_440GX) || \ 853 #if defined(CONFIG_440GX) || \
854 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 854 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
855 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 855 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
856 defined(CONFIG_405EX) 856 defined(CONFIG_405EX)
857 __maybe_unused int ethgroup = -1; 857 __maybe_unused int ethgroup = -1;
858 #endif 858 #endif
859 #endif 859 #endif
860 u32 bd_cached; 860 u32 bd_cached;
861 u32 bd_uncached = 0; 861 u32 bd_uncached = 0;
862 #ifdef CONFIG_4xx_DCACHE 862 #ifdef CONFIG_4xx_DCACHE
863 static u32 last_used_ea = 0; 863 static u32 last_used_ea = 0;
864 #endif 864 #endif
865 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 865 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
866 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 866 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
867 defined(CONFIG_405EX) 867 defined(CONFIG_405EX)
868 int rgmii_channel; 868 int rgmii_channel;
869 #endif 869 #endif
870 870
871 EMAC_4XX_HW_PST hw_p = dev->priv; 871 EMAC_4XX_HW_PST hw_p = dev->priv;
872 872
873 /* before doing anything, figure out if we have a MAC address */ 873 /* before doing anything, figure out if we have a MAC address */
874 /* if not, bail */ 874 /* if not, bail */
875 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) { 875 if (memcmp (dev->enetaddr, "\0\0\0\0\0\0", 6) == 0) {
876 printf("ERROR: ethaddr not set!\n"); 876 printf("ERROR: ethaddr not set!\n");
877 return -1; 877 return -1;
878 } 878 }
879 879
880 #if defined(CONFIG_440GX) || \ 880 #if defined(CONFIG_440GX) || \
881 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 881 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
882 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ 882 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
883 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 883 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
884 defined(CONFIG_405EX) 884 defined(CONFIG_405EX)
885 /* Need to get the OPB frequency so we can access the PHY */ 885 /* Need to get the OPB frequency so we can access the PHY */
886 get_sys_info (&sysinfo); 886 get_sys_info (&sysinfo);
887 #endif 887 #endif
888 888
889 msr = mfmsr (); 889 msr = mfmsr ();
890 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */ 890 mtmsr (msr & ~(MSR_EE)); /* disable interrupts */
891 891
892 devnum = hw_p->devnum; 892 devnum = hw_p->devnum;
893 893
894 #ifdef INFO_4XX_ENET 894 #ifdef INFO_4XX_ENET
895 /* AS.HARNOIS 895 /* AS.HARNOIS
896 * We should have : 896 * We should have :
897 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX 897 * hw_p->stats.pkts_handled <= hw_p->stats.pkts_rx <= hw_p->stats.pkts_handled+PKTBUFSRX
898 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it 898 * In the most cases hw_p->stats.pkts_handled = hw_p->stats.pkts_rx, but it
899 * is possible that new packets (without relationship with 899 * is possible that new packets (without relationship with
900 * current transfer) have got the time to arrived before 900 * current transfer) have got the time to arrived before
901 * netloop calls eth_halt 901 * netloop calls eth_halt
902 */ 902 */
903 printf ("About preceeding transfer (eth%d):\n" 903 printf ("About preceeding transfer (eth%d):\n"
904 "- Sent packet number %d\n" 904 "- Sent packet number %d\n"
905 "- Received packet number %d\n" 905 "- Received packet number %d\n"
906 "- Handled packet number %d\n", 906 "- Handled packet number %d\n",
907 hw_p->devnum, 907 hw_p->devnum,
908 hw_p->stats.pkts_tx, 908 hw_p->stats.pkts_tx,
909 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled); 909 hw_p->stats.pkts_rx, hw_p->stats.pkts_handled);
910 910
911 hw_p->stats.pkts_tx = 0; 911 hw_p->stats.pkts_tx = 0;
912 hw_p->stats.pkts_rx = 0; 912 hw_p->stats.pkts_rx = 0;
913 hw_p->stats.pkts_handled = 0; 913 hw_p->stats.pkts_handled = 0;
914 hw_p->print_speed = 1; /* print speed message again next time */ 914 hw_p->print_speed = 1; /* print speed message again next time */
915 #endif 915 #endif
916 916
917 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */ 917 hw_p->tx_err_index = 0; /* Transmit Error Index for tx_err_log */
918 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */ 918 hw_p->rx_err_index = 0; /* Receive Error Index for rx_err_log */
919 919
920 hw_p->rx_slot = 0; /* MAL Receive Slot */ 920 hw_p->rx_slot = 0; /* MAL Receive Slot */
921 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */ 921 hw_p->rx_i_index = 0; /* Receive Interrupt Queue Index */
922 hw_p->rx_u_index = 0; /* Receive User Queue Index */ 922 hw_p->rx_u_index = 0; /* Receive User Queue Index */
923 923
924 hw_p->tx_slot = 0; /* MAL Transmit Slot */ 924 hw_p->tx_slot = 0; /* MAL Transmit Slot */
925 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */ 925 hw_p->tx_i_index = 0; /* Transmit Interrupt Queue Index */
926 hw_p->tx_u_index = 0; /* Transmit User Queue Index */ 926 hw_p->tx_u_index = 0; /* Transmit User Queue Index */
927 927
928 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) 928 #if defined(CONFIG_440) && !defined(CONFIG_440SP) && !defined(CONFIG_440SPE)
929 /* set RMII mode */ 929 /* set RMII mode */
930 /* NOTE: 440GX spec states that mode is mutually exclusive */ 930 /* NOTE: 440GX spec states that mode is mutually exclusive */
931 /* NOTE: Therefore, disable all other EMACS, since we handle */ 931 /* NOTE: Therefore, disable all other EMACS, since we handle */
932 /* NOTE: only one emac at a time */ 932 /* NOTE: only one emac at a time */
933 reg = 0; 933 reg = 0;
934 out_be32((void *)ZMII0_FER, 0); 934 out_be32((void *)ZMII0_FER, 0);
935 udelay (100); 935 udelay (100);
936 936
937 #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) 937 #if defined(CONFIG_440GP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
938 out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); 938 out_be32((void *)ZMII0_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum));
939 #elif defined(CONFIG_440GX) || \ 939 #elif defined(CONFIG_440GX) || \
940 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 940 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
941 defined(CONFIG_460EX) || defined(CONFIG_460GT) 941 defined(CONFIG_460EX) || defined(CONFIG_460GT)
942 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); 942 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
943 #endif 943 #endif
944 944
945 out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum)); 945 out_be32((void *)ZMII0_SSR, ZMII0_SSR_SP << ZMII0_SSR_V(devnum));
946 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ 946 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
947 #if defined(CONFIG_405EX) 947 #if defined(CONFIG_405EX)
948 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis); 948 ethgroup = ppc_4xx_eth_setup_bridge(devnum, bis);
949 #endif 949 #endif
950 950
951 sync(); 951 sync();
952 952
953 /* provide clocks for EMAC internal loopback */ 953 /* provide clocks for EMAC internal loopback */
954 emac_loopback_enable(hw_p); 954 emac_loopback_enable(hw_p);
955 955
956 /* EMAC RESET */ 956 /* EMAC RESET */
957 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST); 957 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_SRST);
958 958
959 /* remove clocks for EMAC internal loopback */ 959 /* remove clocks for EMAC internal loopback */
960 emac_loopback_disable(hw_p); 960 emac_loopback_disable(hw_p);
961 961
962 failsafe = 1000; 962 failsafe = 1000;
963 while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) { 963 while ((in_be32((void *)EMAC0_MR0 + hw_p->hw_addr) & (EMAC_MR0_SRST)) && failsafe) {
964 udelay (1000); 964 udelay (1000);
965 failsafe--; 965 failsafe--;
966 } 966 }
967 if (failsafe <= 0) 967 if (failsafe <= 0)
968 printf("\nProblem resetting EMAC!\n"); 968 printf("\nProblem resetting EMAC!\n");
969 969
970 #if defined(CONFIG_440GX) || \ 970 #if defined(CONFIG_440GX) || \
971 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 971 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
972 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ 972 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
973 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 973 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
974 defined(CONFIG_405EX) 974 defined(CONFIG_405EX)
975 /* Whack the M1 register */ 975 /* Whack the M1 register */
976 mode_reg = 0x0; 976 mode_reg = 0x0;
977 mode_reg &= ~0x00000038; 977 mode_reg &= ~0x00000038;
978 opbfreq = sysinfo.freqOPB / 1000000; 978 opbfreq = sysinfo.freqOPB / 1000000;
979 if (opbfreq <= 50); 979 if (opbfreq <= 50);
980 else if (opbfreq <= 66) 980 else if (opbfreq <= 66)
981 mode_reg |= EMAC_MR1_OBCI_66; 981 mode_reg |= EMAC_MR1_OBCI_66;
982 else if (opbfreq <= 83) 982 else if (opbfreq <= 83)
983 mode_reg |= EMAC_MR1_OBCI_83; 983 mode_reg |= EMAC_MR1_OBCI_83;
984 else if (opbfreq <= 100) 984 else if (opbfreq <= 100)
985 mode_reg |= EMAC_MR1_OBCI_100; 985 mode_reg |= EMAC_MR1_OBCI_100;
986 else 986 else
987 mode_reg |= EMAC_MR1_OBCI_GT100; 987 mode_reg |= EMAC_MR1_OBCI_GT100;
988 988
989 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); 989 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
990 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ 990 #endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */
991 991
992 #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \ 992 #if defined(CONFIG_GPCS_PHY_ADDR) || defined(CONFIG_GPCS_PHY1_ADDR) || \
993 defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR) 993 defined(CONFIG_GPCS_PHY2_ADDR) || defined(CONFIG_GPCS_PHY3_ADDR)
994 if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { 994 if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
995 /* 995 /*
996 * In SGMII mode, GPCS access is needed for 996 * In SGMII mode, GPCS access is needed for
997 * communication with the internal SGMII SerDes. 997 * communication with the internal SGMII SerDes.
998 */ 998 */
999 switch (devnum) { 999 switch (devnum) {
1000 #if defined(CONFIG_GPCS_PHY_ADDR) 1000 #if defined(CONFIG_GPCS_PHY_ADDR)
1001 case 0: 1001 case 0:
1002 reg = CONFIG_GPCS_PHY_ADDR; 1002 reg = CONFIG_GPCS_PHY_ADDR;
1003 break; 1003 break;
1004 #endif 1004 #endif
1005 #if defined(CONFIG_GPCS_PHY1_ADDR) 1005 #if defined(CONFIG_GPCS_PHY1_ADDR)
1006 case 1: 1006 case 1:
1007 reg = CONFIG_GPCS_PHY1_ADDR; 1007 reg = CONFIG_GPCS_PHY1_ADDR;
1008 break; 1008 break;
1009 #endif 1009 #endif
1010 #if defined(CONFIG_GPCS_PHY2_ADDR) 1010 #if defined(CONFIG_GPCS_PHY2_ADDR)
1011 case 2: 1011 case 2:
1012 reg = CONFIG_GPCS_PHY2_ADDR; 1012 reg = CONFIG_GPCS_PHY2_ADDR;
1013 break; 1013 break;
1014 #endif 1014 #endif
1015 #if defined(CONFIG_GPCS_PHY3_ADDR) 1015 #if defined(CONFIG_GPCS_PHY3_ADDR)
1016 case 3: 1016 case 3:
1017 reg = CONFIG_GPCS_PHY3_ADDR; 1017 reg = CONFIG_GPCS_PHY3_ADDR;
1018 break; 1018 break;
1019 #endif 1019 #endif
1020 } 1020 }
1021 1021
1022 mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); 1022 mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
1023 mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg); 1023 mode_reg |= EMAC_MR1_MF_1000GPCS | EMAC_MR1_IPPA_SET(reg);
1024 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); 1024 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
1025 1025
1026 /* Configure GPCS interface to recommended setting for SGMII */ 1026 /* Configure GPCS interface to recommended setting for SGMII */
1027 miiphy_reset(dev->name, reg); 1027 miiphy_reset(dev->name, reg);
1028 miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */ 1028 miiphy_write(dev->name, reg, 0x04, 0x8120); /* AsymPause, FDX */
1029 miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */ 1029 miiphy_write(dev->name, reg, 0x07, 0x2801); /* msg_pg, toggle */
1030 miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */ 1030 miiphy_write(dev->name, reg, 0x00, 0x0140); /* 1Gbps, FDX */
1031 } 1031 }
1032 #endif /* defined(CONFIG_GPCS_PHY_ADDR) */ 1032 #endif /* defined(CONFIG_GPCS_PHY_ADDR) */
1033 1033
1034 /* wait for PHY to complete auto negotiation */ 1034 /* wait for PHY to complete auto negotiation */
1035 reg_short = 0; 1035 reg_short = 0;
1036 switch (devnum) { 1036 switch (devnum) {
1037 case 0: 1037 case 0:
1038 reg = CONFIG_PHY_ADDR; 1038 reg = CONFIG_PHY_ADDR;
1039 break; 1039 break;
1040 #if defined (CONFIG_PHY1_ADDR) 1040 #if defined (CONFIG_PHY1_ADDR)
1041 case 1: 1041 case 1:
1042 reg = CONFIG_PHY1_ADDR; 1042 reg = CONFIG_PHY1_ADDR;
1043 break; 1043 break;
1044 #endif 1044 #endif
1045 #if defined (CONFIG_PHY2_ADDR) 1045 #if defined (CONFIG_PHY2_ADDR)
1046 case 2: 1046 case 2:
1047 reg = CONFIG_PHY2_ADDR; 1047 reg = CONFIG_PHY2_ADDR;
1048 break; 1048 break;
1049 #endif 1049 #endif
1050 #if defined (CONFIG_PHY3_ADDR) 1050 #if defined (CONFIG_PHY3_ADDR)
1051 case 3: 1051 case 3:
1052 reg = CONFIG_PHY3_ADDR; 1052 reg = CONFIG_PHY3_ADDR;
1053 break; 1053 break;
1054 #endif 1054 #endif
1055 default: 1055 default:
1056 reg = CONFIG_PHY_ADDR; 1056 reg = CONFIG_PHY_ADDR;
1057 break; 1057 break;
1058 } 1058 }
1059 1059
1060 bis->bi_phynum[devnum] = reg; 1060 bis->bi_phynum[devnum] = reg;
1061 1061
1062 if (reg == CONFIG_FIXED_PHY) 1062 if (reg == CONFIG_FIXED_PHY)
1063 goto get_speed; 1063 goto get_speed;
1064 1064
1065 #if defined(CONFIG_PHY_RESET) 1065 #if defined(CONFIG_PHY_RESET)
1066 /* 1066 /*
1067 * Reset the phy, only if its the first time through 1067 * Reset the phy, only if its the first time through
1068 * otherwise, just check the speeds & feeds 1068 * otherwise, just check the speeds & feeds
1069 */ 1069 */
1070 if (hw_p->first_init == 0) { 1070 if (hw_p->first_init == 0) {
1071 #if defined(CONFIG_M88E1111_PHY) 1071 #if defined(CONFIG_M88E1111_PHY)
1072 miiphy_write (dev->name, reg, 0x14, 0x0ce3); 1072 miiphy_write (dev->name, reg, 0x14, 0x0ce3);
1073 miiphy_write (dev->name, reg, 0x18, 0x4101); 1073 miiphy_write (dev->name, reg, 0x18, 0x4101);
1074 miiphy_write (dev->name, reg, 0x09, 0x0e00); 1074 miiphy_write (dev->name, reg, 0x09, 0x0e00);
1075 miiphy_write (dev->name, reg, 0x04, 0x01e1); 1075 miiphy_write (dev->name, reg, 0x04, 0x01e1);
1076 #if defined(CONFIG_M88E1111_DISABLE_FIBER) 1076 #if defined(CONFIG_M88E1111_DISABLE_FIBER)
1077 miiphy_read(dev->name, reg, 0x1b, &reg_short); 1077 miiphy_read(dev->name, reg, 0x1b, &reg_short);
1078 reg_short |= 0x8000; 1078 reg_short |= 0x8000;
1079 miiphy_write(dev->name, reg, 0x1b, reg_short); 1079 miiphy_write(dev->name, reg, 0x1b, reg_short);
1080 #endif 1080 #endif
1081 #endif 1081 #endif
1082 #if defined(CONFIG_M88E1112_PHY) 1082 #if defined(CONFIG_M88E1112_PHY)
1083 if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) { 1083 if (bis->bi_phymode[devnum] == BI_PHYMODE_SGMII) {
1084 /* 1084 /*
1085 * Marvell 88E1112 PHY needs to have the SGMII MAC 1085 * Marvell 88E1112 PHY needs to have the SGMII MAC
1086 * interace (page 2) properly configured to 1086 * interace (page 2) properly configured to
1087 * communicate with the 460EX/GT GPCS interface. 1087 * communicate with the 460EX/GT GPCS interface.
1088 */ 1088 */
1089 1089
1090 /* Set access to Page 2 */ 1090 /* Set access to Page 2 */
1091 miiphy_write(dev->name, reg, 0x16, 0x0002); 1091 miiphy_write(dev->name, reg, 0x16, 0x0002);
1092 1092
1093 miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */ 1093 miiphy_write(dev->name, reg, 0x00, 0x0040); /* 1Gbps */
1094 miiphy_read(dev->name, reg, 0x1a, &reg_short); 1094 miiphy_read(dev->name, reg, 0x1a, &reg_short);
1095 reg_short |= 0x8000; /* bypass Auto-Negotiation */ 1095 reg_short |= 0x8000; /* bypass Auto-Negotiation */
1096 miiphy_write(dev->name, reg, 0x1a, reg_short); 1096 miiphy_write(dev->name, reg, 0x1a, reg_short);
1097 miiphy_reset(dev->name, reg); /* reset MAC interface */ 1097 miiphy_reset(dev->name, reg); /* reset MAC interface */
1098 1098
1099 /* Reset access to Page 0 */ 1099 /* Reset access to Page 0 */
1100 miiphy_write(dev->name, reg, 0x16, 0x0000); 1100 miiphy_write(dev->name, reg, 0x16, 0x0000);
1101 } 1101 }
1102 #endif /* defined(CONFIG_M88E1112_PHY) */ 1102 #endif /* defined(CONFIG_M88E1112_PHY) */
1103 miiphy_reset (dev->name, reg); 1103 miiphy_reset (dev->name, reg);
1104 1104
1105 #if defined(CONFIG_440GX) || \ 1105 #if defined(CONFIG_440GX) || \
1106 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 1106 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1107 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 1107 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1108 defined(CONFIG_405EX) 1108 defined(CONFIG_405EX)
1109 1109
1110 #if defined(CONFIG_CIS8201_PHY) 1110 #if defined(CONFIG_CIS8201_PHY)
1111 /* 1111 /*
1112 * Cicada 8201 PHY needs to have an extended register whacked 1112 * Cicada 8201 PHY needs to have an extended register whacked
1113 * for RGMII mode. 1113 * for RGMII mode.
1114 */ 1114 */
1115 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) { 1115 if (((devnum == 2) || (devnum == 3)) && (4 == ethgroup)) {
1116 #if defined(CONFIG_CIS8201_SHORT_ETCH) 1116 #if defined(CONFIG_CIS8201_SHORT_ETCH)
1117 miiphy_write (dev->name, reg, 23, 0x1300); 1117 miiphy_write (dev->name, reg, 23, 0x1300);
1118 #else 1118 #else
1119 miiphy_write (dev->name, reg, 23, 0x1000); 1119 miiphy_write (dev->name, reg, 23, 0x1000);
1120 #endif 1120 #endif
1121 /* 1121 /*
1122 * Vitesse VSC8201/Cicada CIS8201 errata: 1122 * Vitesse VSC8201/Cicada CIS8201 errata:
1123 * Interoperability problem with Intel 82547EI phys 1123 * Interoperability problem with Intel 82547EI phys
1124 * This work around (provided by Vitesse) changes 1124 * This work around (provided by Vitesse) changes
1125 * the default timer convergence from 8ms to 12ms 1125 * the default timer convergence from 8ms to 12ms
1126 */ 1126 */
1127 miiphy_write (dev->name, reg, 0x1f, 0x2a30); 1127 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1128 miiphy_write (dev->name, reg, 0x08, 0x0200); 1128 miiphy_write (dev->name, reg, 0x08, 0x0200);
1129 miiphy_write (dev->name, reg, 0x1f, 0x52b5); 1129 miiphy_write (dev->name, reg, 0x1f, 0x52b5);
1130 miiphy_write (dev->name, reg, 0x02, 0x0004); 1130 miiphy_write (dev->name, reg, 0x02, 0x0004);
1131 miiphy_write (dev->name, reg, 0x01, 0x0671); 1131 miiphy_write (dev->name, reg, 0x01, 0x0671);
1132 miiphy_write (dev->name, reg, 0x00, 0x8fae); 1132 miiphy_write (dev->name, reg, 0x00, 0x8fae);
1133 miiphy_write (dev->name, reg, 0x1f, 0x2a30); 1133 miiphy_write (dev->name, reg, 0x1f, 0x2a30);
1134 miiphy_write (dev->name, reg, 0x08, 0x0000); 1134 miiphy_write (dev->name, reg, 0x08, 0x0000);
1135 miiphy_write (dev->name, reg, 0x1f, 0x0000); 1135 miiphy_write (dev->name, reg, 0x1f, 0x0000);
1136 /* end Vitesse/Cicada errata */ 1136 /* end Vitesse/Cicada errata */
1137 } 1137 }
1138 #endif /* defined(CONFIG_CIS8201_PHY) */ 1138 #endif /* defined(CONFIG_CIS8201_PHY) */
1139 1139
1140 #if defined(CONFIG_ET1011C_PHY) 1140 #if defined(CONFIG_ET1011C_PHY)
1141 /* 1141 /*
1142 * Agere ET1011c PHY needs to have an extended register whacked 1142 * Agere ET1011c PHY needs to have an extended register whacked
1143 * for RGMII mode. 1143 * for RGMII mode.
1144 */ 1144 */
1145 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) { 1145 if (((devnum == 2) || (devnum ==3)) && (4 == ethgroup)) {
1146 miiphy_read (dev->name, reg, 0x16, &reg_short); 1146 miiphy_read (dev->name, reg, 0x16, &reg_short);
1147 reg_short &= ~(0x7); 1147 reg_short &= ~(0x7);
1148 reg_short |= 0x6; /* RGMII DLL Delay*/ 1148 reg_short |= 0x6; /* RGMII DLL Delay*/
1149 miiphy_write (dev->name, reg, 0x16, reg_short); 1149 miiphy_write (dev->name, reg, 0x16, reg_short);
1150 1150
1151 miiphy_read (dev->name, reg, 0x17, &reg_short); 1151 miiphy_read (dev->name, reg, 0x17, &reg_short);
1152 reg_short &= ~(0x40); 1152 reg_short &= ~(0x40);
1153 miiphy_write (dev->name, reg, 0x17, reg_short); 1153 miiphy_write (dev->name, reg, 0x17, reg_short);
1154 1154
1155 miiphy_write(dev->name, reg, 0x1c, 0x74f0); 1155 miiphy_write(dev->name, reg, 0x1c, 0x74f0);
1156 } 1156 }
1157 #endif /* defined(CONFIG_ET1011C_PHY) */ 1157 #endif /* defined(CONFIG_ET1011C_PHY) */
1158 1158
1159 #endif /* defined(CONFIG_440GX) ... */ 1159 #endif /* defined(CONFIG_440GX) ... */
1160 /* Start/Restart autonegotiation */ 1160 /* Start/Restart autonegotiation */
1161 phy_setup_aneg (dev->name, reg); 1161 phy_setup_aneg (dev->name, reg);
1162 udelay (1000); 1162 udelay (1000);
1163 } 1163 }
1164 #endif /* defined(CONFIG_PHY_RESET) */ 1164 #endif /* defined(CONFIG_PHY_RESET) */
1165 1165
1166 miiphy_read (dev->name, reg, MII_BMSR, &reg_short); 1166 miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
1167 1167
1168 /* 1168 /*
1169 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete 1169 * Wait if PHY is capable of autonegotiation and autonegotiation is not complete
1170 */ 1170 */
1171 if ((reg_short & BMSR_ANEGCAPABLE) 1171 if ((reg_short & BMSR_ANEGCAPABLE)
1172 && !(reg_short & BMSR_ANEGCOMPLETE)) { 1172 && !(reg_short & BMSR_ANEGCOMPLETE)) {
1173 puts ("Waiting for PHY auto negotiation to complete"); 1173 puts ("Waiting for PHY auto negotiation to complete");
1174 i = 0; 1174 i = 0;
1175 while (!(reg_short & BMSR_ANEGCOMPLETE)) { 1175 while (!(reg_short & BMSR_ANEGCOMPLETE)) {
1176 /* 1176 /*
1177 * Timeout reached ? 1177 * Timeout reached ?
1178 */ 1178 */
1179 if (i > PHY_AUTONEGOTIATE_TIMEOUT) { 1179 if (i > PHY_AUTONEGOTIATE_TIMEOUT) {
1180 puts (" TIMEOUT !\n"); 1180 puts (" TIMEOUT !\n");
1181 break; 1181 break;
1182 } 1182 }
1183 1183
1184 if ((i++ % 1000) == 0) { 1184 if ((i++ % 1000) == 0) {
1185 putc ('.'); 1185 putc ('.');
1186 } 1186 }
1187 udelay (1000); /* 1 ms */ 1187 udelay (1000); /* 1 ms */
1188 miiphy_read (dev->name, reg, MII_BMSR, &reg_short); 1188 miiphy_read (dev->name, reg, MII_BMSR, &reg_short);
1189 } 1189 }
1190 puts (" done\n"); 1190 puts (" done\n");
1191 udelay (500000); /* another 500 ms (results in faster booting) */ 1191 udelay (500000); /* another 500 ms (results in faster booting) */
1192 } 1192 }
1193 1193
1194 get_speed: 1194 get_speed:
1195 if (reg == CONFIG_FIXED_PHY) { 1195 if (reg == CONFIG_FIXED_PHY) {
1196 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { 1196 for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) {
1197 if (devnum == fixed_phy_port[i].devnum) { 1197 if (devnum == fixed_phy_port[i].devnum) {
1198 speed = fixed_phy_port[i].speed; 1198 speed = fixed_phy_port[i].speed;
1199 duplex = fixed_phy_port[i].duplex; 1199 duplex = fixed_phy_port[i].duplex;
1200 break; 1200 break;
1201 } 1201 }
1202 } 1202 }
1203 1203
1204 if (i == ARRAY_SIZE(fixed_phy_port)) { 1204 if (i == ARRAY_SIZE(fixed_phy_port)) {
1205 printf("ERROR: PHY (%s) not configured correctly!\n", 1205 printf("ERROR: PHY (%s) not configured correctly!\n",
1206 dev->name); 1206 dev->name);
1207 return -1; 1207 return -1;
1208 } 1208 }
1209 } else { 1209 } else {
1210 speed = miiphy_speed(dev->name, reg); 1210 speed = miiphy_speed(dev->name, reg);
1211 duplex = miiphy_duplex(dev->name, reg); 1211 duplex = miiphy_duplex(dev->name, reg);
1212 } 1212 }
1213 1213
1214 if (hw_p->print_speed) { 1214 if (hw_p->print_speed) {
1215 hw_p->print_speed = 0; 1215 hw_p->print_speed = 0;
1216 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n", 1216 printf ("ENET Speed is %d Mbps - %s duplex connection (EMAC%d)\n",
1217 (int) speed, (duplex == HALF) ? "HALF" : "FULL", 1217 (int) speed, (duplex == HALF) ? "HALF" : "FULL",
1218 hw_p->devnum); 1218 hw_p->devnum);
1219 } 1219 }
1220 1220
1221 #if defined(CONFIG_440) && \ 1221 #if defined(CONFIG_440) && \
1222 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \ 1222 !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) && \
1223 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ 1223 !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \
1224 !defined(CONFIG_460EX) && !defined(CONFIG_460GT) 1224 !defined(CONFIG_460EX) && !defined(CONFIG_460GT)
1225 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) 1225 #if defined(CONFIG_440EP) || defined(CONFIG_440GR)
1226 mfsdr(SDR0_MFR, reg); 1226 mfsdr(SDR0_MFR, reg);
1227 if (speed == 100) { 1227 if (speed == 100) {
1228 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; 1228 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M;
1229 } else { 1229 } else {
1230 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M; 1230 reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_10M;
1231 } 1231 }
1232 mtsdr(SDR0_MFR, reg); 1232 mtsdr(SDR0_MFR, reg);
1233 #endif 1233 #endif
1234 1234
1235 /* Set ZMII/RGMII speed according to the phy link speed */ 1235 /* Set ZMII/RGMII speed according to the phy link speed */
1236 reg = in_be32((void *)ZMII0_SSR); 1236 reg = in_be32((void *)ZMII0_SSR);
1237 if ( (speed == 100) || (speed == 1000) ) 1237 if ( (speed == 100) || (speed == 1000) )
1238 out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum))); 1238 out_be32((void *)ZMII0_SSR, reg | (ZMII0_SSR_SP << ZMII0_SSR_V (devnum)));
1239 else 1239 else
1240 out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum)))); 1240 out_be32((void *)ZMII0_SSR, reg & (~(ZMII0_SSR_SP << ZMII0_SSR_V (devnum))));
1241 1241
1242 if ((devnum == 2) || (devnum == 3)) { 1242 if ((devnum == 2) || (devnum == 3)) {
1243 if (speed == 1000) 1243 if (speed == 1000)
1244 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum)); 1244 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V (devnum));
1245 else if (speed == 100) 1245 else if (speed == 100)
1246 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum)); 1246 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V (devnum));
1247 else if (speed == 10) 1247 else if (speed == 10)
1248 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum)); 1248 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V (devnum));
1249 else { 1249 else {
1250 printf("Error in RGMII Speed\n"); 1250 printf("Error in RGMII Speed\n");
1251 return -1; 1251 return -1;
1252 } 1252 }
1253 out_be32((void *)RGMII_SSR, reg); 1253 out_be32((void *)RGMII_SSR, reg);
1254 } 1254 }
1255 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */ 1255 #endif /* defined(CONFIG_440) && !defined(CONFIG_440SP) */
1256 1256
1257 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 1257 #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1258 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 1258 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1259 defined(CONFIG_405EX) 1259 defined(CONFIG_405EX)
1260 if (devnum >= 2) 1260 if (devnum >= 2)
1261 rgmii_channel = devnum - 2; 1261 rgmii_channel = devnum - 2;
1262 else 1262 else
1263 rgmii_channel = devnum; 1263 rgmii_channel = devnum;
1264 1264
1265 if (speed == 1000) 1265 if (speed == 1000)
1266 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel)); 1266 reg = (RGMII_SSR_SP_1000MBPS << RGMII_SSR_V(rgmii_channel));
1267 else if (speed == 100) 1267 else if (speed == 100)
1268 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel)); 1268 reg = (RGMII_SSR_SP_100MBPS << RGMII_SSR_V(rgmii_channel));
1269 else if (speed == 10) 1269 else if (speed == 10)
1270 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel)); 1270 reg = (RGMII_SSR_SP_10MBPS << RGMII_SSR_V(rgmii_channel));
1271 else { 1271 else {
1272 printf("Error in RGMII Speed\n"); 1272 printf("Error in RGMII Speed\n");
1273 return -1; 1273 return -1;
1274 } 1274 }
1275 out_be32((void *)RGMII_SSR, reg); 1275 out_be32((void *)RGMII_SSR, reg);
1276 #if defined(CONFIG_460GT) 1276 #if defined(CONFIG_460GT)
1277 if ((devnum == 2) || (devnum == 3)) 1277 if ((devnum == 2) || (devnum == 3))
1278 out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg); 1278 out_be32((void *)RGMII_SSR + RGMII1_BASE_OFFSET, reg);
1279 #endif 1279 #endif
1280 #endif 1280 #endif
1281 1281
1282 /* set the Mal configuration reg */ 1282 /* set the Mal configuration reg */
1283 #if defined(CONFIG_440GX) || \ 1283 #if defined(CONFIG_440GX) || \
1284 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 1284 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1285 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ 1285 defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
1286 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 1286 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
1287 defined(CONFIG_405EX) 1287 defined(CONFIG_405EX)
1288 mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | 1288 mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA |
1289 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); 1289 MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000);
1290 #else 1290 #else
1291 mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT); 1291 mtdcr (MAL0_CFG, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT);
1292 /* Errata 1.12: MAL_1 -- Disable MAL bursting */ 1292 /* Errata 1.12: MAL_1 -- Disable MAL bursting */
1293 if (get_pvr() == PVR_440GP_RB) { 1293 if (get_pvr() == PVR_440GP_RB) {
1294 mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB); 1294 mtdcr (MAL0_CFG, mfdcr(MAL0_CFG) & ~MAL_CR_PLBB);
1295 } 1295 }
1296 #endif 1296 #endif
1297 1297
1298 /* 1298 /*
1299 * Malloc MAL buffer desciptors, make sure they are 1299 * Malloc MAL buffer desciptors, make sure they are
1300 * aligned on cache line boundary size 1300 * aligned on cache line boundary size
1301 * (401/403/IOP480 = 16, 405 = 32) 1301 * (401/403/IOP480 = 16, 405 = 32)
1302 * and doesn't cross cache block boundaries. 1302 * and doesn't cross cache block boundaries.
1303 */ 1303 */
1304 if (hw_p->first_init == 0) { 1304 if (hw_p->first_init == 0) {
1305 debug("*** Allocating descriptor memory ***\n"); 1305 debug("*** Allocating descriptor memory ***\n");
1306 1306
1307 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096); 1307 bd_cached = (u32)malloc_aligned(MAL_ALLOC_SIZE, 4096);
1308 if (!bd_cached) { 1308 if (!bd_cached) {
1309 printf("%s: Error allocating MAL descriptor buffers!\n", __func__); 1309 printf("%s: Error allocating MAL descriptor buffers!\n", __func__);
1310 return -1; 1310 return -1;
1311 } 1311 }
1312 1312
1313 #ifdef CONFIG_4xx_DCACHE 1313 #ifdef CONFIG_4xx_DCACHE
1314 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE); 1314 flush_dcache_range(bd_cached, bd_cached + MAL_ALLOC_SIZE);
1315 if (!last_used_ea) 1315 if (!last_used_ea)
1316 #if defined(CONFIG_SYS_MEM_TOP_HIDE) 1316 #if defined(CONFIG_SYS_MEM_TOP_HIDE)
1317 bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE; 1317 bd_uncached = bis->bi_memsize + CONFIG_SYS_MEM_TOP_HIDE;
1318 #else 1318 #else
1319 bd_uncached = bis->bi_memsize; 1319 bd_uncached = bis->bi_memsize;
1320 #endif 1320 #endif
1321 else 1321 else
1322 bd_uncached = last_used_ea + MAL_ALLOC_SIZE; 1322 bd_uncached = last_used_ea + MAL_ALLOC_SIZE;
1323 1323
1324 last_used_ea = bd_uncached; 1324 last_used_ea = bd_uncached;
1325 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE, 1325 program_tlb(bd_cached, bd_uncached, MAL_ALLOC_SIZE,
1326 TLB_WORD2_I_ENABLE); 1326 TLB_WORD2_I_ENABLE);
1327 #else 1327 #else
1328 bd_uncached = bd_cached; 1328 bd_uncached = bd_cached;
1329 #endif 1329 #endif
1330 hw_p->tx_phys = bd_cached; 1330 hw_p->tx_phys = bd_cached;
1331 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE; 1331 hw_p->rx_phys = bd_cached + MAL_TX_DESC_SIZE;
1332 hw_p->tx = (mal_desc_t *)(bd_uncached); 1332 hw_p->tx = (mal_desc_t *)(bd_uncached);
1333 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE); 1333 hw_p->rx = (mal_desc_t *)(bd_uncached + MAL_TX_DESC_SIZE);
1334 debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx); 1334 debug("hw_p->tx=%p, hw_p->rx=%p\n", hw_p->tx, hw_p->rx);
1335 } 1335 }
1336 1336
1337 for (i = 0; i < NUM_TX_BUFF; i++) { 1337 for (i = 0; i < NUM_TX_BUFF; i++) {
1338 hw_p->tx[i].ctrl = 0; 1338 hw_p->tx[i].ctrl = 0;
1339 hw_p->tx[i].data_len = 0; 1339 hw_p->tx[i].data_len = 0;
1340 if (hw_p->first_init == 0) 1340 if (hw_p->first_init == 0)
1341 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE, 1341 hw_p->txbuf_ptr = malloc_aligned(MAL_ALLOC_SIZE,
1342 L1_CACHE_BYTES); 1342 L1_CACHE_BYTES);
1343 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr; 1343 hw_p->tx[i].data_ptr = hw_p->txbuf_ptr;
1344 if ((NUM_TX_BUFF - 1) == i) 1344 if ((NUM_TX_BUFF - 1) == i)
1345 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP; 1345 hw_p->tx[i].ctrl |= MAL_TX_CTRL_WRAP;
1346 hw_p->tx_run[i] = -1; 1346 hw_p->tx_run[i] = -1;
1347 debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr); 1347 debug("TX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->tx[i].data_ptr);
1348 } 1348 }
1349 1349
1350 for (i = 0; i < NUM_RX_BUFF; i++) { 1350 for (i = 0; i < NUM_RX_BUFF; i++) {
1351 hw_p->rx[i].ctrl = 0; 1351 hw_p->rx[i].ctrl = 0;
1352 hw_p->rx[i].data_len = 0; 1352 hw_p->rx[i].data_len = 0;
1353 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i]; 1353 hw_p->rx[i].data_ptr = (char *)NetRxPackets[i];
1354 if ((NUM_RX_BUFF - 1) == i) 1354 if ((NUM_RX_BUFF - 1) == i)
1355 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP; 1355 hw_p->rx[i].ctrl |= MAL_RX_CTRL_WRAP;
1356 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR; 1356 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY | MAL_RX_CTRL_INTR;
1357 hw_p->rx_ready[i] = -1; 1357 hw_p->rx_ready[i] = -1;
1358 debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr); 1358 debug("RX_BUFF %d @ 0x%08x\n", i, (u32)hw_p->rx[i].data_ptr);
1359 } 1359 }
1360 1360
1361 reg = 0x00000000; 1361 reg = 0x00000000;
1362 1362
1363 reg |= dev->enetaddr[0]; /* set high address */ 1363 reg |= dev->enetaddr[0]; /* set high address */
1364 reg = reg << 8; 1364 reg = reg << 8;
1365 reg |= dev->enetaddr[1]; 1365 reg |= dev->enetaddr[1];
1366 1366
1367 out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg); 1367 out_be32((void *)EMAC0_IAH + hw_p->hw_addr, reg);
1368 1368
1369 reg = 0x00000000; 1369 reg = 0x00000000;
1370 reg |= dev->enetaddr[2]; /* set low address */ 1370 reg |= dev->enetaddr[2]; /* set low address */
1371 reg = reg << 8; 1371 reg = reg << 8;
1372 reg |= dev->enetaddr[3]; 1372 reg |= dev->enetaddr[3];
1373 reg = reg << 8; 1373 reg = reg << 8;
1374 reg |= dev->enetaddr[4]; 1374 reg |= dev->enetaddr[4];
1375 reg = reg << 8; 1375 reg = reg << 8;
1376 reg |= dev->enetaddr[5]; 1376 reg |= dev->enetaddr[5];
1377 1377
1378 out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg); 1378 out_be32((void *)EMAC0_IAL + hw_p->hw_addr, reg);
1379 1379
1380 switch (devnum) { 1380 switch (devnum) {
1381 case 1: 1381 case 1:
1382 /* setup MAL tx & rx channel pointers */ 1382 /* setup MAL tx & rx channel pointers */
1383 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR) 1383 #if defined (CONFIG_405EP) || defined (CONFIG_440EP) || defined (CONFIG_440GR)
1384 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); 1384 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
1385 #else 1385 #else
1386 mtdcr (MAL0_TXCTP1R, hw_p->tx_phys); 1386 mtdcr (MAL0_TXCTP1R, hw_p->tx_phys);
1387 #endif 1387 #endif
1388 #if defined(CONFIG_440) 1388 #if defined(CONFIG_440)
1389 mtdcr (MAL0_TXBADDR, 0x0); 1389 mtdcr (MAL0_TXBADDR, 0x0);
1390 mtdcr (MAL0_RXBADDR, 0x0); 1390 mtdcr (MAL0_RXBADDR, 0x0);
1391 #endif 1391 #endif
1392 1392
1393 #if defined(CONFIG_460EX) || defined(CONFIG_460GT) 1393 #if defined(CONFIG_460EX) || defined(CONFIG_460GT)
1394 mtdcr (MAL0_RXCTP8R, hw_p->rx_phys); 1394 mtdcr (MAL0_RXCTP8R, hw_p->rx_phys);
1395 /* set RX buffer size */ 1395 /* set RX buffer size */
1396 mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16); 1396 mtdcr (MAL0_RCBS8, ENET_MAX_MTU_ALIGNED / 16);
1397 #else 1397 #else
1398 mtdcr (MAL0_RXCTP1R, hw_p->rx_phys); 1398 mtdcr (MAL0_RXCTP1R, hw_p->rx_phys);
1399 /* set RX buffer size */ 1399 /* set RX buffer size */
1400 mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16); 1400 mtdcr (MAL0_RCBS1, ENET_MAX_MTU_ALIGNED / 16);
1401 #endif 1401 #endif
1402 break; 1402 break;
1403 #if defined (CONFIG_440GX) 1403 #if defined (CONFIG_440GX)
1404 case 2: 1404 case 2:
1405 /* setup MAL tx & rx channel pointers */ 1405 /* setup MAL tx & rx channel pointers */
1406 mtdcr (MAL0_TXBADDR, 0x0); 1406 mtdcr (MAL0_TXBADDR, 0x0);
1407 mtdcr (MAL0_RXBADDR, 0x0); 1407 mtdcr (MAL0_RXBADDR, 0x0);
1408 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); 1408 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
1409 mtdcr (MAL0_RXCTP2R, hw_p->rx_phys); 1409 mtdcr (MAL0_RXCTP2R, hw_p->rx_phys);
1410 /* set RX buffer size */ 1410 /* set RX buffer size */
1411 mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16); 1411 mtdcr (MAL0_RCBS2, ENET_MAX_MTU_ALIGNED / 16);
1412 break; 1412 break;
1413 case 3: 1413 case 3:
1414 /* setup MAL tx & rx channel pointers */ 1414 /* setup MAL tx & rx channel pointers */
1415 mtdcr (MAL0_TXBADDR, 0x0); 1415 mtdcr (MAL0_TXBADDR, 0x0);
1416 mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); 1416 mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
1417 mtdcr (MAL0_RXBADDR, 0x0); 1417 mtdcr (MAL0_RXBADDR, 0x0);
1418 mtdcr (MAL0_RXCTP3R, hw_p->rx_phys); 1418 mtdcr (MAL0_RXCTP3R, hw_p->rx_phys);
1419 /* set RX buffer size */ 1419 /* set RX buffer size */
1420 mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16); 1420 mtdcr (MAL0_RCBS3, ENET_MAX_MTU_ALIGNED / 16);
1421 break; 1421 break;
1422 #endif /* CONFIG_440GX */ 1422 #endif /* CONFIG_440GX */
1423 #if defined (CONFIG_460GT) 1423 #if defined (CONFIG_460GT)
1424 case 2: 1424 case 2:
1425 /* setup MAL tx & rx channel pointers */ 1425 /* setup MAL tx & rx channel pointers */
1426 mtdcr (MAL0_TXBADDR, 0x0); 1426 mtdcr (MAL0_TXBADDR, 0x0);
1427 mtdcr (MAL0_RXBADDR, 0x0); 1427 mtdcr (MAL0_RXBADDR, 0x0);
1428 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys); 1428 mtdcr (MAL0_TXCTP2R, hw_p->tx_phys);
1429 mtdcr (MAL0_RXCTP16R, hw_p->rx_phys); 1429 mtdcr (MAL0_RXCTP16R, hw_p->rx_phys);
1430 /* set RX buffer size */ 1430 /* set RX buffer size */
1431 mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16); 1431 mtdcr (MAL0_RCBS16, ENET_MAX_MTU_ALIGNED / 16);
1432 break; 1432 break;
1433 case 3: 1433 case 3:
1434 /* setup MAL tx & rx channel pointers */ 1434 /* setup MAL tx & rx channel pointers */
1435 mtdcr (MAL0_TXBADDR, 0x0); 1435 mtdcr (MAL0_TXBADDR, 0x0);
1436 mtdcr (MAL0_RXBADDR, 0x0); 1436 mtdcr (MAL0_RXBADDR, 0x0);
1437 mtdcr (MAL0_TXCTP3R, hw_p->tx_phys); 1437 mtdcr (MAL0_TXCTP3R, hw_p->tx_phys);
1438 mtdcr (MAL0_RXCTP24R, hw_p->rx_phys); 1438 mtdcr (MAL0_RXCTP24R, hw_p->rx_phys);
1439 /* set RX buffer size */ 1439 /* set RX buffer size */
1440 mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16); 1440 mtdcr (MAL0_RCBS24, ENET_MAX_MTU_ALIGNED / 16);
1441 break; 1441 break;
1442 #endif /* CONFIG_460GT */ 1442 #endif /* CONFIG_460GT */
1443 case 0: 1443 case 0:
1444 default: 1444 default:
1445 /* setup MAL tx & rx channel pointers */ 1445 /* setup MAL tx & rx channel pointers */
1446 #if defined(CONFIG_440) 1446 #if defined(CONFIG_440)
1447 mtdcr (MAL0_TXBADDR, 0x0); 1447 mtdcr (MAL0_TXBADDR, 0x0);
1448 mtdcr (MAL0_RXBADDR, 0x0); 1448 mtdcr (MAL0_RXBADDR, 0x0);
1449 #endif 1449 #endif
1450 mtdcr (MAL0_TXCTP0R, hw_p->tx_phys); 1450 mtdcr (MAL0_TXCTP0R, hw_p->tx_phys);
1451 mtdcr (MAL0_RXCTP0R, hw_p->rx_phys); 1451 mtdcr (MAL0_RXCTP0R, hw_p->rx_phys);
1452 /* set RX buffer size */ 1452 /* set RX buffer size */
1453 mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16); 1453 mtdcr (MAL0_RCBS0, ENET_MAX_MTU_ALIGNED / 16);
1454 break; 1454 break;
1455 } 1455 }
1456 1456
1457 /* Enable MAL transmit and receive channels */ 1457 /* Enable MAL transmit and receive channels */
1458 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR) 1458 #if defined(CONFIG_405EP) || defined(CONFIG_440EP) || defined(CONFIG_440GR)
1459 mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2))); 1459 mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> (hw_p->devnum*2)));
1460 #else 1460 #else
1461 mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); 1461 mtdcr (MAL0_TXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
1462 #endif 1462 #endif
1463 mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum)); 1463 mtdcr (MAL0_RXCASR, (MAL_TXRX_CASR >> hw_p->devnum));
1464 1464
1465 /* set transmit enable & receive enable */ 1465 /* set transmit enable & receive enable */
1466 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE); 1466 out_be32((void *)EMAC0_MR0 + hw_p->hw_addr, EMAC_MR0_TXE | EMAC_MR0_RXE);
1467 1467
1468 mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr); 1468 mode_reg = in_be32((void *)EMAC0_MR1 + hw_p->hw_addr);
1469 1469
1470 /* set rx-/tx-fifo size */ 1470 /* set rx-/tx-fifo size */
1471 mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE; 1471 mode_reg = (mode_reg & ~EMAC_MR1_FIFO_MASK) | EMAC_MR1_FIFO_SIZE;
1472 1472
1473 /* set speed */ 1473 /* set speed */
1474 if (speed == _1000BASET) { 1474 if (speed == _1000BASET) {
1475 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) 1475 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE)
1476 unsigned long pfc1; 1476 unsigned long pfc1;
1477 1477
1478 mfsdr (SDR0_PFC1, pfc1); 1478 mfsdr (SDR0_PFC1, pfc1);
1479 pfc1 |= SDR0_PFC1_EM_1000; 1479 pfc1 |= SDR0_PFC1_EM_1000;
1480 mtsdr (SDR0_PFC1, pfc1); 1480 mtsdr (SDR0_PFC1, pfc1);
1481 #endif 1481 #endif
1482 mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST; 1482 mode_reg = mode_reg | EMAC_MR1_MF_1000MBPS | EMAC_MR1_IST;
1483 } else if (speed == _100BASET) 1483 } else if (speed == _100BASET)
1484 mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST; 1484 mode_reg = mode_reg | EMAC_MR1_MF_100MBPS | EMAC_MR1_IST;
1485 else 1485 else
1486 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */ 1486 mode_reg = mode_reg & ~0x00C00000; /* 10 MBPS */
1487 if (duplex == FULL) 1487 if (duplex == FULL)
1488 mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST; 1488 mode_reg = mode_reg | 0x80000000 | EMAC_MR1_IST;
1489 1489
1490 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg); 1490 out_be32((void *)EMAC0_MR1 + hw_p->hw_addr, mode_reg);
1491 1491
1492 /* Enable broadcast and indvidual address */ 1492 /* Enable broadcast and indvidual address */
1493 /* TBS: enabling runts as some misbehaved nics will send runts */ 1493 /* TBS: enabling runts as some misbehaved nics will send runts */
1494 out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE); 1494 out_be32((void *)EMAC0_RXM + hw_p->hw_addr, EMAC_RMR_BAE | EMAC_RMR_IAE);
1495 1495
1496 /* we probably need to set the tx mode1 reg? maybe at tx time */ 1496 /* we probably need to set the tx mode1 reg? maybe at tx time */
1497 1497
1498 /* set transmit request threshold register */ 1498 /* set transmit request threshold register */
1499 out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */ 1499 out_be32((void *)EMAC0_TRTR + hw_p->hw_addr, 0x18000000); /* 256 byte threshold */
1500 1500
1501 /* set receive low/high water mark register */ 1501 /* set receive low/high water mark register */
1502 #if defined(CONFIG_440) 1502 #if defined(CONFIG_440)
1503 /* 440s has a 64 byte burst length */ 1503 /* 440s has a 64 byte burst length */
1504 out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000); 1504 out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x80009000);
1505 #else 1505 #else
1506 /* 405s have a 16 byte burst length */ 1506 /* 405s have a 16 byte burst length */
1507 out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000); 1507 out_be32((void *)EMAC0_RX_HI_LO_WMARK + hw_p->hw_addr, 0x0f002000);
1508 #endif /* defined(CONFIG_440) */ 1508 #endif /* defined(CONFIG_440) */
1509 out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000); 1509 out_be32((void *)EMAC0_TMR1 + hw_p->hw_addr, 0xf8640000);
1510 1510
1511 /* Set fifo limit entry in tx mode 0 */ 1511 /* Set fifo limit entry in tx mode 0 */
1512 out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003); 1512 out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 0x00000003);
1513 /* Frame gap set */ 1513 /* Frame gap set */
1514 out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008); 1514 out_be32((void *)EMAC0_I_FRAME_GAP_REG + hw_p->hw_addr, 0x00000008);
1515 1515
1516 /* Set EMAC IER */ 1516 /* Set EMAC IER */
1517 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE; 1517 hw_p->emac_ier = EMAC_ISR_PTLE | EMAC_ISR_BFCS | EMAC_ISR_ORE | EMAC_ISR_IRE;
1518 if (speed == _100BASET) 1518 if (speed == _100BASET)
1519 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE; 1519 hw_p->emac_ier = hw_p->emac_ier | EMAC_ISR_SYE;
1520 1520
1521 out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */ 1521 out_be32((void *)EMAC0_ISR + hw_p->hw_addr, 0xffffffff); /* clear pending interrupts */
1522 out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier); 1522 out_be32((void *)EMAC0_IER + hw_p->hw_addr, hw_p->emac_ier);
1523 1523
1524 if (hw_p->first_init == 0) { 1524 if (hw_p->first_init == 0) {
1525 /* 1525 /*
1526 * Connect interrupt service routines 1526 * Connect interrupt service routines
1527 */ 1527 */
1528 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum), 1528 irq_install_handler(ETH_IRQ_NUM(hw_p->devnum),
1529 (interrupt_handler_t *) enetInt, dev); 1529 (interrupt_handler_t *) enetInt, dev);
1530 } 1530 }
1531 1531
1532 mtmsr (msr); /* enable interrupts again */ 1532 mtmsr (msr); /* enable interrupts again */
1533 1533
1534 hw_p->bis = bis; 1534 hw_p->bis = bis;
1535 hw_p->first_init = 1; 1535 hw_p->first_init = 1;
1536 1536
1537 return 0; 1537 return 0;
1538 } 1538 }
1539 1539
1540 1540
1541 static int ppc_4xx_eth_send(struct eth_device *dev, void *ptr, int len) 1541 static int ppc_4xx_eth_send(struct eth_device *dev, void *ptr, int len)
1542 { 1542 {
1543 struct enet_frame *ef_ptr; 1543 struct enet_frame *ef_ptr;
1544 ulong time_start, time_now; 1544 ulong time_start, time_now;
1545 unsigned long temp_txm0; 1545 unsigned long temp_txm0;
1546 EMAC_4XX_HW_PST hw_p = dev->priv; 1546 EMAC_4XX_HW_PST hw_p = dev->priv;
1547 1547
1548 ef_ptr = (struct enet_frame *) ptr; 1548 ef_ptr = (struct enet_frame *) ptr;
1549 1549
1550 /*-----------------------------------------------------------------------+ 1550 /*-----------------------------------------------------------------------+
1551 * Copy in our address into the frame. 1551 * Copy in our address into the frame.
1552 *-----------------------------------------------------------------------*/ 1552 *-----------------------------------------------------------------------*/
1553 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH); 1553 (void) memcpy (ef_ptr->source_addr, dev->enetaddr, ENET_ADDR_LENGTH);
1554 1554
1555 /*-----------------------------------------------------------------------+ 1555 /*-----------------------------------------------------------------------+
1556 * If frame is too long or too short, modify length. 1556 * If frame is too long or too short, modify length.
1557 *-----------------------------------------------------------------------*/ 1557 *-----------------------------------------------------------------------*/
1558 /* TBS: where does the fragment go???? */ 1558 /* TBS: where does the fragment go???? */
1559 if (len > ENET_MAX_MTU) 1559 if (len > ENET_MAX_MTU)
1560 len = ENET_MAX_MTU; 1560 len = ENET_MAX_MTU;
1561 1561
1562 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */ 1562 /* memcpy ((void *) &tx_buff[tx_slot], (const void *) ptr, len); */
1563 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len); 1563 memcpy ((void *) hw_p->txbuf_ptr, (const void *) ptr, len);
1564 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len); 1564 flush_dcache_range((u32)hw_p->txbuf_ptr, (u32)hw_p->txbuf_ptr + len);
1565 1565
1566 /*-----------------------------------------------------------------------+ 1566 /*-----------------------------------------------------------------------+
1567 * set TX Buffer busy, and send it 1567 * set TX Buffer busy, and send it
1568 *-----------------------------------------------------------------------*/ 1568 *-----------------------------------------------------------------------*/
1569 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST | 1569 hw_p->tx[hw_p->tx_slot].ctrl = (MAL_TX_CTRL_LAST |
1570 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) & 1570 EMAC_TX_CTRL_GFCS | EMAC_TX_CTRL_GP) &
1571 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA); 1571 ~(EMAC_TX_CTRL_ISA | EMAC_TX_CTRL_RSA);
1572 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot) 1572 if ((NUM_TX_BUFF - 1) == hw_p->tx_slot)
1573 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP; 1573 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_WRAP;
1574 1574
1575 hw_p->tx[hw_p->tx_slot].data_len = (short) len; 1575 hw_p->tx[hw_p->tx_slot].data_len = (short) len;
1576 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY; 1576 hw_p->tx[hw_p->tx_slot].ctrl |= MAL_TX_CTRL_READY;
1577 1577
1578 sync(); 1578 sync();
1579 1579
1580 out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr, 1580 out_be32((void *)EMAC0_TMR0 + hw_p->hw_addr,
1581 in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0); 1581 in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr) | EMAC_TMR0_GNP0);
1582 #ifdef INFO_4XX_ENET 1582 #ifdef INFO_4XX_ENET
1583 hw_p->stats.pkts_tx++; 1583 hw_p->stats.pkts_tx++;
1584 #endif 1584 #endif
1585 1585
1586 /*-----------------------------------------------------------------------+ 1586 /*-----------------------------------------------------------------------+
1587 * poll unitl the packet is sent and then make sure it is OK 1587 * poll unitl the packet is sent and then make sure it is OK
1588 *-----------------------------------------------------------------------*/ 1588 *-----------------------------------------------------------------------*/
1589 time_start = get_timer (0); 1589 time_start = get_timer (0);
1590 while (1) { 1590 while (1) {
1591 temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr); 1591 temp_txm0 = in_be32((void *)EMAC0_TMR0 + hw_p->hw_addr);
1592 /* loop until either TINT turns on or 3 seconds elapse */ 1592 /* loop until either TINT turns on or 3 seconds elapse */
1593 if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) { 1593 if ((temp_txm0 & EMAC_TMR0_GNP0) != 0) {
1594 /* transmit is done, so now check for errors 1594 /* transmit is done, so now check for errors
1595 * If there is an error, an interrupt should 1595 * If there is an error, an interrupt should
1596 * happen when we return 1596 * happen when we return
1597 */ 1597 */
1598 time_now = get_timer (0); 1598 time_now = get_timer (0);
1599 if ((time_now - time_start) > 3000) { 1599 if ((time_now - time_start) > 3000) {
1600 return (-1); 1600 return (-1);
1601 } 1601 }
1602 } else { 1602 } else {
1603 return (len); 1603 return (len);
1604 } 1604 }
1605 } 1605 }
1606 } 1606 }
1607 1607
1608 int enetInt (struct eth_device *dev) 1608 int enetInt (struct eth_device *dev)
1609 { 1609 {
1610 int serviced; 1610 int serviced;
1611 int rc = -1; /* default to not us */ 1611 int rc = -1; /* default to not us */
1612 u32 mal_isr; 1612 u32 mal_isr;
1613 u32 emac_isr = 0; 1613 u32 emac_isr = 0;
1614 u32 mal_eob; 1614 u32 mal_eob;
1615 u32 uic_mal; 1615 u32 uic_mal;
1616 u32 uic_mal_err; 1616 u32 uic_mal_err;
1617 u32 uic_emac; 1617 u32 uic_emac;
1618 u32 uic_emac_b; 1618 u32 uic_emac_b;
1619 EMAC_4XX_HW_PST hw_p; 1619 EMAC_4XX_HW_PST hw_p;
1620 1620
1621 /* 1621 /*
1622 * Because the mal is generic, we need to get the current 1622 * Because the mal is generic, we need to get the current
1623 * eth device 1623 * eth device
1624 */ 1624 */
1625 dev = eth_get_dev(); 1625 dev = eth_get_dev();
1626 1626
1627 hw_p = dev->priv; 1627 hw_p = dev->priv;
1628 1628
1629 /* enter loop that stays in interrupt code until nothing to service */ 1629 /* enter loop that stays in interrupt code until nothing to service */
1630 do { 1630 do {
1631 serviced = 0; 1631 serviced = 0;
1632 1632
1633 uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR); 1633 uic_mal = mfdcr(UIC_BASE_MAL + UIC_MSR);
1634 uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR); 1634 uic_mal_err = mfdcr(UIC_BASE_MAL_ERR + UIC_MSR);
1635 uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR); 1635 uic_emac = mfdcr(UIC_BASE_EMAC + UIC_MSR);
1636 uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR); 1636 uic_emac_b = mfdcr(UIC_BASE_EMAC_B + UIC_MSR);
1637 1637
1638 if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB)) 1638 if (!(uic_mal & (UIC_MAL_RXEOB | UIC_MAL_TXEOB))
1639 && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) 1639 && !(uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE))
1640 && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) { 1640 && !(uic_emac & UIC_ETHx) && !(uic_emac_b & UIC_ETHxB)) {
1641 /* not for us */ 1641 /* not for us */
1642 return (rc); 1642 return (rc);
1643 } 1643 }
1644 1644
1645 /* get and clear controller status interrupts */ 1645 /* get and clear controller status interrupts */
1646 /* look at MAL and EMAC error interrupts */ 1646 /* look at MAL and EMAC error interrupts */
1647 if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) { 1647 if (uic_mal_err & (UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE)) {
1648 /* we have a MAL error interrupt */ 1648 /* we have a MAL error interrupt */
1649 mal_isr = mfdcr(MAL0_ESR); 1649 mal_isr = mfdcr(MAL0_ESR);
1650 mal_err(dev, mal_isr, uic_mal_err, 1650 mal_err(dev, mal_isr, uic_mal_err,
1651 MAL_UIC_DEF, MAL_UIC_ERR); 1651 MAL_UIC_DEF, MAL_UIC_ERR);
1652 1652
1653 /* clear MAL error interrupt status bits */ 1653 /* clear MAL error interrupt status bits */
1654 mtdcr(UIC_BASE_MAL_ERR + UIC_SR, 1654 mtdcr(UIC_BASE_MAL_ERR + UIC_SR,
1655 UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE); 1655 UIC_MAL_SERR | UIC_MAL_TXDE | UIC_MAL_RXDE);
1656 1656
1657 return -1; 1657 return -1;
1658 } 1658 }
1659 1659
1660 /* look for EMAC errors */ 1660 /* look for EMAC errors */
1661 if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) { 1661 if ((uic_emac & UIC_ETHx) || (uic_emac_b & UIC_ETHxB)) {
1662 emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr); 1662 emac_isr = in_be32((void *)EMAC0_ISR + hw_p->hw_addr);
1663 emac_err(dev, emac_isr); 1663 emac_err(dev, emac_isr);
1664 1664
1665 /* clear EMAC error interrupt status bits */ 1665 /* clear EMAC error interrupt status bits */
1666 mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx); 1666 mtdcr(UIC_BASE_EMAC + UIC_SR, UIC_ETHx);
1667 mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB); 1667 mtdcr(UIC_BASE_EMAC_B + UIC_SR, UIC_ETHxB);
1668 1668
1669 return -1; 1669 return -1;
1670 } 1670 }
1671 1671
1672 /* handle MAX TX EOB interrupt from a tx */ 1672 /* handle MAX TX EOB interrupt from a tx */
1673 if (uic_mal & UIC_MAL_TXEOB) { 1673 if (uic_mal & UIC_MAL_TXEOB) {
1674 /* clear MAL interrupt status bits */ 1674 /* clear MAL interrupt status bits */
1675 mal_eob = mfdcr(MAL0_TXEOBISR); 1675 mal_eob = mfdcr(MAL0_TXEOBISR);
1676 mtdcr(MAL0_TXEOBISR, mal_eob); 1676 mtdcr(MAL0_TXEOBISR, mal_eob);
1677 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB); 1677 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_TXEOB);
1678 1678
1679 /* indicate that we serviced an interrupt */ 1679 /* indicate that we serviced an interrupt */
1680 serviced = 1; 1680 serviced = 1;
1681 rc = 0; 1681 rc = 0;
1682 } 1682 }
1683 1683
1684 /* handle MAL RX EOB interrupt from a receive */ 1684 /* handle MAL RX EOB interrupt from a receive */
1685 /* check for EOB on valid channels */ 1685 /* check for EOB on valid channels */
1686 if (uic_mal & UIC_MAL_RXEOB) { 1686 if (uic_mal & UIC_MAL_RXEOB) {
1687 mal_eob = mfdcr(MAL0_RXEOBISR); 1687 mal_eob = mfdcr(MAL0_RXEOBISR);
1688 if (mal_eob & 1688 if (mal_eob &
1689 (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) { 1689 (0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL))) {
1690 /* push packet to upper layer */ 1690 /* push packet to upper layer */
1691 enet_rcv(dev, emac_isr); 1691 enet_rcv(dev, emac_isr);
1692 1692
1693 /* clear MAL interrupt status bits */ 1693 /* clear MAL interrupt status bits */
1694 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB); 1694 mtdcr(UIC_BASE_MAL + UIC_SR, UIC_MAL_RXEOB);
1695 1695
1696 /* indicate that we serviced an interrupt */ 1696 /* indicate that we serviced an interrupt */
1697 serviced = 1; 1697 serviced = 1;
1698 rc = 0; 1698 rc = 0;
1699 } 1699 }
1700 } 1700 }
1701 #if defined(CONFIG_405EZ) 1701 #if defined(CONFIG_405EZ)
1702 /* 1702 /*
1703 * On 405EZ the RX-/TX-interrupts are coalesced into 1703 * On 405EZ the RX-/TX-interrupts are coalesced into
1704 * one IRQ bit in the UIC. We need to acknowledge the 1704 * one IRQ bit in the UIC. We need to acknowledge the
1705 * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well. 1705 * RX-/TX-interrupts in the SDR0_ICINTSTAT reg as well.
1706 */ 1706 */
1707 mtsdr(SDR0_ICINTSTAT, 1707 mtsdr(SDR0_ICINTSTAT,
1708 SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); 1708 SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT);
1709 #endif /* defined(CONFIG_405EZ) */ 1709 #endif /* defined(CONFIG_405EZ) */
1710 } while (serviced); 1710 } while (serviced);
1711 1711
1712 return (rc); 1712 return (rc);
1713 } 1713 }
1714 1714
1715 /*-----------------------------------------------------------------------------+ 1715 /*-----------------------------------------------------------------------------+
1716 * MAL Error Routine 1716 * MAL Error Routine
1717 *-----------------------------------------------------------------------------*/ 1717 *-----------------------------------------------------------------------------*/
1718 static void mal_err (struct eth_device *dev, unsigned long isr, 1718 static void mal_err (struct eth_device *dev, unsigned long isr,
1719 unsigned long uic, unsigned long maldef, 1719 unsigned long uic, unsigned long maldef,
1720 unsigned long mal_errr) 1720 unsigned long mal_errr)
1721 { 1721 {
1722 EMAC_4XX_HW_PST hw_p = dev->priv; 1722 EMAC_4XX_HW_PST hw_p = dev->priv;
1723 1723
1724 mtdcr (MAL0_ESR, isr); /* clear interrupt */ 1724 mtdcr (MAL0_ESR, isr); /* clear interrupt */
1725 1725
1726 /* clear DE interrupt */ 1726 /* clear DE interrupt */
1727 mtdcr (MAL0_TXDEIR, 0xC0000000); 1727 mtdcr (MAL0_TXDEIR, 0xC0000000);
1728 mtdcr (MAL0_RXDEIR, 0x80000000); 1728 mtdcr (MAL0_RXDEIR, 0x80000000);
1729 1729
1730 #ifdef INFO_4XX_ENET 1730 #ifdef INFO_4XX_ENET
1731 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr); 1731 printf ("\nMAL error occured.... ISR = %lx UIC = = %lx MAL_DEF = %lx MAL_ERR= %lx \n", isr, uic, maldef, mal_errr);
1732 #endif 1732 #endif
1733 1733
1734 eth_init (hw_p->bis); /* start again... */ 1734 eth_init (hw_p->bis); /* start again... */
1735 } 1735 }
1736 1736
1737 /*-----------------------------------------------------------------------------+ 1737 /*-----------------------------------------------------------------------------+
1738 * EMAC Error Routine 1738 * EMAC Error Routine
1739 *-----------------------------------------------------------------------------*/ 1739 *-----------------------------------------------------------------------------*/
1740 static void emac_err (struct eth_device *dev, unsigned long isr) 1740 static void emac_err (struct eth_device *dev, unsigned long isr)
1741 { 1741 {
1742 EMAC_4XX_HW_PST hw_p = dev->priv; 1742 EMAC_4XX_HW_PST hw_p = dev->priv;
1743 1743
1744 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr); 1744 printf ("EMAC%d error occured.... ISR = %lx\n", hw_p->devnum, isr);
1745 out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr); 1745 out_be32((void *)EMAC0_ISR + hw_p->hw_addr, isr);
1746 } 1746 }
1747 1747
1748 /*-----------------------------------------------------------------------------+ 1748 /*-----------------------------------------------------------------------------+
1749 * enet_rcv() handles the ethernet receive data 1749 * enet_rcv() handles the ethernet receive data
1750 *-----------------------------------------------------------------------------*/ 1750 *-----------------------------------------------------------------------------*/
1751 static void enet_rcv (struct eth_device *dev, unsigned long malisr) 1751 static void enet_rcv (struct eth_device *dev, unsigned long malisr)
1752 { 1752 {
1753 unsigned long data_len; 1753 unsigned long data_len;
1754 unsigned long rx_eob_isr; 1754 unsigned long rx_eob_isr;
1755 EMAC_4XX_HW_PST hw_p = dev->priv; 1755 EMAC_4XX_HW_PST hw_p = dev->priv;
1756 1756
1757 int handled = 0; 1757 int handled = 0;
1758 int i; 1758 int i;
1759 int loop_count = 0; 1759 int loop_count = 0;
1760 1760
1761 rx_eob_isr = mfdcr (MAL0_RXEOBISR); 1761 rx_eob_isr = mfdcr (MAL0_RXEOBISR);
1762 if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) { 1762 if ((0x80000000 >> (hw_p->devnum * MAL_RX_CHAN_MUL)) & rx_eob_isr) {
1763 /* clear EOB */ 1763 /* clear EOB */
1764 mtdcr (MAL0_RXEOBISR, rx_eob_isr); 1764 mtdcr (MAL0_RXEOBISR, rx_eob_isr);
1765 1765
1766 /* EMAC RX done */ 1766 /* EMAC RX done */
1767 while (1) { /* do all */ 1767 while (1) { /* do all */
1768 i = hw_p->rx_slot; 1768 i = hw_p->rx_slot;
1769 1769
1770 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl) 1770 if ((MAL_RX_CTRL_EMPTY & hw_p->rx[i].ctrl)
1771 || (loop_count >= NUM_RX_BUFF)) 1771 || (loop_count >= NUM_RX_BUFF))
1772 break; 1772 break;
1773 1773
1774 loop_count++; 1774 loop_count++;
1775 handled++; 1775 handled++;
1776 data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */ 1776 data_len = (unsigned long) hw_p->rx[i].data_len & 0x0fff; /* Get len */
1777 if (data_len) { 1777 if (data_len) {
1778 if (data_len > ENET_MAX_MTU) /* Check len */ 1778 if (data_len > ENET_MAX_MTU) /* Check len */
1779 data_len = 0; 1779 data_len = 0;
1780 else { 1780 else {
1781 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */ 1781 if (EMAC_RX_ERRORS & hw_p->rx[i].ctrl) { /* Check Errors */
1782 data_len = 0; 1782 data_len = 0;
1783 hw_p->stats.rx_err_log[hw_p-> 1783 hw_p->stats.rx_err_log[hw_p->
1784 rx_err_index] 1784 rx_err_index]
1785 = hw_p->rx[i].ctrl; 1785 = hw_p->rx[i].ctrl;
1786 hw_p->rx_err_index++; 1786 hw_p->rx_err_index++;
1787 if (hw_p->rx_err_index == 1787 if (hw_p->rx_err_index ==
1788 MAX_ERR_LOG) 1788 MAX_ERR_LOG)
1789 hw_p->rx_err_index = 1789 hw_p->rx_err_index =
1790 0; 1790 0;
1791 } /* emac_erros */ 1791 } /* emac_erros */
1792 } /* data_len < max mtu */ 1792 } /* data_len < max mtu */
1793 } /* if data_len */ 1793 } /* if data_len */
1794 if (!data_len) { /* no data */ 1794 if (!data_len) { /* no data */
1795 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */ 1795 hw_p->rx[i].ctrl |= MAL_RX_CTRL_EMPTY; /* Free Recv Buffer */
1796 1796
1797 hw_p->stats.data_len_err++; /* Error at Rx */ 1797 hw_p->stats.data_len_err++; /* Error at Rx */
1798 } 1798 }
1799 1799
1800 /* !data_len */ 1800 /* !data_len */
1801 /* AS.HARNOIS */ 1801 /* AS.HARNOIS */
1802 /* Check if user has already eaten buffer */ 1802 /* Check if user has already eaten buffer */
1803 /* if not => ERROR */ 1803 /* if not => ERROR */
1804 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) { 1804 else if (hw_p->rx_ready[hw_p->rx_i_index] != -1) {
1805 if (hw_p->is_receiving) 1805 if (hw_p->is_receiving)
1806 printf ("ERROR : Receive buffers are full!\n"); 1806 printf ("ERROR : Receive buffers are full!\n");
1807 break; 1807 break;
1808 } else { 1808 } else {
1809 hw_p->stats.rx_frames++; 1809 hw_p->stats.rx_frames++;
1810 hw_p->stats.rx += data_len; 1810 hw_p->stats.rx += data_len;
1811 #ifdef INFO_4XX_ENET 1811 #ifdef INFO_4XX_ENET
1812 hw_p->stats.pkts_rx++; 1812 hw_p->stats.pkts_rx++;
1813 #endif 1813 #endif
1814 /* AS.HARNOIS 1814 /* AS.HARNOIS
1815 * use ring buffer 1815 * use ring buffer
1816 */ 1816 */
1817 hw_p->rx_ready[hw_p->rx_i_index] = i; 1817 hw_p->rx_ready[hw_p->rx_i_index] = i;
1818 hw_p->rx_i_index++; 1818 hw_p->rx_i_index++;
1819 if (NUM_RX_BUFF == hw_p->rx_i_index) 1819 if (NUM_RX_BUFF == hw_p->rx_i_index)
1820 hw_p->rx_i_index = 0; 1820 hw_p->rx_i_index = 0;
1821 1821
1822 hw_p->rx_slot++; 1822 hw_p->rx_slot++;
1823 if (NUM_RX_BUFF == hw_p->rx_slot) 1823 if (NUM_RX_BUFF == hw_p->rx_slot)
1824 hw_p->rx_slot = 0; 1824 hw_p->rx_slot = 0;
1825 1825
1826 /* AS.HARNOIS 1826 /* AS.HARNOIS
1827 * free receive buffer only when 1827 * free receive buffer only when
1828 * buffer has been handled (eth_rx) 1828 * buffer has been handled (eth_rx)
1829 rx[i].ctrl |= MAL_RX_CTRL_EMPTY; 1829 rx[i].ctrl |= MAL_RX_CTRL_EMPTY;
1830 */ 1830 */
1831 } /* if data_len */ 1831 } /* if data_len */
1832 } /* while */ 1832 } /* while */
1833 } /* if EMACK_RXCHL */ 1833 } /* if EMACK_RXCHL */
1834 } 1834 }
1835 1835
1836 1836
1837 static int ppc_4xx_eth_rx (struct eth_device *dev) 1837 static int ppc_4xx_eth_rx (struct eth_device *dev)
1838 { 1838 {
1839 int length; 1839 int length;
1840 int user_index; 1840 int user_index;
1841 unsigned long msr; 1841 unsigned long msr;
1842 EMAC_4XX_HW_PST hw_p = dev->priv; 1842 EMAC_4XX_HW_PST hw_p = dev->priv;
1843 1843
1844 hw_p->is_receiving = 1; /* tell driver */ 1844 hw_p->is_receiving = 1; /* tell driver */
1845 1845
1846 for (;;) { 1846 for (;;) {
1847 /* AS.HARNOIS 1847 /* AS.HARNOIS
1848 * use ring buffer and 1848 * use ring buffer and
1849 * get index from rx buffer desciptor queue 1849 * get index from rx buffer desciptor queue
1850 */ 1850 */
1851 user_index = hw_p->rx_ready[hw_p->rx_u_index]; 1851 user_index = hw_p->rx_ready[hw_p->rx_u_index];
1852 if (user_index == -1) { 1852 if (user_index == -1) {
1853 length = -1; 1853 length = -1;
1854 break; /* nothing received - leave for() loop */ 1854 break; /* nothing received - leave for() loop */
1855 } 1855 }
1856 1856
1857 msr = mfmsr (); 1857 msr = mfmsr ();
1858 mtmsr (msr & ~(MSR_EE)); 1858 mtmsr (msr & ~(MSR_EE));
1859 1859
1860 length = hw_p->rx[user_index].data_len & 0x0fff; 1860 length = hw_p->rx[user_index].data_len & 0x0fff;
1861 1861
1862 /* Pass the packet up to the protocol layers. */ 1862 /* Pass the packet up to the protocol layers. */
1863 /* NetReceive(NetRxPackets[rxIdx], length - 4); */ 1863 /* NetReceive(NetRxPackets[rxIdx], length - 4); */
1864 /* NetReceive(NetRxPackets[i], length); */ 1864 /* NetReceive(NetRxPackets[i], length); */
1865 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr, 1865 invalidate_dcache_range((u32)hw_p->rx[user_index].data_ptr,
1866 (u32)hw_p->rx[user_index].data_ptr + 1866 (u32)hw_p->rx[user_index].data_ptr +
1867 length - 4); 1867 length - 4);
1868 NetReceive (NetRxPackets[user_index], length - 4); 1868 NetReceive (NetRxPackets[user_index], length - 4);
1869 /* Free Recv Buffer */ 1869 /* Free Recv Buffer */
1870 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY; 1870 hw_p->rx[user_index].ctrl |= MAL_RX_CTRL_EMPTY;
1871 /* Free rx buffer descriptor queue */ 1871 /* Free rx buffer descriptor queue */
1872 hw_p->rx_ready[hw_p->rx_u_index] = -1; 1872 hw_p->rx_ready[hw_p->rx_u_index] = -1;
1873 hw_p->rx_u_index++; 1873 hw_p->rx_u_index++;
1874 if (NUM_RX_BUFF == hw_p->rx_u_index) 1874 if (NUM_RX_BUFF == hw_p->rx_u_index)
1875 hw_p->rx_u_index = 0; 1875 hw_p->rx_u_index = 0;
1876 1876
1877 #ifdef INFO_4XX_ENET 1877 #ifdef INFO_4XX_ENET
1878 hw_p->stats.pkts_handled++; 1878 hw_p->stats.pkts_handled++;
1879 #endif 1879 #endif
1880 1880
1881 mtmsr (msr); /* Enable IRQ's */ 1881 mtmsr (msr); /* Enable IRQ's */
1882 } 1882 }
1883 1883
1884 hw_p->is_receiving = 0; /* tell driver */ 1884 hw_p->is_receiving = 0; /* tell driver */
1885 1885
1886 return length; 1886 return length;
1887 } 1887 }
1888 1888
1889 int ppc_4xx_eth_initialize (bd_t * bis) 1889 int ppc_4xx_eth_initialize (bd_t * bis)
1890 { 1890 {
1891 static int virgin = 0; 1891 static int virgin = 0;
1892 struct eth_device *dev; 1892 struct eth_device *dev;
1893 int eth_num = 0; 1893 int eth_num = 0;
1894 EMAC_4XX_HW_PST hw = NULL; 1894 EMAC_4XX_HW_PST hw = NULL;
1895 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6]; 1895 u8 ethaddr[4 + CONFIG_EMAC_NR_START][6];
1896 u32 hw_addr[4]; 1896 u32 hw_addr[4];
1897 u32 mal_ier; 1897 u32 mal_ier;
1898 1898
1899 #if defined(CONFIG_440GX) 1899 #if defined(CONFIG_440GX)
1900 unsigned long pfc1; 1900 unsigned long pfc1;
1901 1901
1902 mfsdr (SDR0_PFC1, pfc1); 1902 mfsdr (SDR0_PFC1, pfc1);
1903 pfc1 &= ~(0x01e00000); 1903 pfc1 &= ~(0x01e00000);
1904 pfc1 |= 0x01200000; 1904 pfc1 |= 0x01200000;
1905 mtsdr (SDR0_PFC1, pfc1); 1905 mtsdr (SDR0_PFC1, pfc1);
1906 #endif 1906 #endif
1907 1907
1908 /* first clear all mac-addresses */ 1908 /* first clear all mac-addresses */
1909 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) 1909 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++)
1910 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6); 1910 memcpy(ethaddr[eth_num], "\0\0\0\0\0\0", 6);
1911 1911
1912 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { 1912 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1913 int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START; 1913 int ethaddr_idx = eth_num + CONFIG_EMAC_NR_START;
1914 switch (eth_num) { 1914 switch (eth_num) {
1915 default: /* fall through */ 1915 default: /* fall through */
1916 case 0: 1916 case 0:
1917 eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]); 1917 eth_getenv_enetaddr("ethaddr", ethaddr[ethaddr_idx]);
1918 hw_addr[eth_num] = 0x0; 1918 hw_addr[eth_num] = 0x0;
1919 break; 1919 break;
1920 #ifdef CONFIG_HAS_ETH1 1920 #ifdef CONFIG_HAS_ETH1
1921 case 1: 1921 case 1:
1922 eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]); 1922 eth_getenv_enetaddr("eth1addr", ethaddr[ethaddr_idx]);
1923 hw_addr[eth_num] = 0x100; 1923 hw_addr[eth_num] = 0x100;
1924 break; 1924 break;
1925 #endif 1925 #endif
1926 #ifdef CONFIG_HAS_ETH2 1926 #ifdef CONFIG_HAS_ETH2
1927 case 2: 1927 case 2:
1928 eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]); 1928 eth_getenv_enetaddr("eth2addr", ethaddr[ethaddr_idx]);
1929 #if defined(CONFIG_460GT) 1929 #if defined(CONFIG_460GT)
1930 hw_addr[eth_num] = 0x300; 1930 hw_addr[eth_num] = 0x300;
1931 #else 1931 #else
1932 hw_addr[eth_num] = 0x400; 1932 hw_addr[eth_num] = 0x400;
1933 #endif 1933 #endif
1934 break; 1934 break;
1935 #endif 1935 #endif
1936 #ifdef CONFIG_HAS_ETH3 1936 #ifdef CONFIG_HAS_ETH3
1937 case 3: 1937 case 3:
1938 eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]); 1938 eth_getenv_enetaddr("eth3addr", ethaddr[ethaddr_idx]);
1939 #if defined(CONFIG_460GT) 1939 #if defined(CONFIG_460GT)
1940 hw_addr[eth_num] = 0x400; 1940 hw_addr[eth_num] = 0x400;
1941 #else 1941 #else
1942 hw_addr[eth_num] = 0x600; 1942 hw_addr[eth_num] = 0x600;
1943 #endif 1943 #endif
1944 break; 1944 break;
1945 #endif 1945 #endif
1946 } 1946 }
1947 } 1947 }
1948 1948
1949 /* set phy num and mode */ 1949 /* set phy num and mode */
1950 bis->bi_phynum[0] = CONFIG_PHY_ADDR; 1950 bis->bi_phynum[0] = CONFIG_PHY_ADDR;
1951 bis->bi_phymode[0] = 0; 1951 bis->bi_phymode[0] = 0;
1952 1952
1953 #if defined(CONFIG_PHY1_ADDR) 1953 #if defined(CONFIG_PHY1_ADDR)
1954 bis->bi_phynum[1] = CONFIG_PHY1_ADDR; 1954 bis->bi_phynum[1] = CONFIG_PHY1_ADDR;
1955 bis->bi_phymode[1] = 0; 1955 bis->bi_phymode[1] = 0;
1956 #endif 1956 #endif
1957 #if defined(CONFIG_440GX) 1957 #if defined(CONFIG_440GX)
1958 bis->bi_phynum[2] = CONFIG_PHY2_ADDR; 1958 bis->bi_phynum[2] = CONFIG_PHY2_ADDR;
1959 bis->bi_phynum[3] = CONFIG_PHY3_ADDR; 1959 bis->bi_phynum[3] = CONFIG_PHY3_ADDR;
1960 bis->bi_phymode[2] = 2; 1960 bis->bi_phymode[2] = 2;
1961 bis->bi_phymode[3] = 2; 1961 bis->bi_phymode[3] = 2;
1962 #endif 1962 #endif
1963 1963
1964 #if defined(CONFIG_440GX) || \ 1964 #if defined(CONFIG_440GX) || \
1965 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 1965 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
1966 defined(CONFIG_405EX) 1966 defined(CONFIG_405EX)
1967 ppc_4xx_eth_setup_bridge(0, bis); 1967 ppc_4xx_eth_setup_bridge(0, bis);
1968 #endif 1968 #endif
1969 1969
1970 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) { 1970 for (eth_num = 0; eth_num < LAST_EMAC_NUM; eth_num++) {
1971 /* 1971 /*
1972 * See if we can actually bring up the interface, 1972 * See if we can actually bring up the interface,
1973 * otherwise, skip it 1973 * otherwise, skip it
1974 */ 1974 */
1975 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) { 1975 if (memcmp (ethaddr[eth_num], "\0\0\0\0\0\0", 6) == 0) {
1976 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE; 1976 bis->bi_phymode[eth_num] = BI_PHYMODE_NONE;
1977 continue; 1977 continue;
1978 } 1978 }
1979 1979
1980 /* Allocate device structure */ 1980 /* Allocate device structure */
1981 dev = (struct eth_device *) malloc (sizeof (*dev)); 1981 dev = (struct eth_device *) malloc (sizeof (*dev));
1982 if (dev == NULL) { 1982 if (dev == NULL) {
1983 printf ("ppc_4xx_eth_initialize: " 1983 printf ("ppc_4xx_eth_initialize: "
1984 "Cannot allocate eth_device %d\n", eth_num); 1984 "Cannot allocate eth_device %d\n", eth_num);
1985 return (-1); 1985 return (-1);
1986 } 1986 }
1987 memset(dev, 0, sizeof(*dev)); 1987 memset(dev, 0, sizeof(*dev));
1988 1988
1989 /* Allocate our private use data */ 1989 /* Allocate our private use data */
1990 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw)); 1990 hw = (EMAC_4XX_HW_PST) malloc (sizeof (*hw));
1991 if (hw == NULL) { 1991 if (hw == NULL) {
1992 printf ("ppc_4xx_eth_initialize: " 1992 printf ("ppc_4xx_eth_initialize: "
1993 "Cannot allocate private hw data for eth_device %d", 1993 "Cannot allocate private hw data for eth_device %d",
1994 eth_num); 1994 eth_num);
1995 free (dev); 1995 free (dev);
1996 return (-1); 1996 return (-1);
1997 } 1997 }
1998 memset(hw, 0, sizeof(*hw)); 1998 memset(hw, 0, sizeof(*hw));
1999 1999
2000 hw->hw_addr = hw_addr[eth_num]; 2000 hw->hw_addr = hw_addr[eth_num];
2001 memcpy (dev->enetaddr, ethaddr[eth_num], 6); 2001 memcpy (dev->enetaddr, ethaddr[eth_num], 6);
2002 hw->devnum = eth_num; 2002 hw->devnum = eth_num;
2003 hw->print_speed = 1; 2003 hw->print_speed = 1;
2004 2004
2005 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START); 2005 sprintf (dev->name, "ppc_4xx_eth%d", eth_num - CONFIG_EMAC_NR_START);
2006 dev->priv = (void *) hw; 2006 dev->priv = (void *) hw;
2007 dev->init = ppc_4xx_eth_init; 2007 dev->init = ppc_4xx_eth_init;
2008 dev->halt = ppc_4xx_eth_halt; 2008 dev->halt = ppc_4xx_eth_halt;
2009 dev->send = ppc_4xx_eth_send; 2009 dev->send = ppc_4xx_eth_send;
2010 dev->recv = ppc_4xx_eth_rx; 2010 dev->recv = ppc_4xx_eth_rx;
2011 2011
2012 eth_register(dev); 2012 eth_register(dev);
2013 2013
2014 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) 2014 #if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
2015 miiphy_register(dev->name, 2015 miiphy_register(dev->name,
2016 emac4xx_miiphy_read, emac4xx_miiphy_write); 2016 emac4xx_miiphy_read, emac4xx_miiphy_write);
2017 #endif 2017 #endif
2018 2018
2019 if (0 == virgin) { 2019 if (0 == virgin) {
2020 /* set the MAL IER ??? names may change with new spec ??? */ 2020 /* set the MAL IER ??? names may change with new spec ??? */
2021 #if defined(CONFIG_440SPE) || \ 2021 #if defined(CONFIG_440SPE) || \
2022 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ 2022 defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \
2023 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ 2023 defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2024 defined(CONFIG_405EX) 2024 defined(CONFIG_405EX)
2025 mal_ier = 2025 mal_ier =
2026 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE | 2026 MAL_IER_PT | MAL_IER_PRE | MAL_IER_PWE |
2027 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ; 2027 MAL_IER_DE | MAL_IER_OTE | MAL_IER_OE | MAL_IER_PE ;
2028 #else 2028 #else
2029 mal_ier = 2029 mal_ier =
2030 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE | 2030 MAL_IER_DE | MAL_IER_NE | MAL_IER_TE |
2031 MAL_IER_OPBE | MAL_IER_PLBE; 2031 MAL_IER_OPBE | MAL_IER_PLBE;
2032 #endif 2032 #endif
2033 mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */ 2033 mtdcr (MAL0_ESR, 0xffffffff); /* clear pending interrupts */
2034 mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */ 2034 mtdcr (MAL0_TXDEIR, 0xffffffff); /* clear pending interrupts */
2035 mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */ 2035 mtdcr (MAL0_RXDEIR, 0xffffffff); /* clear pending interrupts */
2036 mtdcr (MAL0_IER, mal_ier); 2036 mtdcr (MAL0_IER, mal_ier);
2037 2037
2038 /* install MAL interrupt handler */ 2038 /* install MAL interrupt handler */
2039 irq_install_handler (VECNUM_MAL_SERR, 2039 irq_install_handler (VECNUM_MAL_SERR,
2040 (interrupt_handler_t *) enetInt, 2040 (interrupt_handler_t *) enetInt,
2041 dev); 2041 dev);
2042 irq_install_handler (VECNUM_MAL_TXEOB, 2042 irq_install_handler (VECNUM_MAL_TXEOB,
2043 (interrupt_handler_t *) enetInt, 2043 (interrupt_handler_t *) enetInt,
2044 dev); 2044 dev);
2045 irq_install_handler (VECNUM_MAL_RXEOB, 2045 irq_install_handler (VECNUM_MAL_RXEOB,
2046 (interrupt_handler_t *) enetInt, 2046 (interrupt_handler_t *) enetInt,
2047 dev); 2047 dev);
2048 irq_install_handler (VECNUM_MAL_TXDE, 2048 irq_install_handler (VECNUM_MAL_TXDE,
2049 (interrupt_handler_t *) enetInt, 2049 (interrupt_handler_t *) enetInt,
2050 dev); 2050 dev);
2051 irq_install_handler (VECNUM_MAL_RXDE, 2051 irq_install_handler (VECNUM_MAL_RXDE,
2052 (interrupt_handler_t *) enetInt, 2052 (interrupt_handler_t *) enetInt,
2053 dev); 2053 dev);
2054 virgin = 1; 2054 virgin = 1;
2055 } 2055 }
2056 } /* end for each supported device */ 2056 } /* end for each supported device */
2057 2057
2058 return 0; 2058 return 0;
2059 } 2059 }
2060 2060
drivers/net/npe/miiphy.c
Diff comments   View file @ 1b387ef
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 */ 3 */
4 /*-----------------------------------------------------------------------------+ 4 /*-----------------------------------------------------------------------------+
5 | 5 |
6 | File Name: miiphy.c 6 | File Name: miiphy.c
7 | 7 |
8 | Function: This module has utilities for accessing the MII PHY through 8 | Function: This module has utilities for accessing the MII PHY through
9 | the EMAC3 macro. 9 | the EMAC3 macro.
10 | 10 |
11 | Author: Mark Wisner 11 | Author: Mark Wisner
12 | 12 |
13 | Change Activity- 13 | Change Activity-
14 | 14 |
15 | Date Description of Change BY 15 | Date Description of Change BY
16 | --------- --------------------- --- 16 | --------- --------------------- ---
17 | 05-May-99 Created MKW 17 | 05-May-99 Created MKW
18 | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to 18 | 01-Jul-99 Changed clock setting of sta_reg from 66MHz to 50MHz to
19 | better match OPB speed. Also modified delay times. JWB 19 | better match OPB speed. Also modified delay times. JWB
20 | 29-Jul-99 Added Full duplex support MKW 20 | 29-Jul-99 Added Full duplex support MKW
21 | 24-Aug-99 Removed printf from dp83843_duplex() JWB 21 | 24-Aug-99 Removed printf from dp83843_duplex() JWB
22 | 19-Jul-00 Ported to esd cpci405 sr 22 | 19-Jul-00 Ported to esd cpci405 sr
23 | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS 23 | 23-Dec-03 Ported from miiphy.c to 440GX Travis Sawyer TBS
24 | <travis.sawyer@sandburst.com> 24 | <travis.sawyer@sandburst.com>
25 | 25 |
26 +-----------------------------------------------------------------------------*/ 26 +-----------------------------------------------------------------------------*/
27 27
28 #include <common.h> 28 #include <common.h>
29 #include <miiphy.h> 29 #include <miiphy.h>
30 #include "IxOsal.h" 30 #include "IxOsal.h"
31 #include "IxEthAcc.h" 31 #include "IxEthAcc.h"
32 #include "IxEthAcc_p.h" 32 #include "IxEthAcc_p.h"
33 #include "IxEthAccMac_p.h" 33 #include "IxEthAccMac_p.h"
34 #include "IxEthAccMii_p.h" 34 #include "IxEthAccMii_p.h"
35 35
36 /***********************************************************/ 36 /***********************************************************/
37 /* Dump out to the screen PHY regs */ 37 /* Dump out to the screen PHY regs */
38 /***********************************************************/ 38 /***********************************************************/
39 39
40 void miiphy_dump (char *devname, unsigned char addr) 40 void miiphy_dump (char *devname, unsigned char addr)
41 { 41 {
42 unsigned long i; 42 unsigned long i;
43 unsigned short data; 43 unsigned short data;
44 44
45 45
46 for (i = 0; i < 0x1A; i++) { 46 for (i = 0; i < 0x1A; i++) {
47 if (miiphy_read (devname, addr, i, &data)) { 47 if (miiphy_read (devname, addr, i, &data)) {
48 printf ("read error for reg %lx\n", i); 48 printf ("read error for reg %lx\n", i);
49 return; 49 return;
50 } 50 }
51 printf ("Phy reg %lx ==> %4x\n", i, data); 51 printf ("Phy reg %lx ==> %4x\n", i, data);
52 52
53 /* jump to the next set of regs */ 53 /* jump to the next set of regs */
54 if (i == 0x07) 54 if (i == 0x07)
55 i = 0x0f; 55 i = 0x0f;
56 56
57 } /* end for loop */ 57 } /* end for loop */
58 } /* end dump */ 58 } /* end dump */
59 59
60 60
61 /***********************************************************/ 61 /***********************************************************/
62 /* (Re)start autonegotiation */ 62 /* (Re)start autonegotiation */
63 /***********************************************************/ 63 /***********************************************************/
64 int phy_setup_aneg (char *devname, unsigned char addr) 64 int phy_setup_aneg (char *devname, unsigned char addr)
65 { 65 {
66 unsigned short ctl, adv; 66 unsigned short ctl, adv;
67 67
68 /* Setup standard advertise */ 68 /* Setup standard advertise */
69 miiphy_read (devname, addr, MII_ADVERTISE, &adv); 69 miiphy_read (devname, addr, MII_ADVERTISE, &adv);
70 adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 | 70 adv |= (LPA_LPACK | LPA_RFAULT | LPA_100BASE4 |
71 LPA_100FULL | LPA_100HALF | LPA_10FULL | 71 LPA_100FULL | LPA_100HALF | LPA_10FULL |
72 LPA_10HALF); 72 LPA_10HALF);
73 miiphy_write (devname, addr, MII_ADVERTISE, adv); 73 miiphy_write (devname, addr, MII_ADVERTISE, adv);
74 74
75 /* Start/Restart aneg */ 75 /* Start/Restart aneg */
76 miiphy_read (devname, addr, MII_BMCR, &ctl); 76 miiphy_read (devname, addr, MII_BMCR, &ctl);
77 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART); 77 ctl |= (BMCR_ANENABLE | BMCR_ANRESTART);
78 miiphy_write (devname, addr, MII_BMCR, ctl); 78 miiphy_write (devname, addr, MII_BMCR, ctl);
79 79
80 return 0; 80 return 0;
81 } 81 }
82 82
83 83
84 int npe_miiphy_read (const char *devname, unsigned char addr, 84 int npe_miiphy_read (const char *devname, unsigned char addr,
85 unsigned char reg, unsigned short *value) 85 unsigned char reg, unsigned short *value)
86 { 86 {
87 u16 val; 87 u16 val;
88 88
89 ixEthAccMiiReadRtn(addr, reg, &val); 89 ixEthAccMiiReadRtn(addr, reg, &val);
90 *value = val; 90 *value = val;
91 91
92 return 0; 92 return 0;
93 } /* phy_read */ 93 } /* phy_read */
94 94
95 95
96 int npe_miiphy_write (const char *devname, unsigned char addr, 96 int npe_miiphy_write (const char *devname, unsigned char addr,
97 unsigned char reg, unsigned short value) 97 unsigned char reg, unsigned short value)
98 { 98 {
99 ixEthAccMiiWriteRtn(addr, reg, value); 99 ixEthAccMiiWriteRtn(addr, reg, value);
100 return 0; 100 return 0;
101 } /* phy_write */ 101 } /* phy_write */
102 102
1 /* 1 /*
2 * SPDX-License-Identifier: GPL-2.0 ibm-pibs 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
3 * 3 *
4 * Additions (C) Copyright 2009 Industrie Dial Face S.p.A. 4 * Additions (C) Copyright 2009 Industrie Dial Face S.p.A.
5 */ 5 */
6 /*----------------------------------------------------------------------------+ 6 /*----------------------------------------------------------------------------+
7 | 7 |
8 | File Name: miiphy.h 8 | File Name: miiphy.h
9 | 9 |
10 | Function: Include file defining PHY registers. 10 | Function: Include file defining PHY registers.
11 | 11 |
12 | Author: Mark Wisner 12 | Author: Mark Wisner
13 | 13 |
14 +----------------------------------------------------------------------------*/ 14 +----------------------------------------------------------------------------*/
15 #ifndef _miiphy_h_ 15 #ifndef _miiphy_h_
16 #define _miiphy_h_ 16 #define _miiphy_h_
17 17
18 #include <common.h> 18 #include <common.h>
19 #include <linux/mii.h> 19 #include <linux/mii.h>
20 #include <linux/list.h> 20 #include <linux/list.h>
21 #include <net.h> 21 #include <net.h>
22 #include <phy.h> 22 #include <phy.h>
23 23
24 struct legacy_mii_dev { 24 struct legacy_mii_dev {
25 int (*read)(const char *devname, unsigned char addr, 25 int (*read)(const char *devname, unsigned char addr,
26 unsigned char reg, unsigned short *value); 26 unsigned char reg, unsigned short *value);
27 int (*write)(const char *devname, unsigned char addr, 27 int (*write)(const char *devname, unsigned char addr,
28 unsigned char reg, unsigned short value); 28 unsigned char reg, unsigned short value);
29 }; 29 };
30 30
31 int miiphy_read(const char *devname, unsigned char addr, unsigned char reg, 31 int miiphy_read(const char *devname, unsigned char addr, unsigned char reg,
32 unsigned short *value); 32 unsigned short *value);
33 int miiphy_write(const char *devname, unsigned char addr, unsigned char reg, 33 int miiphy_write(const char *devname, unsigned char addr, unsigned char reg,
34 unsigned short value); 34 unsigned short value);
35 int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui, 35 int miiphy_info(const char *devname, unsigned char addr, unsigned int *oui,
36 unsigned char *model, unsigned char *rev); 36 unsigned char *model, unsigned char *rev);
37 int miiphy_reset(const char *devname, unsigned char addr); 37 int miiphy_reset(const char *devname, unsigned char addr);
38 int miiphy_speed(const char *devname, unsigned char addr); 38 int miiphy_speed(const char *devname, unsigned char addr);
39 int miiphy_duplex(const char *devname, unsigned char addr); 39 int miiphy_duplex(const char *devname, unsigned char addr);
40 int miiphy_is_1000base_x(const char *devname, unsigned char addr); 40 int miiphy_is_1000base_x(const char *devname, unsigned char addr);
41 #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN 41 #ifdef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
42 int miiphy_link(const char *devname, unsigned char addr); 42 int miiphy_link(const char *devname, unsigned char addr);
43 #endif 43 #endif
44 44
45 void miiphy_init(void); 45 void miiphy_init(void);
46 46
47 void miiphy_register(const char *devname, 47 void miiphy_register(const char *devname,
48 int (*read)(const char *devname, unsigned char addr, 48 int (*read)(const char *devname, unsigned char addr,
49 unsigned char reg, unsigned short *value), 49 unsigned char reg, unsigned short *value),
50 int (*write)(const char *devname, unsigned char addr, 50 int (*write)(const char *devname, unsigned char addr,
51 unsigned char reg, unsigned short value)); 51 unsigned char reg, unsigned short value));
52 52
53 int miiphy_set_current_dev(const char *devname); 53 int miiphy_set_current_dev(const char *devname);
54 const char *miiphy_get_current_dev(void); 54 const char *miiphy_get_current_dev(void);
55 struct mii_dev *mdio_get_current_dev(void); 55 struct mii_dev *mdio_get_current_dev(void);
56 struct mii_dev *miiphy_get_dev_by_name(const char *devname); 56 struct mii_dev *miiphy_get_dev_by_name(const char *devname);
57 struct phy_device *mdio_phydev_for_ethname(const char *devname); 57 struct phy_device *mdio_phydev_for_ethname(const char *devname);
58 58
59 void miiphy_listdev(void); 59 void miiphy_listdev(void);
60 60
61 struct mii_dev *mdio_alloc(void); 61 struct mii_dev *mdio_alloc(void);
62 int mdio_register(struct mii_dev *bus); 62 int mdio_register(struct mii_dev *bus);
63 void mdio_list_devices(void); 63 void mdio_list_devices(void);
64 64
65 #ifdef CONFIG_BITBANGMII 65 #ifdef CONFIG_BITBANGMII
66 66
67 #define BB_MII_DEVNAME "bb_miiphy" 67 #define BB_MII_DEVNAME "bb_miiphy"
68 68
69 struct bb_miiphy_bus { 69 struct bb_miiphy_bus {
70 char name[16]; 70 char name[16];
71 int (*init)(struct bb_miiphy_bus *bus); 71 int (*init)(struct bb_miiphy_bus *bus);
72 int (*mdio_active)(struct bb_miiphy_bus *bus); 72 int (*mdio_active)(struct bb_miiphy_bus *bus);
73 int (*mdio_tristate)(struct bb_miiphy_bus *bus); 73 int (*mdio_tristate)(struct bb_miiphy_bus *bus);
74 int (*set_mdio)(struct bb_miiphy_bus *bus, int v); 74 int (*set_mdio)(struct bb_miiphy_bus *bus, int v);
75 int (*get_mdio)(struct bb_miiphy_bus *bus, int *v); 75 int (*get_mdio)(struct bb_miiphy_bus *bus, int *v);
76 int (*set_mdc)(struct bb_miiphy_bus *bus, int v); 76 int (*set_mdc)(struct bb_miiphy_bus *bus, int v);
77 int (*delay)(struct bb_miiphy_bus *bus); 77 int (*delay)(struct bb_miiphy_bus *bus);
78 #ifdef CONFIG_BITBANGMII_MULTI 78 #ifdef CONFIG_BITBANGMII_MULTI
79 void *priv; 79 void *priv;
80 #endif 80 #endif
81 }; 81 };
82 82
83 extern struct bb_miiphy_bus bb_miiphy_buses[]; 83 extern struct bb_miiphy_bus bb_miiphy_buses[];
84 extern int bb_miiphy_buses_num; 84 extern int bb_miiphy_buses_num;
85 85
86 void bb_miiphy_init(void); 86 void bb_miiphy_init(void);
87 int bb_miiphy_read(const char *devname, unsigned char addr, 87 int bb_miiphy_read(const char *devname, unsigned char addr,
88 unsigned char reg, unsigned short *value); 88 unsigned char reg, unsigned short *value);
89 int bb_miiphy_write(const char *devname, unsigned char addr, 89 int bb_miiphy_write(const char *devname, unsigned char addr,
90 unsigned char reg, unsigned short value); 90 unsigned char reg, unsigned short value);
91 #endif 91 #endif
92 92
93 /* phy seed setup */ 93 /* phy seed setup */
94 #define AUTO 99 94 #define AUTO 99
95 #define _1000BASET 1000 95 #define _1000BASET 1000
96 #define _100BASET 100 96 #define _100BASET 100
97 #define _10BASET 10 97 #define _10BASET 10
98 #define HALF 22 98 #define HALF 22
99 #define FULL 44 99 #define FULL 44
100 100
101 /* phy register offsets */ 101 /* phy register offsets */
102 #define MII_MIPSCR 0x11 102 #define MII_MIPSCR 0x11
103 103
104 /* MII_LPA */ 104 /* MII_LPA */
105 #define PHY_ANLPAR_PSB_802_3 0x0001 105 #define PHY_ANLPAR_PSB_802_3 0x0001
106 #define PHY_ANLPAR_PSB_802_9 0x0002 106 #define PHY_ANLPAR_PSB_802_9 0x0002
107 107
108 /* MII_CTRL1000 masks */ 108 /* MII_CTRL1000 masks */
109 #define PHY_1000BTCR_1000FD 0x0200 109 #define PHY_1000BTCR_1000FD 0x0200
110 #define PHY_1000BTCR_1000HD 0x0100 110 #define PHY_1000BTCR_1000HD 0x0100
111 111
112 /* MII_STAT1000 masks */ 112 /* MII_STAT1000 masks */
113 #define PHY_1000BTSR_MSCF 0x8000 113 #define PHY_1000BTSR_MSCF 0x8000
114 #define PHY_1000BTSR_MSCR 0x4000 114 #define PHY_1000BTSR_MSCR 0x4000
115 #define PHY_1000BTSR_LRS 0x2000 115 #define PHY_1000BTSR_LRS 0x2000
116 #define PHY_1000BTSR_RRS 0x1000 116 #define PHY_1000BTSR_RRS 0x1000
117 #define PHY_1000BTSR_1000FD 0x0800 117 #define PHY_1000BTSR_1000FD 0x0800
118 #define PHY_1000BTSR_1000HD 0x0400 118 #define PHY_1000BTSR_1000HD 0x0400
119 119
120 /* phy EXSR */ 120 /* phy EXSR */
121 #define ESTATUS_1000XF 0x8000 121 #define ESTATUS_1000XF 0x8000
122 #define ESTATUS_1000XH 0x4000 122 #define ESTATUS_1000XH 0x4000
123 123
124 #endif 124 #endif
125 125